Output harmonics, output power, and efficiency control for radio frequency (RF) power amplifiers

Abstract

The invention provides a method, a device and a system for wireless communication. The present implementations more particularly relate to reducing power consumption of a radio frequency (RF) power amplifier without sacrificing power efficiency. In some aspects, the RF transmitter may include a modulator, a power amplifier, and a duty cycle controller coupled between the modulator and the power amplifier. The modulator is configured to modulate data onto a carrier signal according to a frequency modulation (FM) scheme. The duty cycle controller is configured to adjust a duty cycle of the FM signal based on a target output power associated with the power amplifier. In some implementations, the duty cycle controller may reduce the duty cycle of the FM signal such that the adjusted duty cycle causes the power amplifier to operate at the target output power. A power amplifier amplifies the adjusted FM signal for transmission over the wireless communication channel.

Description

Technical Field

[0001] The present implementations relate generally to wireless communications, and specifically to output harmonics, output power, and efficiency control of radio frequency (RF) power amplifiers. Background Art

[0002] Wireless communication devices rely on radio frequency (RF) transmitters and receivers (also referred to as "wireless radios") to communicate with other devices over wireless communication channels. The RF transmitter modulates data or other information onto a carrier wave, and upconverts the modulated waveform to a radio frequency (such as 2.4 GHz), for example, by mixing the modulated waveform with a local oscillator (LO) signal that oscillates at a radio frequency. The resulting RF signal is further amplified by a power amplifier for transmission through a wireless channel via one or more antennas. Different classes of power amplifiers are designed to provide different levels of power efficiency. For example, linear class power amplifiers (such as class A amplifiers, class B amplifiers, and class AB amplifiers) sacrifice power efficiency to provide a more linear response or power curve. In contrast, nonlinear class power amplifiers (such as class C amplifiers, class D amplifiers, class E amplifiers, and class F amplifiers) provide greater power efficiency, but suffer from nonlinear response.

[0003] Many wireless communication devices are battery operated devices with limited power budgets. As such, many wireless communication devices implement wireless radios with nonlinear class power amplifiers to achieve better power efficiency. However, nonlinear class power amplifiers achieve their maximum power efficiency when operating at their maximum supported output power, while the power efficiency tends to decrease when operating at lower output powers. In other words, nonlinear class power amplifiers have a relatively narrow dynamic range in terms of linearity and efficiency. Thus, there is a need to reduce the power consumption of RF power amplifiers without sacrificing power efficiency. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] One innovative aspect of the disclosed subject matter can be implemented in a method performed by a duty cycle controller for a wireless communication device. The method includes: receiving a frequency modulated (FM) signal having a constant envelope waveform; adjusting the duty cycle of the constant envelope FM signal based at least in part on a target output power associated with a power amplifier of the wireless communication device; and after adjusting the duty cycle, outputting the constant envelope FM signal to the power amplifier for transmission over a wireless communication channel.

[0006] Another innovative aspect of the subject matter of the present disclosure can be implemented in a duty cycle controller for a wireless communication device. The duty cycle controller includes a delay line and a control circuit system coupled to the delay line. The delay line is configured to receive an FM signal having a constant envelope waveform. The control circuit system is configured to: adjust the duty cycle of the constant envelope FM signal based at least in part on a target output power associated with a power amplifier of the wireless communication device; and after adjusting the duty cycle, output the constant envelope FM signal to the power amplifier for transmission over a wireless communication channel.

[0007] Another innovative aspect of the subject matter of the present disclosure can be implemented in a system including a modulator, a power amplifier, and a duty cycle controller. The modulator is configured to modulate data onto a carrier signal according to a constant envelope frequency modulation (FM) scheme. The power amplifier is configured to amplify the modulated carrier signal for transmission over a wireless communication channel. The duty cycle controller is configured to adjust the duty cycle of the modulated carrier signal based at least in part on a target output power associated with the power amplifier before amplification by the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present implementations are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings.

[0009] Figure 1 A block diagram of an example radio frequency (RF) transmitter is shown in accordance with some implementations.

[0010] Figure 2 A block diagram of an example duty cycle controller is shown in accordance with some implementations.

[0011] Figure 3 A timing diagram depicting example operation of a duty cycle controller is shown according to some implementations.

[0012] Figure 4 A circuit diagram of an example duty cycle controller is shown in accordance with some implementations.

[0013] Figure 5 Another circuit diagram of an example duty cycle controller is shown according to some implementations.

[0014] Figure 6 Another block diagram of an example RF transmitter is shown in accordance with some implementations.

[0015] Figure 7 Another block diagram of an example RF transmitter is shown in accordance with some implementations.

[0016] Figure 8 An illustrative flow chart depicting example operations performed by a duty cycle controller for a wireless communication device is shown in accordance with some implementations. DETAILED DESCRIPTION

[0017] In the following description, many specific details, such as examples of specific components, circuits and processes, are set forth to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means directly connected to or connected through one or more intermediate components or circuits. The terms "electronic system" and "electronic device" can be used interchangeably to refer to any system that can electronically process information. Similarly, in the following description, and for the purpose of explanation, specific terms are set forth to provide a thorough understanding of aspects of the present disclosure. However, it will be apparent to those skilled in the art that these specific details may not be required to practice the exemplary embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid making the present disclosure difficult to understand. The subsequent parts of the detailed description are presented in terms of processes, logic blocks, processing, and other symbolic representations of the operation of data bits in a computer memory.

[0018] These descriptions and representations are the means by which the technical personnel in the field of data processing use to most effectively communicate the essence of their work to other technical personnel in the field. In the present disclosure, processes, logic blocks, processes, etc. are considered to be self-consistent sequences of steps or instructions that lead to a desired result. Steps are those steps that require the physical manipulation of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer system. However, it should be remembered that all terms in these terms and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to these quantities.

[0019] Unless otherwise specifically stated, as will be apparent from the following discussion, it is appreciated that throughout this application, discussions utilizing terms such as "access," "receive," "send," "use," "select," "determine," "normalize," "multiply," "average," "monitor," "compare," "apply," "update," "measure," "derive," etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.

[0020] In the accompanying drawings, a single block may be described as performing one or more functions; however, in actual practice, one or more functions performed by the block may be performed in a single component or across multiple components, and / or may be performed using hardware, using software, or using a combination of hardware and software. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described below generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Similarly, the example input device may include components other than those shown, including well-known components such as processors, memories, etc.

[0021] Unless the techniques described herein are specifically described as being implemented in a specific manner, the techniques may be implemented in hardware, software, firmware, or any combination thereof. Any features described as modules or components may also be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the techniques may be implemented at least in part by a non-transitory processor-readable storage medium that includes instructions that, when executed, perform one or more of the methods described above. The non-transitory processor-readable data storage medium may form part of a computer program product, which may include packaging materials.

[0022] Non-transitory processor-readable storage media may include random access memory (RAM) such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, other known storage media, etc. Additionally or alternatively, the technology may be at least partially implemented by a processor-readable communication medium that carries or communicates code in the form of instructions or data structures and can be accessed, read, and / or executed by a computer or other processor.

[0023] The various illustrative logical blocks, modules, circuits, and instructions described in conjunction with the embodiments disclosed herein may be executed by one or more processors (or processing systems). The term "processor" as used herein may refer to any general purpose processor, special purpose processor, conventional processor, controller, microcontroller, and / or state machine capable of executing scripts or instructions of one or more software programs stored in memory.

[0024] As described above, a radio frequency (RF) transmitter modulates data or other information onto a carrier wave, and upconverts the modulated waveform to a radio frequency (such as 2.4 GHz), for example, by mixing a constant envelope modulated waveform with a local oscillator (LO) signal oscillating at a radio frequency. The resulting RF signal is further amplified by a power amplifier for transmission through a wireless communication channel via one or more antennas. Many wireless communication devices are battery-operated devices with limited power budgets. As such, many wireless communication devices implement wireless radios with nonlinear class power amplifiers to achieve better power efficiency. However, nonlinear class power amplifiers achieve their maximum power efficiency when operating at their maximum supported output power, and when operating at lower output power, the power efficiency tends to decrease. In other words, nonlinear class power amplifiers have a relatively narrow dynamic range in terms of linearity and efficiency.

[0025] Many nonlinear class power amplifiers are designed with transistors that operate as switches that supply current to an output load. For example, the drain (or source) of the transistor may be coupled to a high voltage potential (such as a voltage source), the source (or drain) of the transistor may be coupled to a low voltage potential (such as ground), and the gate of the transistor may be driven by an input RF signal. As a result, the transistor typically operates in a saturation region, passing a certain amount of current between its source and drain terminals depending on the voltage or amplitude of the input RF signal. The power consumption of the power amplifier depends on the amount and duration of the current supplied by the transistor to the output load (such as when the voltage of the input RF signal is above a voltage threshold). Aspects of the present disclosure recognize that the power consumption of such a power amplifier can be reduced without sacrificing efficiency by reducing or shortening the duty cycle of the input RF signal.

[0026] Various aspects generally relate to RF power amplifiers, and more particularly to techniques for reducing the power consumption of RF power amplifiers without sacrificing power efficiency. In some aspects, an RF transmitter may include an FM modulator, a power amplifier, and a duty cycle controller coupled between the modulator and the power amplifier. The FM modulator is configured to modulate data onto a carrier signal according to a frequency modulation scheme. Thus, the modulated carrier signal may also be referred to as a frequency modulated (FM) signal. The duty cycle controller is configured to adjust the duty cycle of the FM signal based at least in part on a target output power associated with the power amplifier. The target output power may be less than the maximum power output of the power amplifier. In some implementations, the duty cycle controller may reduce the duty cycle of the FM signal so that the adjusted duty cycle causes the power amplifier to operate at the target output power. The power amplifier amplifies the adjusted FM signal for transmission through a wireless communication channel.

[0027] Particular implementations of the subject matter described in the present disclosure can be implemented to achieve one or more of the following potential advantages. By reducing the duty cycle of an FM signal prior to being amplified by a power amplifier, aspects of the present disclosure can significantly reduce the power consumption of the power amplifier with little reduction in power efficiency. For example, reducing the duty cycle of the FM signal reduces the duration in which the power amplifier is conducting current and also reduces the output power of the power amplifier while maintaining constant or consistent power efficiency over a relatively large dynamic range. This allows the power amplifier to operate with relatively high power efficiency while reducing overall power consumption over time. For example, an FM signal with a 25% duty cycle consumes significantly less power from the power amplifier for a given duration than an FM signal modulated with the same data or information having a 50% duty cycle.

[0028] Figure 1 A block diagram of an example RF transmitter 100 according to some implementations is shown. The RF transmitter 100 is configured to transmit (TX) data 102 or other digital information over a wireless communication channel on behalf of a wireless communication device. In some aspects, the RF transmitter 100 can comply with one or more wireless communication standards. Example suitable wireless communication standards include Digital Enhanced Cordless Telecommunications (DECT), Zigbee, and Bluetooth, among other examples.

[0029] The RF transmitter 100 includes a modulator 110, an RF mixer 120, a duty cycle controller 130, and a power amplifier (PA) 140. The modulator 110 is configured to modulate the TX data 102 onto a carrier signal or waveform. In some implementations, the modulator 110 may be an FM modulator that modulates the TX data 102 onto a carrier signal according to a frequency modulation scheme. More specifically, the modulator 110 varies the frequency of the carrier signal without changing its amplitude to produce a frequency modulated (FM) signal 104 having a constant envelope. Exemplary suitable FM modulators include, among other examples, a voltage controlled oscillator (VCO), a crystal oscillator (XO), and a phase locked loop (PLL) circuit.

[0030] The RF mixer 120 upconverts the FM signal 104 to a radio frequency. For example, the RF mixer 120 can mix the FM signal 104 with a local oscillator (LO) signal 106 that oscillates at a radio frequency. The resulting upconverted FM signal can be referred to as a "radio frequency" (RF) signal 108. The power amplifier 140 is configured to amplify the RF signal for transmission via one or more antennas 150. In some implementations, the power amplifier 140 can be a nonlinear class RF power amplifier with relatively high power efficiency. Among other examples, example suitable nonlinear class power amplifiers include class C amplifiers, class D amplifiers, class E amplifiers, and class F amplifiers.

[0031] Aspects of the present disclosure recognize that the duty cycle of the RF signal amplified by the power amplifier 140 controls the duration in which current flows through the power amplifier 140 (which is related to the power consumption of the power amplifier 140) within a given oscillation period. However, many FM modulators are designed to generate FM signals with a fixed duty cycle (such as 50%). In some aspects, the duty cycle controller 130 can control the power consumption of the power amplifier 140 by adjusting the duty cycle of the RF signal 108. More specifically, the duty cycle controller 130 can generate an RF signal 109 having the same frequency and amplitude as the RF signal 108, but a different duty cycle. As a result, the TX data 102 is also carried on the RF signal 109, and the power efficiency of the power amplifier 140 remains relatively unchanged.

[0032] In some implementations, the duty cycle controller 130 can reduce the duty cycle of the RF signal 109 (such as below 50%). The reduced duty cycle reduces both the output power and the power consumption of the power amplifier 140 over time without sacrificing power efficiency. Thus, in some implementations, the duty cycle controller 130 can reduce the duty cycle of the RF signal 108 based at least in part on a target or desired output power associated with the power amplifier 140. For example, the target output power can be less than the maximum power output of the power amplifier 140, but still suitable for a given wireless communication application.

[0033] Figure 2 2 shows a block diagram of an example duty cycle controller 200 according to some implementations. The duty cycle controller 200 is configured to adjust the duty cycle of a frequency modulated (FM) signal 202. More specifically, the duty cycle controller 200 generates a duty cycle adjusted (DCA) FM signal 206 having the same frequency and amplitude as the FM signal 202, but a different duty cycle. In some implementations, the duty cycle controller 200 may be Figure 1 An example of a duty cycle controller 130 is shown in FIG. Figure 1 , FM signal 202 may be an example of RF signal 108 input to duty cycle controller 130 , and DCA FM signal 206 may be an example of RF signal 109 output by duty cycle controller 130 to power amplifier 140 .

[0034] The duty cycle controller 200 includes a programmable delay component 210 and a combinatorial logic component 220. The programmable delay component 210 is configured to delay the FM signal 202 for a given duration, thereby resulting in a delayed FM signal 204. Accordingly, the delayed FM signal 204 and the input FM signal 202 have the same frequency and amplitude, but a different phase. In some implementations, the programmable delay component 210 can be based on a power amplifier (such as a DCA FM signal) used to transmit the DCA FM signal 206. Figure 1 The FM signal 202 is delayed by the target output power 203 associated with the power amplifier 140. Figure 1 As described above, the target output power 203 may represent the power at which the DCA FM signal 206 will be delivered by the power amplifier.

[0035] The combinatorial logic component 220 is configured to generate the DCA FM signal 206 based on the FM signal 202 and the delayed FM signal 204. In some implementations, the combinatorial logic component 220 may use combinatorial logic to combine the FM signal 202 with the delayed FM signal 204 to generate the DCA FM signal 206. For example, the combinatorial logic component 220 may include an AND logic gate having inputs that receive the FM signal 202 and the delayed FM signal 204 and an output that provides the DCA FM signal 206 as a logical AND combination of the input signals 202 and 204. As a result, the DCA FM signal 206 has the same frequency as the original FM signal 202, but a different duty cycle (due to the difference in phase between the FM signal 202 and the delayed FM signal 204).

[0036] Aspects of the present disclosure recognize that the difference in phase between the FM signal 202 and the delayed FM signal 204 determines the duty cycle of the DCA FM signal 206. Thus, the programmable delay component can control the duty cycle of the DCA FM signal 206 based on the delay applied to the FM signal 202. Figure 1 As described above, when transmitting the DCA FM signal 206, the duty cycle of the DCA FM signal 206 affects the output power of the power amplifier. For example, reducing the duty cycle of the DCA FM signal 206 also reduces the output power of the power amplifier. In some implementations, the programmable delay component 210 can tune the delay associated with the delayed FM signal 204 so that the resulting duty cycle of the DCA FM signal 206 causes the power amplifier to transmit the DCA FM signal 206 at the target output power 203.

[0037] Figure 3A timing diagram 300 depicting an example operation of a duty cycle controller according to some implementations is shown. The duty cycle controller is configured to adjust the duty cycle of an FM signal 302. More specifically, the duty cycle controller delays the FM signal 302 to produce a delayed FM signal 304, and uses combinational logic to combine the FM signal 302 with the delayed FM signal 304 to produce a DCAFM signal 306, which has the same frequency and amplitude as the FM signal 302, but a different duty cycle. In some implementations, the duty cycle controller may be Figure 2 An example of a duty cycle controller 200 is shown in FIG. Figure 2 , FM signal 302 , delayed FM signal 304 , and DCA FM signal 306 may be examples of FM signal 202 , delayed FM signal 204 , and DCA FM signal 206 , respectively.

[0038] like Figure 3 As shown in , FM signal 302 has a 50% duty cycle across a period (T0) from time t0 to time t4. More specifically, FM signal 302 has a relatively high amplitude or voltage (indicating a "high" logic state) between time t0 and time t2 and a relatively low amplitude or voltage (indicating a "low" logic state) between time t2 and time t4. Delayed FM signal 304 has a 50% duty cycle across period T0 from time t1 to time t5. More specifically, delayed FM signal 304 has a relatively high amplitude or voltage between time t1 and time t3 and a relatively low amplitude or voltage between time t3 and time t5. Figure 3 In the example of , the delayed FM signal 304 is 90° out of phase with the FM signal 302. In other words, the delayed FM signal 304 transitions from low to high halfway between time t0 and time t2 (at time t1), and transitions from high to low halfway between time t2 and time t4 (at time t3).

[0039] exist Figure 3In the example of , the DCA FM signal 306 represents the logical AND of the FM signal 302 and the delayed FM signal 304. Thus, the DCA FM signal 306 has a relatively low amplitude or voltage from time t0 to time t1 before transitioning to a relatively high amplitude or voltage at time t1 (coinciding with a low-to-high transition of the delayed FM signal 304). The DCA FM signal 306 maintains a high amplitude or voltage from time t1 to time t2 until transitioning back to a low amplitude or voltage at time t2 (coinciding with a high-to-low transition of the FM signal 302). The DCA FM signal 306 maintains a low amplitude or voltage from time t2 to time t5 until transitioning back to a high amplitude or voltage at time t5 (coinciding with another low-to-high transition of the delayed FM signal 304). As a result, the DCA FM signal 306 has a 25% duty cycle across the period T0 from time t1 to time t5. In other words, Figure 3 The duty cycle controller reduces the duty cycle of the FM signal 302 by half.

[0040] Figure 4 4 is a circuit diagram of an example duty cycle controller 400 according to some implementations. The duty cycle controller 400 is configured to adjust the duty cycle of the FM signal 402. More specifically, the duty cycle controller 400 generates a DCA FM signal 406 having the same frequency and amplitude as the FM signal 402, but a different duty cycle. In some implementations, the duty cycle controller 400 may be Figure 2 An example of a duty cycle controller 200 is shown in FIG. Figure 2 , FM signal 402 may be an example of FM signal 202 , and DCA FM signal 406 may be an example of DCAFM signal 206 .

[0041] The duty cycle controller 400 includes a tapped delay line formed by a series of delay stages 410(1)-410(8), a switching circuit system formed by multiple stages of multiplexers 420(1)-420(4), 430(1), 430(2) and 440(1), and a logic gate 450. The first delay stage 410(1) delays the FM signal 402 by a fixed or predetermined amount, resulting in a delayed FM signal 404(1). Each subsequent delay stage in the subsequent delay stages 410(2)-410(8) (such as the first delay stage 410(1)) applies an equal amount of delay to the output of the previous delay stage, resulting in additional delayed FM signals 404(2)-404(8). Thus, each of the delayed FM signals 404(1)-404(8) has a different phase offset relative to the original FM signal 402. Although in Figure 4Eight delay stages 410(1)-410(8) are shown in FIG. 4 , but in actual implementations, the delay line may include fewer or more delay stages.

[0042] The switch circuit system is configured to select one of the delayed FM signals 410(1)-410(8) to be combined with the original FM signal 402 at the logic gate 450. In some implementations, each of the multiplexers 420(1)-420(4), 430(1), 430(2), and 440(1) can be selectively enabled or disabled based on a corresponding enable signal (EN_A-EN_G). When a particular multiplexer is enabled (such as when the corresponding enable signal is driven to a logic high state), the multiplexer outputs one of the delayed FM signals at its input terminal in response to the corresponding select signal (SEL_A-SEL_G). When a particular multiplexer is disabled (such as when the corresponding enable signal is driven to a logic low state), the multiplexer does not output any of the delayed FM signals at its input terminal. In some implementations, the switching circuitry may iteratively halve the number of delayed FM signals across each layer of multiplexers until only one of the delayed FM signals 410 ( 1 )- 410 ( 8 ) remains.

[0043] exist Figure 4 In the example of , the first stage multiplexers 420(1)-420(3) can selectively output up to four delayed FM signals from the delayed FM signals 410(1)-410(8). For example, when the multiplexer 420(1) is enabled (such as when the enable signal EN_A is high), the multiplexer 420(1) can output one of the delayed FM signals 404(1) or 404(2) based on the first selection signal SEL_A. When the multiplexer 420(2) is enabled (such as when the enable signal EN_B is high), the multiplexer 420(2) can output one of the delayed FM signals 404(3) or 404(4) based on the second selection signal SEL_B. When multiplexer 420(3) is enabled (such as when enable signal EN_C is high), multiplexer 420(3) may output one of delayed FM signals 404(5) or 404(6) based on third select signal SEL_C. When multiplexer 420(4) is enabled (such as when enable signal EN_D is high), multiplexer 420(4) may output one of delayed FM signals 404(7) or 404(8) based on fourth select signal (SEL_D).

[0044] The second stage multiplexers 430(1) and 430(2) can selectively output up to two delayed FM signals from the delayed FM signals output by the first stage multiplexers 420(1)-420(4). For example, when the multiplexer 430(1) is enabled (such as when the enable signal EN_E is high), the multiplexer 430(1) can output one of the delayed FM signals from the multiplexer 420(1) or 420(2) based on the fifth selection signal SEL_E. When the multiplexer 430(2) is enabled (such as when the enable signal EN_F is high), the multiplexer 430(2) can output one of the delayed FM signals from the multiplexer 420(3) or 420(4) based on the sixth selection signal SEL_F. As such, multiplexer 430(1) may output one of delayed FM signals 404(1)-404(4), and multiplexer 430(2) may output one of delayed FM signals 404(5)-404(8). When multiplexer 440(1) is enabled (such as when enable signal EN_G is high), multiplexer 440(1) outputs one of the delayed FM signals from multiplexers 430(1) and 430(2) based on the seventh select signal (SEL_G). As a result, multiplexer 440(1) may accurately output one of delayed FM signals 404(1)-404(8).

[0045] Logic gate 450 is configured to combine the delayed FM signal output by multiplexer 440(1) with FM signal 402 using combinatorial logic to produce DCA FM signal 406. Figure 4 In the example of FIG. 4 , logic gate 450 is depicted as an AND logic gate (such as reference 400 ) that generates an output signal based on the logical AND of two input signals. Figure 3 In some other implementations, the logic gate 450 may implement various other logics (such as NAND logic) suitable for generating the DCA FM signal 406. Figure 3 , FM signal 402 may be an example of FM signal 302, the delayed FM signal output by multiplexer 440(1) may be an example of delayed FM signal 304, and DCA FM signal 406 may be an example of DCA FM signal 306. As a result, DCA FM signal 406 has the same amplitude as original FM signal 402, but a different duty cycle.

[0046] The duty cycle of DCA FM signal 406 depends on which of delayed FM signals 404(1)-404(8) is provided as an input to logic gate 450. For example, a delayed FM signal associated with fewer delay stages (such as delayed FM signal 404(1)) may produce a DCA FM signal 406 having a greater duty cycle than a delayed FM signal associated with more delay stages (such as delayed FM signal 404(8)). Select signals SEL_A-SEL_G, in combination with enable signals EN_A-EN_G, control the outputs of multiplexers 420(1)-420(4), 430(1), 430(2), and 440(1). As such, the values ​​of select signals SEL_A-SEL_G and enable signals EN_A-EN_G determine the duty cycle of DCA FM signal 406. In some implementations, the duty cycle controller 400 may receive a digital control word indicating the values ​​of the select signals SEL_A-SEL_G and the enable signals EN_A-EN_G. Figure 2 As described above, the duty cycle of the DCA FM signal 406 affects the output power of the power amplifier used to transmit the DCA FM signal 406. Thus, in some implementations, the digital control word can be associated with a target output power of the power amplifier (such as Figure 2 The target output power 203) is associated with the output power.

[0047] Aspects of the present disclosure recognize that each of multiplexers 420(1)-420(4), 430(1), 430(2), and 440(1) can add an amount of switching delay to the delayed FM signal at its output. In some aspects, duty cycle controller 400 can adjust FM signal 402 to compensate for the switching delays associated with multiplexers 420(1)-420(4), 430(1), 430(2), and 440(1). For example, duty cycle controller 400 can include a switching delay (SD) compensation component 460 that applies an amount of delay to FM signal 402 that is substantially equal to the delay applied to delayed FM signal 404(1)-404(8) by multiplexers 420(1)-420(4), 430(1), 430(2), and 440(1). In some implementations, the SD compensation component 460 may include a series of multiplexers 420 ( 0 ), 430 ( 0 ), and 440 ( 0 ) associated with a first stage multiplexer, a second stage multiplexer, and a third stage multiplexer, respectively, thereby forming a switching circuit system of the duty cycle controller 400 .

[0048] The first multiplexer 420(0) is configured to receive the FM signal 402 as its input(s) and output the FM signal 402 to the second multiplexer 430(0), which outputs the FM signal 402 to the third multiplexer 440(0), which outputs the FM signal 402 to the logic gate 450. Thus, the FM signal 402 is delayed by the first multiplexer 420(0) by a switching delay equal to the switching delay associated with the multiplexers 420(1)-420(4). The resulting FM signal 402 is delayed by the second multiplexer 430(0) by another switching delay equal to the switching delay associated with the multiplexers 430(1) and 430(2). The resulting FM signal 402 is delayed by a third multiplexer 440(0) by a further switching delay equal to the switching delay associated with multiplexer 440(1). As a result, when the signals are combined at logic gate 450, the switching delay offset applied to FM signal 402 at the first input of logic gate 450 is applied to the switching delay of the delayed FM signal.

[0049] Figure 5 Another circuit diagram of an example duty cycle controller 500 according to some implementations is shown. The duty cycle controller 500 is configured to adjust the duty cycle of the FM signal 502. More specifically, the duty cycle controller 500 generates a DCA FM signal 506 having the same frequency and amplitude as the FM signal 502, but a different duty cycle. In some implementations, the duty cycle controller 500 may be Figure 2 An example of a duty cycle controller 200 is shown in FIG. Figure 2 , FM signal 502 may be an example of FM signal 202 , and DCAFM signal 506 may be an example of DCAFM signal 206 .

[0050] The duty cycle controller 500 includes a tapped delay line formed by a series of delay stages 510(1)-510(4), a switching circuit system formed by a number of multiplexers 520(1)-520(4) (which can also be implemented using AND logic gates, each AND logic gate having an inverting input gate, where the transfer function ) and a series of logic gates 530(1)-530(4). The first delay stage 510(1) delays the FM signal 502 by a fixed or predetermined amount, resulting in a delayed FM signal 504(1). Each of the subsequent delay stages 510(2)-510(4), such as the first delay stage 510(1), applies an equal amount of delay to the output of the previous delay stage, resulting in additional delayed FM signals 504(2)-504(4). Thus, each of the delayed FM signals 504(1)-504(4) has a different phase offset relative to the original FM signal 502. Although in Figure 5 Four delay stages 510(1)-510(4) are shown in FIG. 5 , but in actual implementations, the delay line may include fewer or more delay stages.

[0051] The switch circuitry is configured to select one or more FM signals (including the original FM signal 502 or any of the delayed FM signals 504(1)-504(3)) to be combined with the delayed FM signal 504(4) via logic gates 530(1)-530(4). In some implementations, each of the multiplexers 520(1)-520(4) may output a corresponding FM signal associated with a high logic state or a constant voltage (V H For example, the multiplexer 520 (1) can output the original FM signal 502 or the constant voltage V based on the first selection signal (SEL_W). H , the multiplexer 520 (2) can output the delayed FM signal 504 (1) or the constant voltage V based on the second selection signal (SEL_X) H , the multiplexer 520 (3) can output the delayed FM signal 504 (2) or the constant voltage V based on the third selection signal (SEL_Y). H , and the multiplexer 520 (4) can output the delayed FM signal 504 (3) or the constant voltage V based on the fourth selection signal (SEL_Z) H .

[0052] Logic gates 530(1)-530(4) are configured to combine delayed FM signal 504(4) with the outputs of multiplexers 520(1)-520(4) using combinatorial logic to produce DCAFM signal 506. Figure 5 In the example of FIG. 5 , each of logic gates 530 ( 1 )- 530 ( 4 ) is depicted as an AND logic gate that generates an output signal based on a logical AND of two input signals (such as reference 54 ). Figure 3506). In some other implementations, logic gates 530(1)-530(4) may implement various other logic (such as NAND logic) suitable for generating DCAFM signal 506. In some implementations, logic gates 530(1)-530(4) may be coupled in a cascade configuration such that the output of each logic gate is provided as an input to the next logic gate in the cascade, where the last logic gate in the cascade outputs DCAFM signal 506. More specifically, each logic gate combines the output of a corresponding multiplexer with the output of the previous logic gate in the cascade (or delayed FM signal 504(4)).

[0053] For example, logic gate 530(4) uses AND logic to combine delayed FM signal 504(4) with the output of multiplexer 520(4) to produce first intermediate FM signal 505(1). Multiplexer 520(4) outputs a constant voltage V (based on select signal SEL_Z). H , the intermediate FM signal 505(1) simply tracks the delayed FM signal 504(4). In other words, the constant voltage V H Logic gate 530(4) is caused to output delayed FM signal 504(4) unchanged. However, when multiplexer 520(4) outputs delayed FM signal 504(3), intermediate FM signal 505(1) has a different duty cycle than delayed FM signal 504(4). Figure 3 , delayed FM signal 504 ( 3 ) may be an example of FM signal 302 , delayed FM signal 504 ( 4 ) may be an example of delayed FM signal 304 , and intermediate FM signal 505 ( 1 ) may be an example of DCAFM signal 306 .

[0054] Logic gate 530 (3) uses AND logic to combine intermediate FM signal 505 (1) with the output of multiplexer 520 (3) to produce a second intermediate FM signal 505 (2). Multiplexer 520 (3) outputs a constant voltage V based on the select signal SEL_Y. H , intermediate FM signal 505(2) simply tracks intermediate FM signal 505(1). In other words, the constant voltage V H Logic gate 530(3) is caused to output intermediate FM signal 505(1) unchanged. However, when multiplexer 520(3) outputs delayed FM signal 504(2), intermediate FM signal 505(2) has a different duty cycle than intermediate FM signal 505(1). Figure 3, delayed FM signal 504 ( 2 ) may be an example of FM signal 302 , intermediate FM signal 505 ( 1 ) may be an example of delayed FM signal 304 , and intermediate FM signal 505 ( 2 ) may be an example of DCA FM signal 306 .

[0055] Logic gate 530(2) uses AND logic to combine intermediate FM signal 505(2) with the output of multiplexer 520(2) to produce third intermediate FM signal 505(3). Multiplexer 520(2) outputs a constant voltage V based on select signal SEL_X. H , intermediate FM signal 505(3) simply tracks intermediate FM signal 505(2). In other words, the constant voltage V H Logic gate 530(2) is caused to output intermediate FM signal 505(2) unchanged. However, when multiplexer 520(2) outputs delayed FM signal 504(1), intermediate FM signal 505(3) has a different duty cycle than intermediate FM signal 505(2). Figure 3 , delayed FM signal 504 ( 1 ) may be an example of FM signal 302 , intermediate FM signal 505 ( 2 ) may be an example of delayed FM signal 304 , and intermediate FM signal 505 ( 3 ) may be an example of DCA FM signal 306 .

[0056] Logic gate 530(1) uses AND logic to combine intermediate FM signal 505(3) with the output of multiplexer 520(1) to generate DCAFM signal 506. Multiplexer 520(1) outputs a constant voltage V based on select signal SEL_W. H , the DCA FM signal 506 simply tracks the intermediate FM signal 505 (3). In other words, the constant voltage V H The logic gate 530(1) is caused to output the intermediate FM signal 505(3) unchanged. However, when the multiplexer 520(1) outputs the original FM signal 502, the DCA FM signal 506 has a different duty cycle than the intermediate FM signal 505(3). Figure 3 , original FM signal 502 may be an example of FM signal 302 , intermediate FM signal 505 ( 3 ) may be an example of delayed FM signal 304 , and DCA FM signal 506 may be an example of DCA FM signal 306 .

[0057] The duty cycle of the DCA FM signal 506 depends on which of the FM signals 502 or 504(1)–504(3) is provided as an input to the logic gates 530(1)–530(4). For example, combining the delayed FM signal 504(4) with the original FM signal 502 results in the DCA FM signal 506 having a relatively small duty cycle, while combining the delayed FM signal 504(4) with the delayed FM signal 504(3) results in the DCA FM signal 506 having a much larger duty cycle. The select signals SEL_W–SEL_Z control the outputs of the multiplexers 520(1)–520(4). As such, the values ​​of the select signals SEL_W–SEL_Z determine the duty cycle of the DCA FM signal 506. In some implementations, the duty cycle controller 500 may receive a digital control word indicating the values ​​of the select signals SEL_W–SEL_Z. As described with reference to Figure 2 As described above, the duty cycle of the DCA FM signal 506 affects the output power of the power amplifier used to transmit the DCA FM signal 506. Thus, in some implementations, the digital control word can be related to the target output power of the power amplifier (such as Figure 2 The target output power 203) is associated with the output power.

[0058] In some implementations, the digital control word may cause only one of the multiplexers 520(1)-520(4) to output an FM signal, while the remaining multiplexers output a constant voltage V H In some other implementations, the digital control word may cause multiple multiplexers 520(1)-520(4) to output respective FM signals. Because the outputs of multiplexers 520(1)-520(4) are combined in a cascaded fashion, changes in duty cycle can be accumulated across a series of logic gates 530(1)-530(4). Aspects of the present disclosure recognize that accumulating multiple incremental changes in duty cycle may result in a more linear DCA FM signal 506. More generally, the number of incremental changes in duty cycle affects the linearity of the DCA FM signal 506.

[0059] In some implementations, to reduce redundancy, the duty cycle controller 500 may accept only certain permutations or patterns of digital control words (as input). More specifically, the pattern of the digital control words may be selected to achieve a more linear response for the power amplifier. For some applications where two different patterns of digital control words produce corresponding DCA FM signals 506 that result in the same output power at the power amplifier (where one of the digital control words produces a more linear DCA FM signal 506 than the other digital control word), the pattern associated with the more nonlinear DCA FM signal 506 may be selected as an input to the duty cycle controller 500 over the pattern associated with the more linear DCA FM signal 506. For some other applications, the pattern associated with the more linear DCA FM signal 506 may be selected as an input to the duty cycle controller 500 over the pattern associated with the more nonlinear DCA FM signal 506.

[0060] Aspects of the present disclosure further recognize that each of the logic gates 530(1)-530(3) can add an amount of gate delay to the intermediate FM signal at its output. In some aspects, the duty cycle controller 500 can adjust the FM signal 502 and the delayed FM signals 504(1) and 504(2) to compensate for the gate delays associated with the logic gates 530(1)-530(3). For example, the duty cycle controller 500 can include a first gate delay (GD) compensation component 540 that compensates for the delay applied by the logic gate 530(4) to the intermediate FM signal 505(1), a second GD compensation component 550 that compensates for the delay applied by the logic gates 530(3) and 530(4) to the intermediate FM signal 502(2), and a third GD compensation component 560 that compensates for the delay applied by the logic gates 530(2), 530(3), and 530(4) to the intermediate FM signal 505(3).

[0061] The first GD compensation component 540 includes a single AND logic gate configured to receive the output of the multiplexer 520(3) as its input. Thus, the output of the multiplexer 520(3) is delayed by a gate delay equal to the gate delay associated with the logic gate 530(4) through the first GD compensation component 540. The second GD compensation component 550 includes a pair of AND logic gates coupled in series, wherein the first logic gate is configured to receive the output of the multiplexer 520(2) as its input and the second logic gate is configured to receive the output of the first logic gate as its input. Thus, the output of the multiplexer 520(2) is delayed by a plurality of gate delays equal to the gate delays associated with the logic gates 530(3) and 530(4) through the second GD compensation component 550.

[0062] The third GD compensation component 560 includes three AND logic gates coupled in series, wherein a first logic gate is configured to receive the output of the multiplexer 520(1) as its input, a second logic gate is configured to receive the output of the first logic gate as its input, and a third logic gate is configured to receive the output of the second logic gate as its input. Thus, the output of the multiplexer 520(1) is delayed by the third GD compensation component 560 by a plurality of gate delays equal to the gate delays associated with the logic gates 530(2), 530(3), and 530(4). As a result, when the signals are combined at the logic gates 530(1)-530(3), the gate delay offset applied to the FM signal 502 and the delayed FM signals 504(1) and 504(2) is applied to the gate delays of the intermediate FM signals 505(1)-505(3).

[0063] Figure 6 Another block diagram of an example RF transmitter 600 according to some implementations is shown. The RF transmitter 600 is configured to transmit a frequency modulated differential RF signal over a wireless communication channel, where the differential RF signal is represented by a pair of complementary RF signals 602(P) and 602(N). As a differential pair, the RF signals 602(P) and 602(N) have the same frequency and amplitude, but opposite polarity to each other.

[0064] The RF transmitter 600 includes a pair of duty cycle controllers 610(P) and 610(N) and a differential power amplifier (PA) 620. The first duty cycle controller 610(P) is configured to adjust the duty cycle of the RF signal 602(P) based on a first control word 603(P). More specifically, the first duty cycle controller 610(P) can generate an RF signal 604(P) having the same frequency and amplitude as the RF signal 602(P), but a different duty cycle. The second duty cycle controller 610(N) is configured to adjust the duty cycle of the RF signal 602(N) based on a second control word 603(N). More specifically, the second duty cycle controller 610(N) can generate an RF signal 604(N) having the same frequency and amplitude as the RF signal 602(N), but a different duty cycle.

[0065] The differential power amplifier 620 amplifies the difference in phase and duty cycle between the RF signals 604(P) and 604(N) to produce an amplified RF signal 606 for transmission over a wireless communication channel. As a result, the amplified RF signal 606 has a higher output power than either of the RF signals 604(P) or 604(N). In some implementations, each of the duty cycle controllers 610(P) and 610(N) may be a duty cycle controller 610(P), 610(N), respectively. Figure 1 , 2, 4 and 5. For example, the duty cycle controllers 610(P) and 610(N) can adjust the duty cycle of the RF signals 604(P) and 604(N) based on the target output power associated with the differential power amplifier 620. In some implementations, the control words 603(P) and 603(N) can be associated with the target output power of the differential power amplifier 620 (such as reference 1). Figure 2 and description).

[0066] Aspects of the present disclosure recognize that by amplifying the difference between the RF signals 604(P) and 604(N), the differential power amplifier 620 can cancel or remove output harmonics from the amplified RF signal 606. More specifically, when the complementary RF signals 604(P) and 604(N) are 180° out of phase, the even harmonics cancel in an ideal differential power amplifier 620. However, when the differential power amplifier 620 is non-ideal, the RF signals 604(P) and 604(N) are not completely differential. In other words, the phase difference between the complementary stages of the power amplifier is not equal to 180°. In some implementations, the duty cycle controllers 610(P) and 610(N) can further adjust the phase of one or more of the RF signals 604(P) or 604(N) to ensure that when combined in the differential power amplifier 620, the signals are 180° out of phase. In this manner, duty cycle controllers 610 (P) and 610 (N) may further reduce output harmonics of amplified RF signal 606 .

[0067] Figure 7 Another block diagram of an example RF transmitter 700 according to some implementations is shown. The RF transmitter 700 is configured to transmit a frequency modulated differential RF signal over a wireless communication channel, where the differential RF signal is represented by a pair of complementary RF signals 702(P) and 702(N). As a differential pair, the RF signals 702(P) and 702(N) have the same frequency and amplitude, but opposite polarity to each other.

[0068] The RF transmitter 700 includes a pair of duty cycle controllers 710(P) and 710(N), power amplifiers 720(P) and 720(N), and an RF signal combiner 730. The first duty cycle controller 710(P) is configured to adjust the duty cycle of the RF signal 702(P) based on a first control word 703(P). More specifically, the first duty cycle controller 710(P) can generate an RF signal 704(P) having the same frequency and amplitude as the RF signal 702(P), but a different duty cycle. The second duty cycle controller 710(N) is configured to adjust the duty cycle of the RF signal 702(N) based on a second control word 703(N). More specifically, the second duty cycle controller 710(N) can generate an RF signal 704(N) having the same frequency and amplitude as the RF signal 702(N), but a different duty cycle.

[0069] Power amplifiers 720(P) and 720(N) amplify RF signals 704(P) and 704(N), respectively, to generate amplified RF signals 706(P) and 706(N). RF signal combiner 730 is configured to combine amplified RF signals 706(P) and 706(N) to generate combined RF signal 708, which has a higher output power than either amplified RF signal 706(P) or 706(N). In some implementations, each of duty cycle controllers 710(P) and 710(N) may be a duty cycle controller, respectively. Figure 1 , 2 , 4 and 5. For example, the first duty cycle controller 710(P) can adjust the duty cycle of the RF signal 704(P) based on the target output power associated with the power amplifier 720(P), and the second duty cycle controller 710(N) can adjust the duty cycle of the RF signal 704(N) based on the target output power associated with the power amplifier 720(N). In some implementations, the control words 703(P) and 703(N) can be associated with the target output powers of the power amplifiers 720(P) and 720(N), respectively (such as reference 1 to 1). Figure 2 and description).

[0070] Aspects of the present disclosure recognize that by combining the amplified RF signals 706(P) and 706(N), the RF signal combiner 730 can cancel or remove output harmonics from the combined RF signal 708. More specifically, when the amplified RF signals 706(P) and 706(N) are 180° out of phase, when the amplified RF signals 706(P) and 706(N) are combined in an ideal RF signal combiner 730, the even harmonics cancel. However, when the power amplifiers 720(P) and 720(N) and the RF signal combiner 730 are non-ideal, the RF signals 706(P) and 706(N) are not completely differential. In other words, when the signals are combined in the RF signal combiner 730, the phase difference between the RF signals 706(P) and 706(N) is not equal to 180°. In some implementations, the duty cycle controllers 710(P) and 710(N) can further adjust the phase of one or more of the RF signals 704(P) or 704(N) to ensure that the amplified RF signals 706(P) and 706(N) are 180° out of phase when combined in the RF signal combiner 730. In this way, the duty cycle controllers 710(P) and 710(N) can further reduce the output harmonics of the combined RF signal 708.

[0071] Figure 8 An illustrative flow chart depicting example operations 800 performed by a duty cycle controller for a wireless communication device according to some implementations is shown. In some implementations, the duty cycle controller may be Figure 1 , 2 An example of any duty cycle controller in duty cycle controllers 120 , 200 , 400 or 500 of , 4 and 5 .

[0072] A duty cycle controller receives a frequency modulated (FM) signal (810). The duty cycle controller adjusts the duty cycle of the FM signal based at least in part on a target output power associated with a power amplifier of the wireless communication device (820). In some implementations, the adjusted duty cycle of the FM signal may cause the power amplifier to operate at the target output power. In some implementations, the target output power may be less than a maximum power output of the power amplifier. In some implementations, the adjustment of the duty cycle may include reducing the duty cycle of the FM signal. In some implementations, the adjusted duty cycle may be less than 50%. After adjusting the duty cycle, the duty cycle controller outputs the FM signal to the power amplifier for transmission over a wireless communication channel (830).

[0073] In some aspects, the adjustment of the duty cycle may include: delaying the FM signal for a duration associated with the target output power; and combining the FM signal with the delayed FM signal based on the combination logic. In some implementations, the adjustment of the duty cycle may include: applying a series of delays to the FM signal, which produces a series of delayed FM signals; selecting one or more delayed FM signals in the series of delayed FM signals based on the target output power; and combining the FM signal with the one or more delayed FM signals based on the combination logic. In some implementations, the selection of the one or more delayed FM signals may include receiving a digital control word indicating the selection of the one or more delayed FM signals.

[0074] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0075] In addition, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0076] The methods, sequences or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or in any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor.

[0077] In the foregoing description, embodiments have been described with reference to specific examples thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader scope of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method performed by a duty cycle controller for a wireless communication device, comprising: receiving a frequency modulated (FM) signal having a constant envelope waveform; adjusting a duty cycle of the FM signal based at least in part on a target output power associated with a power amplifier of the wireless communication device; as well as After adjusting the duty cycle, the FM signal is output to the power amplifier for transmission over a wireless communication channel. 2 . The method of claim 1 , wherein the adjusted duty cycle of the FM signal causes the power amplifier to operate at the target output power. The method according to claim 1 , wherein the target output power is less than a maximum power output of the power amplifier. The method of claim 1 , wherein the adjustment of the duty cycle comprises reducing the duty cycle of the FM signal. The method of claim 1 , wherein the adjusted duty cycle is less than 50%.

6. The method of claim 1 , wherein the adjusting of the duty cycle comprises: delaying the FM signal for a duration associated with the target output power; as well as The FM signal is combined with the delayed FM signal based on combinational logic.

7. The method of claim 1 , wherein the adjusting of the duty cycle comprises: applying a series of delays to the FM signal respectively, which produces a series of delayed FM signals; selecting one or more delayed FM signals from the series of delayed FM signals based on the target output power; as well as The FM signal is combined with the one or more delayed FM signals based on combinational logic.

8. The method of claim 7, wherein the selection of the one or more delayed FM signals comprises: A digital control word indicative of the selection of the one or more delayed FM signals is received.

9. A duty cycle controller for a wireless communication device, the duty cycle controller comprising: a delay line configured to receive a frequency modulated (FM) signal having a constant envelope waveform; as well as control circuitry coupled to the delay line and configured to: adjusting a duty cycle of the FM signal based at least in part on a target output power associated with a power amplifier of the wireless communication device; and After adjusting the duty cycle, the FM signal is output to the power amplifier for transmission over a wireless communication channel.

10. The duty cycle controller of claim 9, wherein the adjusted duty cycle of the FM signal causes the power amplifier to operate at the target output power.

11. The duty cycle controller of claim 9, wherein the target output power is less than a maximum power output of the power amplifier.

12. The duty cycle controller of claim 9, wherein the adjustment of the duty cycle comprises decreasing the duty cycle of the FM signal.

13. The duty cycle controller of claim 9, wherein the adjusted duty cycle is less than 50%.

14. The duty cycle controller of claim 9, wherein the delay line is further configured to apply a series of delays to the FM signal respectively, which produces a series of delayed FM signals.

15. The duty cycle controller of claim 14, wherein the control circuit system comprises: switching circuitry configured to select one or more delayed FM signals from the series of delayed FM signals based on the target output power; as well as One or more logic gates configured to generate the adjusted duty cycle based on the received FM signal and the one or more delayed FM signals.

16. The duty cycle controller of claim 15, wherein the switching circuitry comprises one or more multiplexers each having a plurality of inputs.

17. The duty cycle controller of claim 16, wherein each of the one or more multiplexers has an output switchably coupled to one of the plurality of inputs based on a digital control word.

18. The duty cycle controller of claim 16, wherein the plurality of inputs comprises: a first input configured to receive a first delayed FM signal of the series of delayed FM signals; as well as A second input is configured to receive a second delayed FM signal of the series of delayed FM signals.

19. The duty cycle controller of claim 16, wherein the plurality of inputs comprises: a first input configured to receive a respective delayed FM signal of the series of delayed FM signals; as well as A second input is configured to receive a voltage representing a logic high state associated with the one or more logic gates.

20. A system comprising: a modulator configured to modulate data onto a carrier signal according to a constant envelope frequency modulation (FM) scheme; a power amplifier configured to amplify the modulated carrier signal for transmission over a wireless communication channel; as well as A duty cycle controller is configured to adjust a duty cycle of the modulated carrier signal based at least in part on a target output power associated with the power amplifier prior to amplification by the power amplifier.

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