A distributed matrix switching system, a packet forwarding method and a chip

Abstract

The application relates to a distributed matrix switching system, a message forwarding method and a chip, and the system comprises a plurality of input ports and a plurality of output ports, each input port is connected with a switching module, the number of the plurality of input ports is consistent with the number of the plurality of output ports, each output port is connected with a buffer module, each switching module is connected with all buffer modules respectively, each switching module is used for performing message scheduling and forwarding on an original message received by the corresponding input port, so that the message after the message scheduling and forwarding processing is output from any one of all output ports. Through the message forwarding of the system, the head blocking problem is solved, the message forwarding delay is reduced, and the forwarding efficiency of the whole chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular, the present application relates to a kind of distributed matrix type switching system, message forwarding method and chip. BACKGROUND

[0002] Network communication has become an indispensable communication technology in our daily life and production.In the network communication process,switch is usually used to realize the switching of network message.Switch chip is the core chip in switch, and the performance of switch is directly affected by the design of switch chip architecture.Therefore, switch chip architecture design is the key link of switch chip design.

[0003] The main function of switch chip is to realize the data forwarding function between multiple ports, which is usually realized by table lookup forwarding to realize two-layer, three-layer, four-layer and other switching.The existing single bus switching architecture is as shown in Figure 1 .

[0004] Based on the single bus switching architecture as shown in Figure 1 , the message switching process is as follows:

[0005] (1) Port processing module Port receives original message from physical interface and puts it into input buffer (Port_0 to Port_N);

[0006] (2) In port scheduling module In_mux schedules the message from a certain port input buffer to the next stage according to the relevant algorithm;

[0007] (3) Message analysis module Pkt_parser extracts the key from the original message, which is usually dmac+vlan_id+port_id or five-tuple+port_id, etc.; look up switch_tbl through the key, and write the original message to cache Data_Ram, and give the control information to the next stage module through cfifo;

[0008] (4) Message editing module Pkt_edit obtains the table lookup return result (including message editing information and information for sending out from a certain port); take out the message from Data_Ram through the control information in cfifo, and edit the message according to the table lookup return result, and send the processed message to the next stage distribution module for forwarding;

[0009] (5) Out port distribution module Out_dmux receives the control information and message transmitted by Pkt_edit module, and sends the message to the buffer of corresponding output port according to the forwarding port (FW_port) returned by the table lookup;

[0010] (6) Port processing module Port reads data from the output buffer and sends it out from the physical interface.

[0011] For the existing single-table single-bus forwarding process, there is a first technical problem (head blocking problem), which is analyzed as follows: as an example, referring to Figure 2 , the message of port 0 is forwarded to port 3, the message of port 1 is forwarded to port 4, and the message of port 2 is forwarded to port 5. RR scheduling is used between ports, and each port has a message to be forwarded at the same time. At this time, the forwarding is shown in Figure 2 . Port 0 is forwarded to port 3, port 1 is forwarded to port 4, and port 2 is forwarded to port 5. Logically, they are independent and have no relationship with each other. However, when using a single-bus architecture, the message of port 1 forwarded to port 4 has to wait for port 0 to complete the forwarding of a message before it can be executed, and the message of port 2 forwarded to port 5 has to wait for port 1 to complete the forwarding of a message before it can be executed. The above message forwarding, which is not related (such as port 0 forwarding to port 3 should not affect the processing of port 1 forwarding to port 4), has a head blocking problem between each other due to the use of single-table single-bus architecture, and the more the number of ports, the more serious the "head blocking" problem.

[0012] For the existing single-table single-bus forwarding process, there is a second technical problem, referring to Figure 3 , the processing on the switching bus is in units of a complete message, and the switching bus processing rate is much higher than the port rate. When the In_mux module uses non-integer packet scheduling between multiple input ports (i.e. when part of the data in the input buffer of a port is not a complete message, it is scheduled for processing), the "waiting waste" problem will occur. Especially when the rates of the ports are inconsistent, this "waiting waste" is more obvious.

[0013] In summary, the above-mentioned single-table single-bus switching mode has the following problems:

[0014] (1) Multiple-port message switching has a "head blocking" problem;

[0015] (2) When multiple-port non-integer packet scheduling is used, the bus will have a "waiting waste" problem. SUMMARY

[0016] The technical problem to be solved by the present application is to provide a distributed matrix switching system, a message forwarding method and a chip, which aims to solve at least one of the above technical problems.

[0017] The first aspect, the technical scheme that the present application solves above-mentioned technical problem is as follows: a kind of distributed matrix switching system, including multiple input ports and multiple output ports, each described input port connects a switching module, the number of multiple described input ports is consistent with the number of multiple described output ports, each described output port connects a buffer module, each described switching module is connected with all buffer modules respectively, each described switching module is used to the original message received by corresponding input port is carried out message scheduling and forwards, to make the message after message scheduling and forwarding processing from any one of all output ports output.

[0018] The beneficial effects of the present application are: in the present scheme, a switching module is provided for each input port, so that the original message received from any one of multiple input ports can be output from any one of all output ports, so that there is no "head blocking problem" in the process of message forwarding based on the system, the message forwarding delay is reduced, and the forwarding efficiency of the whole chip is improved.

[0019] Based on the above technical scheme, the present application can also be improved as follows.

[0020] Further, each described switching module is connected with all buffer modules respectively by full cross connection mode.

[0021] Further, for each described buffer module, the original cache space and the new cache space are included in the buffer module, the original cache space is used to store the message after message scheduling and forwarding processing, and the new cache space is used to store the whole packet identifier, and the whole packet identifier is used to represent whether the message after message scheduling and forwarding processing has been stored completely.

[0022] The second aspect, the present application is also provided to solve the above technical problems A message forwarding method applied to the distributed matrix switching system of the first aspect, the method comprises:

[0023] Original message is received through any one of multiple input ports and is analyzed and edited;

[0024] The message after analysis and editing is forwarded to the buffer module of corresponding output port by using whole packet scheduling processing mode;

[0025] The message after analysis and editing is output from corresponding output port by the buffer module.

[0026] The beneficial effects of the present application are: in the process of message forwarding based on a distributed matrix switching system, the message after the parsing and editing processing is forwarded to the buffer module of the corresponding output port by using the whole packet scheduling processing mode, which can avoid the problem of "waiting waste" on the internal bus of the chip, and improve the utilization rate of the internal bus of the chip.

[0027] Further, the whole packet scheduling processing mode for forwarding the message after the parsing and editing processing to the buffer module of the corresponding output port comprises:

[0028] When the buffer module receives the message after the parsing and editing processing, the message after the parsing and editing processing is written into the original cache space in the buffer module, and the whole packet identifier is stored in the new cache space in the buffer module, the whole packet identifier is used to represent whether the message after the parsing and editing processing has been completely stored, and the whole packet identifier is written into the new cache space after the message after the parsing and editing processing is completely written into the original cache space.

[0029] Further, the whole packet identifier is read from the buffer module after the message after the parsing and editing processing, and the message after the parsing and editing processing is output from the corresponding output port through the buffer module, comprising:

[0030] In the process of reading the message after the parsing and editing processing from the original cache space of the buffer module, when the whole packet identifier is read, the message after the parsing and editing processing is output from the corresponding output port.

[0031] Further, the width of the new cache space is 1, and the depth is determined based on the bit width and depth of the original cache space.

[0032] In a third aspect, the present application also provides a chip to solve the above technical problems, which comprises the distributed matrix switching system of the first aspect.

[0033] In a fourth aspect, the present application also provides an electronic device to solve the above technical problems, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the message forwarding method of the present application when executing the computer program.

[0034] In a fifth aspect, the present application also provides a computer readable storage medium to solve the above technical problems, which stores a computer program, and the computer program is executed by a processor to implement the message forwarding method of the present application.

[0035] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the attendant drawings or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced.

[0037] Figure 1 A single bus switching architecture schematic diagram provided for an embodiment of the present application;

[0038] Figure 2 A single bus switching process schematic diagram provided for an embodiment of the present application;

[0039] Figure 3 A single bus switching rate schematic diagram provided for an embodiment of the present application;

[0040] Figure 4 A distributed switching matrix system structure schematic diagram provided for an embodiment of the present application;

[0041] Figure 5 A message forwarding method flow schematic diagram provided for an embodiment of the present application;

[0042] Figure 6 A message processing flow schematic diagram provided for an embodiment of the present application;

[0043] Figure 7 A message forwarding process schematic diagram based on a distributed switching matrix system provided for an embodiment of the present application;

[0044] Figure 8 A whole packet fifo structure schematic diagram provided for an embodiment of the present application;

[0045] Figure 9 A whole packet scheduling bus schematic diagram provided for an embodiment of the present application;

[0046] Figure 10 A structure schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0047] The principles and features of the present application are described below, and the examples are only used to explain the present application, and are not used to limit the scope of the present application.

[0048] The technical solutions of the present application and how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0049] The scheme provided by the embodiments of the present application can be applied to any application scenario that needs to forward a message.

[0050] The embodiments of the present application provide a possible implementation manner, as shown in Figure 4 A distributed matrix switching system is provided, which includes a plurality of input ports and a plurality of output ports, each of the input ports is connected to a switching module, the number of the plurality of input ports is consistent with the number of the plurality of output ports, each of the output ports is connected to a buffer module, each of the switching modules is connected to all the buffer modules, and each of the switching modules is configured to perform message scheduling and forwarding on an original message received by the corresponding input port, so that the message after the message scheduling and forwarding processing is output from any one of the output ports. In this way, for the original message received by any one of the input ports, the original message can be output from any one of the output ports. The input and output of each port are independent of each other, that is, each input port and each output port are independent of each other and do not affect each other.

[0051] Referring to Figure 4 , the plurality of input ports are specifically Figure 4 ports 0 to N shown on the left, the switching modules corresponding to the plurality of input ports are specifically Figure 4 Switch_0 to Switch_N shown in , and each of the output ports is specifically Figure 4 ports 0 to N shown on the right, and the buffer modules corresponding to each of the output ports are specifically Figure 4 MUX_0 to MUX_N shown in .

[0052] For each of the switching modules, the internal structure of the switching module can be seen from Figure 4 the structure diagram on the left. A switching module includes a pkt_parser, a switch_tbl, a pkt_edit (Pkt_edit), a data_ram (Data_Ram), and a dmx (Out_dmux) and the like. The functions of each module are the same as those of each module in the prior art, and will not be described again here.

[0053] Wherein, based on the distributed matrix switching system, the distributed forwarding of multiple messages can be performed, i.e. multiple messages enter from multiple input ports and output from multiple output ports. Wherein, the meaning of message scheduling and forwarding refers to the original message received from the input port, which is processed by each module in the distributed matrix switching system. The specific working principle and processing process will be described in detail in the message forwarding method below, which will not be described here.

[0054] Optionally, each of the switching modules is connected with all the buffer modules through full cross connection mode.

[0055] Optionally, for each of the buffer modules, the buffer module includes an original cache space and a new cache space, the original cache space is used to store the message processed by the message scheduling and forwarding, and the new cache space is used to store a whole packet identifier, the whole packet identifier is used to represent whether the message processed by the message scheduling and forwarding has been completely stored.

[0056] On the basis of the original cache space, the new cache space is added, and the whole packet identifier stored in the new cache space is used to judge whether the message processed by the message scheduling and forwarding has been completely stored in the buffer module, so as to realize the whole packet storage and whole packet scheduling.

[0057] Based on the above-mentioned distributed matrix switching system, the application further provides a message forwarding method, which is described with reference to the flow chart shown in Figure 5 The method can include the following steps:

[0058] S10, receiving an original message through any one of the multiple input ports and performing parsing and editing processing;

[0059] Wherein, the specific implementation process of the input port for parsing and editing processing of the original message can be referred to the input processing flowchart on the left side: Figure 6

[0060] (1) the input port receives the original message and puts it into the input buffer;

[0061] (2) the input port scheduling module In_mux reads the original message from the input buffer according to the relevant algorithm and parses the message, extracts the key from the original message through the message parsing module Pkt_parser, and stores the original message in the data cache;

[0062] (3) the switch_tbl is used to look up the key and obtain the lookup return result;

[0063] (4) the message editing module Pkt_edit is used to edit the original message according to the lookup return result; ​

[0064] (5) According to the table lookup return result, the out port distribution module Out_dmux forwards the edited packet to the buffer module Data_Ram of the corresponding output port.

[0065] Wherein, the transmission structure body defined in the code of the original packet is as follows:

[0066]

[0067] S20, the packet editing processed packet is forwarded to the buffer module of the corresponding output port in the whole packet scheduling processing mode;

[0068] Specifically, one implementation of the above S20 is:

[0069] When the buffer module receives the packet editing processed packet, the packet editing processed packet is written into the original cache space in the buffer module, and the whole packet identifier is stored in the new cache space in the buffer module, the whole packet identifier is used to represent whether the packet editing processed packet has been stored completely, and the whole packet identifier is written into the new cache space after the packet editing processed packet is completely written into the original cache space.

[0070] Wherein, in the scheme of the application, the buffer module Data_Ram can also be expressed as New_Data_fifo, and the New_Data_fifo includes the original cache space Data_fifo and the new cache space Eop_fifo. That is, on the basis of the original cache space Data_fifo, a new cache space Eop_fifo is added. For details, see Figure 8 ; In the scheme of the application, the whole packet identifier (also called eop information) in the new cache space Eop_fifo is used to represent whether a complete packet has been stored in Data_fifo.

[0071] Specifically, the packet editing processed packet is written into the original cache space, and when the eop is valid, the eop information is written into the new cache space Eop_fifo. In this way, when the new cache space Eop_fifo is not empty, it means that there is a complete packet in the original cache space Data_fifo at this time, that is, when the eop information is stored in the new cache space Eop_fifo, it means that there is a complete packet in the original cache space Data_fifo.

[0072] Wherein, eop valid means that the new cache space Eop_fifo is idle and does not store other information.

[0073] Optionally, the width of the new cache space Eop_fifo is 1, and the depth is a value determined based on the bit width and depth of the original cache space Data_fifo.

[0074] Specifically, the parsed and edited packet and the packet identifier can be written through the write interface of the buffer module New_data_fifo.

[0075] As an example, the write interface signal is specifically implemented as follows:

[0076] New_data_fifo.full = Data_fifo.full | Eop_fifo.full

[0077] Data_fifo.wr = New_data_fifo.wr

[0078] Eop_fifo.wr = New_data_fifo.wr & New_data_fifo.eop

[0079] S30, output the parsed and edited packet from the corresponding output port through the buffer module.

[0080] Optionally, the packet identifier is read from the buffer module after the parsed and edited packet, and in the step S30, outputting the parsed and edited packet from the corresponding output port through the buffer module comprises:

[0081] When the packet identifier is read in the process of reading the parsed and edited packet from the original cache space of the buffer module, the parsed and edited packet is output from the corresponding output port.

[0082] When the packet identifier is read, it indicates that the parsed and edited packet has been completely read from the buffer module.

[0083] Specifically, the parsed and edited packet can be read through the read interface of the buffer module New_data_fifo. For the read interface of the buffer module New_data_fifo, only when Data_fifo and Eop_fifo are non-empty at the same time, it indicates that New_data_fifo is non-empty, and the data (parsed and edited packet) can be read. In the process of reading New_data_fifo, data is first read directly from Data_fifo, and when the last beat of data of a frame of packet is read, one beat of eop information is read from Eop_fifo, indicating that a complete packet is read.

[0084] As an example, the specific implementation of the read interface signal is as follows:

[0085] New_data_fifo.empty=Data_fifo.empty|Eop_fifo.empty

[0086] Data_fifo.rd=New_data_fifo.rd

[0087] Eop_fifo.rd=New_data_fifo.rd&Data_fifo.eop

[0088] Through the above processing, whole packet scheduling can be achieved. With whole packet scheduling added, Figure 3 In the same environment, the bus scheduling situation becomes... Figure 9 As shown, at this point, a complete message is processed continuously, and there are no more idle waiting situations on the bus, greatly improving bus utilization.

[0089] During the process of reading, parsing, and editing the message through the read interface, you can also refer to Figure 6 The output processing flow shown on the right involves selecting one of the N channels for data reading from the N channels. After selecting the channel, the parsed and edited message is read from the buffer module based on the selected channel. During the reading of a parsed and edited message frame, it is determined whether it is the end of a message frame. If so, the channel is reselected to read the next message frame. If not, the reading of the parsed and edited message continues until the end of the parsed and edited message frame is reached.

[0090] Based on the solution in this application, see [link to relevant documentation]. Figure 7 As shown, for Figure 2 Under the same forwarding conditions, ports 0, 1, and 2 can process data in parallel, eliminating the "header block problem," reducing packet forwarding latency, and improving the overall forwarding efficiency of the chip. Figure 7 The message lookup and forwarding shown refers to the processing procedure of each switching module, and is related to... Figure 2 The message scheduling and forwarding process shown is the same, except that... Figure 2 The message received from each input port is processed one by one. Figure 7 The message received from each input interface is processed in parallel.

[0091] Based on the system and method described above, the system and method involved in the scheme of the present application can be implemented in hardware, such as in a chip, which can be a network card chip or a switching chip, and the network card chip or the switching chip can be an FPGA (Field Programmable Gate Array) chip.

[0092] Based on the same principle of the packet forwarding method provided in the scheme of the present application, a packet forwarding device can also be provided. The packet forwarding device of the embodiments of the present application can execute the packet forwarding method provided by the embodiments of the present application, and the implementation principle is similar. The actions performed by each module and unit in the packet forwarding device in the embodiments of the present application are corresponding to the steps in the packet forwarding method in the embodiments of the present application. For the detailed function description of each module of the packet forwarding device, please refer to the description of the corresponding packet forwarding method in the foregoing description, which will not be described here.

[0093] The packet forwarding device can be a computer program (including program code) running in a computer device, for example, the packet forwarding device is an application software. The device can be used to execute the corresponding steps in the method provided by the embodiments of the present application.

[0094] In some embodiments, the packet forwarding device provided by the embodiments of the present application can be implemented in a combination of software and hardware. As an example, the packet forwarding device provided by the embodiments of the present application can be a processor in the form of a hardware decoding processor, which is programmed to execute the packet forwarding method provided by the embodiments of the present application. For example, the processor in the form of a hardware decoding processor can use one or more ASICs (Application Specific Integrated Circuits), DSPs, PLDs (Programmable Logic Devices), CPLDs (Complex Programmable Logic Devices), FPGAs (Field-Programmable Gate Arrays) or other electronic elements.

[0095] The modules described in the embodiments of the present application can be implemented in the form of software or hardware. In some cases, the name of the module does not constitute a limitation on the module itself.

[0096] Based on the same principles as the method shown in the embodiments of the present application, an electronic device is also provided in the embodiments of the present application, which can include but is not limited to: a processor and a memory; the memory is configured to store a computer program; and the processor is configured to execute the method shown in any of the embodiments of the present application by invoking the computer program.

[0097] In an optional embodiment, an electronic device is provided, which can include but is not limited to: a processor and a memory; the memory is configured to store a computer program; and the processor is configured to execute the method shown in any of the embodiments of the present application by invoking the computer program. Figure 10 As shown in the above, Figure 10 The electronic device 4000 shown in the above includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, through a bus 4002. Optionally, the electronic device 4000 can also include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception, etc. It should be noted that the transceiver 4004 is not limited to one in actual application, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0098] The processor 4001 can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure. The processor 4001 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0099] The bus 4002 can include a path for transmitting information between the above-mentioned components. The bus 4002 can be a PCI (Peripheral Component Interconnect, peripheral component interconnect) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 10 In the above, only one thick line is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0100] The memory 4003 can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0101] The memory 4003 is used to store application program codes (computer programs) for implementing the solutions of the present application, and is controlled by the processor 4001 to perform. The processor 4001 is used to execute the application program codes stored in the memory 4003 to realize the content shown in the foregoing method embodiments.

[0102] The electronic device can also be a terminal device, Figure 10 The electronic device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present application.

[0103] The embodiments of the present application provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program runs on a computer, the computer can execute the corresponding content in the foregoing method embodiments.

[0104] According to another aspect of the present application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute the method provided in the various implementation manners of the above embodiments.

[0105] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0106] It should be understood that the flowchart and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of various embodiments of the present application. In this regard, each block in the flowchart and block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or combinations of hardware and software.

[0107] The computer readable storage medium of the present application can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, the computer readable storage medium can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0108] The computer readable storage medium described above bears one or more programs, when the one or more programs are executed by the electronic device, cause the electronic device to execute the method shown in the above embodiment.

[0109] The above description is merely the preferred embodiments of the present application and the explanation of the applied technical principles. It should be understood by those skilled in the art that the disclosed range of the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combinations of the above technical features or their equivalent features without departing from the disclosed concept. For example, the technical solutions formed by the mutual replacement of the above features and the technical features disclosed in the present application (but not limited to) having similar functions.

Claims

1. A distributed matrix switching system, characterized in that, It includes multiple input ports and multiple output ports. Each input port is connected to a switching module, and the number of input ports is the same as the number of output ports. Each output port is connected to a buffer module, and each switching module is connected to all buffer modules. Each switching module is used to perform packet scheduling and forwarding on the original packets received by the corresponding input port, so that the packets processed by packet scheduling and forwarding can be output from any one of the output ports. Each input port and each output port are independent of each other. For each of the buffer modules, the buffer module includes an original buffer space and an additional buffer space. The original buffer space is used to store the packets after message scheduling and forwarding processing. The whole packet identifier is used to indicate whether the packets after message scheduling and forwarding processing have been completely stored. After the packets after message scheduling and forwarding processing are completely written into the original buffer space, the whole packet identifier is written into the additional buffer space. Each of the aforementioned switching modules is connected to all buffer modules via a fully cross-connection method; The width of the newly added cache space is 1, and the depth is determined based on the bit width and depth of the original cache space.

2. A message forwarding method, characterized in that, The method of using the distributed matrix switching system according to claim 1 includes: The original message can be received and parsed and edited through any one of the multiple input ports; The parsed and edited messages are forwarded to the corresponding output port buffer module using a whole packet scheduling method. The buffer module outputs the parsed and edited message from the corresponding output port. The method of forwarding the parsed and edited message to the corresponding output port buffer module using the whole packet scheduling processing includes: When the buffer module receives the parsed and edited message, it writes the parsed and edited message into the original cache space in the buffer module and stores the whole packet identifier into the newly added cache space in the buffer module. The whole packet identifier is used to indicate whether the parsed and edited message has been completely stored. The whole packet identifier is written into the newly added cache space after the parsed and edited message has been completely written into the original cache space. The complete packet identifier is read from the buffer module after the parsed and edited message, and the step of outputting the parsed and edited message from the corresponding output port through the buffer module includes: During the process of reading the parsed and edited message from the original cache space of the buffer module, when the whole packet identifier is read, the parsed and edited message is output from the corresponding output port.

3. A chip, characterized in that, Includes the distributed matrix switching system described in claim 1.

4. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method of claim 2.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of claim 2.

Images