Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The embodiment of the present application provides a semiconductor device and a manufacturing method thereof, and an electronic device. It belongs to the field of semiconductor technology. In the manufacturing method, by forming a first hole segment and a second hole segment of different sizes and alternating distribution when making a first via hole, the sacrificial layer surrounding the hole wall is filled in the first hole segment with a larger hole diameter and patterned to form a ring-shaped sacrificial structure with a second via hole, and then the semiconductor layers of the first hole segment and the second hole segment are formed in the second via hole. A hole is opened in the area between adjacent combined film layers to expose the sacrificial structure of the first hole segment, and the sacrificial structure is etched away to expose the semiconductor layer of the parasitic MOS located in the first hole segment. Since the conductive layer and semiconductor layer of the second hole segment do not have a sacrificial structure, removing the semiconductor layer of the first hole segment does not affect the semiconductor layer of the first hole segment. The embodiment of the present application can eliminate parasitic MOS and the manufacturing process is less difficult and easy to implement.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of semiconductor technology, the number of components integrated in semiconductor devices is increasing.

[0003] For example, in the manufacturing process of three-dimensional stacked semiconductor devices, in order to form transistors, it is necessary to sequentially form a semiconductor material layer, a dielectric material layer, and a conductive material layer covering the sidewalls of the vias, and then form independent transistors between adjacent layers by etching the semiconductor material layers between adjacent layers, thereby eliminating parasitic MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Summary of the Invention

[0004] In view of the shortcomings of the existing methods, this application proposes a semiconductor device and a manufacturing method thereof, and an electronic device, at least to improve the deficiencies in the background technology.

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] A plurality of composite film layers are formed on one side of a substrate; the plurality of composite film layers are periodically spaced in different regions of the substrate, and the composite film layers in different regions correspond to different storage cells; each of the composite film layers includes a plurality of alternately stacked first dielectric layers and first conductive layers, and a first via; the hole in the first via that passes through the first dielectric layer is a first hole segment, and the hole that passes through the first conductive layer is a second hole segment; trenches are formed between adjacent composite film layers, and the trenches are filled with a third dielectric layer;

[0007] filling a sacrificial layer in the first via hole, wherein the material of the sacrificial layer is different from the material of the first dielectric layer;

[0008] The sacrificial layer is patterned to form a second via hole coaxial with the first via hole, so that the remaining sacrificial layer in the first hole segment forms a ring-shaped sacrificial structure and the sacrificial layer in the second hole segment is completely removed; along a direction parallel to the substrate, the size of the second hole segment is smaller than that of the first hole segment;

[0009] forming a semiconductor layer, a gate dielectric layer, and a word line covering the inner wall of the second via hole in sequence in the second via hole, wherein the semiconductor layer in the corresponding area of ​​the first dielectric layer is surrounded by the annular sacrificial structure;

[0010] Opening a via hole between adjacent combined film layers to expose a portion of the sacrificial structure, and removing the annular sacrificial structure to expose the annular semiconductor layer located in a corresponding area of ​​the first dielectric layer;

[0011] The semiconductor layer exposed between the adjacent combined film layers is removed.

[0012] In some embodiments of the present application, along a direction parallel to the substrate, a diameter of a second hole segment of the first via hole penetrating the first conductive layer is smaller than a target diameter;

[0013] The aperture of the second via hole is consistent with the target aperture, and the target aperture can cause the first conductive layer to be divided into two parts.

[0014] In some embodiments of the present application, a plurality of combined film layers are formed on one side of a substrate, including:

[0015] forming a plurality of initial composite film layers on one side of the substrate, wherein the initial composite film layers include a first initial dielectric layer and a first initial conductive layer that are overlapped;

[0016] forming an initial via hole on the initial combined film layer, penetrating the initial combined film layer;

[0017] Using the first initial conductive layer of the initial via hole as a mask, the first initial dielectric layer is laterally etched to form the first hole segment in the first dielectric layer, wherein the aperture of the first hole segment is larger than the aperture of the initial via hole, so that a laterally extending annular groove is formed between adjacent first initial conductive layers;

[0018] The first initial conductive layer is etched in the initial via hole to form a second hole segment in the first conductive layer, so that the first initial conductive layer is divided into two parts.

[0019] In some embodiments of the present application, the material of the third dielectric layer is the same as that of the first dielectric layer.

[0020] In some embodiments of the present application, a via hole is opened between adjacent combined film layers to expose a portion of the sacrificial structure, and the annular sacrificial structure is removed to expose the annular semiconductor layer located in a region corresponding to the first dielectric layer, including:

[0021] A via hole is opened in the third dielectric layer between adjacent combined film layers to expose a portion of the sacrificial structure in the corresponding area of ​​each first dielectric layer. The annular sacrificial structure in the corresponding area of ​​each first dielectric layer is removed by wet etching in the via hole to expose the annular semiconductor layer in each area surrounded by the first dielectric layer.

[0022] In some embodiments of the present application, after removing the annular semiconductor layer exposed between adjacent combined film layers, the method further includes:

[0023] The via holes between adjacent combined film layers are filled with a second dielectric layer; the material of the second dielectric layer is the same as that of the first dielectric layer.

[0024] In some embodiments of the present application, the following are included:

[0025] The material of the sacrificial layer includes silicon germanium; and the first dielectric layer is an oxide containing silicon.

[0026] In some embodiments of the present application, along a direction parallel to the substrate, the aperture of the initial via hole penetrating the initial combined film layer is 70% to 90% of the target aperture;

[0027] The aperture of the first hole section of the first via hole that passes through the first dielectric layer is 110% to 130% of the target aperture.

[0028] In some embodiments of the present application, a semiconductor device is provided, which is manufactured based on the above-mentioned manufacturing method.

[0029] In some embodiments of the present application, the following are included:

[0030] Multiple memory cell arrays, with memory cells at the same position periodically stacked and distributed;

[0031] Each memory cell comprises a gate extending longitudinally, a gate insulating layer and a semiconductor layer surrounding the sidewall of the gate in sequence, a source electrode and a drain electrode surrounding the semiconductor layer and located in the same layer, and a semiconductor layer between the source electrode and the drain electrode;

[0032] The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells at different layers are isolated by a first dielectric layer;

[0033] The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells in the same layer are isolated by a first dielectric layer;

[0034] The first dielectric layer contacts the semiconductor layer between the source electrode and the drain electrode of each memory cell, and contacts the gate insulating layer between adjacent memory cells.

[0035] In some embodiments of the present application, the semiconductor layer only includes a film layer extending in a direction perpendicular to the substrate, and a first dielectric layer is filled between different adjacent semiconductor layers, and the first dielectric layer contacts the outer sidewalls and ends of the semiconductor layer.

[0036] In some embodiments of the present application, the semiconductor layer and the gate insulating layer are located in the second via hole;

[0037] The apertures of the semiconductor layer in each region in the vertical direction are the same;

[0038] The apertures of the gate insulating layer in each region in the vertical direction are the same.

[0039] An embodiment of the present application provides an electronic device, including: the semiconductor device described in any of the above embodiments.

[0040] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0041] In the manufacturing method, when making the first via hole, first and second hole segments of different sizes and alternating distribution are formed. After the first hole segment with the larger hole diameter is filled with a sacrificial layer surrounding the hole wall and patterned to form a ring-shaped sacrificial structure with the second via hole, the semiconductor layers of the first and second hole segments are formed in the second via hole. A hole is opened in the area between adjacent combined film layers to expose the sacrificial structure of the first hole segment. The sacrificial structure is etched away to expose the semiconductor layer of the parasitic MOS located in the first hole segment. Because the conductive layer and semiconductor layer of the second hole segment do not have a sacrificial structure, removing the semiconductor layer of the first hole segment does not affect the semiconductor layer of the first hole segment. The embodiments of the present application can eliminate parasitic MOS and the manufacturing process is relatively simple and easy to implement.

[0042] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0044] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0045] Figure 2 A schematic flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] Figure 3 A schematic top view of a film structure after a combined film layer is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0047] Figure 4 、 Figure 5 They are Figure 3 Schematic diagram of the cross-section of the membrane layer at aa' and bb' in the membrane layer structure shown;

[0048] Figure 6 A schematic top view of a film structure after an initial via hole is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0049] Figure 7 、 Figure 8 They are Figure 6 Schematic diagram of the cross-section of the membrane layer at aa' and bb' in the membrane layer structure shown;

[0050] Figure 9 A schematic diagram of a cross-sectional film layer at point aa' after forming a first dielectric layer and a first hole segment in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0051] Figure 10 A schematic diagram of a cross-sectional film layer at point bb' after forming a first dielectric layer and a first hole segment in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0052] Figure 11 A schematic top view of a film structure after forming a first conductive layer and a second hole segment in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0053] Figure 12 、 Figure 13 They are Figure 11 Schematic diagram of the cross-section of the membrane layer at aa' and bb' in the membrane layer structure shown;

[0054] Figure 14 A schematic top view of a film structure after a sacrificial layer is filled in a first via hole in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0055] Figure 15 、 Figure 16 They are Figure 14 Schematic diagram of the cross-section of the membrane layer at aa' and bb' in the membrane layer structure shown;

[0056] Figure 17 A schematic diagram of a cross-sectional film layer at point aa' after forming a second via hole in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0057] Figure 18 A schematic diagram of a cross-sectional film layer at point bb' after forming a second via hole in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0058] Figure 19 A schematic top view of a film structure after sequentially forming a semiconductor layer covering the inner wall of a second via hole, a gate dielectric layer, and a word line in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0059] Figure 20 A schematic top view of a film structure between a semiconductor layer, a gate dielectric layer, and a word line in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0060] Figure 21 、 Figure 22 They are Figure 19 Schematic diagram of the cross-section of the membrane layer at aa' and bb' in the membrane layer structure shown;

[0061] Figure 23 A schematic diagram of a cross-sectional film layer at point aa' after removing the sacrificial structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0062] Figure 24 A schematic diagram of a cross-sectional film layer at point bb' after removing a sacrificial structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0063] Figure 25 A schematic diagram of a cross-sectional film layer at point cc' after removing a sacrificial structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0064] Figure 26 A schematic diagram of a cross-sectional film layer at point aa' after forming a transistor in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0065] Figure 27 for Figure 26 A partial enlarged view of the transistor 10;

[0066] Figure 28 This is a schematic diagram of a cross-sectional film layer at point bb' after forming a semiconductor structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0067] Figure 29 A schematic diagram of a cross-sectional film layer at point aa' after the second dielectric layer is fully filled in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0068] Figure 30 A schematic diagram of a cross-sectional film layer at point bb' after the second dielectric layer is fully filled in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0069] Figure 31 This is a schematic diagram of a cross-sectional film layer at point cc' after the second dielectric layer is fully filled in a method for manufacturing a semiconductor device provided by an embodiment of the present application.

[0070] Description of reference numerals:

[0071] 100-substrate; 101-first dielectric layer; 102-first conductive layer;

[0072] 103-first via hole; 1031-first hole section; 1032-second hole section;

[0073] 104-sacrificial layer; 1041-second via hole; 1042-sacrificial structure;

[0074] 1051- semiconductor layer;

[0075] 106-first initial dielectric layer; 1061-first transition dielectric layer;

[0076] 107-first initial conductive layer; 1071-first transition conductive layer;

[0077] 108 - initial via hole; 109 - third dielectric layer; 1091 - via hole; 110 - second dielectric layer;

[0078] 111 - protective layer; 112 - fourth dielectric layer;

[0079] 10-transistor; 11-gate; 12-gate dielectric layer; 13-semiconductor structure;

[0080] 20 - bit line; 30 - word line; 40 - electrode structure. DETAILED DESCRIPTION

[0081] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0082] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may include plural forms as well.

[0083] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0084] Generally, the steps for making a transistor in the related art include: sequentially forming a semiconductor material layer, a dielectric material layer, and a conductive material layer covering the sidewalls of the via in the via, and then etching the semiconductor material layer between adjacent layers from the inside of the via outward to form independent transistors between adjacent layers, thereby removing the parasitic MOS between the adjacent layers. Among them, the method of removing parasitic MOS in the via, where the semiconductor material layer contacts the material forming the sidewalls of the first via, may cause incomplete etching when etching the semiconductor material layer, resulting in residual semiconductor material layer, and further forming parasitic MOS. If the semiconductor material layer to be etched is to be completely removed, a more precise process is required, which is costly and difficult to implement.

[0085] The semiconductor device, manufacturing method thereof, and electronic device provided in this application are intended to solve the above technical problems of the prior art.

[0086] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0087] The present invention provides a method for manufacturing a semiconductor device. The flowchart of the method is shown in FIG. Figure 1 As shown, the method includes steps S101 to S106.

[0088] S101 , forming a plurality of composite film layers on one side of the substrate 100 .

[0089] Multiple combined film layers are periodically distributed in different regions of the substrate 100, and the combined film layers in different regions correspond to different storage units; each combined film layer includes multiple stacked storage units, and the storage units between different combined film layers are distributed in an array.

[0090] Each composite film layer includes multiple alternating layers of first dielectric layers 101 and first conductive layers 102, as well as first vias 103. In the first vias 103, the hole that passes through the first dielectric layer 101 is a first hole segment 1031, and the hole that passes through the first conductive layer 102 is a second hole segment 1032. There are trenches between adjacent composite film layers, and the trenches are filled with a third dielectric layer 109.

[0091] In this embodiment, each combined film layer corresponds to one or two memory cells sequentially distributed in the row direction; different combined film layers are separated by trenches in the column direction and insulated by the third dielectric layer 109 in the trenches.

[0092] S102 , filling the first via hole 103 with a sacrificial layer 104 . The material of the sacrificial layer 104 is different from that of the first dielectric layer 101 .

[0093] S103, patterning the sacrificial layer 104 to form a second via 1041 coaxial with the first via 103, so that the remaining sacrificial layer 104 in the first hole segment 1031 forms a ring-shaped sacrificial structure 1042, and the sacrificial layer 104 in the second hole segment 1032 is completely removed; along the direction parallel to the substrate 100, the size of the second hole segment 1032 is smaller than the size of the first hole segment 1031.

[0094] The size of the hole or hole segment mentioned in the embodiments of the present application is the pore diameter. The size or pore diameter can be the average of the diameters at multiple positions, or the maximum or minimum value of the pore diameter.

[0095] S104 , a semiconductor layer 1051 , a gate dielectric layer 12 , and a word line 30 are sequentially formed in the second via hole 1041 to cover the inner wall of the second via hole 1041 . The semiconductor layer 1051 in the corresponding area of ​​the first dielectric layer 101 is surrounded by the sacrificial structure 1042 .

[0096] Optionally, in the embodiment of the present application, the sacrificial structure 1042 is annular; the material of the semiconductor layer 1051 includes a metal oxide semiconductor material or a silicon-containing material.

[0097] Optionally, the metal oxide semiconductor material includes IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), IWO (Indium Wolfram Oxide, tungsten-doped indium oxide), InGaO (indium gallium oxide), ZnO (zinc oxide), InO (indium oxide), InO (indium oxide), InWO (indium tungsten oxide), SnO (tin oxide), TiO (titanium oxide), InSnO (indium tin oxide), ZnON (nitrogen-doped zinc oxide), MgZnO (magnesium zinc oxide), InZnO (indium zinc oxide), InGaZnO (indium gallium zinc oxide), ZrInZnO (zirconium indium zinc oxide), HfInZnO (hafnium indium zinc oxide), SnInZnO (tin indium zinc oxide), AlZnO (aluminum zinc oxide), AlSnInZnO (aluminum tin indium zinc oxide), SiInZnO (silicon indium zinc oxide), ZnSnO (zinc tin oxide), AlZnSnO (aluminum zinc tin oxide), GaZnSnO (gallium zinc tin oxide), ZrZnSnO (zirconium zinc tin oxide) and InGaSiO (indium gallium silicon oxide).

[0098] S105 , opening a via hole 1091 between adjacent combined film layers to expose a portion of the sacrificial structure 1042 , and removing the entire sacrificial structure 1042 to expose all of the semiconductor layer 1051 located in a corresponding area of ​​the first dielectric layer 101 .

[0099] S106 , removing the annular semiconductor layer 1051 exposed between adjacent combined film layers.

[0100] In the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first via 103 is first formed in a composite film layer, such that a first via segment 1031 is formed in the first dielectric layer 101 of the composite film layer, and a second via segment 1032 is formed in the first conductive layer 102. The first via 103 is then filled and patterned to form a sacrificial layer 104 surrounding the via wall. Because the size of the first via segment 1031 is larger than that of the second via segment 1032, the sacrificial layer 104 is patterned to form a second via 1041, completely removing the sacrificial layer 104 within the second via segment 1032 to expose the side surface of the first conductive layer 102. A portion of the sacrificial layer 104 can remain within the first via segment 1031, forming a ring-shaped sacrificial structure 1042. After a semiconductor layer 1051 is formed within the second via 1041, the sacrificial structure 1042 can cover the semiconductor layer 1051 in the corresponding area of ​​the first dielectric layer 101. A hole is opened outside the first via 103 and in the area between adjacent combined film layers to expose the sacrificial structure 1042. The sacrificial structure 1042 is etched away to expose the semiconductor layer of the parasitic MOS located within the first hole segment. Because there is no sacrificial structure in the corresponding area of ​​the first conductive layer, the removal of the sacrificial structure 1042 in the corresponding area of ​​the first dielectric layer 101 does not affect the semiconductor layer 1051 in the corresponding area of ​​the first conductive layer 102, thereby preserving the semiconductor layer 1051 in the corresponding area of ​​the first conductive layer 102. The present embodiment can effectively eliminate parasitic transistors. Moreover, the manufacturing method provided by this embodiment is relatively simple to manufacture and easy to implement.

[0101] It can be understood that in the embodiment of the present application, the area corresponding to the first dielectric layer 101 refers to the area of ​​the film layer where the first dielectric layer 101 is located in the first direction, and the area corresponding to the first conductive layer 102 refers to the area of ​​the film layer where the first conductive layer 102 is located in the first direction.

[0102] Optionally, the first conductive layer 102 has a second hole segment 1032, wherein the second hole segment 1032 can cut off the first conductive layer 102, so that the first conductive layer 102 is disconnected to form a subsequent electrode structure 40 (such as an inner electrode or source electrode of a capacitor) and a bit line 20 (an integrated structure of a drain electrode and a bit line).

[0103] In some possible implementations, along a direction parallel to substrate 100, the diameter of second hole segment 1032 in first via 103 that passes through first conductive layer 102 is smaller than the target diameter; the diameter of second via 1041 is consistent with the target diameter. The target diameter is sufficient to separate first conductive layer 102 into two parts, while second hole segment 1032 in first via 103 that passes through first conductive layer 102 cannot separate first conductive layer 102 into two parts.

[0104] In this embodiment, the size of the second hole segment 1032 can be smaller than the size of the second via 1041, so that when the second via 1041 is manufactured, the inner wall of the second hole segment 1032 (i.e., the side surface at the cutoff point of the first conductive layer 102) can be exposed in the second via 1041, thereby ensuring that when the transistor 10 is subsequently manufactured in the second via 1041, the semiconductor layer 1051 can be effectively connected to the first conductive layer 102.

[0105] Optionally, in step S101, a plurality of composite film layers corresponding to different memory cells are formed on one side of the substrate 100. Each composite film layer includes a plurality of alternately stacked first dielectric layers 101 and first conductive layers 102, and a first via 103. The hole penetrating the first dielectric layer 101 is a first via segment 1031, and the hole penetrating the first conductive layer 102 is a second via segment 1032, including:

[0106] A plurality of initial composite film layers are formed on one side of the substrate 100 . The initial composite film layers include a first initial dielectric layer 106 and a first initial conductive layer 107 that are overlapped.

[0107] An initial via hole 108 is formed on the initial combined film layer and penetrates the initial combined film layer.

[0108] Using the first initial conductive layer 107 of the initial via 108 as a mask, the first initial dielectric layer 106 is laterally etched to form a first hole segment 1031 in the first dielectric layer 101. The aperture of the first hole segment 1031 is larger than the aperture of the initial via 108, so that a laterally extending annular groove is formed between adjacent first initial conductive layers 107.

[0109] The first initial conductive layer 107 is etched in the initial via hole 108 to form a second hole segment 1032 in the first conductive layer 102 , so that the first initial conductive layer 107 is divided into two parts.

[0110] Optionally, after step S101, the following steps may be further performed:

[0111] A third dielectric layer 109 is formed between adjacent initial combined film layers on one side of the substrate 100 . The material of the third dielectric layer 109 is the same as that of the first dielectric layer 101 .

[0112] Optionally, in the above step S105, a via hole 1091 is opened between adjacent combined film layers to expose part of the sacrificial structure 1042, and the sacrificial structure 1042 is removed to expose the semiconductor layer 1051 located in the corresponding area of ​​the first dielectric layer 101, including: opening a via hole 1091 in the third dielectric layer 109 between adjacent combined film layers to expose part of the sacrificial structure 1042 in the corresponding area of ​​each first dielectric layer 101, and removing the sacrificial structure 1042 in the corresponding area of ​​each first dielectric layer 101 by wet etching in the via hole 1091 to expose the semiconductor layer 1051 in each area surrounded by the first dielectric layer 101.

[0113] Optionally, after the above step S106 , the method further includes: filling the via holes 1091 between adjacent combined film layers with a second dielectric layer 110 , where the material of the second dielectric layer 110 is the same as that of the first dielectric layer 101 .

[0114] Optionally, the material of the sacrificial layer 104 includes silicon germanium; the material of the first conductive layer 102 includes metal; and the first dielectric layer 101 includes silicon oxide.

[0115] Optionally, along a direction parallel to the substrate 100 , the aperture of the initial via hole 108 penetrating the initial combined film layer is 70% to 90% of the target aperture; the aperture of the first hole segment 1031 in the first via hole 103 penetrating the first dielectric layer 101 is 110% to 130% of the target aperture.

[0116] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device. The flowchart of the manufacturing method is as follows: Figure 2 As shown, the method includes steps S201 to S211.

[0117] S201 , forming a plurality of initial composite film layers on one side of the substrate 100 , the initial composite film layers including a first initial dielectric layer 106 and a first initial conductive layer 107 that are overlapped.

[0118] like Figure 4-Figure 5 As shown, the first initial dielectric layer 106 and the first initial conductive layer 107 are stacked on the substrate 100 in the third direction.

[0119] It is understandable that Figure 4 and Figure 5 They are Figure 3 For the convenience of description, Figure 3 In fact, it is a top view after removing the protective layer 111, or in other words, Figure 3 It is a top view of the protective layer 111 , the uppermost fourth dielectric layer 112 , and the first initial dielectric layer 106 after being rendered transparent.

[0120] Optionally, in an embodiment of the present application, after the above step S201 , the process further includes: filling a third dielectric layer 109 between adjacent combined film layers, where the material of the third dielectric layer 109 is the same as that of the first dielectric layer 101 .

[0121] In this embodiment, a third dielectric layer 109 is filled between each memory cell to isolate each memory cell. The material of the third dielectric layer 109 is the same as that of the first dielectric layer 101, so that a larger first hole segment 1031 can be subsequently etched through a single etching process.

[0122] Optionally, in an embodiment of the present application, before the above step S201 , the process further includes: forming a protective layer 111 on a side of the first initial dielectric layer 106 located at the topmost layer in the combined film layer away from the substrate 100 based on a deposition process.

[0123] Optionally, the fourth dielectric layer 112 is provided on the same layer as the first initial dielectric layer 106, and a portion of the first initial conductive layer 107 will later form an electrode structure 40 of a capacitor (see Figure 12 ), the fourth dielectric layer 112 is disposed between the capacitors to isolate the capacitors that overlap in the third direction, which is similar to the prior art and will not be described in detail herein.

[0124] S202, forming an initial via hole 108 penetrating the initial combined film layer on the initial combined film layer. The film layer structure obtained after step S202 is shown in FIG. Figure 6-Figure 8 shown.

[0125] Optionally, the initial vias 108 penetrate the initial combined film layer, the initial vias 108 are all closed, all areas of the hole walls of the initial vias 108 on the first initial dielectric layer 106 are the first initial dielectric layer 106 body, and all areas of the hole walls of the initial vias 108 on the first initial conductive layer 107 are the first initial conductive layer 107 body.

[0126] Optionally, it can be assumed that the size of the via ultimately required to form the transistor 10 in the embodiment of the present application is the design size, and the size of the initial via 108 is smaller than the design size. For example, the size of the initial via 108 is 70% to 90% (including the endpoint values) of the design size, for example, 80%.

[0127] S203, using the first initial conductive layer 107 of the initial via 108 as a mask, the first initial dielectric layer 106 is laterally etched to form a first hole segment 1031 in the first dielectric layer 101. The aperture of the first hole segment 1031 is larger than the aperture of the initial via 108, so that a laterally extending groove is formed between adjacent first initial conductive layers 107. The film structure after this step is shown in FIG. Figure 9 and Figure 10 shown.

[0128] In this step, the first initial dielectric layer 106 and the first initial conductive layer 107 are made of different materials. The first initial conductive layer 107 can be used as a mask to only laterally etch the first initial dielectric layer 106, so that the initial via hole 108 in the first initial dielectric layer 106 forms the first hole segment 1031, and the first dielectric layer 101 is formed.

[0129] The mask described in the embodiment of the present application can be understood as an etching stop.

[0130] Optionally, the size of the first hole segment 1031 is larger than the design size. In some embodiments, the size of the first hole segment 1031 can be between 110% and 130% (including the endpoint values) of the size of the second via hole, for example, 120%, to reserve accommodation space for the subsequent sacrificial structure 1042.

[0131] S204, etching the first initial conductive layer 107 in the initial via hole 108 to form a second hole segment in the first conductive layer 102, so that the first initial conductive layer 107 is divided into two parts. The schematic diagram of the film structure after this step is as follows Figure 11-13 shown.

[0132] In this step, if Figure 12 As shown, since the first initial dielectric layer 106 has been etched, the first initial conductive layer 107 is not blocked by the first initial dielectric layer 106 in the longitudinal direction. Therefore, the first initial conductive layer 107 can be etched in the longitudinal direction, so that the first initial conductive layer 107 is cut into two parts by the formed second hole segment 1032, forming the electrode structure 40 and the bit line 20 distributed in the same layer, as shown in FIG. Figure 13 As shown, the first initial conductive layer 107 no longer exists on the bb' cross section, that is, the first initial conductive layer 107 is disconnected.

[0133] It is understood that the size of the second hole segment 1032 is larger than that of the initial via 108. The initial via 108 is closed, and its hole wall is completely located on the first initial conductive layer 107. The first initial conductive layer 107 is not interrupted by the initial via 108. After etching the first initial conductive layer 107, the size of the initial via 108 gradually increases to form the second hole segment 1032. The length or width of the first initial conductive layer 107 in the first direction or the second direction is limited. Ultimately, the first initial conductive layer 107 is interrupted by the second hole segment 1032 to form an independent electrode structure 40 and bit line 20.

[0134] Optionally, in the above steps, the second hole segment 1032 may be formed by laterally etching the first initial conductive layer 107 , which depends on the actual manufacturing process.

[0135] S205, filling the first via hole 103 with a sacrificial layer 104 made of a material different from the first dielectric layer. The film structure after step S205 is shown in FIG. Figure 14-16 shown.

[0136] Alternatively, the sacrificial layer 104 may be made of polysilicon, such as germanium-doped polysilicon, such as silicon germanium. The material of the first conductive layer 102 may include a conductive layer and an isolation layer, such as a stack of tungsten and titanium nitride, or a stack of copper and TiN. Based on this, by using an etching material with a suitable etching selectivity, the sacrificial layer 104 can be etched without affecting the first conductive layer 102.

[0137] In this step, see Figure 15 and Figure 16 The sacrificial layer 104 completely fills the first hole section 1031 and the second hole section 1032 of the first via hole 103 .

[0138] S206, patterning the sacrificial layer 104 to form a second via hole 1041 coaxial with the first via hole 103, so that the remaining sacrificial layer 104 in the first hole section 1031 forms a ring-shaped sacrificial structure 1042, and the sacrificial layer 104 in the second hole section 1032 is completely removed. Along the direction parallel to the substrate 100, the size of the second hole section 1032 is smaller than that of the first hole section 1031. The film structure after step S206 is shown in FIG. Figure 17-18 shown.

[0139] In this step, refer to Figure 17 The second via 1041 has a designed size (corresponding to the target aperture described in this application). That is, the sidewalls of the second via 1041 form a via hole that forms the semiconductor layer, gate insulation layer, and gate of the transistor 10. The second via 1041 is coaxial with the first via 103. Because the size of the first via section 1031 is larger than the designed size, a portion of the sacrificial layer 104 is located within the first via section 1031 and outside the second via 1041, and is not etched away and remains, forming a sacrificial structure 1042.

[0140] Alternatively, as Figure 11 As shown, the size of the second hole segment 1032 is consistent with the design size, that is, the size of the second hole segment 1032 is consistent with the size of the second via hole 1041, so that when the second via hole 1041 is formed, the sacrificial layer 104 in the second hole segment 1032 is also just etched away, so that no sacrificial layer 104 remains in the second hole segment 1032.

[0141] Optionally, the size of the second hole segment 1032 is smaller than the design size, that is, the size of the second hole segment 1032 is smaller than the size of the second via 1041, so that when the second via 1041 is formed, the sacrificial layer 104 and part of the second transition conductive layer in the second hole segment 1032 are etched away, so that no sacrificial layer 104 remains in the second hole segment 1032 finally formed.

[0142] S207, a semiconductor layer 1051, a gate dielectric layer 12 and a word line 30 covering the inner wall of the second via hole 1041 are sequentially formed in the second via hole 1041, and the semiconductor layer 1051 in the corresponding area of ​​the first dielectric layer 101 is surrounded by the sacrificial structure 1042. The film structure after step S207 is shown in FIG. Figures 19-22 shown.

[0143] In this step, refer to Figure 21 First, a semiconductor layer 1051 is formed to cover the second via hole 1041. A fifth via hole is formed conformally at the semiconductor layer 1051. Then, a gate dielectric layer 12 is formed in the fifth via hole to cover the inner wall of the fifth via hole. A sixth via hole is formed conformally at the gate dielectric layer 12. Then, the sixth via hole is filled with a conductive material to form a word line 30. Therefore, referring to Figure 20 The semiconductor layer 1051 , the gate dielectric layer 12 and the word line 30 are sequentially arranged in the second via hole 1041 , with the semiconductor layer 1051 located at the outermost side. The periphery of the semiconductor layer 1051 is connected to the electrode structure 40 and the bit line 20 respectively.

[0144] Among them, such as Figure 26 As shown, the word line 30 includes a gate 11 in the third direction. In the first direction, a portion of the word line 30 is located in the second hole segment 1032 and overlaps with the semiconductor structure 13. This portion is the gate 11, and the portion other than the gate 11 serves as an electrical connection.

[0145] S208 , opening a via hole 1091 between adjacent combined film layers to expose a portion of the sacrificial structure 1042 , and removing the sacrificial structure 1042 to expose the semiconductor layer 1051 located in a corresponding region of the first dielectric layer 101 .

[0146] Alternatively, as Figure 3 、 Figure 5 As shown, before the via hole 1091 is formed in the third dielectric layer 109, the third dielectric layer 109 is located between adjacent combined film layers. The third dielectric layer 109 is made of the same material as the first dielectric layer 101 of the combined film layer (or the first initial dielectric layer 106 in the combined initial film layer). Before the via hole 1091 is formed, the third dielectric layer 109 can be made at the same time as the first initial dielectric layer 106 in step S201, playing the role of isolating the electrode structure 40 in the adjacent combined film layers. Then, as needed, after step S207, the via hole 1091 (as shown in FIG. 1 ) is etched on the third dielectric layer 109. Figure 25 shown).

[0147] Optionally, wet etching is used to remove the sacrificial structure 1042 in the via hole 1091, so that the semiconductor layer 1051 located in the first hole section 1031 is spaced apart from the inner wall of the first hole section 1031. The film structure after step S208 is shown in FIG. Figure 23-24 shown.

[0148] Optionally, the via hole 1091 is at least partially connected to the first hole section 1031 accommodating the sacrificial structure 1042, and then the sacrificial structure 1042 in the first hole section 1031 is washed away through the via hole 1091, so that in the first hole section 1031, Figure 23 There is a gap between the semiconductor layer 1051 and the inner wall of the first hole segment 1031 (ie, the first dielectric layer 101 ), so that the outer side of the semiconductor layer 1051 in the first hole segment 1031 is exposed.

[0149] like Figure 25 As shown, the via hole 1091 is opened in the third dielectric layer 109 .

[0150] S209, remove the semiconductor layer 1051 exposed between adjacent combined film layers. The film layer structure after step S210 is shown in FIG. Figure 26-Figure 28 shown.

[0151] Optionally, the exposed semiconductor layer 1051 can be removed by wet etching. The inner and outer sides of the semiconductor layer 1051 in the second hole segment 1032 are respectively contacted by the first conductive layer 102 and the gate dielectric layer 12 and are not exposed, so they are retained to form a semiconductor structure 13. In the first direction, there is no semiconductor layer 1051 between adjacent transistors 10, ensuring that the semiconductor layer 1051 between adjacent transistors 10 is disconnected and no parasitic transistors exist.

[0152] S210, the via holes 1091 between adjacent combined film layers are filled with the second dielectric layer 110, and the material of the second dielectric layer 110 is the same as that of the first dielectric layer 101. The film structure after step S210 is shown in FIG. Figure 29-Figure 31 shown.

[0153] In this step, the sacrificial structure 1042 is removed, leaving some space within the first hole segment 1031. The first hole segment 1031 and the via 1091 are then filled with the second dielectric layer 110 through the via 1091, completing the fabrication of the transistor 10. Furthermore, the material of the second dielectric layer 110 is the same as that of the first dielectric layer 101, both of which have a low dielectric constant, such as silicon oxide, and exhibit good isolation device performance.

[0154] Based on the same inventive concept, an embodiment of the present application provides a semiconductor device, which is obtained based on any of the above-mentioned methods for manufacturing the semiconductor device.

[0155] Optionally, the semiconductor device includes: a plurality of word lines 30, a plurality of bit lines 20 and a multi-layer stacked memory cell. The memory cell includes transistors and capacitors distributed and electrically connected along a first direction parallel to the substrate 100. Figure 19 、 Figure 29 and Figure 31 As shown, the bit lines 20 extend along a second direction parallel to the substrate 100. In the memory cells located in the same layer, the bit lines 20 are electrically connected to the semiconductor structures 13 of the transistors 10 of a column of memory cells arranged along the second direction. The word lines 30 extend along a third direction perpendicular to the substrate 100. The word lines 30 are electrically connected to the gates 11 of the transistors 10 of a group of memory cells stacked along the third direction.

[0156] In the embodiments of the present application, since the semiconductor device is obtained based on any of the above-mentioned semiconductor device manufacturing methods, its principles and technical effects can be referred to in the above-mentioned embodiments and will not be repeated here.

[0157] Optionally, in the embodiment of the present application, the memory cell is a 1T (Transistor) 1C (Capacitor) structure, and the transistor 10 and the capacitor of the same memory cell are arranged in the same layer.

[0158] Optionally, in one embodiment of the present application, reference Figure 20 and Figure 27 The gate dielectric layer 12 and the semiconductor structure 13 of the transistor 10 surround the periphery of the gate 11 in sequence.

[0159] In this embodiment, the gate dielectric layer 12 and the semiconductor structure 13 are both ring-shaped, and the gate 11 can be a solid structure or a ring-shaped structure.

[0160] Alternatively, as Figure 29 As shown, along a first direction, transistor 10 is located between bit line 20 and capacitor 20 .

[0161] An electrode structure 40 of the capacitor extends along a first direction, and the electrode structure 40 is connected to the semiconductor structure 13 of the transistor 10 .

[0162] In this embodiment, the electrode structure 40 and the bit line 20 are formed by the cut-off first conductive layer 102 , and the transistor 10 is formed between the electrode structure 40 and the bit line 20 . The electrode structure 40 serves as an electrode structure 40 of a capacitor and is electrically connected to the semiconductor structure 13 of the transistor 10 .

[0163] In the aforementioned method for manufacturing a semiconductor device, there are at least two first vias 103 in each combined film layer, which can form an electrode structure 40, a bit line 20 and another electrode structure 40 in the first direction. Each electrode structure 40 serves as an electrode structure 40 of a capacitor, and the same layer has two storage units distributed along the first direction.

[0164] Alternatively, as Figure 29As shown, in the memory cells located in the same layer, the semiconductor structures 13 of the transistors 10 of two adjacent columns of memory cells are connected to the same bit line 20 .

[0165] Optionally, in one embodiment of the present application, in the memory cells located in the same layer, each bit line 20 is connected to the semiconductor structures 13 of the field effect transistors of two adjacent columns of memory cells.

[0166] Optionally, in an embodiment of the present application, the semiconductor device is a three-dimensional stacked structure semiconductor device, wherein each layer includes a plurality of memory cells arranged in columns, i.e., the plurality of memory cells are arranged in columns along the second direction. Memory cells whose orthographic projections onto the substrate 100 overlap along the third direction are grouped together.

[0167] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: any semiconductor device provided by the above embodiments.

[0168] Semiconductor devices include:

[0169] Multiple memory cell arrays, with memory cells at the same position periodically stacked and distributed;

[0170] Each memory cell comprises a gate extending longitudinally (perpendicular to the substrate), a gate insulating layer and a semiconductor layer 1051 surrounding the sidewalls of the gate, a source electrode and a drain electrode surrounding the semiconductor layer and located in the same layer, and a semiconductor layer between the source electrode and the drain electrode;

[0171] The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells at different layers are isolated by a first dielectric layer;

[0172] The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells in the same layer are isolated by a first dielectric layer;

[0173] The first dielectric layer contacts the semiconductor layer between the source electrode and the drain electrode of each memory cell, and contacts the gate insulating layer between adjacent memory cells.

[0174] The semiconductor layer only includes a film layer extending in a direction perpendicular to the substrate. A first dielectric layer is filled between different adjacent semiconductor layers. The first dielectric layer is in contact with the outer sidewall and end of the semiconductor layer.

[0175] The semiconductor layer 1051 and the gate insulating layer 12 are located in the second via hole;

[0176] The apertures of the semiconductor layer in each region in the vertical direction are the same;

[0177] The apertures of the gate insulating layer 12 in each region in the vertical direction are the same.

[0178] The same aperture can be understood as the size of the apertures in different regions in the direction perpendicular to the substrate does not exceed the thickness of the semiconductor layer, does not protrude outward or recess inward relative to the semiconductor layer, but extends downward along the approximately vertical hole wall, and no recess or protrusion is formed on the hole wall through further processing.

[0179] In the embodiments of the present application, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be repeated here.

[0180] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0181] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0182] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices include any semiconductor device provided in the above embodiments.

[0183] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0184] In the manufacturing method of the semiconductor device provided in the embodiment of the present application, a portion of the sacrificial layer 104 is retained in the first hole segment 1031 to form a ring-shaped sacrificial structure 1042. After the semiconductor layer 1051 is formed in the second via 1041, the sacrificial structure 1042 can cover the semiconductor layer 1051 in the corresponding area of ​​the first dielectric layer 101. A hole is opened outside the first via 103 and in the area between adjacent combined film layers to expose the sacrificial structure 1042. The sacrificial structure 1042 is etched and removed to expose the semiconductor layer of the parasitic MOS located in the first hole segment. Because there is no sacrificial structure in the corresponding area of ​​the first conductive layer, the removal of the sacrificial structure 1042 in the corresponding area of ​​the first dielectric layer 101 does not affect the semiconductor layer 1051 in the corresponding area of ​​the first conductive layer 102, thereby retaining the semiconductor layer 1051 in the corresponding area of ​​the first conductive layer 102. The embodiment of the present application can effectively eliminate parasitic transistors. Moreover, the manufacturing method provided by this embodiment has a relatively low manufacturing process difficulty and is easy to implement.

[0185] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0186] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0187] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0188] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A plurality of composite film layers are formed on one side of a substrate; the plurality of composite film layers are periodically spaced in different regions of the substrate, and the composite film layers in different regions correspond to different storage cells; each of the composite film layers includes a plurality of alternately stacked first dielectric layers and first conductive layers, and a first via; the hole in the first via that passes through the first dielectric layer is a first hole segment, and the hole that passes through the first conductive layer is a second hole segment; trenches are formed between adjacent composite film layers, and the trenches are filled with a third dielectric layer; filling a sacrificial layer in the first via hole, wherein the material of the sacrificial layer is different from the material of the first dielectric layer; The sacrificial layer is patterned to form a second via hole coaxial with the first via hole, so that the remaining sacrificial layer in the first hole segment forms a ring-shaped sacrificial structure and the sacrificial layer in the second hole segment is completely removed; along a direction parallel to the substrate, the size of the second hole segment is smaller than that of the first hole segment; forming a semiconductor layer, a gate dielectric layer, and a word line covering the inner wall of the second via hole in sequence in the second via hole, wherein the semiconductor layer in the corresponding area of ​​the first dielectric layer is surrounded by the annular sacrificial structure; Opening a via hole between adjacent combined film layers to expose a portion of the sacrificial structure, and removing the annular sacrificial structure to expose the annular semiconductor layer located in a corresponding area of ​​the first dielectric layer; The semiconductor layer exposed between the adjacent combined film layers is removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Along a direction parallel to the substrate, a diameter of a second hole segment of the first via hole penetrating the first conductive layer is smaller than a target diameter; The aperture of the second via hole is consistent with the target aperture, and the target aperture can cause the first conductive layer to be divided into two parts.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: A plurality of composite film layers are formed on one side of the substrate, including: forming a plurality of initial composite film layers on one side of the substrate, wherein the initial composite film layers include a first initial dielectric layer and a first initial conductive layer that are overlapped; forming an initial via hole on the initial combined film layer, penetrating the initial combined film layer; Using the first initial conductive layer of the initial via hole as a mask, the first initial dielectric layer is laterally etched to form the first hole segment in the first dielectric layer, wherein the aperture of the first hole segment is larger than the aperture of the initial via hole, so that a laterally extending annular groove is formed between adjacent first initial conductive layers; The first initial conductive layer is etched in the initial via hole to form a second hole segment in the first conductive layer, so that the first initial conductive layer is divided into two parts.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the third dielectric layer is the same as that of the first dielectric layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: Opening a via hole between adjacent combined film layers to expose a portion of the sacrificial structure, and removing the annular sacrificial structure to expose the annular semiconductor layer located in a corresponding area of ​​the first dielectric layer, comprising: A via hole is opened in the third dielectric layer between adjacent combined film layers to expose a portion of the sacrificial structure in the corresponding area of ​​each first dielectric layer. The annular sacrificial structure in the corresponding area of ​​each first dielectric layer is removed by wet etching in the via hole to expose the annular semiconductor layer in each area surrounded by the first dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: After removing the annular semiconductor layer exposed between the adjacent combined film layers, the method further includes: The via holes between adjacent combined film layers are filled with a second dielectric layer; the material of the second dielectric layer is the same as that of the first dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: include: The material of the sacrificial layer includes silicon germanium; and the first dielectric layer is an oxide containing silicon.

8. The method for manufacturing a semiconductor device according to claim 3, wherein: The diameter of the initial via hole penetrating the initial combined film layer along a direction parallel to the substrate is 70% to 90% of the target diameter; The aperture of the first hole section of the first via hole that passes through the first dielectric layer is 110% to 130% of the target aperture.

9. A semiconductor device, characterized in that: The method is manufactured based on any one of claims 1 to 8.

10. The semiconductor device according to claim 9, wherein include: Multiple memory cell arrays, with memory cells at the same position periodically stacked and distributed; Each memory cell comprises a gate extending longitudinally, a gate insulating layer and a semiconductor layer surrounding the sidewall of the gate in sequence, a source electrode and a drain electrode surrounding the semiconductor layer and located in the same layer, and a semiconductor layer between the source electrode and the drain electrode; The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells at different layers are isolated by a first dielectric layer; The semiconductor layers, source electrodes and drain electrodes of adjacent memory cells in the same layer are isolated by a first dielectric layer; The first dielectric layer contacts the semiconductor layer between the source electrode and the drain electrode of each memory cell, and contacts the gate insulating layer between adjacent memory cells.

11. The semiconductor device according to claim 10, wherein: The semiconductor layer only includes a film layer extending in a direction perpendicular to the substrate. A first dielectric layer is filled between different adjacent semiconductor layers. The first dielectric layer is in contact with the outer sidewall and end of the semiconductor layer.

12. The semiconductor device according to claim 11, wherein The semiconductor layer and the gate insulating layer are located in the second via hole; The apertures of the semiconductor layer in each region in the vertical direction are the same; The apertures of the gate insulating layer in each region in the vertical direction are the same.

13. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 9 to 12.

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