Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a common conductive line extending in a first direction; a memory cell array including a plurality of horizontal layers stacked in a first direction and sharing a common conductive line; and a selector structure operably coupled to the common conductive line, where the selector structure includes a plurality of selection transistors stacked in the first direction and a selector commonly coupled to the plurality of selection transistors.

Description

[0001] Cross-references to related applications

[0002] This application claims priority from Korean Patent Application No. 10-2023-0115452, filed on August 31, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional memory cell and a method for manufacturing the semiconductor device. Background Art

[0004] In order to cope with demands for large capacity and miniaturization of memory devices, a technology for providing a three-dimensional (3D) memory device in which a plurality of memory cells are stacked has been proposed. Summary of the Invention

[0005] Various embodiments of the present invention are directed to a semiconductor device including a highly integrated memory cell, and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a common conductive line extending in a first direction; a memory cell array including multiple horizontal layers stacked in the first direction and sharing the common conductive line; and a selector structure operably coupled to the common conductive line, wherein the selector structure includes multiple selection transistors stacked in the first direction and a selector commonly coupled to the multiple selection transistors.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack by sequentially forming a lower-level stack and an upper-level stack; forming a conductive line passing through the lower-level stack and the upper-level stack; forming a memory cell array in the lower-level stack, the memory cell array including a plurality of horizontal layers commonly coupled to the conductive line; forming a plurality of selection transistors in the upper-level stack, the plurality of selection transistors including a plurality of selector-level horizontal layers commonly coupled to the conductive line; and forming a selector that passes through the plurality of selector-level horizontal layers.

[0008] According to an embodiment of the present invention, a semiconductor device includes: a common conductive line extending vertically in a first direction; a memory cell array including multiple horizontal layers vertically stacked in the first direction and sharing the common conductive line; and a selector structure operably coupled to the common conductive line, wherein the selector structure includes multiple selection transistors vertically stacked in the first direction and a selector commonly coupled to the multiple selection transistors.

[0009] These and other features and advantages of the present invention will be better understood by those skilled in the art from the following drawings and detailed description of example embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a schematic perspective view showing a semiconductor device according to an embodiment of the present invention.

[0011] Figure 1B is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2 It is along Figure 1B Schematic cross-sectional view taken along line A1-A1'.

[0013] Figure 3 It is along Figure 1B Schematic cross-sectional view taken along line A2-A2'.

[0014] Figures 4 to 29 is a schematic plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] Figures 30A to 30C is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0016] Figures 31 to 33 is a schematic perspective view showing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0017] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be exhaustive and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same components in the various figures and embodiments of the present invention.

[0018] The drawings are not necessarily drawn to scale, and in some cases, the proportions may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0019] According to embodiments of the present invention described below, memory cells may be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0020] Figure 1Ais a schematic perspective view showing a semiconductor device according to an embodiment of the present invention. Figure 1B is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Figure 2 It is along Figure 1B Schematic cross-sectional view taken along line A1-A1'. Figure 3 It is along Figure 1B Schematic cross-sectional view taken along line A2-A2'.

[0021] Reference Figures 1A to 3 The semiconductor device 100 may include a memory cell array MCA and a selector structure BLS. The memory cell array MCA may include a plurality of memory cells MC. The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1. The row array of memory cells MC may include a plurality of memory cells MC arranged horizontally in a second direction D2 and a third direction D3.

[0022] Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0023] The memory cell array MCA may include sub-memory cell arrays adjacent to each other in the second direction D2. The sub-memory cell arrays may have a mirror-type structure, in which two memory cells MC share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 100 may further include a sub-memory cell array having a mirror-type structure, in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays, in which the memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays arranged horizontally in a third direction D3. According to another embodiment of the present invention, the memory cell array MCA may include a plurality of sub-memory cell arrays arranged in the second direction D2. For example, in the second direction D2, the data storage element CAP, the switching element TR, the first conductive line BL, and the switching element TR may be arranged alternately in the above order.

[0024] An inter-cell dielectric layer IL may be disposed between memory cells MC stacked along a first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may also be referred to as a "horizontal inter-cell dielectric layer." A first top dielectric layer HM1 may be disposed on the uppermost-level inter-cell dielectric layer IL.

[0025] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3. Each of the first conductive lines BL may extend in the first direction D1. Each of the first conductive lines BL may have a columnar shape, for example, a rectangular cross-section.

[0026] The memory cell array MCA may be disposed above the lower structure LS. The selector structure BLS may be disposed above the memory cell array MCA. The selector structure BLS may be disposed to overlap with the memory cell array MCA.

[0027] The first conductive line BL may be vertically oriented in the first direction D1. The first conductive line BL may include a bit line. The first conductive line BL may also be referred to as a vertical conductive line, a vertically oriented bit line, a vertically extending bit line, or a pillar bit line. The first conductive line BL may include a conductive material. The first conductive line BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductive line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0028] The switching element TR may have a function of controlling the voltage (or current) supplied to the data storage element CAP during a data write operation and a data read operation performed on the data storage element CAP. The switching element TR may include a horizontal layer HL, an inter-level dielectric layer GD, and a second conductive line DWL. The second conductive line DWL may include a horizontal conductive line or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second conductive line DWL may serve as a gate electrode. The second conductive line DWL may also be referred to as a "horizontal gate electrode or a horizontal word line." The switching element TR may serve as a cell transistor. The switching element TR may also be referred to as an "access element or a selection element."

[0029] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second conductive line DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), and the second conductive line DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0030] The horizontal layer HL may be oriented horizontally in a second direction D2 from the first conductive line BL. The second conductive line DWL may have a dual structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL interposed between the upper horizontal line G1 and the lower horizontal line G2. The inter-level dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL. The inter-level dielectric layer GD may be formed in direct contact with the upper and lower surfaces of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL, and the lower horizontal line G2 may be disposed below the horizontal layer HL. The second conductive line DWL may include a pair of upper horizontal lines G1 and lower horizontal lines G2. In the second conductive line DWL, the same drive voltage may be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 may form a pair and be coupled to a single memory cell MC. According to another embodiment of the present invention, different drive voltages may be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one horizontal line disposed between the upper horizontal line G1 and the lower horizontal line G2 may serve as a back gate or a shield gate.

[0031] Each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping with the horizontal layer HL, which is greater than a width of a non-overlapping portion that does not overlap with the horizontal layer HL. The second conductive line DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP refers to a portion overlapping with the channel CH of the horizontal layer HL. The channel non-overlapping portion NOL refers to a portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a diamond shape. The channel overlapping portion WLP may completely overlap with the channel CH. The second conductive line DWL extending in the third direction D3 may include a plurality of channel overlapping portions WLP. Since the channel overlapping portion WLP and the channel non-overlapping portion NOL are alternately repeated in the third direction D3, the second conductive line DWL may have a notched sidewall.

[0032] From a top view perspective, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0033] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon-germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0034] The upper surface and the lower surface of the horizontal layer HL may have flat surfaces. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0035] The horizontal layer HL may include a channel CH, a first doped region SR disposed between the channel CH and the first conductive line BL, and a second doped region DR disposed between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of the oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an "active layer or thin body." The channel overlap portion WLP of the channel CH and the second conductive line DWL may overlap each other. The channel CH may have a cross shape or a diamond shape. The channel overlap portion WLP of the second conductive line DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0036] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type conductive impurities or P-type conductive impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may also be referred to as "first and second source / drain regions."

[0037] The inter-level dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The inter-level dielectric layer GD may also be referred to as a gate dielectric layer. The inter-level dielectric layer GD may also be referred to as a horizontal layer side dielectric layer. The inter-level dielectric layer GD may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The inter-level dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The inter-level dielectric layer GD may be formed by a thermal oxidation process of a semiconductor material.

[0038] The second conductive line DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductive line DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive line DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second conductive line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or more. The second conductive line DWL may include a stack of a low work function material and a high work function material.

[0039] The data storage element CAP may include a storage element, such as a capacitor. The data storage element CAP may be arranged horizontally in a second direction D2 from the switching element TR. The data storage element CAP may include a first electrode SN extending horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN above the first electrode SN and a dielectric layer DE disposed between the first and second electrodes SN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an interior space and multiple exterior surfaces, and the interior space of the first electrode SN may include multiple interior surfaces. The exterior surface of the first electrode SN may include a vertical exterior surface and multiple horizontal exterior surfaces. The vertical exterior surface of the first electrode SN may extend vertically in the first direction D1, while the horizontal exterior surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The interior space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the interior and exterior surfaces of the first electrode SN. The second electrode PN may be disposed above the dielectric layer DE in the interior space of the first electrode SN. Part of the exterior surface of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0040] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, and the three-dimensional first electrode SN may have a horizontal three-dimensional structure oriented in the second direction D2. For example, in the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include an inner cylindrical surface and an outer cylindrical surface. A portion of the outer cylindrical surface of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the inner cylindrical surface of the first electrode SN.

[0041] According to another embodiment of the present invention, the first electrode SN may have a pillar shape or a pylinder shape. The pylinder shape refers to a structure in which a pillar shape and a pylinder shape are combined.

[0042] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, and titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0043] The dielectric layer DE may also be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0044] The dielectric layer DE may be formed of a zirconium-based oxide (Zr-based oxide). The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may also be referred to as zirconium oxide-based layers (ZrO2-based layers). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium-based oxide (Hf-based oxide). The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may also be referred to as a hafnium oxide-based layer (HfO2-based layer). In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, aluminum oxide (Al2O3) may have a larger band gap energy than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a band gap energy larger than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as a high-bandgap material. By including a high-bandgap material in the dielectric layer DE, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacked structures, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0045] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material, and the dielectric layer DE may have a stacked structure in which multiple high-k materials and multiple high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0046] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0047] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0048] According to another embodiment of the present invention, an interface control layer may be further formed between the first electrode SN and the dielectric layer DE to improve leakage current. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0049] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced by another data storage material. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0050] For example, the memory cell MC may include a thyristor, the first conductive line BL may be a cathode line, and the data storage element CAP may be replaced by an anode line. Thus, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows, or a low conductance state in which a small amount of current or no current flows. The memory cell MC according to this embodiment of the present invention can have a "1" state and a "0" state, respectively, by utilizing the high conductance state and the low conductance state of the thyristor.

[0051] Each memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0052] A first cover layer BC may be disposed between the second conductive line DWL and the first conductive line BL. A second cover layer CC may be disposed between the second conductive line DWL and the first electrode SN of the data storage element CAP. The first cover layer BC may be disposed between the upper horizontal line G1 and the first conductive line BL, and the first cover layer BC may be disposed between the lower horizontal line G2 and the first conductive line BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. A memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0053] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap, or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0054] The cell dielectric layer IL may be disposed between the memory cells MC stacked in the first direction D1. The second electrodes PN of the data storage elements CAP adjacent in the first direction D1 may be coupled to each other.

[0055] A plurality of first passivation layers BF1 may be disposed between the bottommost second conductive line DWL among the second conductive lines DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first conductive line BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first conductive line BL, the second conductive line DWL, and the data storage element CAP may be electrically disconnected from the lower structure LS by the first to third passivation layers BF1, BF2, and BF3, respectively. The first to third passivation layers BF1, BF2, and BF3 may also be referred to as bottom dielectric layers or bottom passivation layers. A bottommost inter-cell dielectric layer LIL may be disposed between the first passivation layer BF2 and the data storage element CAP.

[0056] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit portion.

[0057] For example, the lower structure LS may include a structure in which a peripheral circuit portion, a metal interconnection structure, and a bonding pad structure are sequentially stacked in the stated order. The memory cell array MCA and the peripheral circuit portion of the lower structure LS may be coupled by wafer bonding.

[0058] The peripheral circuit portion of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may also be referred to as a COP (cell over peripheral circuit) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell array MCA. The at least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, etc. The at least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0059] For example, the peripheral circuit portion may include a sub-word line driver and a sense amplifier. The first conductive line BL may be coupled to the sense amplifier, and the second conductive line DWL may be coupled to the sub-word line driver.

[0060] According to another embodiment of the present invention, the peripheral circuit may include: a first peripheral circuit including a selector structure BLS; a second peripheral circuit including a sub-wordline driver; and a third peripheral circuit including a sense amplifier. The first peripheral circuit may be arranged at a higher level than the memory cell array MCA, and the second and third peripheral circuits may be arranged at higher levels than the first peripheral circuit. The second and third peripheral circuits may be arranged at the same level. The second and third peripheral circuits may be coupled to the memory cell array MCA and the selector structure BLS by wafer bonding using bonding pads.

[0061] According to another embodiment of the present invention, the memory cell array MCA may be arranged at a higher level than the selector structure BLS. For example, the back side of the lower structure LS may be arranged at the top, and thus the selector structure BLS, the memory cell array MCA, and the lower structure LS may be arranged in the stated order.

[0062] According to another embodiment of the present invention, the peripheral circuit portion can be arranged at a level higher than the memory cell array MCA. This can also be referred to as a POC (peripheral circuit above cell) structure. In this case, the peripheral circuit portion can be arranged at a level higher than the selector structure BLS.

[0063] According to another embodiment of the present invention, the memory cell array MCA may include dynamic random access memory (DRAM), embedded DRAM, NAND, ferroelectric RAM (FeRAM), spin torque transfer RAM (STTRAM), phase change RAM (PCRAM) or resistive RAM (ReRAM).

[0064] The selector structure BLS can be coupled to the first conductive lines BL of the memory cell array MCA. The selector structure BLS can be an element for selecting the first conductive lines BL. For example, a used first conductive line BL can be connected and used, while other first conductive lines BL can be disconnected. Therefore, sufficient sensing margin can be ensured in the multi-layer stacked memory cell array MCA.

[0065] The selector structure BLS can use a multi-cell structure. For example, the selector structure BLS may include at least four select transistors STR. The multi-cell structure refers to a selector CP and multiple select transistors STR. The selector CP can be commonly coupled to the select transistor (STR). The select transistor STR can also be referred to as a "selector level switch element."

[0066] The selector structure BLS may include a select transistor array STA and a selector (selector level plug, CP). The select transistor array STA may include a plurality of select transistors STR. The select transistor STR may have the same structure as the switch element TR of the memory cell MC. The select transistors STR stacked in the first direction D1 may share one selector CP.

[0067] The selector structure BLS may include a plurality of selection transistors STR stacked vertically in a first direction D1. The selector structure BLS may include a plurality of selector-level horizontal conductive lines SDWL stacked vertically in the first direction D1. The selector structure BLS may include a plurality of selector-level horizontal layers SHL stacked vertically in the first direction D1. The selector structure BLS and the memory cell array MCA may share a first conductive line BL and a first contact node BLC. The selector structure BLS and the memory cell array MCA may share a dielectric layer DE and a second electrode PN of a data storage element CAP. The dielectric layer of the selector structure BLS may be referred to as a “selector-level dielectric layer SDE”, and the second electrode of the selector structure BLS may be referred to as a “selector-level plate SPN”.

[0068] Each selection transistor STR may include a selector-level horizontal conductive line SDWL and a selector-level horizontal layer SHL.

[0069] The selector-level horizontal conductive line SDWL may extend in a third direction D3 along its longitudinal axis, and the selector-level horizontal layer SHL may extend in a second direction D2 along its longitudinal axis. The selector-level horizontal layer SHL may be arranged horizontally starting from the first conductive line BL. The selector-level horizontal conductive line SDWL may have a dual structure. For example, the selector-level horizontal conductive line SDWL may include a selector-level upper horizontal line G11 and a selector-level lower horizontal line G12 facing each other, with the selector-level horizontal layer SHL being placed between the selector-level upper horizontal line G11 and the selector-level lower horizontal line G12. The selector-level inter-level dielectric layer SGD may be formed on the upper and lower surfaces of the selector-level horizontal layer SHL. The selector-level upper horizontal line G11 may be disposed above the selector-level horizontal layer SHL, and the selector-level lower horizontal line G12 may be disposed below the selector-level horizontal layer SHL. The selector-level horizontal conductive lines SDWL may include a pair of selector-level upper horizontal lines G11 and selector-level lower horizontal lines G12. In the selector-level horizontal conductive lines SDWL, the same driving voltage may be applied to the selector-level upper horizontal lines G11 and the selector-level lower horizontal lines G12. The selector-level horizontal conductive lines SDWL may also be referred to as selector-level horizontal word lines or selector-level horizontal gates.

[0070] The second conductive line DWL and the selector level horizontal conductive line SDWL may include the same structure and the same material.

[0071] The selector level horizontal layer SHL may extend in the second direction D2. The selector level horizontal layer SHL may include a semiconductor material. For example, the selector level horizontal layer SHL may include polycrystalline silicon, single crystal silicon, germanium or silicon-germanium. According to another embodiment of the present invention, the selector level horizontal layer SHL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). The selector level horizontal layer SHL and the horizontal layer HL may include the same material. The horizontal length of the selector level horizontal layer SHL may be greater than the horizontal length of the horizontal layer HL. For example, when comparing the horizontal lengths in the second direction D2, the horizontal length of the selector level horizontal layer SHL may be greater than the horizontal length of the horizontal layer HL. The horizontal layer HL may also be referred to as a "unit level horizontal layer".

[0072] The upper surface and the lower surface of the selector level horizontal layer SHL may have flat surfaces.The upper surface and the lower surface of the selector level horizontal layer SHL may be parallel to each other in the second direction D2.

[0073] The selector-level horizontal layer SHL may include a selector-level channel SCH, a selector-level first doping region SSR disposed between the selector-level channel SCH and the first conductive line BL, and a selector-level second doping region SDR disposed between the selector-level channel SCH and the selector CP. When the selector-level horizontal layer SHL is formed of an oxide semiconductor material, the selector-level channel SCH may be formed of an oxide semiconductor material, and the selector-level first doping region SSR and the selector-level second doping region SDR may be omitted. The selector-level horizontal layer SHL may also be referred to as an active layer or a thin body.

[0074] The selector-level first doping region SSR and the selector-level second doping region SDR may be doped with impurities of the same conductivity type. The selector-level first doping region SSR and the selector-level second doping region SDR may be doped with N-type impurities or P-type impurities. The selector-level first doping region SSR and the selector-level second doping region SDR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The selector-level first doping region SSR may be coupled to a first conductive line BL, and the selector-level second doping region SDR may be coupled to a selector CP. The selector-level first doping region SSR of the select transistors STR stacked in the first direction D1 may be commonly coupled to the first conductive line BL. The selector-level second doping region SDR of the select transistors STR stacked in the first direction D1 may be commonly coupled to the selector CP. The selector CP may have a pillar shape that passes through the selector-level second doping region SDR of the select transistors STR stacked in the first direction D1. The memory cell array MCA and the selector structure BLS may share the first conductive line BL. The first conductive line BL may be a common conductive line.

[0075] The selector level inter-level dielectric layer SGD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The selector level inter-level dielectric layer SGD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof.

[0076] The selector-level inter-level dielectric layer SGD may be disposed on a first surface (or upper surface) and a second surface (or lower surface) of the selector-level horizontal layer SHL. The first surface and the second surface of the selector-level horizontal layer SHL may be flat surfaces.

[0077] The selector level horizontal conductive line SDWL may include a metal-based material, a semiconductor material, or a combination thereof. The selector level horizontal conductive line SDWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the selector level horizontal conductive line SDWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The selector level horizontal conductive line SDWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more. The selector level horizontal conductive line SDWL may include a stack of a low work function material and a high work function material.

[0078] As described above, the selection transistor STR and the switching element TR may be formed in the same structure, and the horizontal layer HL and the selector level horizontal layer SHL may have different horizontal lengths.

[0079] The selector CP may include a conductive material. The selector CP may include a semiconductor material, a metal-based material, or a combination thereof. The selector CP may include doped polysilicon. The selector CP may include a metal silicide, a metal nitride, a metal, or a combination thereof. The selector CP may include a stack of TiSi2 / TiN / W. The selector-level second doped region SDR may include impurities diffused from the selector CP. The selector-level first doped region SSR may include impurities diffused from the first contact node BLC. The selector CP may be a hole-shaped column. The selector CP may also be referred to as a "conductive column structure." From a top view perspective, the cross-section of the selector CP may be square, circular, elliptical, or polygonal. The selector CP may be used in common based on a cell mat. For example, the memory device may include a plurality of memory banks arranged in a matrix structure, and each memory bank may include a plurality of cell groups. Each cell group may include a plurality of memory cells MC. The selector CP may also be referred to as a selector-level plug. The selector CP may be disposed between the selector-level horizontal conductive line SDWL and the selector-level plate SPN.

[0080] The plurality of selector level horizontal layers SHL and one first conductive line BL may be electrically connected to one selector CP. Thus, one selector CP may select one of the first conductive lines BL of the memory cell array MCA.

[0081] A plurality of pad layers L1 and L2 may be disposed between the selector-level horizontal conductive line SDWL and the selector-level plate SPN, and a spacer L3 may be disposed between the pad layers L1 and L2 and the selector-level plate SPN. The pad layers L1 and L2 and the spacer L3 may include a dielectric material. The selector CP may pass through the pad layers L1 and L2 and the selector-level horizontal layer SHL.

[0082] The semiconductor device 100 may further include a metal interconnect ML. The metal interconnect ML may be coupled to the first conductive line BL and the selector CP, respectively. A second top dielectric layer HM2 may be disposed above the first top dielectric layer HM1, and the metal interconnect ML may pass through the second top dielectric layer HM2. The first top dielectric layer HM1 and the second top dielectric layer HM2 may also be referred to as interlayer dielectric layers. When the first conductive line BL includes a bit line, the first conductive line BL may be coupled to a sense amplifier via the metal interconnect ML.

[0083] Reference Figures 1A to 3, the semiconductor device 100 may include a 3D DRAM, and the memory cell array MCA may include a memory cell array of the DRAM, and the selector structure BLS may include a bit line selector. The first conductive line BL may include a bit line, and the data storage element CAP may include a capacitor. The switching element TR may include a cell transistor. From another perspective, the semiconductor device 100 may include: a memory cell array MCA, which includes a bit line BL extending vertically from the upper part of the lower structure LS and a plurality of horizontal layers HL vertically stacked and sharing the bit line BL; and a selector structure BLS, which is arranged at a higher level than the memory cell array MCA. The selector structure BLS may include a plurality of selection transistors STR stacked vertically and a bit line selector CP commonly coupled to the selection transistors STR.

[0084] According to the above description, by forming the selector structure BLS of the multi-cell structure, the first vertical conductive line capacitance Cb can be reduced. Therefore, a sufficient sensing margin can be ensured even in a higher stack structure of the three-dimensional memory cells MC.

[0085] Figures 4 to 29 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0086] Reference Figure 4 , an etching target layer may be formed on the lower structure 11. The lower structure 11 may be made of or include a material suitable for semiconductor processing. The lower structure 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. Different materials may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a material containing silicon. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials, such as germanium. The lower structure 11 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0087] The etching target layer may include a stack SB. The stack SB may include a plurality of sub-stacks SB1 stacked several times. Each sub-stack SB1 may include a first layer 12, a second layer 13, a third layer 14, and a fourth layer 15 stacked sequentially in the order described. The first layer 12 and the third layer 14 may include the same material, and the first layer 12 and the third layer 14 may include silicon germanium or single crystal silicon germanium. The second layer 13 and the fourth layer 15 may be the same material and may include single crystal silicon. The first layer 12, the second layer 13, the third layer 14, and the fourth layer 15 may be formed by an epitaxial growth process. The first layer 12 at the lowest level may serve as a seed layer during the epitaxial growth process. The first layer 12 and the third layer 14 may be thinner than the second layer 13, and the fourth layer 15 may be thicker than the second layer 13.

[0088] As shown in the above-described embodiment of the present invention, when stacking memory cells, a stack body SB can be formed by stacking sub-stacks SB1 multiple times. A hard mask level sub-stack SB2 can be provided on top of the stack body SB. The hard mask level sub-stack SB2 can include a first layer 12, a second layer 13, a third layer 14, and a second layer 13 stacked sequentially in the order described.

[0089] Each sub-stack SB1 may be a four-layer stack of a first layer 12 / a second layer 13 / a third layer 14 / a fourth layer 15. For example, when the first layer 12 and the third layer 14 include silicon germanium layers and the second layer 13 and the fourth layer 15 include single crystal silicon layers, each sub-stack SB1 may include a stack of a first silicon germanium / a first single crystal silicon / a second silicon germanium / a second single crystal silicon (SiGe / Si / SiGe / Si). The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0090] The first layer 12, the second layer 13, and the third layer 14 may also be referred to as "sacrificial layers," and the fourth layer 15 may also be referred to as a recessed target layer. The stack SB may also be referred to as a vertical stack. The stack SB may be formed by alternating multiple sacrificial layers and multiple recessed target layers. The sacrificial layers may include the first layer 12, the second layer 13, and the third layer 14, and the recessed target layer may include the fourth layer 15. Each sacrificial layer may include a three-layer stack of a first silicon germanium layer, a first single crystal silicon layer, and a second silicon germanium layer. Each recessed target layer may include a single-layer second single crystal silicon layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0091] The stack body SB may include a lower-level stack body SBL arranged above the lower structure 11 and an upper-level stack body SBU arranged above the lower-level stack body SBL. Each of the lower-level stack body SBL and the upper-level stack body SBU may include a plurality of sub-stacks SB1. The lower-level stack body SBL may be a region in which a memory cell array MCA is to be formed, and the upper-level stack body SBU may be a region in which a selector BLS is to be formed. The hard mask level sub-stack SB2 may be arranged above the upper-level stack body SBU. Hereinafter, the reference numeral "MCA" may be referred to simply as the memory cell array region, and the reference numeral "BLS" may be referred to simply as the selector region.

[0092] Reference Figure 5 , a hard mask pattern 16A may be formed above the stack SB. The hard mask pattern 16A may be formed in direct contact with the stack SB. The hard mask level sub-stack SB2 and sub-stack SB1 of the stack SB may be etched using the hard mask pattern 16A as an etch barrier. As a result, a plurality of sacrificial vertical openings 17A and 17B may be formed. The sacrificial vertical openings 17A and 17B may include a first sacrificial vertical opening 17A and a second sacrificial vertical opening 17B. The first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may have the same size. The first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may pass through the stack SB and extend into the lower structure 11. From a top view perspective, the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be hole-shaped openings. The cross-sections of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be square, circular, or elliptical. The hard mask pattern 16A may have an etching selectivity relative to the stack SB. The hard mask pattern 16A may include silicon nitride, silicon oxide, amorphous carbon, photoresist, or a combination thereof.

[0093] The first and second sacrificial vertical openings 17A and 17B may be simultaneously formed in the selector region BLS and the memory cell array region MCA.

[0094] Reference Figure 6, both side surfaces of the hard mask pattern 16A may be trimmed (see reference numeral “16T”). Subsequently, using the trimmed hard mask pattern 16 as a barrier, the first layer 12 and the third layer 14 may be selectively removed through the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B. In order to selectively remove the first layer 12 and the third layer 14, the difference between the etching selectivity of the second layer 13 and the fourth layer 15 and the etching selectivity of the first layer 12 and the third layer 14 may be utilized. The first layer 12 and the third layer 14 may be removed using a wet etching process or a dry etching process. For example, when the first layer 12 and the third layer 14 include silicon germanium layers and the second layer 13 and the fourth layer 15 include single crystal silicon layers, the silicon germanium layers may be etched using an etchant or etchant gas that is selective for the silicon germanium layers, and the single crystal silicon layer may be left intact.

[0095] Subsequently, the second layer 13 and the fourth layer 15 can be recessed. To recess the second layer 13 and the fourth layer 15, a wet etching process or a dry etching process can be performed. According to this embodiment of the present invention, the fourth layer 15 can be partially etched while removing the second layer 13. As a result, the second layer 13 can be removed, and the fourth layer 15 can be thinned, as indicated by reference numeral "15A." The recessing process used to form the thin fourth layer 15A (i.e., the preliminary horizontal layer 15A) can also be referred to as a thinning process or trimming process of the fourth layer 15. To form the preliminary horizontal layer 15A, the upper surface (i.e., top surface), lower surface (i.e., bottom surface), and side surfaces (also referred to as lateral surfaces) of the fourth layer 15 can be recessed. The preliminary horizontal layer 15A can also be referred to as a thin-body active layer. The preliminary horizontal layer 15A can include a single crystal silicon layer. The recessing process used to form the preliminary horizontal layer 15A can use, for example, HSC1 (Hot SC-1). The HSC1 may include a solution of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and water (H 2 O) mixed in a weight ratio of about 1:4:20. The second layer 13 and the fourth layer 15 may be selectively etched by using the HSC1.

[0096] The preliminary horizontal layer 15A may be formed by the recessing process of the fourth layer 15 as described above, and the horizontal recess 18 may be formed between the vertically stacked preliminary horizontal layers 15A. Each of the upper and lower surfaces of the preliminary horizontal layer 15A may include a flat surface.

[0097] The preliminary horizontal layer 15A may have a cross shape from a top view perspective, and a side surface of the preliminary horizontal layer 15A may have a curved shape or a rounded shape.

[0098] After forming the preliminary horizontal layer 15A, the depth and width of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be expanded. When forming the preliminary horizontal layer 15A, the surface 11A of the lower structure 11 may be recessed to a predetermined depth (see reference numeral 11B). As a result, the depth of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be increased.

[0099] The preliminary horizontal layers 15A may be formed in the selector region BLS and the memory cell array region MCA. According to another embodiment of the present invention, the number of preliminary horizontal layers 15A formed in the memory cell array region MCA may be greater than that formed in the selector region BLS.

[0100] Reference Figure 7 A first dielectric layer 19 may be formed around the preliminary horizontal layer 15A. The first dielectric layer 19 may include silicon nitride. The first dielectric layer 19 may completely cover the upper surface, the lower surface, and the side surfaces of the preliminary horizontal layer 15A.

[0101] When forming the first dielectric layer 19, a dummy dielectric layer 19D may be formed on the surface of the lower structure 11. The first dielectric layer 19 may also be formed to completely surround the hard mask layer pattern 16, that is, may cover the upper surface, lower surface and side surfaces of the hard mask layer pattern 16.

[0102] Subsequently, a second dielectric layer 20 may be formed over the first dielectric layer 19. The second dielectric layer 20 may be formed on the first dielectric layer 19 and in direct contact with the first dielectric layer 19. The second dielectric layer 20 may fill the space between vertically adjacent first dielectric layers 19. The second dielectric layer 20 may include silicon oxide. Portions of the second dielectric layer 20 may be conformally formed on the surfaces of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B. Horizontal recess (see Figure 6 18 ) may be filled with a first dielectric layer 19 and a second dielectric layer 20 .

[0103] Subsequently, a sacrificial interstitial layer 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B. The sacrificial interstitial layer 21 may be a sacrificial material and may include amorphous carbon. According to another embodiment of the present invention, a column cover layer may be further formed on the sacrificial interstitial layer 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial interstitial layer 21 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial interstitial layer 21 may be performed until the uppermost level first dielectric layer 19 is exposed. Subsequently, the uppermost level second dielectric layer 20 may also be planarized until the uppermost level first dielectric layer 19 is exposed. As Figure 7As shown, the sacrificial interstitial layer 21 is not formed between the vertically stacked first dielectric layers 19 .

[0104] The second dielectric layer 20 and the sacrificial interstitial layer 21 can form a first sacrificial post structure SV1 and a second sacrificial post structure SV2, respectively filling the first sacrificial vertical opening 17A and the second sacrificial post structure SV2. Thus, the first sacrificial post structure SV1 can fill the first sacrificial vertical opening 17A, and the second sacrificial post structure SV2 can fill the second sacrificial vertical opening 17B, respectively. According to another embodiment of the present invention, the first sacrificial post structure SV1 and the second sacrificial post structure SV2 can include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, the first sacrificial post structure SV1 and the second sacrificial post structure SV2 can include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From a top view, the first sacrificial post structure SV1 and the second sacrificial post structure SV2 can be hole-shaped sacrificial posts. According to another embodiment of the present invention, a portion of the first dielectric layer 19 can be conformally formed on the surface of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B. As a result, the first sacrificial post structure SV1 and the second sacrificial post structure SV2 can also include a portion of the first dielectric layer 19.

[0105] As described above, with the formation of the preliminary horizontal layer 15A, the first dielectric layer 19, and the second dielectric layer 20, a unit mold structure can be formed. The unit mold structure can include multiple unit molds. Each unit mold can include multiple mold layers. The mold layer refers to the preliminary horizontal layer 15A, the first dielectric layer 19, and the second dielectric layer 20. Each unit mold can include an ONSN (oxide-nitride-silicon-nitride) stack. An ONSN stack refers to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are stacked in sequence. The silicon oxide can correspond to the second dielectric layer 20, the first silicon nitride and the second silicon nitride can correspond to the first dielectric layer 19, and the single crystal silicon layer can correspond to the preliminary horizontal layer 15A. A unit mold structure including multiple unit molds can also be referred to as a vertical stack. From another perspective, the unit mold structure can include an ONSNO (oxide-nitride-silicon-nitride-oxide) stack. An ONSNO stack refers to a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are stacked in sequence.

[0106] As described above, the sub-stack SB1 of the stack SB can be formed by Figures 4 to 7 The first layer 12, the second layer 13, and the third layer 14 can be replaced by a first dielectric layer 19 and a second dielectric layer 20. The fourth layer 15 can be converted into a preliminary horizontal layer 15A through a recess process. The first dielectric layer 19 can also be referred to as a trimming target layer.

[0107] According to another embodiment of the present invention, a trimming process may be performed on the first dielectric layer 19. For example, from a top view perspective, the first dielectric layer 19 may be trimmed to form a cross-shaped pattern.

[0108] Reference Figure 8 , the hard mask pattern 16 and the uppermost-level first dielectric layer 19 may be removed to form a hard mask layer-level recess 22. The hard mask layer-level recess 22 may be formed in the selector region BLS.

[0109] Reference Figure 9 , a top dielectric layer 23 may be formed to fill the hard mask layer-level recess 22. The top dielectric layer 23 may include silicon oxide.

[0110] Reference Figure 10 , the upper end portion of sacrificial interstitial layer 21 can be replaced with a top-level sacrificial post 24. Top-level sacrificial post 24 can include silicon oxide. Forming top-level sacrificial post 24 can include recessing the upper portion of sacrificial interstitial layer 21 and filling the recessed upper portion of sacrificial interstitial layer 21 with a sacrificial material.

[0111] The first and second sacrificial post structures SV1 and SV2 may include a second dielectric layer 20 , a sacrificial interstitial layer 21 , and top-level sacrificial posts 24 .

[0112] Reference Figure 11 , the initial vertical opening 25 can be formed by removing the second sacrificial pillar structure SV2. The initial vertical opening 25 can be a hole-shaped opening.

[0113] Subsequently, the second dielectric layer 20 may be selectively recessed. As a result, the first side surfaces of the first dielectric layer 19 and the dummy dielectric layer 19D may be exposed.

[0114] Reference Figure 12 , the first dielectric layer 19 and the dummy dielectric layer 19D can be selectively horizontally recessed from the preliminary vertical opening 25. As a result, a first dielectric layer pattern 19A and a dielectric layer level recess 19B can be formed. Portions of the preliminary horizontal layer 15A can be exposed through the dielectric layer level recess 19B. From a top view perspective, the first dielectric layer pattern 19A can have a cross shape.

[0115] A first dielectric layer pattern 19A and a dielectric layer level recess 19B may be formed in the selector region BLS and the memory cell array region MCA.

[0116] Reference Figure 13, a vertical sacrificial structure 29 may be formed to fill the dielectric layer level recess 19B. Vertical sacrificial structure 29 may include a stack of a first liner layer 26, a second liner layer 27, and an interstitial layer 28. The first liner layer 26 may include silicon oxide, and the second liner layer 27 may include silicon nitride. The interstitial layer 28 may include amorphous carbon, titanium nitride, or a combination thereof. The dielectric layer level recess 19B may be filled with the first liner layer 26 and the second liner layer 27. The stack of the first liner layer 26, the second liner layer 27, and the interstitial layer 28 may fill the initial vertical opening 25. The interstitial layer 28 may not be formed in the dielectric layer level recess 19B.

[0117] Reference Figure 14 , the top-level sacrificial posts 24 and the sacrificial interstitial layer 21 may be selectively removed from the first sacrificial post structure SV1. As a result, a vertical-level path 30' may be formed.

[0118] Subsequently, the dummy dielectric layer 19D below the vertical level path 30 ′ may be removed to form a lower level gap 19R.

[0119] Reference Figure 15 , the second dielectric layer 20 may be cut in the vertical level path 30' to form the first hole-shaped vertical opening 30. The first hole-shaped vertical opening 30 may be formed in the selector area BLS and the memory cell array area MCA.

[0120] Subsequently, a first passivation layer 31 may be formed to fill the lower-level gap 19R. The first passivation layer 31 may include silicon oxide. Forming the first passivation layer 31 may include depositing silicon oxide to fill the lower-level gap 19R and etching the silicon oxide. When forming the first passivation layer 31, the second dielectric layer 20 may be partially recessed.

[0121] Subsequently, the second passivation layer 32 may be formed in a lower region of the first hole-shaped vertical opening 30. For example, the surface of the lower structure 11 may be oxidized to form the second passivation layer 32.

[0122] Reference Figure 16 To form the horizontal level recess 33, the first dielectric layer pattern 19A may be removed through the first hole-shaped vertical opening 30. From a top view perspective, the horizontal level recess 33 may have a cross shape. A portion of the preliminary horizontal layer 15A may be exposed by the horizontal level recess 33. The horizontal level recess 33 may be disposed between the second dielectric layer 20 and the preliminary horizontal layer 15A. Two horizontal level recesses 33 may face each other, with one preliminary horizontal layer 15A located therebetween.

[0123] Horizontal level recesses 33 may be formed in the selector region BLS and the memory cell array region MCA.

[0124] Reference Figure 17, an inter-level dielectric layer 34 may be formed on the exposed portion of the preliminary horizontal layer 15A. The inter-level dielectric layer 34 may also be referred to as a gate dielectric layer. The inter-level dielectric layer 34 may correspond to Figure 1B The inter-level dielectric layer GD is shown.

[0125] The inter-level dielectric layer 34 can be formed by oxidizing the surface of the preliminary horizontal layer 15A. According to another embodiment of the present invention, the inter-level dielectric layer 34 can be formed by a silicon oxide deposition process. The inter-level dielectric layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The inter-level dielectric layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0126] Subsequently, horizontal conductive lines 35 filling the horizontal level recesses 33 may be formed over the inter-level dielectric layer 34. Forming the horizontal conductive lines 35 may include depositing a conductive material filling the horizontal level recesses 33 over the inter-level dielectric layer 34 and performing an etch-back process on the conductive material.

[0127] The horizontal conductive lines 35 may include a pair of first and second horizontal conductive lines 35A and 35B facing each other, with the preliminary horizontal layer 15A located therebetween. The first and second horizontal conductive lines 35A and 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first and second horizontal conductive lines 35A and 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first and second horizontal conductive lines 35A and 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first and second horizontal conductive lines 35A and 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or more.

[0128] The horizontal conductive lines 35 may correspond to Figures 1A to 3 The second conductive line DWL shown in FIG. 1A and the first horizontal conductive line 35A and the second horizontal conductive line 35B may correspond to the upper horizontal line G1 and the lower horizontal line G2, respectively. Figure 3 As shown, each of the first horizontal conductive line 35A and the second horizontal conductive line 35B may have a cross shape and may include a channel overlapping portion WLP and a channel non-overlapping portion NOL.

[0129] A plurality of horizontal conductive lines DWL may be formed in the memory cell array area MCA, and a selector level horizontal conductive line SDWL may be formed in the selector area BLS.

[0130] The selector-level horizontal conductive line SDWL may have a dual structure. For example, the selector-level horizontal conductive line SDWL may include a first horizontal conductive line 35A and a second horizontal conductive line 35B facing each other, with the preliminary horizontal layer 15A interposed therebetween. The selector-level horizontal conductive line SDWL may include a pair of the first horizontal conductive line 35A and the second horizontal conductive line 35B. In the selector-level horizontal conductive line SDWL, the same driving voltage may be applied to the first horizontal conductive line 35A and the second horizontal conductive line 35B.

[0131] The selector level horizontal conductive lines SDWL and the horizontal conductive lines DWL may have the same structure and may be formed of the same material.

[0132] Reference Figure 18 , a first capping layer 36 may be formed on the first side surface of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, silicon oxycarbide, an embedded air gap, or a combination thereof. A deposition and etch-back process of the capping material may be performed to form the first capping layer 36. When the first capping layer 36 is formed, the first hole-shaped vertical opening may be expanded, as indicated by "30A". When or after the first capping layer 36 is formed, a portion of the inter-level dielectric layer 34 may be removed to expose a first edge portion of each preliminary horizontal layer 15A. When or after the first capping layer 36 is formed, a portion of the second passivation layer 32 may be etched.

[0133] Subsequently, a first doped region 37 may be formed in the first edge portion of each preliminary horizontal layer 15A. Forming the first doped region 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doped region 37 may be formed by a process of doping impurities.

[0134] A plurality of first doping regions 37 may be formed in the memory cell array area MCA. A selector-level first doping region 37A may be formed in the selector area BLS.

[0135] The first doping region 37 and the selector-level first doping region 37A may be formed simultaneously.

[0136] Reference Figure 19 , vertical conductive lines 39 may be formed to couple to the first edge portion of each preliminary horizontal layer 15A. Vertical conductive lines 39 may fill first hole-shaped vertical openings 30A. Vertical conductive lines 39 may be collectively coupled to preliminary horizontal layer 15A. Vertical conductive lines 39 may include titanium nitride, tungsten, or a combination thereof. Vertical conductive lines 39 may also be referred to as bit lines or vertical bit lines.

[0137] Before forming vertical conductive line 39, first contact node 38 may be formed. First contact node 38 may include doped polysilicon. First doped region 37 may include impurities diffused from first contact node 38. After forming first contact node 38, impurities may diffuse from first contact node 38 to form first doped region 37. A metal silicide layer may be further formed between vertical conductive line 39 and first contact node 38.

[0138] The vertical conductive lines 39 may correspond to Figures 1A to 3 The first conductive line BL is shown.

[0139] The vertical conductive line 39 may be formed in the selector region BLS and may extend vertically to be disposed in the memory cell array region MCA. The vertical conductive line 39 may be shared by the selector region BLS and the memory cell array region MCA.

[0140] Reference Figure 20 , a selector level contact hole 40 may be formed through the preliminary horizontal layer 15A. To form the selector level contact hole 40, the top dielectric layer 23 disposed in the selector BLS, the uppermost level second dielectric layer 20, the vertical sacrificial structure 29, and the preliminary horizontal layer 15A may be etched.

[0141] The selector level contact hole 40 may be formed in the selector region BLS, but may not be formed in the memory cell array MCA.

[0142] Reference Figure 21 , a selector 41 may be formed to fill the selector level contact hole 40. The selector 41 may have a pillar-type structure. The selector 41 may include doped polysilicon. The selector 41 may include metal silicide, metal nitride, metal, or a combination thereof. The selector 41 may include a stack of TiSi2 / TiN / W.

[0143] Impurities may diffuse from the selector 41 to form a selector-level second doping region 41A. The preliminary horizontal layer 15A in which the selector-level first doping region 37A and the selector-level second doping region 41A are formed may be a selector-level horizontal layer 15HL.

[0144] As described above, a plurality of selection transistors STR and selectors 41 may be formed in the selector region BLS. The selection transistor STR may include a selector-level horizontal conductive line SDWL and a selector-level horizontal layer 15HL. Each selector-level horizontal layer 15HL may include a selector-level first doping region 37A and a selector-level second doping region 41A disposed horizontally. The selector-level channel 15C may be defined between the selector-level first doping region 37A and the selector-level second doping region 41A. Figure 2 As shown, the selector level horizontal layer 15HL may have a cross shape, and the selector level channel 15C may also have a cross shape.

[0145] Each selector 41 may share a plurality of selection transistors STR and may be electrically connected to the vertical conductive line 39 through the selection transistors STR.

[0146] Reference Figure 22 After forming mask layer 42, interstitial layer 28 of vertical sacrificial structure 29 may be recessed from selector region BLS. Interstitial layer 28 may remain in memory cell array region MCA. Top dielectric layer 23 may also be referred to as a "first top dielectric layer," and mask layer 42 may also be referred to as a "second top dielectric layer."

[0147] Reference Figure 23 , spacers 43 may be formed in the selector region BLS. The spacers 43 may be formed on the gap-filling layer 28. The spacers 43 may include a dielectric material. The spacers 43 may include silicon oxide.

[0148] The interstitial layer 28 may be removed from the memory cell array area MCA. Subsequently, the first liner layer 26 and the second liner layer 27 may be cut. As a result, a memory cell array level opening 44 may be formed. The cut first liner layer 26 and the second liner layer 27 may remain between the second dielectric layer 20 and the preliminary horizontal layer 15A.

[0149] Subsequently, a third passivation layer 44L may be formed on the surface of the lower structure 11. The third passivation layer 44L may include silicon oxide. The third passivation layer 44L may be formed by an oxidation process. According to another embodiment of the present invention, the third passivation layer 44L may cover the lowermost first liner layer 26 and the lowermost second liner layer 27.

[0150] Reference Figure 24 , the second edge portion of the preliminary horizontal layer 15A may be horizontally recessed to form a recess 45. As a result, the horizontal layer may remain, as indicated by reference numeral 'HL'.

[0151] As described above, a plurality of horizontal layers HL may be formed in the memory cell array area MCA. A plurality of selector-level horizontal layers 15HL may be formed in the selector area BLS. The horizontal length of the selector-level horizontal layer 15HL may be greater than the horizontal length of the horizontal layer HL. The selector 41 may be coupled to the selector-level horizontal layer 15HL, but may not be coupled to the horizontal layer HL. The bottom surface of the selector 41 may be blocked by the first liner layer 26 and the second liner layer 27.

[0152] Reference Figure 25, the first liner layer 26 and the second liner layer 27 may be recessed from the memory cell array level opening 44. As a result, a storage opening 45A may be formed in the memory cell array area MCA. The end of the second side of the horizontal layer HL may be exposed by the storage opening 45A. The storage opening 45A may also be referred to as a capacitor opening.

[0153] The horizontal layer HL may include a first edge and a second edge. The first edge refers to a portion coupled to the first contact node 38 and the vertical conductive line 39, and the second edge refers to a portion exposed by the storage opening 45A.

[0154] The storage opening 45A may be provided between the second dielectric layers 20. The second cover layer CC may be provided in the lower and upper portions of the horizontal layer HL, respectively. The second cover layer CC may include a stack of a first liner layer 26 and a second liner layer 27.

[0155] A lowermost dielectric layer LIL may be formed between the lower structure 11 and the lowermost second dielectric layer 20. The lowermost dielectric layer LIL may include a stack of a first liner layer 26 and a second liner layer 27. A portion of the third passivation layer 44L may extend to cover the lowermost dielectric layer LIL. Therefore, the lowermost dielectric layer LIL may be prevented from being lost when forming the storage opening 45A.

[0156] The storage opening 45A may not be formed in the selector region BLS.

[0157] Subsequently, second doped regions 47 may be formed in the second edges of the horizontal layer HL, respectively. Forming the second doped regions 47 may include depositing polysilicon doped with N-type impurities, performing a thermal treatment, and removing the doped polysilicon. The second doped regions 47 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the doped polysilicon may remain after the thermal treatment.

[0158] Reference Figure 26 , a second contact node 46 may be formed on the second edge of the horizontal layer HL. The second contact node 46 may include doped polysilicon. The second doped region 47 may include impurities diffused from the second contact node 46. According to another embodiment of the present invention, after forming the second contact node 46, impurities may diffuse from the second contact node 46 to form the second doped region 47. The second contact nodes 46 may be respectively disposed in the storage openings 45A.

[0159] The second contact node 46 and the storage opening 45A may be formed in the memory cell array area MCA, but may not be formed in the selector area BLS.

[0160] Each horizontal layer HL may include a first doping region 37 and a second doping region 47 arranged horizontally. Figure 3As shown, a channel may be defined between the first doping region 37 and the second doping region 47. Figure 3 As shown, the horizontal layer HL may have a cross shape, and the channel may also have a cross shape.

[0161] Reference Figure 27 The first electrodes 48 of the data storage element may be formed on the second contact nodes 46. The first electrodes 48 may have a horizontally oriented cylindrical shape. The first electrodes 48 may be respectively disposed in the storage openings 45A.

[0162] The first electrode 48 may be formed in the memory cell array region MCA, but may not be formed in the selector region BLS.

[0163] Reference Figure 28 , the second dielectric layer 20 may be horizontally recessed (see reference numeral 49). As a result, the outer wall of the first electrode 48 may be exposed. The recessed second dielectric layer 20 may correspond to Figure 1B The inter-cell dielectric layer IL is shown.

[0164] Reference Figure 29 , a dielectric layer 50 and a second electrode 51 may be sequentially formed on the first electrode 48. The first electrode 48, the dielectric layer 50, and the second electrode 51 may be a data storage element CAP. The dielectric layer 50 and the second electrode 51 may be formed in the memory cell array area MCA and may be extended to be disposed in the selector area BLS. The dielectric layer and the second electrode extended to be disposed in the selector area BLS may correspond to the following example. Figure 1B The selector level dielectric layer SDE and the selector level plate SPN are shown.

[0165] Each first electrode 48 may include an interior space and multiple exterior surfaces, and the interior space of the first electrode 48 may include multiple interior surfaces. The exterior surface of the first electrode 48 may include a vertical exterior surface and multiple horizontal exterior surfaces. The interior space of the first electrode 48 may be a three-dimensional space. The dielectric layer 50 may conformally cover the interior and exterior surfaces of the first electrode 48. The second electrode 51 may be disposed in the interior space of the first electrode 48 over the dielectric layer 50. Portions of the exterior surfaces of the first electrode 48 may be electrically connected to the second doped region 47 and the second contact node 46 of the horizontal layer HL.

[0166] The first electrode 48 may have a cylindrical shape. The cylindrical shape of the first electrode 48 may include a cylindrical inner surface and a cylindrical outer surface. Part of the cylindrical outer surface of the first electrode 48 may be electrically connected to the second doped region 47 and the second contact node 46 of the horizontal layer HL. The dielectric layer 50 and the second electrode 51 may be disposed on the cylindrical inner surface of the first electrode 48. The second electrode 51 may extend vertically.

[0167] The first electrode 48 and the second electrode 51 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 48 and the second electrode 51 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 51 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 51 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling an inner space of the first electrode 48, and titanium nitride (TiN) may be used as a second electrode 51 of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0168] The dielectric layer 50 may also be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer 50 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 50 may include a high-k material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The dielectric layer 50 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0169] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode 48 and the dielectric layer 50. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 51 and the dielectric layer 50.

[0170] Figures 30A to 30Cis a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0171] Reference Figure 30A , a stacked body SB10 may be formed on the lower structure 11. The stacked body SB10 may include an alternating stack of first semiconductor layers and second semiconductor layers. For example, the alternating stack may include a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 15' alternately stacked by epitaxial growth. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 15' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4 The first layer 12 or the third layer 14, the single crystal silicon layer 15' may correspond to Figure 4 The fourth floor 15. Figure 4 The stacked body SB is different from the stacked body SB in that the stacked body SB10 is formed by alternating stacking of silicon germanium layers 12 and single crystal silicon layers 15 ′.

[0172] Reference Figure 30B , a hard mask layer pattern 16 may be formed over the stacked body SB10.

[0173] Subsequently, the stacked body SB10 may be etched by using the hard mask layer pattern 16 as an etch barrier. As a result, a plurality of first and second sacrificial vertical openings 17A and 17B may be formed in the stacked body SB10.

[0174] Reference Figure 30C , a preliminary horizontal layer 15A' and a horizontal concave portion 19 can be formed. The preliminary horizontal layer 15A' and the horizontal concave portion 19 can be formed by Figure 30B After removing the silicon germanium layer 12, a process of recessing the single crystal silicon layer 15' may be performed. The preliminary horizontal layer 15A' may correspond to Figure 6 A preliminary horizontal layer 15A.

[0175] In order to recess the silicon germanium layer 12 , a wet etching process or a dry etching process may be performed. The silicon germanium layer 12 may be etched using an etchant or an etching gas that is selective to the silicon germanium layer 12 .

[0176] The process of recessing the single crystal silicon layer 15' to form the preliminary horizontal layer 15A' can use, for example, HSC1 (Hot SC-1). HSC1 can include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of approximately 1:4:20. By using HSC1, the single crystal silicon layer 15' can be selectively etched.

[0177] After forming the preliminary horizontal layer 15A', the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be expanded. When forming the preliminary horizontal layer 15A', the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral "11A"). As a result, the depth of the first sacrificial vertical opening 17A and the second sacrificial vertical opening 17B may be increased.

[0178] Then, you can execute Figures 7 to 29 A series of processes shown.

[0179] Figures 31 to 33 1 is a schematic perspective view showing a semiconductor device according to another embodiment of the present invention. The semiconductor devices M100, M200 and M300 may be similar to Figure 1A and Figure 1B The semiconductor device 100 is described below. Figure 1A and Figure 1B For a detailed description of the constituent elements also appearing in the present invention, reference can be made to the above-described embodiments of the present invention.

[0180] Reference Figure 31 The semiconductor device M100 may include a memory cell array MCA and a selector structure BLS. The selector structure BLS may be disposed above the memory cell array MCA.

[0181] The memory cell array MCA may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1, and the row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0182] Each memory cell MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. Detailed descriptions of the first conductive line BL and the data storage element CAP may also refer to the above embodiments of the present invention.

[0183] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0184] The second conductive line DWL may have a dual structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other with a horizontal layer HL interposed therebetween. Figure 1B As shown, the inter-level dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL.

[0185] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS refer to vertical sidewalls. The flat sidewalls FS may have a linear shape extending in the third direction D3.

[0186] The selector structure BLS may include a selector CP and a plurality of select transistors STR. Each select transistor STR may include a selector-level horizontal layer SHL and a selector-level horizontal conductive line SDWL. The selector-level horizontal conductive line SDWL may have a dual structure. For example, the selector-level horizontal conductive line SDWL may include an upper horizontal line G11 and a lower horizontal line G12 facing each other, with the selector-level horizontal layer SHL interposed therebetween.

[0187] The selector CP may be a pillar plug vertically passing through the selector level horizontal layer SHL. A plurality of vertically stacked selection transistors STR may share one selector CP.

[0188] Reference Figure 32 The semiconductor device M200 may include a memory cell array MCA and a selector structure BLS. The selector structure BLS may be disposed above the memory cell array MCA.

[0189] The memory cell array MCA may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0190] Each memory cell MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. Detailed descriptions of the first conductive line BL and the data storage element CAP may also refer to the above embodiments of the present invention.

[0191] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0192] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed on the horizontal layer HL. Figure 1B As shown, the inter-level dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. According to another embodiment of the present invention, the second conductive line SWL may be disposed below the horizontal layer HL.

[0193] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS refer to vertical sidewalls.

[0194] The selector structure BLS may include a selector CP and a plurality of select transistors STR. Each select transistor STR may include a selector-level horizontal layer SHL and a selector-level horizontal conductive line S-SDWL. The selector-level horizontal conductive line S-SDWL may have a single structure. For example, the selector-level horizontal conductive line S-SDWL may be disposed above the selector-level horizontal layer SHL.

[0195] The selector CP may be a pillar plug vertically passing through the selector level horizontal layer SHL. A plurality of vertically stacked selection transistors STR may share one selector CP.

[0196] According to another embodiment of the present invention, the second conductive line SWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. Figure 3 shown.

[0197] Reference Figure 33 The semiconductor device M300 may include a memory cell array MCA and a selector structure BLS. The selector structure BLS may be disposed above the memory cell array MCA.

[0198] The memory cell array MCA may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may have a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0199] Each memory cell MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. Detailed descriptions of the first conductive line BL and the data storage element CAP may also refer to the above embodiments of the present invention.

[0200] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0201] The second conductive line GAA-WL may have a gate-all-around structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 and surround the horizontal layer HL. An inter-level dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The inter-level dielectric layer GD may surround each horizontal layer HL.

[0202] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS refer to vertical sidewalls.

[0203] The selector structure BLS may include a selector CP and a plurality of selection transistors STR. Each selection transistor STR may include a selector-level horizontal layer SHL and a selector-level horizontal conductive line GAA-SDWL. The selector-level horizontal conductive line GAA-SDWL may be a gate-all-around structure GAA. For example, the selector-level horizontal conductive line GAA-SDWL may extend in a third direction D3 and surround the selector-level horizontal layer SHL. A selector-level inter-level dielectric layer SGD may be formed between the selector-level horizontal layer SHL and the selector-level horizontal conductive line GAA-SDWL. The selector-level inter-level dielectric layer SGD may surround each selector-level horizontal layer SHL.

[0204] The selector CP may be a pillar plug vertically passing through the selector level horizontal layer SHL. A plurality of vertically stacked selection transistors STR may share one selector CP.

[0205] According to this embodiment of the present invention, the semiconductor device may include: a bit line extending vertically in a first direction; a memory cell array including a plurality of horizontal layers vertically stacked in the first direction and sharing the bit line; and a selector structure arranged at a higher level than the memory cell array and coupled to the bit line, wherein the selector structure may include: a plurality of selector-level horizontal layers coupled to the bit line, vertically stacked in the first direction, and extending horizontally in a second direction intersecting the first direction; a selector-level word line extending in a third direction intersecting the selector-level horizontal layers; and a column-type selector vertically passing through the selector-level horizontal layers.

[0206] According to this embodiment of the present invention, the semiconductor device may include: a bit line extending vertically in a first direction; a memory cell array including a plurality of cell transistors vertically stacked in the first direction and sharing the bit line; and a selector structure operably coupled to the bit line, wherein the selector structure may include: a plurality of selection transistors coupled to the bit line and vertically stacked in the first direction; and a columnar selector commonly coupled to the selection transistors.

[0207] The method for manufacturing a semiconductor device according to this embodiment of the present invention may include: forming a stack by stacking cell-level horizontal layers and selector-level horizontal layers; forming a horizontal word line intersecting each cell-level horizontal layer; forming a selector-level word line intersecting each selector-level horizontal layer; forming a vertical bit line commonly coupled to the cell-level horizontal layer and the selector-level horizontal layer; forming a data storage element coupled to the cell-level horizontal layer; forming a selector-level contact hole by etching the selector-level horizontal layer; and forming a column-type selector in the selector-level contact hole.

[0208] The method for manufacturing a semiconductor device according to this embodiment of the present invention may include: forming a vertically extending bit line above a lower structure; forming a memory cell array, the memory cell array including a plurality of cell transistors vertically stacked and sharing the bit line; forming a bit line selector including a plurality of selection transistors, the plurality of selection transistors being arranged at a level higher than the memory cell array; and forming a selector level plug commonly coupled to the selection transistors.

[0209] According to the embodiments of the present invention, a sensing margin can be increased by forming a three-dimensional memory cell array and a selector in a multi-cell structure, thereby improving a yield rate.

[0210] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a common conductive line extending in a first direction; A memory cell array comprising a plurality of horizontal layers stacked in the first direction and sharing the common conductive line; as well as a selector structure operably coupled to the common conductive line, Wherein, the selector structure includes: a plurality of selection transistors stacked in the first direction; and The selector is commonly coupled to the plurality of selection transistors.

2. The semiconductor device according to claim 1, wherein The plurality of selection transistors are commonly coupled to the common conductive line and the selector.

3. The semiconductor device according to claim 1, wherein The selector includes semiconductor material, metal, metal silicide, metal nitride or a combination thereof.

4. The semiconductor device according to claim 1, wherein: The selector structure is disposed at a higher level than the memory cell array.

5. The semiconductor device according to claim 1, wherein Each of the selection transistors comprises: a selector hierarchy horizontal layer extending horizontally in a second direction intersecting the first direction; and A selector level horizontal conductive line extends horizontally in a third direction intersecting the selector level horizontal layer.

6. The semiconductor device according to claim 5, wherein: The selector level horizontal layer and the horizontal layer include the same material.

7. The semiconductor device according to claim 5, wherein: The selector level horizontal layer and the horizontal layer include single crystal silicon, polycrystalline silicon or oxide semiconductor material.

8. The semiconductor device according to claim 5, wherein: The selector includes a columnar structure that passes through the selector hierarchy levels.

9. The semiconductor device according to claim 5, wherein: The memory cell array further includes a plurality of horizontal conductive lines extending in the third direction intersecting each of the horizontal layers.

10. The semiconductor device according to claim 9, wherein Each of the horizontal conductive line and the selector-level horizontal conductive line includes a single structure, a double structure, or a gate-all-around structure.

11. The semiconductor device according to claim 1, wherein The memory cell array further includes a plurality of data storage elements respectively coupled to the second side of the horizontal layer.

12. The semiconductor device according to claim 11, wherein Each of the data storage elements comprises: a first electrode having a cylindrical shape; a dielectric layer over the first electrode; and a second electrode on the dielectric layer, The dielectric layer and the second electrode extend to be horizontally spaced apart from the selector.

13. The semiconductor device according to claim 1, wherein The common conductive line is a bit line, and the selector is a bit line selector.

14. A method for manufacturing a semiconductor device, the method comprising: forming a stacked body by sequentially forming a lower-level stacked body and an upper-level stacked body; forming a conductive line passing through the lower-level stack and the upper-level stack; forming a memory cell array in the lower level stack, the memory cell array comprising a plurality of horizontal layers commonly coupled to the conductive lines; forming a plurality of select transistors in the upper level stack, the plurality of select transistors comprising a plurality of selector level horizontal layers commonly coupled to the conductive line; as well as A selector is formed that passes through the plurality of selector hierarchy levels in common.

15. The method according to claim 14, wherein: Forming the selector comprises: forming a selector level contact hole by etching the plurality of selector level horizontal layers; and The selector is formed in the selector level contact hole.

16. The method according to claim 14, wherein: The plurality of selector level horizontal layers are stacked in a direction in which the conductive lines extend.

17. The method according to claim 14, wherein: The selector includes semiconductor material, metal, metal silicide, metal nitride or a combination thereof.

18. The method according to claim 14, wherein: Forming the selection transistor includes: forming said selector hierarchy level layers; forming a selector level inter-level dielectric layer over the selector level horizontal layer; and A plurality of selector-level horizontal conductive lines extending in directions respectively intersecting the selector-level horizontal layers are formed.

19. The method according to claim 14, wherein: The horizontal length of the selector level horizontal layer is greater than the horizontal length of the horizontal layer.

20. The method according to claim 14, wherein: The selector level horizontal layer and the horizontal layer include single crystal silicon, polycrystalline silicon or oxide semiconductor material.

21. The method according to claim 14, wherein: Forming the memory cell array comprises: forming a plurality of horizontal conductive lines extending in directions respectively intersecting the horizontal layers; and A plurality of data storage elements are formed that are respectively coupled to the horizontal layers.

22. The method according to claim 14, wherein: Each of the lower-level stack and the upper-level stack includes: A stack of silicon germanium layers and single crystal silicon layers.

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