Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the same are provided. The semiconductor device may include a substrate, a plurality of cell strings perpendicular to an upper surface of the substrate, and bit lines connected to at least six of the cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to an upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line. A first one of the first to fourth ground selection transistors may have a first threshold voltage distribution, and a second one of the first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different than the first threshold voltage distribution.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and an electronic system including the same. Background Art

[0002] In an electronic system requiring data storage, a semiconductor device capable of storing high-capacity data may be required. Therefore, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including a three-dimensionally arranged storage cell rather than a two-dimensionally arranged storage cell has been proposed. Summary of the invention

[0003] Some example embodiments provide a semiconductor device having improved reliability and integration.

[0004] Some example embodiments provide an electronic system including a semiconductor device.

[0005] The present disclosure is not limited to the above-mentioned aspects, and other aspects not mentioned will be clearly understood from the following description by those skilled in the art.

[0006] According to example embodiments, a semiconductor device may include: a substrate; a plurality of cell strings arranged perpendicular to an upper surface of the substrate; and a bit line connected to at least six of the plurality of cell strings. Each of the plurality of cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. Based on the string selection transistors and the first to fourth ground selection transistors in each of the plurality of cell strings, the plurality of cell strings may provide a plurality of string selection transistors, a plurality of first ground selection transistors, a plurality of second ground selection transistors, a plurality of third ground selection transistors, and a plurality of fourth ground selection transistors. The plurality of string selection transistors of the plurality of cell strings may be electrically separated from each other. The plurality of first ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of second ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of third ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of fourth ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The first of the plurality of first to fourth ground selection transistors may have a first threshold voltage distribution. The second of the plurality of first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.

[0007] According to example embodiments, a semiconductor device may include: a substrate; a plurality of cell strings, perpendicular to an upper surface of the substrate; and a bit line, connected to at least six of the plurality of cell strings. Each of the plurality of cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, a plurality of ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. In each of the plurality of cell strings, the plurality of ground selection transistors may include a first ground selection transistor having a first threshold voltage distribution, a second ground selection transistor having a second threshold voltage distribution, and a third ground selection transistor having a third threshold voltage distribution. The first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution may be different from each other.

[0008] According to example embodiments, an electronic system may include: a semiconductor device including a peripheral circuit structure and a cell array structure on the peripheral circuit structure; and a controller electrically connected to the semiconductor device through an input / output pad and configured to control the semiconductor device. The cell array structure may include a substrate, a plurality of cell strings arranged perpendicular to an upper surface of the substrate, and a bit line connected to at least six of the plurality of cell strings. Each of the plurality of cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. Based on the string selection transistors and the first to fourth ground selection transistors in each of the plurality of cell strings, the plurality of cell strings may provide a plurality of string selection transistors, a plurality of first ground selection transistors, a plurality of second ground selection transistors, a plurality of third ground selection transistors, and a plurality of fourth ground selection transistors. The plurality of string selection transistors of the plurality of cell strings may be electrically separated from each other. The plurality of first ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of second ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of third ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The plurality of fourth ground selection transistors in the plurality of cell strings may be configured to be controlled in common. The first of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors may have a first threshold voltage distribution. The second of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.

[0009] Specific details of other example embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 2 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 3 and Figure 4 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the inventive concept.

[0014] Figure 5 is a schematic block diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 6 is a circuit diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0016] Fig. 7A and Figure 7B is a plan view illustrating a portion of a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0017] Fig. 8A is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0018] Figure 8B is an enlarged view of a portion of a semiconductor device according to an embodiment of the inventive concept.

[0019] Fig. 9 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation.

[0020] Fig.10 is a diagram illustrating threshold voltage distributions of ground selection transistors in a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0021] Fig.11 It is shown Fig. 9 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0022] Fig.12is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation.

[0023] Fig.13 It is shown Fig.12 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0024] Fig.14 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation.

[0025] Fig.15 is a diagram illustrating threshold voltage distributions of ground selection transistors in a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0026] Fig.16 It is shown Fig.14 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0027] Fig.17 is a plan view illustrating a portion of a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0028] Fig.18 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0029] Fig.19 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation.

[0030] Fig. 20 It is shown Fig.19 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0031] Fig.21 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation.

[0032] Fig. 22 It is shown Fig.21 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0033] Fig.23 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0034] Hereinafter, a semiconductor device and an electronic system including the same according to embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an embodiment of the inventive concept.

[0036] Reference Figure 1 , an electronic system 1000 according to some embodiments of the inventive concept may include a semiconductor device 1100 and a controller 1200 electrically connected to each other. The electronic system 1000 may be or may include a storage device including one or more semiconductor devices 1100 and / or an electronic device including the storage device. For example, the electronic system 1000 may be or may include at least one of a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system, in which at least one semiconductor device 1100 is provided.

[0037] The semiconductor device 1100 may be a nonvolatile memory device, and may be, for example, a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. According to some embodiments, the first structure 1100F may alternatively be disposed on a side of the second structure 1100S.

[0038] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0039] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to various embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously changed.

[0040] In an embodiment, the upper transistors UT1 and UT2 may include at least one string selection transistor, and the lower transistors LT1 and LT2 may include at least one ground selection transistor. The gate lower lines LL1 and LL2 may be used as gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be used as gate electrodes of the memory cell transistors MCT, respectively, and the gate upper lines UL1 and UL2 may be used as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0041] The memory cells MCT of each memory cell string CSTR may be controlled by a back gate line.

[0042] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F into the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from the first structure 1100F into the second structure 1100S.

[0043] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may be configured to perform a control operation on at least one selected memory cell transistor among the memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101, which is electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection line 1135, which is provided in the first structure 1100F and extends into the second structure 1100S.

[0044] Although not shown in the drawings, the first structure 1100F may include a voltage generator (not shown). The voltage generator may generate at least one of a program voltage, a read voltage, a pass voltage, a verification voltage, etc. used or required to operate the memory cell string CSTR. Here, the program voltage may be a relatively high voltage (e.g., 20V to 40V) compared to any one of the read voltage, the pass voltage, and the verification voltage.

[0045] In an embodiment, the first structure 1100F may include a high voltage transistor (e.g., a transistor having a high threshold voltage) and a low voltage transistor (e.g., a transistor having a lower threshold voltage). The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high voltage transistor that can withstand a high voltage (e.g., a programming voltage) applied to the word line WL during a programming operation or operate at a high voltage (e.g., a programming voltage) applied to the word line WL. The page buffer 1120 may also be a high voltage transistor that can withstand a high voltage.

[0046] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the semiconductor devices 1100 .

[0047] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on specific firmware and / or software and / or hardware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor device 1100. The NAND interface 1221 may be used to send and receive control commands for controlling the semiconductor device 1100 and / or data to be written to or read from the memory cell transistors MCT of the semiconductor device 1100, etc. The host interface 1230 may be configured to allow communication between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0048] Figure 2 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an embodiment of the inventive concept.

[0049] Reference Figure 2 , an electronic system 2000 according to some embodiments of the inventive concept may include a main board 2001, and a controller 2002, at least one semiconductor package 2003, and a DRAM 2004 mounted on the main board 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 and to each other through an interconnection pattern 2005 formed in the main board 2001.

[0050] The mainboard 2001 may include a connector 2006 including a plurality of pins connected to an external host. In the connector 2006, the number and / or arrangement of the pins may depend on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to one of the interfaces (such as a universal serial bus (USB), a peripheral component interconnect (PCI-Express), a serial advanced technology attachment (SATA), a universal flash memory (UFS) M-Phy, etc.). In some embodiments, the electronic system 2000 may be driven by power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power (not shown) supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0051] The controller 2002 may be configured to control a write operation or a read operation on the semiconductor package 2003 and improve an operation speed of the electronic system 2000 .

[0052] DRAM 2004 may be or may include a buffer memory that alleviates or helps alleviate technical difficulties caused by the speed difference between semiconductor package 2003 used as a data storage device and an external host. In some embodiments, DRAM 2004 in electronic system 2000 may be used as a high-speed cache memory and may provide a storage space to temporarily store data during a control operation of semiconductor package 2003. When electronic system 2000 includes DRAM 2004, controller 2002 may include a DRAM controller that controls DRAM 2004 in addition to a NAND controller that controls semiconductor package 2003; alternatively, there may be one controller that controls DRAM 2004 and semiconductor package 2003.

[0053] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on respective bottom surfaces of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 disposed on the package substrate 2100 to cover the semiconductor chip 2200 and the connection structure 2400.

[0054] The package substrate 2100 may be or may include a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 1 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack 3210 and a vertical structure 3220. Each semiconductor chip 2200 may include a semiconductor device according to some embodiments of the inventive concept, which will be described below.

[0055] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the package on-pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the form of a bonding wire, and may be electrically connected to the package on-pad 2130 of the package substrate 2100. Alternatively or additionally, in some example embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other by a connection structure including a through-silicon via (TSV) instead of by a connection structure 2400 provided in the form of a bonding wire.

[0056] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate independent of the main board 2001 and may be connected to each other through interconnection lines provided in the interposer substrate.

[0057] Figure 3 and Figure 4 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 3 and Figure 4 is along Figure 2 A cross-sectional view taken along line II' shows Figure 2 Embodiments of semiconductor packages.

[0058] Reference Figure 3 In the semiconductor package 2003, the package substrate 2100 may be or may include a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, a package substrate main body portion 2120 disposed on a top surface (eg, Figure 2The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the interconnection pattern 2005 provided in the main board 2001 of the electronic system 2000 through the conductive connection portion 2800, as shown in FIG. Figure 2 as shown in .

[0059] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region in which a peripheral line 3110 is provided. The second structure 3200 may include a source structure 3205, a stacked structure 3210 on the source structure 3205, a vertical structure 3220 and a separation structure 3230 penetrating the stacked structure 3210, a bit line 3240 electrically connected to the vertical structure 3220, and a (e.g., Figure 1 Each of the first and second structures 3100 and 3200 and the semiconductor chip 2200 may further include a separation structure to be described below.

[0060] Each semiconductor chip 2200 may include a penetration line 3245 electrically connected to the peripheral line 3110 of the first structure 3100 and extending into the second structure 3200. The penetration line 3245 may be disposed outside the stacked structure 3210, and in some embodiments, the penetration line 3245 may be provided to further penetrate the stacked structure 3210. Each semiconductor chip 2200 may also include an input / output interconnection line 3265 electrically connected to the peripheral line 3110 of the first structure 3100 and extending in the second structure 3200, and an input / output pad 2210 electrically connected to the input / output interconnection line 3265. For example, the input / output interconnection line 3265 may extend from the first structure 3100 through the second structure 3200 in a vertical direction to contact the input / output pad 2210.

[0061] Reference Figure 4 In the semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 provided on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner.

[0062] The first structure 4100 may include a peripheral circuit region in which a peripheral line 4110 and a first junction structure 4150 are provided. The second structure 4200 may include a source structure 4205, a stack structure 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 and a separation structure 4230 penetrating the stack structure 4210, and (for example, Figure 1 The second junction structure 4250 of the word line WL. For example, the second junction structure 4250 may be electrically connected to the bit line 4240 of the vertical structure 4220 and electrically connected to (for example, Figure 1 The cell contact plugs of the word lines WL are electrically connected to the vertical structures 4220 and (for example, Figure 1 The first junction structure 4150 of the first structure 4100 may contact and be coupled to the second junction structure 4250 of the second structure 4200. A coupling portion of the first junction structure 4150 and the second junction structure 4250 may be formed of or include, for example, copper (Cu); however, example embodiments are not limited thereto.

[0063] Each of the first structure 4100, the second structure 4200 and the semiconductor chip 2200a may further include a source structure, as will be described below with reference to some embodiments. Each semiconductor chip 2200a may further include (for example, Figure 2 The semiconductor chip 2200a may further include an input / output pad 2210 and an input / output interconnection line 4265 below the input / output pad 2210. The input / output interconnection line 4265 may be electrically connected to the peripheral line 4110 of the first structure 4100.

[0064] Figure 3 The semiconductor chip 2200 and Figure 4 The semiconductor chips 2200a may be electrically connected to each other through a connection structure 2400 provided in the form of a bonding wire. Figure 3 The semiconductor chip 2200 and Figure 4 The semiconductor chips in the same semiconductor package of the semiconductor chip 2200a may be electrically connected to each other through a connection structure including through silicon vias (TSVs).

[0065] Figure 5 is a schematic block diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0066] Reference Figure 5, a semiconductor device according to an embodiment may include a memory cell array and a peripheral circuit for controlling the memory cell array. The peripheral circuit may include a decoder 1110 (refer to Figure 1 ), page buffer 1120 (refer to Figure 1 ) and logic circuit 1130 (refer to Figure 1 ).

[0067] The memory cell array may include a plurality of memory blocks BLK1, BLK2, ..., BLKn, where "n" is a positive integer. Each of the memory blocks BLK1, BLK2, ..., BLKn may include a stacked structure including a conductive pattern stacked in a third direction D3 on a plane defined by a first direction D1 and a second direction D2. The stacked structure may be connected to a plurality of vertical structures (vertical columns) to form a three-dimensionally arranged memory cell. In addition, each of the memory blocks BLK1, BLK2, ..., BLKn may include a bit line electrically connected to the memory cell. The memory blocks BLK1, BLK2, ..., BLKn will refer to Figure 6 Described in detail.

[0068] Figure 6 is a circuit diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the inventive concept.

[0069] Reference Figure 6 , the memory cell array may include a first memory block BLK1 and a second memory block BLK2. Each of the first memory block BLK1 and the second memory block BLK2 may include a plurality of pages, and each page may include a plurality of memory cells MC. For example, each of the memory blocks BLK1 and BLK2 may be a unit of erasure, and a page may be a unit of writing and reading. Each memory cell MC may store one or more bits. In detail, each memory cell MC is a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

[0070] Each of the first storage block BLK1 and the second storage block BLK2 has a plurality of word lines WL, a plurality of string selection lines SSL0 to SSL5, a plurality of ground selection lines GSL0 to GSL3, and a plurality of bit lines BL1, BL2, and BL3. In addition, each of the first storage block BLK1 and the second storage block BLK2 has a plurality of cell strings CS1, CS2, CS3, CS4, CS5, and CS6 arranged in a first direction D1 and a second direction D2 intersecting each other. The cell strings CS1 to CS6 may be connected to the bit lines BL1 to BL3 in parallel, respectively. The two-dimensionally arranged cell strings CS1 to CS6 may be connected in common to a common source line CSL.

[0071] Each of the cell strings CS1 to CS6 may include a plurality of memory cells MC connected in series in a third direction D3 perpendicular to the first direction D1 and the second direction D2. In addition, each of the cell strings CS1 to CS6 may include a string selection transistor SST connected between corresponding bit lines BL1, BL2, and BL3 and the memory cells MC, and a plurality of ground selection transistors GST0, GST1, GST2, and GST3 connected in series between a common source line CSL and the memory cells MC.

[0072] According to an embodiment, the number of ground selection transistors GST0, GST1, GST2 and GST3 connected in series in each cell string CS1 to CS6 can be variously changed depending on the number of cell strings CS1 to CS6 connected in parallel to one bit line BL1, BL2 and BL3 (that is, the number of string selection lines SSL0 to SSL5).

[0073] As an example, the bit lines BL1 to BL3 may include a first bit line BL1, a second bit line BL2, and a third bit line BL3, and the cell strings CS1 to CS6 may include first to sixth cell strings CS1 to CS6 connected to each of the bit lines BL1, BL2, and BL3. The inventive concept is not limited thereto, and the number of cell strings connected to each bit line may be variously changed.

[0074] Each of the first and second memory blocks BLK1 and BLK2 may include six first to sixth string selection lines SSL0 to SSL5 electrically separated from each other. Each of the first to sixth string selection lines SSL0 to SSL5 may be commonly connected to gate electrodes of string selection transistors SST arranged in the first direction D1.

[0075] The memory cells MC may be controlled by a plurality of word lines WL0-WLn, respectively. In each of the first memory block BLK1 and the second memory block BLK2, the gate electrodes of the memory cells MC located at the same level from the common source line CSL may be commonly connected to one of the word lines WL0 to WLn. In addition, each memory cell MC may include a data storage element. That is, in each of the first memory block BLK1 and the second memory block BLK2, the memory cells MC located at the same height among the memory cells MC of the first cell string CS1 to the sixth cell string CS6 may share the same word line (one of WL0 to WLn).

[0076] In an embodiment, each of the first to sixth cell strings CS1 to CS6 may include 2, 3, 4, 5, or 6 or more ground selection transistors. In addition, in each of the cell strings CS1 to CS6, the plurality of ground selection transistors GST0, GST1, GST2, and GST3 may have different threshold voltages.

[0077] In each of the first and second memory blocks BLK1 and BLK2, string selection transistors SST of the first to sixth cell strings CS1 to CS6 may be controlled by first to sixth string selection lines SSL0 to SSL5. That is, string selection transistors SST of the first to sixth cell strings CS1 to CS6 connected to each of the bit lines BL1 to BL3 may be electrically separated from each other.

[0078] In each of the first and second memory blocks BLK1 and BLK2 , memory cells MC located at the same height among the memory cells MC of the first to sixth cell strings CS1 to CS6 may share the same word line (one of WL0 to WLn).

[0079] Among the ground selection transistors GST0 to GST3 , the ground selection transistors GST0 , GST1 , GST2 , or GST3 located at the same level may be connected to the same ground selection line GSL0 , GSL1 , GSL2 , or GSL3 .

[0080] For example, in each of the first storage block BLK1 and the second storage block BLK2, the first ground selection transistor GST0 of the first cell string CS1 to the sixth cell string CS6 can be commonly connected to the first ground selection line GSL0, the second ground selection transistor GST1 can be commonly connected to the second ground selection line GSL1, the third ground selection transistor GST2 can be commonly connected to the third ground selection line GSL2, and the fourth ground selection transistor GST3 can be connected to the fourth ground selection line GSL3.

[0081] Fig. 7A and Figure 7B is a plan view illustrating a portion of a memory cell array of a semiconductor device according to an embodiment of the inventive concept. Fig. 8A is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept. Figure 8B is an enlarged view of a portion of a semiconductor device according to an embodiment of the inventive concept.

[0082] Reference Fig. 7A , Figure 7B and Fig. 8A The substrate 100 may include a cell array region CAR and a connection region CNR. The connection region CNR may be adjacent to the cell array region CAR in a first direction D1 parallel to the upper surface of the substrate 100.

[0083] The substrate 100 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The substrate 100 may include a semiconductor doped with impurities and / or an intrinsic semiconductor without doping. The substrate 100 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. As another example, the substrate 100 may be formed of an insulating material such as silicon oxide.

[0084] The separation structures SS may extend from the cell array region CAR to the connection region CNR in parallel with each other in a first direction D1 on the substrate 100. The separation structures SS may be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 may be parallel to the upper surface of the substrate 100.

[0085] Each separation structure SS may have a single-layer or multi-layer structure. The separation structure SS may include an insulating layer covering both walls of the stack structure ST. The separation structure SS may include at least one of silicon oxide, silicon nitride, or polysilicon.

[0086] The width of the lower portion of the separation structure SS may be smaller than the width of the upper portion thereof. The upper surface of the separation structure SS may be located at a higher level than the upper surface of the vertical structure VS. The upper surface of the separation structure SS may be located at substantially the same level as the upper surface of the upper insulating layer 110.

[0087] Reference Figure 7B , at least one dummy separation structure DSS may penetrate the stack structure ST in the connection region CNR. In the first direction D1, the length of the dummy separation structure DSS may be less than the length of the separation structure SS. The dummy separation structure DSS may be spaced apart from the string selection lines SSL0 to SSL5. Although one dummy separation structure DSS is shown in the drawings, the inventive concept is not limited thereto, and a plurality of dummy separation structures DSS may be provided in the connection region CNR.

[0088] According to an embodiment, the stacked structure ST may be disposed between adjacent separation structures SS. The stacked structure ST may extend from the cell array region CAR to the connection region CNR in the first direction D1. The stacked structure ST may have a step structure on the connection region CNR. Alternatively, the stacked structure ST may have a uniform thickness in the cell array region CAR and the connection region CNR.

[0089] The stack structure ST may include a ground selection structure GSLS, a word line structure WLS, and string selection structures SSL0 to SSL5 sequentially stacked on the substrate 100 .

[0090] The ground selection structure GSLS may include a plurality of ground selection lines GSL0 to GSL3 vertically stacked on the substrate 100 with an interlayer insulating layer ILD interposed therebetween. Also, the ground selection structure GSLS may include common ground selection lines CGSLu and CGSLd between the substrate 100 and the first ground selection line GSL0.

[0091] The word line structure WLS may include a plurality of word lines WL0 to WLn (wherein "n" is a positive integer) vertically stacked on the ground selection structure GSLS, and an interlayer insulating layer ILD is interposed between the plurality of word lines WL0 to WLn. The string selection structure may include a plurality of string selection lines SSL0 to SSL5 horizontally spaced apart from each other on the word line structure WLS. The string selection lines SSL0 to SSL5 may be spaced apart from each other in the second direction D2 by a separation insulating pattern SIP provided on the word line structure WLS.

[0092] As an example, the stack structure ST may include first to fourth ground selection lines GSL0 to GSL3 stacked vertically, and first to sixth string selection lines SSL0 to SSL5 spaced horizontally apart from each other. When viewed in a plan view, the first to sixth string selection lines SSL0 to SSL5 may overlap the first to fourth ground selection lines GSL0 to GSL3, respectively. In the second direction D2, the width of each of the word lines WL0 to WLn may be greater than the sum of the widths of the string selection lines SSL0 to SSL5. In the second direction D2, the width of each of the ground selection lines GSL0 to GSL3 may be greater than the sum of the widths of the string selection lines SSL0 to SSL5.

[0093] Each of the first to fourth ground selection lines GSL0 to GSL3 may not be physically separated from the separation structure SS, and may be a single layer in a line form.

[0094] In an embodiment, the upper common ground selection line CGSLu and the lower common ground selection line CGSLd, the ground selection lines GSL0 to GSL3, the word lines WL0 to WLn, and the string selection lines SSL0 to SSL5 may include at least one selected from, for example, a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). The interlayer dielectric layer ILD may include a silicon oxide layer and / or a low dielectric layer.

[0095] A plurality of vertical structures VS may penetrate the stacked structure ST in the cell array region CAR. When viewed in a plan view, the vertical structures VS may be arranged in one direction or in a zigzag form. As an example, the vertical structures VS arranged in the first direction D1 may form a column, and a plurality of columns may be arranged to be staggered with each other in the second direction D2.

[0096] Each vertical structure VS may have a maximum width at the upper surface of the uppermost insulating layer ILD. Each vertical structure VS may have a minimum width at its bottom layer, and the minimum width may be smaller than the maximum width. Alternatively, each vertical structure VS may have a width at its upper layer and a width at its bottom layer, and the width at its upper layer and the width at its bottom layer are substantially the same. The distance between adjacent vertical structures VS may be smaller than the maximum width of each vertical structure VS.

[0097] For details, refer to Figure 8B , each of the vertical structures VS may include a vertical semiconductor pattern VP and a data storage pattern DSP surrounding a sidewall of the vertical semiconductor pattern VP, and a gap-filling insulating pattern VI inside the vertical semiconductor pattern VP.

[0098] In detail, the vertical semiconductor pattern VP may have a tube shape or a macaroni shape having a closed bottom. The vertical semiconductor pattern VP may have a U-shape, and the inside thereof may be filled with a gap-filling insulating pattern VI. A bit line conductive pad may be formed on an upper end of the vertical semiconductor pattern VP, and the bit line conductive pad may be formed of a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material.

[0099] The vertical semiconductor pattern VP may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern VP including the semiconductor material may serve as a channel of a memory cell constituting a cell string.

[0100] The data storage pattern DSP may extend in the third direction D3 to surround the sidewall of each vertical semiconductor pattern VP. The data storage pattern DSP may be in the form of a pipe with the top and bottom open or in a macaroni shape. The data storage pattern DSP may be formed by one thin layer or a plurality of thin layers. In an embodiment of the inventive concept, the data storage pattern DSP may be a data storage layer of a NAND flash memory device, and may include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BLK sequentially stacked on the sidewall of the vertical semiconductor pattern VP. For example, the charge storage layer CIL may be a trap insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots. In detail, the charge storage layer CIL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer (Si-rich nitride), nanocrystalline silicon (nanocrystalline Si), and a stacked trap layer. The tunnel insulating layer TIL may be one of the materials having a larger band gap than the charge storage layer CIL, and the blocking insulating layer BLK may be a high-k dielectric layer, such as an aluminum oxide layer or a hafnium oxide layer.

[0101] A horizontal insulating pattern HP may be provided between one sidewall of the conductive patterns GSL and WL and the data storage pattern DSP. The horizontal insulating pattern HP may extend on one sidewall of the conductive patterns GSL0, GSL1, GSL2, DWL, CGSLu, and CGSLd to upper and lower surfaces thereof. The horizontal insulating pattern HP may include, for example, a silicon oxide layer and / or a high-k dielectric layer.

[0102] Refer again Fig. 7A and Fig. 8A The bit lines BL1 and BL2 may cross the stack structure ST on the cell array region CAR. The bit lines BL1 and BL2 are spaced apart from each other in the first direction D1 on the stack structure ST and may extend in the second direction D2.

[0103] In detail, the bit lines BL1 and BL2 may be disposed on the upper insulating layer 110. The bit lines BL1 and BL2 may be arranged at a constant pitch in the first direction D1.

[0104] Each of the two bit lines BL1 and BL2 may be disposed on the vertical structures VS arranged in a row along the second direction D2. That is, a pair of bit lines BL1 and BL2 may be disposed on an upper portion of each vertical structure VS. The line width of each of the bit lines BL1 and BL2 may be less than half of the diameter of each vertical structure VS.

[0105] The bit lines BL1 and BL2 may include a first bit line BL1 and a second bit line BL2 disposed on each vertical structure VS, and the first bit line BL1 and the second bit line BL2 may be repeatedly arranged in the first direction D1 .

[0106] Each of the first bit lines BL1 may be electrically connected to the vertical structures VS of odd-numbered columns, and each of the second bit lines BL2 may be electrically connected to the vertical structures VS of even-numbered columns.

[0107] Common source line CSL ( Figure 6 The common source line may be an impurity region (eg, an n-type impurity region (eg, arsenic (As) or phosphorus (P) region)) provided in the substrate 100. In this case, the common source line may extend in the first direction D1 under the separation structure SS.

[0108] Alternatively, as the common source line CSL ( Figure 6 ), a common source structure may be provided between the substrate 100 and the stacked structure ST.

[0109] For details, refer to Figure 8B , the source structure CST may include a source pattern SC and a support pattern SP on the source pattern SC. The source structure CST may be parallel to the upper surface of the substrate 100 and may extend in a first direction D1 parallel to the stack structure ST.

[0110] The source pattern SC may contact a portion of a sidewall of the vertical semiconductor pattern VP of each vertical structure VS. The sidewall of the support pattern SP may contact the data storage pattern DSP. The source pattern SC may include a sidewall portion disposed between the sidewall of the vertical semiconductor pattern VP and the support pattern SP and between the sidewall of the vertical semiconductor pattern VP and the substrate 100.

[0111] The source pattern SC may be formed of a semiconductor material doped with a dopant having a first conductivity type, such as phosphorus (P) or arsenic (As). As an example, the source pattern may be formed of a polysilicon layer doped with an n-type dopant.

[0112] The support pattern SP may cover the upper surface of the source pattern SC, and a portion of the support pattern SP may penetrate the source pattern SC and may contact the substrate 100. The support pattern SP may include a semiconductor doped with a dopant having a first conductivity type (e.g., n-type) and / or an undoped intrinsic semiconductor. The concentration of the n-type dopant in the support pattern SP may be lower than the concentration of the n-type dopant in the source pattern SC.

[0113] Fig. 9 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation. Fig.10 is a diagram illustrating threshold voltage distributions of ground selection transistors in a memory cell array of a semiconductor device according to an embodiment of the inventive concept. Fig.11 It is shown Fig. 90047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0114] Reference Fig. 9 , in each memory block BLK1 or BLK2 ( Figure 6 ), each bit line BL may include first to sixth cell strings CS1 to CS6.

[0115] Each of the first to sixth cell strings CS1 to CS6 may include a string selection transistor SST, a plurality of memory cells MC connected in series, a plurality of ground selection transistors GST0 , GST1 , GST2 , and GST3 connected in series, and common ground selection transistors CGSTu and CGSTd.

[0116] The string selection transistors SST of the first to sixth cell strings CS1 to CS6 may be controlled by first to sixth string selection lines SSL0 to SSL5 , respectively.

[0117] Each of the first to sixth cell strings CS1 to CS6 may include a first ground selection transistor GST0, a second ground selection transistor GST1, a third ground selection transistor GST2, and a fourth ground selection transistor GST3. In the first to sixth cell strings CS1 to CS6, the first ground selection transistor GST0 located at the same level may be controlled by one first ground selection line GSL0. The second ground selection transistor GST1 located at the same level may be controlled by one second ground selection line GSL1. The third ground selection transistor GST2 located at the same level may be controlled by one third ground selection line GSL2. The fourth ground selection transistor GST3 located at the same level may be controlled by one fourth ground selection line GSL3.

[0118] Memory cells MC of first to sixth cell strings CS1 to CS6 may be controlled by word lines WL0 to WLn. Common ground selection transistors CGSTu and CGSTd of first to sixth cell strings CS1 to CS6 may be controlled by upper and lower common ground selection lines CGSLu and CGSLd.

[0119] Reference Fig. 9 and Fig.10 , the first, second, third, and fourth ground selection transistors GST0, GST1, GST2, and GST3 in each of the first to sixth cell strings CS1 to CS6 may have the first threshold voltage distribution Vth1 or the second threshold voltage distribution Vth2.

[0120] According to an embodiment, the first to fourth ground selection transistors GST0 to GST3 of each cell string may be programmed to have the first threshold voltage distribution Vth1 or the second threshold voltage distribution Vth2, such as Fig.11 Here, the second threshold voltage distribution Vth2 may be at a higher level than the first threshold voltage distribution Vth1.

[0121] As an example, before the first to fourth ground selection transistors GST0 to GST3 are programmed, the first to fourth ground selection transistors GST0 to GST3 connected to the first to fourth ground selection lines GSL0 to GSL3 may have a first threshold voltage distribution Vth1, and then, in each cell string CS1 to CS6, a program voltage may be applied to a selected one of the first to fourth ground selection lines GSL0 to GSL3, and by applying a pass voltage to the other ground selection lines, the first to fourth ground selection transistors GST0 to GST3 may be selectively programmed. The selected first to fourth ground selection transistors GST0 to GST3 may have a second threshold voltage distribution Vth2 at a level higher than the first threshold voltage distribution Vth1.

[0122] Reference Fig. 9 , Fig.10 and Fig.11 , in the first cell string CS1 , the first and second ground selection transistors GST0 and GST1 may have the first threshold voltage distribution Vth1 , and the third and fourth ground selection transistors GST2 and GST3 may have the second threshold voltage distribution Vth2 .

[0123] In the second cell string CS2 , the first and third ground selection transistors GST0 and GST2 may have a first threshold voltage distribution Vth1 , and the second and fourth ground selection transistors GST1 and GST3 may have a second threshold voltage distribution Vth2 .

[0124] In the third cell string CS3 , the second and third ground selection transistors GST1 and GST2 may have the first threshold voltage distribution Vth1 , and the first and fourth ground selection transistors GST0 and GST3 may have the second threshold voltage distribution Vth2 .

[0125] In the fourth cell string CS4 , the first and fourth ground selection transistors GST0 and GST3 may have the first threshold voltage distribution Vth1 , and the second and third ground selection transistors GST1 and GST2 may have the second threshold voltage distribution Vth2 .

[0126] In the fifth cell string CS5 , the second and fourth ground selection transistors GST1 and GST3 may have the first threshold voltage distribution Vth1 , and the first and third ground selection transistors GST0 and GST2 may have the second threshold voltage distribution Vth2 .

[0127] In the sixth cell string CS6 , the third and fourth ground selection transistors GST2 and GST3 may have the first threshold voltage distribution Vth1 , and the first and second ground selection transistors GST0 and GST1 may have the second threshold voltage distribution Vth2 .

[0128] Reference Fig. 9 During a read operation, a ground voltage Vss (or 0V) may be applied to a selected bit line BL, and when a first cell string CS1 is selected, a power supply voltage Vcc may be applied to a selected first string selection line SSL0, and a ground voltage Vss (or 0V) may be applied to unselected string selection lines SSL1 to SSL5.

[0129] When the first to fourth ground selection transistors GST0 to GST4 of the first to sixth cell strings CS1 to CS6 are programmed to have Fig.11 When the threshold voltage distribution shown in , during the read operation, the first read voltage Vread1 may be applied to the first ground selection line GSL0 and the second ground selection line GSL1, and the second read voltage Vread2 greater than the first read voltage Vread1 may be applied to the third ground selection line GSL2 and the fourth ground selection line GSL3. Under this voltage condition, the first ground selection transistor GST0 to the fourth ground selection transistor GST3 of the first cell string CS1 may all be turned on. The second ground selection transistor GST1 of the second cell string CS2, the fourth cell string CS4, and the sixth cell string CS6 may be turned off, and the first ground selection transistor GST0 of the third cell string CS3, the fifth cell string CS5, and the sixth cell string CS6 may be turned off.

[0130] The pass voltage Vpass may be applied to the word lines WL0 to WLn and the upper and lower common ground selection lines CGSLu and CGSLd. In this case, the pass voltage Vpass may be selected within a range greater than the threshold voltage of the memory cell and less than the programming voltage Vpgm. When the pass voltage Vpass is applied to the word lines WL0 to WLn and the upper and lower common ground selection lines CGSLu and CGSLd, the memory cell MC and the upper and lower common ground transistors CGSTu and CGSTd may be turned on.

[0131] Therefore, when the selected first cell string CS1 is electrically connected between the bit line BL and the common source line CSL, the unselected second cell string CS2, third cell string CS3, fourth cell string CS4, fifth cell string CS5 and sixth cell string CS6 can be electrically separated from the common source line CSL and the bit line BL by the second ground selection transistor GST1, the third ground selection transistor GST2 and the fourth ground selection transistor GST3.

[0132] Fig.12 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation. Fig.13 It is shown Fig.12 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0133] Reference Fig.12 and Fig.13 In each memory block, the first to sixth cell strings CS1 to CS6 may be connected to the bit lines BL, respectively. Each of the first to sixth cell strings CS1 to CS6 may include a string selection transistor SST, a plurality of memory cells MC connected in series, a plurality of ground selection transistors GST0, GST1, and GST2 connected in series, and common ground selection transistors CGSTu and CGSTd.

[0134] In detail, each of the first to sixth cell strings CS1 to CS6 may include first, second, and third ground selection transistors GST0 , GST1 , and GST2 , and upper and lower common ground selection transistors CGSTu and CGSTd.

[0135] The first to third ground selection transistors GST0 to GST2 of the first to sixth cell strings CS1 to CS6 may be controlled by first to third ground selection lines GSL0 to GSL2 , respectively.

[0136] Furthermore, each of the first to sixth cell strings CS1 to CS6 may include dummy transistors DT between the memory cell MC and the ground selection transistor GST2 , between the ground selection transistor GST0 and the common ground selection transistor CGST, and between the ground selection transistors GST0 , GST1 , and GST2 .

[0137] At least one dummy transistor DT may be connected between the upper common ground selection transistor CGSTu and the first ground selection transistor GST0. For example, three dummy transistors DT may be connected in series between the upper common ground selection transistor CGSTu and the first ground selection transistor GST0.

[0138] The dummy transistors DT may be connected between the first, second, and third ground selection transistors GST0, GST1, and GST2, respectively. At least one dummy transistor DT may be connected between the third ground selection transistor GST2 and the first word line WL0.

[0139] According to the implementation mode, Fig.10 As shown, the first to third ground selection transistors GST0 to GST2 of each of the cell strings CS1 to CS6 may have the first threshold voltage distribution Vth1 or the second threshold voltage distribution Vth2.

[0140] As an example, see Fig.13 , the first ground selection transistor GST0 of the first cell string CS1 and the second cell string CS2 may have a first threshold voltage distribution Vth1, and the second and third ground selection transistors GST1 and GST2 of the first and second cell strings CS1 and CS2 may have a second threshold voltage distribution Vth2 greater than the first threshold voltage distribution Vth1.

[0141] The second ground selection transistors GST1 of the third and fourth cell strings CS3 and CS4 may have a first threshold voltage distribution Vth1, and the first and third ground selection transistors GST0 and GST2 of the third and fourth cell strings CS3 and CS4 may have a second threshold voltage distribution Vth2 greater than the first threshold voltage distribution Vth1.

[0142] The third ground selection transistor GST2 of the fifth and sixth cell strings CS5 and CS6 may have a first threshold voltage distribution Vth1, and the first and second ground selection transistors GST0 and GST1 of the fifth and sixth cell strings CS5 and CS6 may have a second threshold voltage distribution Vth2 greater than the first threshold voltage distribution Vth1.

[0143] In accordance with Fig.12 and Fig.13 During a read operation of the semiconductor device of the embodiment shown in , a ground voltage Vss (or 0V) may be applied to the selected bit line BL, and when the first cell string CS1 is selected, a power supply voltage Vcc may be applied to the selected first string selection line SSL0, and a ground voltage Vss (or 0V) may be applied to the unselected string selection lines SSL1 to SSL5. In addition, a first read voltage Vread1 may be applied to the first ground selection line GSL0, and a second read voltage Vread2 greater than the first read voltage Vread1 may be applied to the second and third ground selection lines GSL1 and GSL2.

[0144] Under this voltage condition, the first to third ground selection transistors GST0 to GST2 of the first cell string CS1 may all be turned on, the second ground selection transistors GST1 of the third and fourth cell strings CS3 and CS4 may be turned off, and the third ground selection transistors GST2 of the fifth and sixth cell strings CS5 and CS6 may be turned off.

[0145] In addition, during a read operation, a pass voltage Vpass may be applied to the word lines WL0 to WLn, the upper common ground selection line CGSLu and the lower common ground selection line CGSLd, and the dummy word line DWL. In this case, the pass voltage Vpass may be selected within a range greater than the threshold voltage of the memory cell MC and less than the programming voltage Vpgm. When the pass voltage Vpass is applied to the word lines WL0 to WLn and the upper common ground selection line CGSLu and the lower common ground selection line CGSLd, the memory cell MC and the upper common ground transistor CGSTu and the lower common ground transistor CGSTd may be turned on.

[0146] Therefore, when the first cell string CS1 in the selected bit line BL is electrically connected to the bit line BL and the common source line CSL, the unselected third cell string CS3, the fourth cell string CS4, the fifth cell string CS5, and the sixth cell string CS6 can be electrically separated from the common source line CSL and the bit line BL by the second ground selection transistor GST1 and the third ground selection transistor GST2. In the case of the second cell string CS2, the first ground selection transistor GST0 to the third ground selection transistor GST2 can all be turned on, and the string selection transistor SST of the second cell string CS2 can be turned off, so the second cell string CS2 can be electrically separated from the selected bit line BL.

[0147] Fig.14 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation. Fig.15 is a diagram illustrating threshold voltage distributions of ground selection transistors in a memory cell array of a semiconductor device according to an embodiment of the inventive concept. Fig.16 It is shown Fig.14 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0148] Reference Fig.14 and Fig.15, the first to sixth cell strings CS1 to CS6 may be connected to each bit line BL, and each of the first to sixth cell strings CS1 to CS6 may include a first ground selection transistor GST0, a second ground selection transistor GST1, and a third ground selection transistor GST2. Here, the first ground selection transistor GST0, the second ground selection transistor GST1, and the third ground selection transistor GST2 may be programmed to have a first threshold voltage distribution Vth1, a second threshold voltage distribution Vth2, or a third threshold voltage distribution Vth3. Here, the second threshold voltage distribution Vth2 may be at a higher level than the first threshold voltage distribution Vth1, and the third threshold voltage distribution Vth3 may be at a higher level than the second threshold voltage distribution Vth2. According to some embodiments, as described with reference to Fig.12 As described, each of the first to sixth cell strings CS1 to CS6 may include dummy transistors DT between the memory cell MC and the ground selection transistor GST2 , between the ground selection transistor GST0 and the common ground selection transistor CGST, and between the ground selection transistors GST0 , GST1 , and GST2 .

[0149] As an example, before the first to third ground selection transistors GST0 to GST2 are programmed, the first to third ground selection transistors GST0 to GST2 connected to the first to third ground selection lines GSL0 to GSL2 may have a first threshold voltage distribution Vth1, and then, in each of the cell strings CS1 to CS6, a program voltage may be applied to a selected one of the first to third ground selection lines GSL0 to GSL2, and a pass voltage may be applied to the other ground selection lines to selectively program the first to third ground selection transistors GST0 to GST2. Two programming operations may be performed on some of the first to third ground selection transistors GST0 to GST2 to have a third threshold voltage distribution Vth3.

[0150] Reference Fig.15 The first ground selection transistor GST0 of the first cell string CS1 and the third cell string CS3 may have a first threshold voltage distribution Vth1, the first ground selection transistor GST0 of the second cell string CS2 and the fifth cell string CS5 may have a second threshold voltage distribution Vth2, and the first ground selection transistor GST0 of the fourth cell string CS4 and the sixth cell string CS6 may have a third threshold voltage distribution Vth3.

[0151] The second ground selection transistors GST1 of the first cell string CS1 and the sixth cell string CS6 may have the second threshold voltage distribution Vth2, the second ground selection transistors GST1 of the second cell string CS2 and the fourth cell string CS4 may have the first threshold voltage distribution Vth1, and the second ground selection transistors GST1 of the third cell string CS3 and the fifth cell string CS5 may have the third threshold voltage distribution Vth3.

[0152] The third ground selection transistors GST2 of the first and second cell strings CS1 and CS2 may have a third threshold voltage distribution Vth3, the third ground selection transistors GST2 of the third and fourth cell strings CS3 and CS4 may have a second threshold voltage distribution Vth2, and the third ground selection transistors GST2 of the fifth and sixth cell strings CS5 and CS6 may have a first threshold voltage distribution Vth1.

[0153] In accordance with Fig.14 and Fig.16 During a read operation of the semiconductor device of the embodiment shown in , a ground voltage Vss (or 0V) may be applied to a selected bit line BL, and when a first cell string CS1 is selected, a power supply voltage Vcc may be applied to a selected first string selection line SSL0, and a ground voltage Vss (or 0V) may be applied to unselected string selection lines SSL1 to SSL5.

[0154] In addition, a first read voltage Vread1 may be applied to the first ground selection line GSL0, a second read voltage Vread2 greater than the first read voltage Vread1 may be applied to the second ground selection line GSL1, and a third read voltage Vread3 greater than the second read voltage Vread2 may be applied to the third ground selection line GSL2.

[0155] Under this voltage condition, the first to third ground selection transistors GST0 to GST2 of the first cell string CS1 may all be turned on. The first ground selection transistor GST0 of the second cell string CS2 and the first ground selection transistor GST0 of the fourth cell string CS4 may be turned off, and the second ground selection transistor GST1 of the third cell string CS3 may be turned off. The first and second ground selection transistors GST0 and GST1 of the fifth cell string CS5 and the first ground selection transistor GST0 of the sixth cell string CS6 may be turned off.

[0156] Therefore, when the first cell string CS1 in the selected bit line BL is electrically connected to the bit line BL and the common source line CSL, the unselected second cell string CS2, the third cell string CS3, the fourth cell string CS4, the fifth cell string CS5 and the sixth cell string CS6 can be electrically separated from the common source line CSL and the bit line BL by the first ground selection transistor GST0 and the second ground selection transistor GST1.

[0157] Fig.17 is a plan view illustrating a portion of a memory cell array of a semiconductor device according to an embodiment of the inventive concept. Fig.18 2 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept. For simplicity of explanation, description of technical features identical to those of the above-described semiconductor device may be omitted, and differences will be described in detail.

[0158] Reference Fig.17 and Fig.18 , as previously referenced Fig. 7A and Fig. 8A As described, the stack structure ST may be disposed between two adjacent separation structures SS. The stack structure ST may include a ground selection structure GSLS, a word line structure WLS, and string selection structures SSL0 to SSL9 sequentially stacked on the substrate 100.

[0159] As an example, the ground selection structure GSLS may include first to fifth ground selection lines GSL0 to GSL4 vertically stacked on the substrate 100 with an interlayer insulating layer ILD interposed therebetween, and the ground selection structure GSLS may include an upper common ground selection line CGSLu and a lower common ground selection line CGSLd between the substrate 100 and the first ground selection line GSL0. Each of the first to fifth ground selection lines GSL0 to GSL4 may not be physically separated between the separation structures SS, but may be a single layer in the form of a line.

[0160] In addition, the stacked structure ST may include first to tenth string selection lines SSL0 to SSL9 horizontally spaced apart from each other on the word line structure WLS. The first to tenth string selection lines SSL0 to SSL9 may be spaced apart from each other in the second direction D2 by a separation insulating pattern SIP disposed on the word line structure WLS. When viewed in a plan view, the first to tenth string selection lines SSL0 to SSL9 may overlap the first to fifth ground selection lines GSL0 to GSL4, respectively.

[0161] The bit lines BL1 and BL2 may cross the stacked structure ST on the cell array region CAR. Each of the two bit lines BL1 and BL2 may be disposed on the vertical structures VS arranged in a row along the second direction D2. As an example, each of the bit lines BL1 and BL2 may be electrically connected to 10 vertical structures VS.

[0162] Fig.19 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation. Fig. 20 It is shown Fig.19 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0163] Reference Fig.19 and Fig. 20 In each memory block, the first to tenth cell strings CS1 to CS10 may be connected to the bit lines BL, respectively. Each of the first to tenth cell strings CS1 to CS10 may include a string selection transistor SST, a plurality of memory cells MC connected in series, a plurality of ground selection transistors GST0 to GST4 connected in series, and common ground selection transistors CGSTu and CGSTd.

[0164] In detail, each of the first to tenth cell strings CS1 to CS10 may include first to fifth ground selection transistors GST0 to GST4 and upper and lower common ground selection transistors CGSTu and CGSTd. Fig.12 As described, each of the first to tenth cell strings CS1 to CS10 may include dummy transistors DT between the memory cell MC and the ground selection transistor GST2 , between the ground selection transistor GST0 and the common ground selection transistor CGST, and between the ground selection transistors GST0 , GST1 , and GST2 .

[0165] The first to fifth ground selection transistors GST0 to GST4 of the first to tenth cell strings CS1 to CS10 may be controlled by first to fifth ground selection lines GSL0 to GSL4 , respectively.

[0166] The first to fifth ground selection transistors GST0 to GST5 of each of the cell strings CS1 to CS10 may have Fig.10 The first threshold voltage distribution Vth1 or the second threshold voltage distribution Vth2 which is greater than the first threshold voltage distribution Vth1 is shown.

[0167] As an example, see Fig. 20, the first ground selection transistors GST0 of the first cell string CS1, the second cell string CS2, the third cell string CS3, the fifth cell string CS5 and the seventh cell string CS7 may have the second threshold voltage distribution Vth2, and the first ground selection transistors GST0 of the fourth cell string CS4, the sixth cell string CS6, the eighth cell string CS8, the ninth cell string CS9 and the tenth cell string CS10 may have the first threshold voltage distribution Vth1.

[0168] The second ground selection transistors GST1 of the first cell string CS1, the second cell string CS2, the fourth cell string CS4, the sixth cell string CS6 and the eighth cell string CS8 may have the second threshold voltage distribution Vth2, and the second ground selection transistors GST1 of the third cell string CS3, the fifth cell string CS5, the seventh cell string CS7, the ninth cell string CS9 and the tenth cell string CS10 may have the first threshold voltage distribution Vth1.

[0169] The third ground selection transistors GST2 of the first cell string CS1, the third cell string CS3, the fourth cell string CS4, the fifth cell string CS5 and the ninth cell string CS9 may have the second threshold voltage distribution Vth2, and the third ground selection transistors GST2 of the second cell string CS2, the sixth cell string CS6, the seventh cell string CS7, the eighth cell string CS8 and the tenth cell string CS10 have the first threshold voltage distribution Vth1.

[0170] The fourth ground selection transistors GST3 of the second cell string CS2, the third cell string CS3, the fourth cell string CS4, the fifth cell string CS5 and the tenth cell string CS10 may have the second threshold voltage distribution Vth2, and the fourth ground selection transistors GST3 of the first cell string CS1, the sixth cell string CS6, the seventh cell string CS7, the eighth cell string CS8 and the ninth cell string CS9 have the first threshold voltage distribution Vth1.

[0171] The fourth ground selection transistors GST3 of the first to tenth cell strings CS1 to CS10 may have the second threshold voltage distribution Vth2 .

[0172] In accordance with Fig.19 and Fig. 20During a read operation of the semiconductor device of the embodiment shown in , a ground voltage Vss (or 0V) may be applied to the selected bit line BL, and when the first cell string CS1 is selected, a power supply voltage Vcc may be applied to the selected first string selection line SSL0, and a ground voltage Vss (or 0V) may be applied to the unselected string selection lines SSL1 to SSL9. In addition, a first read voltage Vread1 may be applied to a fourth ground selection line (GSL3), and a second read voltage Vread2 greater than the first read voltage Vread1 may be applied to the first ground selection line GSL0, the second ground selection line GSL1, the third ground selection line GSL2, and the fifth ground selection line GSL4.

[0173] Under this voltage condition, all of the first to fifth ground selection transistors GST0 to GST4 of the first cell string CS1 may be turned on.

[0174] Unselected second to tenth cell strings CS2 to CS10 may be electrically separated from the common source line CSL and the bit line BL by the first to fifth ground selection transistors GST0 to GST4 .

[0175] Fig.21 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the inventive concept, and illustrates voltage conditions during a read operation. Fig. 22 It is shown Fig.21 0047 is a table of threshold voltages of ground selection transistors in the semiconductor device shown in .

[0176] Reference Fig.21 and Fig. 22 In each memory block, the first to tenth cell strings CS1 to CS10 may be connected to the bit lines BL, respectively. Each of the first to tenth cell strings CS1 to CS10 may include a string selection transistor SST, a plurality of memory cells MC connected in series, first to fourth ground selection transistors GST0 to GST3, and upper and lower common ground selection transistors CGSTu and CGSTd.

[0177] The first to fourth ground selection transistors GST0 to GST3 of the first to tenth cell strings CS1 to CS10 may be controlled by first to fourth ground selection lines GSL0 to GSL3 , respectively.

[0178] The first to fourth ground selection transistors GST0 to GST3 of each of the cell strings CS1 to CS10 may have Fig.15The first threshold voltage distribution Vth1, the second threshold voltage distribution Vth2 greater than the first threshold voltage distribution Vth1, or the third threshold voltage distribution Vth3 greater than the second threshold voltage distribution Vth2.

[0179] As an example, see Fig. 22 The first ground selection transistor GST0 of the first cell string CS1, the second cell string CS2, the fifth cell string CS5 and the seventh cell string CS7 may have a first threshold voltage distribution Vth1, the first ground selection transistor GST0 of the third cell string CS3, the fourth cell string CS4, the sixth cell string CS6 and the ninth cell string CS9 may have a second threshold voltage distribution Vth2, and the first ground selection transistor GST0 of the eighth cell string CS8 and the tenth cell string CS10 may have a third threshold voltage distribution Vth3.

[0180] The second ground selection transistor GST1 of the third cell string CS3, the sixth cell string CS6 and the eighth cell string CS8 may have a first threshold voltage distribution Vth1, the second ground selection transistor GST1 of the first cell string CS1, the fifth cell string CS5 and the tenth cell string CS10 may have a second threshold voltage distribution Vth2, and the second ground selection transistor GST1 of the second cell string CS2, the fourth cell string CS4, the seventh cell string CS7 and the ninth cell string CS9 may have a third threshold voltage distribution Vth3.

[0181] The third ground selection transistor GST2 of the fourth cell string CS4, the ninth cell string CS9 and the tenth cell string CS10 may have a first threshold voltage distribution Vth1, the third ground selection transistor GST2 of the second cell string CS2, the third cell string CS3, the seventh cell string CS7 and the eighth cell string CS8 may have a second threshold voltage distribution Vth2, and the third ground selection transistor GST2 of the first cell string CS1, the fifth cell string CS5 and the sixth cell string CS6 may have a third threshold voltage distribution Vth3.

[0182] The fourth ground selection transistor GST3 of the eighth cell string CS8, the ninth cell string CS9 and the tenth cell string CS10 may have a first threshold voltage distribution Vth1, the fourth ground selection transistor GST3 of the fifth cell string CS5, the sixth cell string CS6 and the seventh cell string CS7 may have a second threshold voltage distribution Vth2, and the fourth ground selection transistor GST3 of the first cell string CS1 to the fourth cell string CS4 may have a third threshold voltage distribution Vth3.

[0183] In accordance with Fig.21 and Fig. 22During a read operation of the semiconductor device of the embodiment shown in , a ground voltage Vss (or 0V) may be applied to a selected bit line BL, and when a first cell string CS1 is selected, a power supply voltage Vcc may be applied to a selected first string selection line SSL0, and a ground voltage Vss (or 0V) may be applied to unselected string selection lines SSL1 to SSL9.

[0184] In addition, a first read voltage Vread1 may be applied to the first ground selection line GSL0, a second read voltage Vread2 greater than the first read voltage Vread1 may be applied to the second ground selection line GSL1, and a third read voltage Vread3 greater than the second read voltage Vread2 may be applied to the third and fourth ground selection lines GSL2 and GSL3.

[0185] Under this voltage condition, all of the first to fifth ground selection transistors GST0 to GST4 of the first cell string CS1 may be turned on.

[0186] The unselected second cell string CS2, the third cell string CS3, the fourth cell string CS4, the sixth cell string CS6 to the tenth cell string CS10 can be electrically separated from the common source line CSL and the bit line BL by the first ground selection transistor GST0 to the fourth ground selection transistor GST3. In the case of the fifth cell string CS5, the first ground selection transistor GST0 to the fifth ground selection transistor GST4 can all be turned on, and the string selection transistor SST of the fifth cell string CS5 can be turned off, so the fifth cell string CS5 can be electrically separated from the selected bit line BL.

[0187] Fig.23 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0188] Reference Fig.23 , a semiconductor device according to an embodiment of the inventive concept may include a peripheral circuit structure PS on a semiconductor substrate 200 and a cell array structure CS on the peripheral circuit structure PS.

[0189] According to the embodiment, when the cell array structure CS is combined on the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor device according to the embodiment of the inventive concept can be increased. In addition, since the peripheral circuit structure PS and the cell array structure CS are manufactured separately and combined with each other, damage to the peripheral circuit PTR due to various heat treatment processes can be prevented, thereby improving the electrical characteristics and reliability of the semiconductor device according to the inventive concept.

[0190] The cell array structure CS may include a memory cell array including memory cells arranged three-dimensionally.

[0191] The cell array structure CS of the semiconductor device may include a cell array region CAR and a connection region CNR, and the connection region CNR may be adjacent to the cell array region CAR.

[0192] The cell array structure CS may include a stack structure ST, a vertical structure VS, a bit line BL, a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG.

[0193] The stack structure ST of the cell array structure CS may be provided in plural. Fig. 7A When viewed in a plan view of FIG. 1 , the plurality of stacked structures ST may extend in the first direction D1 and be spaced apart from each other in the second direction D2. Hereinafter, for convenience of explanation, a single stacked structure ST will be described, but the following description may be equally applied to other stacked structures ST.

[0194] As previously referenced Fig. 7A , Figure 7B , Fig. 8A and Figure 8B As described, the stack structure ST may include stacked ground selection lines CGSLd, CGSLu, GSL0 to GSL3 and word lines WL0 to WLn and a string selection line SSL.

[0195] In an embodiment, the stack structure ST may include a first stack structure ST1 and a second stack structure ST2 on the first stack structure ST1. The first stack structure ST1 may include ground selection lines CGSLd, CGSLu, GSL0 to GSL3 and some of the word lines WL0 to WLn. The second stack structure ST2 may include the other parts of the word lines WL0 to WLn and a string selection line SSL.

[0196] The second stacked structure ST2 may be disposed between the first stacked structure ST1 and the peripheral circuit structure PS. The lowermost conductive line among the conductive lines of the second stacked structure ST2 may have the smallest length in the first direction D1, and the uppermost conductive line among the conductive lines of the first stacked structure ST1 may have the largest length in the first direction D1.

[0197] The conductive lines of the stacked structure ST may be stacked in the connection region CNR to have an inverted staircase structure. Each conductive line may include a pad portion in the connection region CNR. The pad portions of the conductive lines may be located at different positions horizontally and vertically. The cell contact plugs CPLG may be connected to the pad portions of the conductive lines, respectively.

[0198] A plurality of vertical structures VS may penetrate the stacked structure ST in the cell array region CAR. When viewed in a plan view, the vertical structures VS may be arranged in one direction or in a zigzag shape. The vertical structures VS may be provided to penetrate the stacked structure ST also in the connection region CNR.

[0199] In an embodiment, each vertical structure VS may be provided in a vertical channel hole penetrating the stack structure ST. In an embodiment, the vertical channel hole may include a first vertical channel hole penetrating the first stack structure ST1 and a second vertical channel hole penetrating the second stack structure ST2 and connected to the first vertical channel hole, respectively.

[0200] Each vertical structure VS may include a first vertical extension in the first vertical channel hole and a second vertical extension in the second vertical channel hole. The first vertical extension and the second vertical extension may be a structure that extends continuously without an interface. Here, the first vertical extension may have a sidewall with a uniform slope from its bottom to the top. Similarly, the second vertical extension may have a sidewall with a uniform slope from its bottom to the top. That is, the width of each of the first vertical extension and the second vertical extension in the first direction D1 or the second direction D2 may decrease as the distance from the semiconductor substrate 200 increases. The portions where the first vertical extension and the second vertical extension are connected to each other may have different diameters. A step may be formed at the portion where the first vertical extension and the second vertical extension are connected to each other.

[0201] However, the inventive concept is not limited thereto, and unlike what is shown, each first vertical structure VS1 may have three or more vertical extensions each having steps at two or more interfaces. As another example, each first vertical structure VS1 may have a flat sidewall without any steps.

[0202] A bit line conductive pad may be formed at a lower end of each vertical structure VS, and the bit line BL may be connected to the bit line conductive pad through a bit line contact plug.

[0203] In the connection region CNR, the cell contact plug CPLG may penetrate the upper insulating layer 110 and the planar insulating layer 105 to be connected to the pad portions of the conductive line, respectively. As the cell contact plug becomes adjacent to the cell array region CAR, the vertical length of the cell contact plug CPLG may decrease. The upper surfaces of the cell contact plug CPLG may be substantially coplanar.

[0204] The peripheral contact plug PPLG and the input / output contact plug IOPLG may be connected to the upper conductive pattern UCP by penetrating the upper insulating layer 110 and the planar insulating layer 105 in the connection region CNR.

[0205] Each of the cell contact plug CPLG, the peripheral contact plug PPLG, and the input / output contact plug IOPLG may include a barrier metal layer including a conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.) and a metal layer including a metal (eg, tungsten, titanium, tantalum, etc.).

[0206] Upper and lower conductive lines UCL and LCL may be disposed in the upper insulating layer 110 and may be electrically connected to the bit lines BL, the cell contact plugs CPLG, the peripheral contact plugs PPLG, and the input / output contact plugs IOPLG.

[0207] The upper conductive lines UCL and the lower conductive lines LCL may include at least one of metal (eg, tungsten, copper, aluminum, etc.), conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.), or transition metal (eg, titanium, tantalum, etc.).

[0208] The first bonding pad BP1 may be disposed in the uppermost insulating layer 120. The first bonding pad BP1 may be electrically connected to the upper conductive line UCL. The first bonding pad BP1 may be formed of aluminum, copper, or tungsten.

[0209] The peripheral circuit structure PS including the second bonding pad BP2 may be disposed under the cell array structure CS.

[0210] In detail, the peripheral circuit structure PS may include a semiconductor substrate 200, a peripheral circuit PTR controlling a memory cell array, and peripheral interlayer insulating layers 210 and 220 covering the peripheral circuit PTR. The peripheral circuit PTR may be integrated on the upper surface of the semiconductor substrate 200. A surface insulating layer 201 may be provided on the rear surface of the semiconductor substrate 200.

[0211] The semiconductor substrate 200 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The semiconductor substrate 200 may have an upper surface parallel to the first direction D1 and the second direction D2 intersecting the first direction D1 and orthogonal to the third direction D3. For example, the first to third directions D1, D2, and D3 may be directions orthogonal to each other.

[0212] The peripheral circuit PTR may be a row decoder and a column decoder, a page buffer, and a control circuit. In detail, the peripheral circuit PTR may include NMOS and PMOS transistors. The peripheral circuit wiring PLP may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP.

[0213] For example, the width of the peripheral contact plug PCP in the first direction D1 or the second direction D2 may increase toward the third direction D3. The peripheral contact plug PCP and the peripheral circuit wiring PLP may include a conductive material such as metal.

[0214] Peripheral interlayer insulating layers 210 and 220 may be provided on the upper surface of the semiconductor substrate 200. The peripheral interlayer insulating layers 210 and 220 may cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit wiring PLP on the semiconductor substrate 200. The peripheral contact plug PCP and the peripheral circuit wiring PLP may be electrically connected to the peripheral circuit PTR. The peripheral interlayer insulating layers 210 and 220 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer.

[0215] The second bonding pad BP2 may be disposed in the uppermost peripheral interlayer insulating layer 220. The peripheral interlayer insulating layer 220 may not cover the upper surface of the second bonding pad BP2. The upper surface of the uppermost peripheral interlayer insulating layer 220 may be substantially coplanar with the upper surface of the second bonding pad BP2. The second bonding pad BP2 may be electrically connected to the peripheral circuit PTR through the peripheral circuit wiring PLP and the peripheral contact plug PCP.

[0216] The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 by bonding. That is, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0217] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The second bonding pad BP2 may have substantially the same shape, the same width, or the same area as those of the first bonding pad BP1.

[0218] The upper insulating layer 310 may be disposed on the stacked structure ST of the cell array structure CS. The upper insulating layer 310 may cover the stacked structure ST and the upper conductive pattern UCP. The input / output pad IOPAD may be disposed on the upper insulating layer 310. The input / output pad IOPAD may be electrically connected to the input / output contact plug IOPLG. The input / output pad IOPAD may be electrically connected to the peripheral circuit PTR of the peripheral circuit structure PS through the input / output contact plug IOPLG.

[0219] The cover insulating layer 320 may be disposed on the upper insulating layer 310 , and the cover insulating layer 320 may cover the input / output pad IOPAD.

[0220] A capping insulating layer 320, an interlayer film 330 (e.g., a dielectric film, a hard mask layer), and a passivation layer 340 may be sequentially formed on the entire surface of the upper insulating layer 310. The capping insulating layer 320 may be, for example, a silicon nitride layer or a silicon oxynitride layer. The passivation layer 340 may be, for example, a polyimide-based material such as photosensitive polyimide (PSPI).

[0221] The capping insulating layer 320 , the interlayer film 330 , and the passivation layer 340 may have a pad opening OP exposing a portion of the input / output pad IOPAD.

[0222] According to an embodiment of the inventive concept, a semiconductor device may share a single ground selection line that is not physically separated in one memory block, and may include ground selection transistors having different threshold voltages.

[0223] Since the ground selection transistors located at the same level or in the same plane share a ground selection line that is not physically separated, a process or structure for physically separating the ground selection lines can be omitted. Therefore, the integration and productivity of the semiconductor device can be further improved.

[0224] One or more elements disclosed above may include or be implemented in a processing circuit, which is hardware such as a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0225] Although the above describes the implementation, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Therefore, the exemplary implementation of the inventive concept should be considered in all aspects as illustrative and not restrictive, and the spirit and scope of the inventive concept are indicated by the appended claims.

[0226] This application claims the priority benefit of Korean Patent Application No. 10-2023-0114192 filed on August 30, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; A plurality of cell strings are arranged perpendicular to the upper surface of the substrate; as well as A bit line connected to at least six of the plurality of cell strings, wherein Each of the plurality of cell strings includes a plurality of memory cells connected in series with each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series with each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line, The plurality of cell strings provide a plurality of string selection transistors, a plurality of first ground selection transistors, a plurality of second ground selection transistors, a plurality of third ground selection transistors, and a plurality of fourth ground selection transistors based on the string selection transistor and the first to fourth ground selection transistors in each of the plurality of cell strings, The plurality of string selection transistors of the plurality of cell strings are electrically separated from each other, The plurality of first ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of second ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of third ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of fourth ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The first of the plurality of first to fourth ground selection transistors has a first threshold voltage distribution, The second of the plurality of first to fourth ground selection transistors has a second threshold voltage distribution, and The second threshold voltage distribution is different from the first threshold voltage distribution. 2 . The semiconductor device according to claim 1 , wherein at least two of the plurality of first to fourth ground selection transistors have the first threshold voltage distribution.

3. The semiconductor device according to claim 1, further comprising: A first ground selection line, a second ground selection line, a third ground selection line and a fourth ground selection line are vertically stacked on the substrate, wherein Each of the first ground selection line, the second ground selection line, the third ground selection line, and the fourth ground selection line is a single conductive pattern extending in a first direction, The first direction is parallel to the upper surface of the substrate, and The first, second, third and fourth ground selection lines are connected to the plurality of first, second, third and fourth ground selection transistors, respectively.

4. The semiconductor device according to claim 3, further comprising: A first separated structure and a second separated structure are on the substrate and extend in the first direction, wherein The first ground selection line, the second ground selection line, the third ground selection line, and the fourth ground selection line are between the first separation structure and the second separation structure.

5. The semiconductor device according to claim 4, further comprising: a plurality of string selection lines spaced apart from each other at regular intervals between the first separation structure and the second separation structure, wherein The plurality of string selection lines are located at the same level from the substrate.

6. The semiconductor device according to claim 5, wherein A width of the first ground selection line, a width of the second ground selection line, a width of the third ground selection line, and a width of the fourth ground selection line are each greater than a sum of widths of at least six of the plurality of string selection lines.

7. The semiconductor device according to claim 1, wherein Each of the plurality of cell strings further includes a common ground selection transistor connected in series with each other between the substrate and the first ground selection transistor.

8. The semiconductor device according to claim 7, wherein The plurality of cell strings provide a plurality of common ground selection transistors having the same threshold voltage distribution based on the common ground selection transistor in each of the plurality of cell strings. 9 . The semiconductor device according to claim 7 , wherein each corresponding cell string of the plurality of cell strings further comprises at least two dummy transistors connected in series with each other between the common ground selection transistor and the first ground selection transistor of the corresponding cell string.

10. The semiconductor device according to claim 1, further comprising: Semiconductor substrates; a peripheral circuit structure, comprising a peripheral circuit integrated on the semiconductor substrate and a first bonding pad connected to the peripheral circuit; as well as a second bonding pad bonded to the first bonding pad, The second bonding pad is electrically connected to the plurality of cell strings.

11. A semiconductor device comprising: substrate; A plurality of cell strings are perpendicular to the upper surface of the substrate; as well as A bit line connected to at least six of the plurality of cell strings, wherein Each of the plurality of cell strings includes a plurality of memory cells connected in series with each other in a direction perpendicular to the upper surface of the substrate, a plurality of ground selection transistors connected in series with each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line, In each of the plurality of cell strings, the plurality of ground selection transistors include a first ground selection transistor having a first threshold voltage distribution, a second ground selection transistor having a second threshold voltage distribution, and a third ground selection transistor having a third threshold voltage distribution, and The first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are different from each other.

12. The semiconductor device according to claim 11, wherein the second threshold voltage distribution is greater than the first threshold voltage distribution, and The third threshold voltage distribution is greater than the second threshold voltage distribution.

13. The semiconductor device according to claim 11, wherein The string selection transistor of each of the plurality of cell strings provides a plurality of string selection transistors, The plurality of string selection transistors of the cell string are electrically separated from each other, and The ground selection transistors located at the same level in the plurality of cell strings are configured to be commonly controlled.

14. The semiconductor device according to claim 11, further comprising: A first ground selection line, a second ground selection line and a third ground selection line are vertically stacked on the substrate, wherein The first ground selection transistor, the second ground selection transistor, and the third ground selection transistor of each of the plurality of cell strings provide a plurality of first ground selection transistors, a plurality of second ground selection transistors, and a plurality of third ground selection transistors, The first ground selection line, the second ground selection line, and the third ground selection line are respectively connected to at least one of the plurality of first ground selection transistors, at least one of the plurality of second ground selection transistors, and at least one of the plurality of third ground selection transistors.

15. The semiconductor device according to claim 11, further comprising: a first separation structure and a second separation structure on the substrate and extending in a first direction; a first ground selection line, a second ground selection line, and a third ground selection line vertically stacked on the substrate and between the first separation structure and the second separation structure; as well as a plurality of string selection lines horizontally spaced apart from each other between the first separation structure and the second separation structure, wherein Each of the first ground selection line, the second ground selection line, and the third ground selection line is a single conductive pattern extending in the first direction, and The first direction is parallel to the upper surface of the substrate.

16. The semiconductor device according to claim 15, further comprising: A plurality of word lines are vertically stacked between the third ground selection line and the plurality of string selection lines, wherein Each of the plurality of word lines is commonly connected to the memory cells located at the same level in the plurality of cell strings.

17. The semiconductor device according to claim 11, wherein Each of the plurality of cell strings further includes a common ground selection transistor connected in series with each other between the substrate and the first ground selection transistor. 18 . The semiconductor device according to claim 17 , wherein each of the plurality of cell strings further comprises at least two dummy transistors connected in series with each other between the common ground selection transistor and the first ground selection transistor.

19. An electronic system comprising: A semiconductor device comprising a peripheral circuit structure and a cell array structure on the peripheral circuit structure; as well as a controller electrically connected to the semiconductor device through an input / output pad and configured to control the semiconductor device, wherein The cell array structure includes a substrate, a plurality of cell strings arranged perpendicular to an upper surface of the substrate, and bit lines connected to at least six of the plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells connected in series with each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series with each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line, The plurality of cell strings provide a plurality of string selection transistors, a plurality of first ground selection transistors, a plurality of second ground selection transistors, a plurality of third ground selection transistors, and a plurality of fourth ground selection transistors based on the string selection transistor and the first to fourth ground selection transistors in each of the plurality of cell strings, The plurality of string selection transistors of the plurality of cell strings are electrically separated from each other, The plurality of first ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of second ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of third ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The plurality of fourth ground selection transistors in the plurality of cell strings are configured to be commonly controlled, The first of the plurality of first to fourth ground selection transistors has a first threshold voltage distribution, The second of the plurality of first to fourth ground selection transistors has a second threshold voltage distribution, and The second threshold voltage distribution is different from the first threshold voltage distribution.

20. The electronic system of claim 19, wherein The cell array structure further includes: a first separation structure and a second separation structure on the substrate and a plurality of string selection lines horizontally spaced apart from each other between the first separation structure and the second separation structure, the first separation structure and the second separation structure extending in a first direction; as well as A first ground selection line, a second ground selection line and a third ground selection line are vertically stacked on the substrate, wherein The first ground selection line, the second ground selection line, and the third ground selection line are between the first separation structure and the second separation structure, Each of the first ground selection line, the second ground selection line, and the third ground selection line is a single conductive pattern extending in the first direction, The first direction is parallel to the upper surface of the substrate, and The first ground selection line, the second ground selection line, and the third ground selection line are connected to the plurality of first ground selection transistors, the plurality of second ground selection transistors, and the plurality of third ground selection transistors, respectively.

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