Planar SiGe heterojunction transistor compatible with SOI CMOS process and its fabrication method

Abstract

This invention discloses a planar SiGe heterojunction transistor compatible with SOI CMOS technology and its manufacturing method. The planar SiGe heterojunction transistor includes an emitter, base, and collector disposed on an SOI wafer, arranged in a planar pattern with lateral current flow. The emitter and collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer. The base is composed of a p-type doped silicon-germanium alloy with a specific composition. Polycrystalline silicon is used for contacting the emitter, base, and collector. This invention discloses a planar SiGe heterojunction transistor compatible with SOI CMOS technology and its manufacturing method, addressing the problem of traditional vertical SiGe HBTs being incompatible with advanced CMOS process nodes.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a planar SiGe heterojunction transistor compatible with SOI CMOS process and a method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process. Background Technology

[0002] Compared to other types of device structures, bipolar transistors have at least four unique advantages:

[0003] 1. High working speed.

[0004] 2. Extremely high driving capability and transconductance.

[0005] 3. Excellent threshold voltage controllability.

[0006] 4. Excellent analog device application capabilities (low noise, high signal-to-noise ratio, low offset, and large gain bandwidth).

[0007] In bipolar devices, SiGe heterojunction transistors primarily introduce an additional barrier in the valence band, thereby suppressing hole injection from the base region to the emitter, resulting in improved emitter injection efficiency. Therefore, SiGe HBTs can achieve higher current gain without increasing the emitter resistance. SiGe HBT devices offer advantages in high speed and performance, and are compatible with mature CMOS process technologies, injecting new vitality into the development of high-speed and high-performance integrated circuits.

[0008] Currently, significant progress has been made in SiGe BiCMOS research abroad, and it has played a crucial role in high-speed, high-performance integrated circuits. SiGe heterojunction devices and integrated circuits have important applications and a broad market in both military and civilian fields. However, traditional vertical SiGe HBTs are difficult to integrate with advanced CMOS process nodes, making manufacturing relatively complicated. Therefore, further improvements are needed to address these issues. Summary of the Invention

[0009] The main objective of this invention is to provide a planar SiGe heterojunction transistor compatible with SOI CMOS technology and its manufacturing method, in order to solve the problem that traditional vertical SiGe HBTs are difficult to be compatible with advanced CMOS process nodes.

[0010] To achieve the above objectives, the present invention provides a method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS technology, comprising the following steps:

[0011] Step S1: Pattern the base region on the SOI wafer (including SOI and silicon dioxide), and deposit and grow (low-quality) silicon-germanium alloy on the substrate by MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) process.

[0012] Step S2: Thermal oxidation is performed to separate germanium from silicon dioxide in the SOI wafer and drive it into the base region to form a silicon-germanium base region with (good) crystallinity (germanium molar fraction of 20% to 30%, uniformly distributed or linearly gradient distributed. The field effect generated by the linear gradient will improve the device cutoff frequency);

[0013] Step S3: Etch silicon dioxide to expose the silicon-germanium base region and p-type dope the silicon-germanium base region. After annealing, deposit polysilicon on top of the silicon-germanium base region as an extended base region to serve as the base of the transistor.

[0014] Step S4: Pattern the emitter and collector regions on the SOI wafer and perform n-type doping to form contact electrodes, which serve as the emitter and collector of the transistor, respectively, thereby completing the fabrication of the planar SiGe heterojunction transistor.

[0015] As a further preferred technical solution of the above technical solution, in step S1, the SOI wafer needs to be pre-treated before growing the silicon-germanium alloy. This pre-treatment is divided into wet chemical cleaning and heat treatment. The wet chemical cleaning uses the standard RCA cleaning step, and the heat treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature (the composition, thickness, etc. of the grown silicon-germanium alloy need to be determined according to the design performance parameters of the device, and the MBE or CVD equipment is corrected accordingly).

[0016] As a further preferred technical solution of the above technical solution, in step S3, the method for etching silicon dioxide is reactive ion etching; the annealing method includes rapid thermal annealing, flash lamp annealing and laser annealing; the method for depositing polycrystalline silicon in the extended base region includes sputtering, chemical vapor deposition and molecular beam epitaxy.

[0017] As a further preferred technical solution of the above technical solution, in step S4, a nitride barrier layer is formed around the extended base region before placing the contact electrode to prevent the electrodes of the emitter region and collector region from short-circuiting with the extended base region.

[0018] To achieve the above objectives, the present invention also provides a planar SiGe heterojunction transistor (HBT) compatible with SOI CMOS technology, comprising an emitter, a base, and a collector disposed on an SOI wafer, the three regions being arranged in a planar manner with lateral current flow. The emitter and collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer (i.e., silicon dioxide of the SOI wafer). The base is composed of a p-type doped silicon-germanium alloy with a certain composition structure. Polycrystalline silicon is used to contact the emitter, base, and collector respectively.

[0019] As a further preferred technical solution of the above technical solution, the emitter and collector widths are 30-100 nanometers, the base width is 30-50 nanometers (to ensure partial depletion of the base region); the SOI wafer includes an insulating layer and an SOI layer, the thickness of the insulating layer and the SOI layer is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

[0020] As a further preferred technical solution to the above technical solution, the n-type silicon doping of the substrate in the SOI wafer is 10^16 to 10^18 per cubic centimeter.

[0021] As a further preferred embodiment of the above technical solution, the n-type silicon doping of the emitter and collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon-germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

[0022] The beneficial effects of this invention are: the manufacturing method of this invention is fully compatible with standard SOI CMOS processes; the SiGe base region does not require an additional mask and is generated in the first step, eliminating the need for wafer transfer in subsequent steps; compared with traditional vertical SiGe HBTs, this invention can be matched with smaller CMOS process nodes and has advantages such as higher cutoff frequency and easier integration. Attached Figure Description

[0023] Figure 1 (a) is a schematic diagram of an SOI wafer.

[0024] Figure 1 (b) is a schematic diagram of silicon-germanium alloy deposition on a substrate surface using MBE or CVD.

[0025] Figure 2 This is a schematic diagram of the silicon-germanium-based region with good crystallinity formed after thermal oxidation.

[0026] Figure 3 (a) is a schematic diagram of ion implantation into the doped base region after etching silicon oxide.

[0027] Figure 3 (b) is a schematic diagram of polycrystalline silicon deposited above the base region to form an extended base region.

[0028] Figure 4 (a) is a schematic diagram of ion implantation after patterning the emitter region and collector region.

[0029] Figure 4 (b) is a schematic diagram of the device structure after the process is completed (electrodes are not shown). Detailed Implementation

[0030] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0031] In the preferred embodiments of the present invention, those skilled in the art should note that SOI wafers and the like involved in the present invention can be considered as prior art.

[0032] Preferred embodiment.

[0033] like Figure 1-4 As shown, this invention discloses a method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS technology, comprising the following steps:

[0034] Step S1: As Figure 1 As shown in (a) to (b), base regions are patterned on SOI wafers (including SOI and silicon dioxide), and (low-quality) silicon-germanium alloys are deposited and grown on the substrate by MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) processes.

[0035] Step S2: As Figure 2 As shown, germanium is separated from silicon dioxide in the SOI wafer through thermal oxidation and driven into the base region to form a silicon-germanium base region with (good) crystallinity (the molar fraction of germanium is 20% to 30%, uniformly distributed or in a linear gradient distribution. The field effect generated by the linear gradient will improve the device cutoff frequency).

[0036] Step S3: As Figure 3 As shown in (a), silicon dioxide is etched to expose the silicon-germanium base region, which is then p-type doped. After annealing, polysilicon is deposited on top of the silicon-germanium base region as an extended base region to serve as the base of the transistor. Figure 3 As shown in (b);

[0037] Step S4: As Figure 4As shown in (a), emitter and collector regions are patterned on an SOI wafer and n-type doped to form contact electrodes, which serve as the emitter and collector of the transistor, respectively, thus completing the fabrication of a planar SiGe heterojunction transistor. Figure 4 As shown in (b).

[0038] Specifically, in step S1, the SOI wafer needs to be pre-treated before growing the silicon-germanium alloy. This pre-treatment is divided into wet chemical cleaning and thermal treatment. The wet chemical cleaning uses the standard RCA cleaning step, and the thermal treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature (the composition, thickness, etc. of the grown silicon-germanium alloy need to be determined according to the design performance parameters of the device, and the MBE or CVD equipment is corrected accordingly).

[0039] More specifically, in step S3, the method for etching silicon dioxide is reactive ion etching; the annealing methods include rapid thermal annealing, flash lamp annealing, and laser annealing; and the methods for depositing polycrystalline silicon in the extended base region include sputtering, chemical vapor deposition, and molecular beam epitaxy.

[0040] Furthermore, in step S4, a nitride barrier layer is formed around the extended base region before the contact electrode is placed, in order to prevent the electrodes of the emitter region and collector region from short-circuiting with the extended base region.

[0041] This invention also discloses a planar SiGe heterojunction transistor (HBT) compatible with SOI CMOS technology, comprising an emitter, a base, and a collector disposed on an SOI wafer, the three regions being arranged in a planar manner with lateral current flow. The emitter and collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer (i.e., silicon dioxide of the SOI wafer). The base is composed of a p-type doped silicon-germanium alloy with a certain composition structure. Polycrystalline silicon is used to contact the emitter, base, and collector respectively.

[0042] Specifically, the emitter and collector widths are 30-100 nanometers, and the base width is 30-50 nanometers (to ensure partial depletion of the base region); the SOI wafer includes an insulating layer and an SOI layer, the thickness of which is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

[0043] More specifically, the n-type silicon doping of the substrate in the SOI wafer is 10^16 to 10^18 per cubic centimeter.

[0044] More specifically, the n-type silicon doping of the emitter and collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon-germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

[0045] Furthermore, the electrode materials for the emitter, base, and collector are selected from tungsten, aluminum, nickel, copper, or polycrystalline silicon.

[0046] It is worth mentioning that the SOI wafer and other technical features involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0047] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS technology, characterized in that, Includes the following steps: Step S1: Pattern the base region on the SOI wafer, and deposit and grow silicon-germanium alloy on the substrate using MBE or CVD process; Step S2: Perform thermal oxidation to separate germanium from silicon dioxide in the SOI wafer and drive it to the base region to form a crystalline silicon-germanium base region; Step S3: Etch silicon dioxide to expose the silicon-germanium base region and p-type dope the silicon-germanium base region. After annealing, deposit polysilicon on top of the silicon-germanium base region as an extended base region to serve as the base of the transistor. Step S4: Pattern the emitter and collector regions on the SOI wafer and perform n-type doping to form contact electrodes, which serve as the emitter and collector of the transistor, respectively, thereby completing the fabrication of the planar SiGe heterojunction transistor.

2. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 1, characterized in that, In step S1, the SOI wafer needs to be pretreated before growing the silicon-germanium alloy. This pretreatment consists of wet chemical cleaning and heat treatment. The wet chemical cleaning uses the standard RCA cleaning procedure, and the heat treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature.

3. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 2, characterized in that, In step S3, the method for etching silicon dioxide is reactive ion etching; the annealing methods include rapid thermal annealing, flash lamp annealing, and laser annealing; the methods for depositing polycrystalline silicon in the extended base region include sputtering, chemical vapor deposition, and molecular beam epitaxy.

4. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 3, characterized in that, In step S4, a nitride barrier layer is formed around the extended base region before the contact electrode is placed to prevent the electrodes of the emitter and collector regions from short-circuiting with the extended base region.

5. A planar SiGe heterojunction transistor compatible with SOI CMOS technology, implemented in the method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS technology as described in any one of claims 1-4, characterized in that, The device includes an emitter, base, and collector on an SOI wafer, arranged in a planar pattern with lateral current flow. The emitter and collector are completely symmetrical and are made of n-type doped silicon on an insulating layer. The base is made of a p-type doped silicon-germanium alloy with a specific composition. Polycrystalline silicon is used to contact the emitter, base, and collector.

6. A planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 5, characterized in that, The emitter and collector widths are 30-100 nanometers, and the base width is 30-50 nanometers; the SOI wafer includes an insulating layer and an SOI layer, the thickness of which is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

7. A planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 6, characterized in that, The n-type silicon doping of the substrate in the SOI wafer is between 10^16 and 10^18 per cubic centimeter.

8. A planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 7, characterized in that, The n-type silicon doping of the emitter and collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon-germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

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