Silicon carbide MOSFET device and preparation method thereof
By forming heavily doped N+ and P+ regions at the bottom of the P-body region of the SiC MOSFET device and setting the P+ region on both sides of the N+ region, the problem of bipolar degradation effect in long-term use of the device is solved, and the stability and reverse voltage resistance of the device are improved.
Patent Information
- Application Number
- CN202411544378.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-28
AI Technical Summary
SiC MOSFET devices are prone to bipolar degradation during long-term use, resulting in deterioration of device performance.
By forming heavily doped N+ regions and P+ regions at the bottom of the P-body region, the P+ region is set on both sides of the N+ region to form a hole cutoff region to prevent the hole from recombining with the electrons of the Drift layer.
It effectively reduces the occurrence of bipolar degradation effects, improves the long-term stability and reverse voltage resistance of the device, and at the same time reduces the device resistance and improves performance.
Smart Images
Figure CN119545834A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device and a preparation method thereof. Background Art
[0002] Compared with traditional Si materials, SiC materials have advantages such as large bandgap, high critical breakdown field, small intrinsic carrier concentration, fast electron saturation velocity, and high thermal conductivity, making the performance of power devices made of SiC materials more outstanding, such as SiC MOSFET. In actual device comparisons, in addition to the excellent switching characteristics of Si MOSFET, SiC MOSFET also has the advantages of high voltage and low conduction loss of SiIGBT. Therefore, it has very good performance in both static and dynamic usage scenarios, and is particularly popular in the field of new energy vehicles.
[0003] Although SiC MOSFET has excellent performance, the device still has obvious disadvantages during long-term use. For example, during the freewheeling process of SiC MOSFET, when the parasitic PN junction diode inside the device starts to work as a leakage path, the holes in the internal P region will easily enter the Drift layer, causing the P region holes to recombine with the Drift layer electrons, thereby stimulating the spread of defects in the Drift layer. When the spread reaches a certain extent, part of the device area will be unusable, which will also deteriorate the device performance. This phenomenon is called the bipolar degradation effect. Therefore, how to avoid the bipolar degradation effect of SiCMOSFET devices is of great benefit to the long-term stable use of the device. Summary of the invention
[0004] In view of the above problems, the present invention provides a silicon carbide MOSFET device and a preparation method which prevents the recombination of holes and drift layer electrons, reduces the occurrence of bipolar degradation effects, and reduces device resistance, thereby improving device performance and reverse withstand voltage capability.
[0005] The technical solution of the present invention is: A method for preparing a silicon carbide MOSFET device comprises the following steps: S100, forming an N- Drift layer and an N+ region on the top surface of the N+ Sub layer; S200, forming a P+ region on the top surface of the N+ region by ion implantation; S300, forming a CSL layer on the top surfaces of the N+ region and the P+ region by epitaxial deposition; S400, forming a P-body region, a NP region and a PP region in sequence on the top surface of the CSL layer by ion implantation; S500, directly growing a gate oxide layer on the top surfaces of the CSL layer, the P-body region and the NP region by high temperature dry oxygen oxidation; S600, forming a Poly layer on the top surface of the gate oxide layer by depositing polysilicon; S700, forming an isolation dielectric layer on the top surface of the NP region and the Poly layer by oxide deposition; S800, forming an ohmic contact alloy layer on the top surface of the NP region and the PP region by Ni metal sputtering followed by thermal annealing; S900, forming a front electrode metal layer on the top of the device by sputtering Ti and AlCu metals.
[0006] Specifically, in step S100, the doping concentration of the N-Drift layer is 5E15-3E16cm -2 .
[0007] Specifically, in step S100, the depth of the N+ region is 0.4um-1.2um, and the doping concentration is 1E17-5E18cm -2 .
[0008] Specifically, in step S200, the depth of the P+ region is 0.4um-1.5um, and the doping concentration is 3E17-1E19cm -2 .
[0009] Specifically, in step S300, the thickness of the CSL layer is 0.6um-2um, and the doping concentration is 1E17-5E17cm -2 .
[0010] Specifically, in step S400, the depth of the P-body region is 0.6um-2um, and the doping concentration is 5E17-1E18cm -2 .
[0011] Specifically, in step S400, the depth of the NP region is 0.3um-1.4um, and the doping concentration is 1E18-1E19cm -2 .
[0012] Specifically, in step S400, the depth of the PP region is 0.3um-1.6um, and the doping concentration is 1E18-1E19cm -2 .
[0013] A silicon carbide MOSFET device includes an N+ Sub layer, an N- Drift layer, and a doping concentration of 1E17-5E18cm -2 N+ region, CSL layer, gate oxide layer, Poly layer, isolation dielectric layer and front electrode metal layer; The top surface of the N+ region is provided with a plurality of P+ regions extending downward; the doping concentration of the P+ region is 3E17-1E19cm -2 ; The CSL layer includes: The P-body region extends downward from the top surface of the CSL layer and is connected to the top surface of the P+ region; the doping concentration of the P-body region is 5E17-1E18cm -2 ; NP regions, provided with a plurality of them, extending downward from the top surface of the P-body region respectively; A plurality of PP regions are provided, each extending downward from the top surface of the P-body region and located between a pair of the NP regions; The bottom surface of the gate oxide layer is connected to the CSL layer, the P-body region and the NP region respectively; The side of the isolation dielectric layer extends downward to connect with the NP region; An ohmic contact alloy layer connected to the NP region and the PP region respectively is provided between adjacent isolation dielectric layers.
[0014] Specifically, the bottom surface of the front electrode metal layer is connected to the isolation dielectric layer and the ohmic contact alloy layer respectively.
[0015] The present invention forms heavily doped N+ and P+ regions at the bottom of the P-body region in the planar gate SiC MOSFET, thereby achieving three benefits: 1. In the freewheeling region, the P+ region is arranged on both sides of the N+ region, so that the holes of the parasitic PN junction diode of the device will be cut off in the N+ region in the middle of the P+ region during the freewheeling process, and will not move to the Drift layer, thereby avoiding the recombination of holes and Drift layer electrons, reducing the occurrence of bipolar degradation effect, and improving the long-term stable use of the device; Second, the N+ region at the bottom of the JFET region has a high doping concentration, which can reduce the device resistance and thus improve the device performance; 3. When the device is operating in the reverse cutoff process, the P+ region at the bottom of the P-body region can improve the reverse voltage withstand capability of the device due to its deep junction depth and high doping concentration. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of the structure of SiC MOSFET of the present invention; Figure 2 is a structural schematic diagram of step S100 of the present invention; Figure 3 is a schematic structural diagram of step S200 of the present invention; Figure 4 is a schematic structural diagram of step S300 of the present invention; Figure 5 is a structural schematic diagram of step S400 of the present invention; Figure 6 is a schematic structural diagram of step S500 of the present invention; Figure 7 is a schematic structural diagram of step S600 of the present invention; Figure 8 is a schematic structural diagram of step S700 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a schematic diagram of the structure of step S1100 of the present invention; Fig.12 is a schematic diagram of the structure of step S1200 of the present invention; Fig.13 is a schematic diagram of the structure of step S1300 of the present invention; In the figure, 1 is N+ Sub layer, 2 is N-Drift layer, 3 is N+ region, 4 is P+ region, 5 is CSL layer, 6 is P-body region, 7 is NP region, 8 is PP region, 9 is gate oxide layer, 10 is Poly layer, 11 is isolation dielectric layer, 12 is ohmic contact alloy layer, and 13 is front electrode metal layer. DETAILED DESCRIPTION
[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0018] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0020] A method for preparing a silicon carbide MOSFET device comprises the following steps: S100, forming an N- Drift layer 2 on the top surface of the N+ Sub layer 1 by epitaxial deposition; The doping concentration of N+ Sub layer 1 in step S100 is 1E19cm -2 , N-Drift layer 2 doping concentration is 5E15-3E16cm -2 .
[0021] S200, forming an N+ region 3 on the top surface of the N-Drift layer 2 by N ion implantation; The depth of N+ region 3 in step S200 is 0.4um-1.2um, and the doping concentration is 1E17-5E18cm -2 .
[0022] S300, forming a P+ region 4 on the top surface of the N+ region 3 by Al ion implantation; The depth of the P+ region 4 in step S300 is 0.4um-1.5um, and the doping concentration is 3E17-1E19cm -2 .
[0023] S400, forming a CSL layer 5 on the top surfaces of the N+ region 3 and the P+ region 4 again by epitaxial deposition; The thickness of the CSL layer 5 in step S400 is 0.6um-2um, and the doping concentration is 1E17-5E17cm -2 .
[0024] S500, forming a P-body region 6 on the top surface of the CSL layer 5 by Al ion implantation; The depth of the P-body region 6 in step S500 is 0.6um-2um, and the doping concentration is 5E17-1E18cm -2 .
[0025] S600, forming an NP region 7 on the top surface of the P-body region 6 by N ion implantation; The NP region in step S600 has a thickness of 0.3um-1.4um and a doping concentration of 1E18-1E19cm -2.
[0026] S700, forming a PP region 8 on the top surface of the P-body region 6 by Al ion implantation; The depth of the PP region 8 in step S700 is 0.3um-1.6um, and the doping concentration is 1E18-1E19cm -2 .
[0027] S800, all implanted regions are activated and formed by high temperature ion annealing; The high temperature ion annealing temperature in step S800 is between 1600°C and 1900°C.
[0028] S900, directly growing a gate oxide layer 9 on the top surfaces of the CSL layer 5, the P-body region 6 and the NP region 7 by high temperature dry oxygen oxidation; The thickness of the gate oxide layer 9 in step S900 is 40 nm-70 nm.
[0029] S1000, forming a Poly layer 10 on the top surface of the gate oxide layer 9 by depositing polysilicon; S1100, forming an isolation dielectric layer 11 on the top surfaces of the NP region 7 and the Poly layer 10 by oxide deposition; S1200, forming an ohmic contact alloy layer 12 on the top surfaces of the NP region 7 and the PP region 8 by sputtering Ni metal followed by thermal annealing; The Ni metal thickness in step S1200 is 0.3um-1um.
[0030] S1300, forming a front electrode metal layer 13 on the top of the device by sputtering Ti and AlCu metals; The thickness of the Ti metal in step S1300 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.
[0031] A silicon carbide MOSFET device includes an N+ Sub layer 1, an N- Drift layer 2, and a doping concentration of 1E17-5E18cm -2 N+ region 3, CSL layer 5, gate oxide layer 9, Poly layer 10, isolation dielectric layer 11 and front electrode metal layer 13; The top surface of the N+ region 3 is provided with a plurality of P+ regions 4 extending downward; the depth of the P+ region 4 is not less than the depth of the N+ region 3; the doping concentration of the P+ region 4 is 3E17-1E19cm -2 ; The CSL layer 5 is provided with: The P-body region 6 extends downward from the top surface of the CSL layer 5 and is connected to the top surface of the P+ region 4; the doping concentration of the P-body region 6 is 5E17-1E18cm-2 ; There are several NP regions 7, each extending downward from the top surface of the P-body region 6 and spaced apart from the bottom surface of the P-body region 6; in this case, a pair of NP regions 7 is provided in each P-body region 6; A plurality of PP regions 8 are provided, each extending downward from the top surface of the P-body region 6 and located between a pair of the NP regions 7; the depth of the PP region 8 is not less than the depth of the NP region 7; The bottom surface of the gate oxide layer 9 is connected to the CSL layer 5, the P-body region 6 and the NP region 7 respectively; The side of the isolation dielectric layer 11 extends downward to connect with the NP region 7; An ohmic contact alloy layer 12 connected to the NP region 7 and the PP region 8 respectively is disposed between adjacent isolation dielectric layers 11 .
[0032] The bottom surface of the front electrode metal layer 13 is connected to the isolation dielectric layer 11 and the ohmic contact alloy layer 12 respectively.
[0033] like Figure 1 As shown, heavily doped N+ region 3 and P+ region 4 are formed at the bottom of the P-body region in the SiC MOSFET. In the freewheeling region, the P+ region 4 is respectively arranged on both sides of the N+ region 3 to form a hole cut-off region of the N+ region 3. During the freewheeling process of the device, the holes of the parasitic PN junction body diode will be cut off in the hole cut-off region of the N+ region 3 and will not move to the Drift layer, thereby avoiding the recombination of holes and Drift layer electrons, reducing the occurrence of bipolar degradation effects, and improving the long-term stable performance of the device.
[0034] A heavily doped N+ region 3 is formed at the bottom of the P-body region 6 in the SiC MOSFET, so the N+ region 3 reduces the resistance of the device at the JFET region, thereby improving the device's conduction performance. At the same time, a heavily doped P+ region 4 is formed at the bottom of the P-body region 6 in the SiC MOSFET. The P+ region 4 has a deep junction depth and a high doping concentration, so when the device is working in the reverse cutoff process, the reverse voltage withstand capability of the device can be improved.
Claims
1. A method for preparing a silicon carbide MOSFET device, characterized in that: The steps include: S100, forming an N-Drift layer (2) and an N+ region (3) on the top surface of the N+ Sub layer (1); S200, forming a P+ region (4) on the top surface of the N+ region (3) by ion implantation; S300, forming a CSL layer (5) on the top surfaces of the N+ region (3) and the P+ region (4) by epitaxial deposition; S400, forming a P-body region (6), a NP region (7) and a PP region (8) in sequence on the top surface of the CSL layer (5) by ion implantation; S500, directly growing a gate oxide layer (9) on the top surfaces of the CSL layer (5), the P-body region (6) and the NP region (7) by high temperature dry oxygen oxidation; S600, forming a Poly layer (10) on the top surface of the gate oxide layer (9) by means of polysilicon deposition; S700, forming an isolation dielectric layer (11) on the top surfaces of the NP region (7) and the Poly layer (10) by means of oxide deposition; S800, forming an ohmic contact alloy layer (12) on the top surface of the NP region (7) and the PP region (8) by Ni metal sputtering followed by thermal annealing; S900, forming a front electrode metal layer (13) on the top of the device by sputtering Ti and AlCu metals.
2. A method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S100, the doping concentration of the N-Drift layer (2) is 5E15-3E16cm -2 .
3. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S100, the depth of the N+ region (3) is 0.4um-1.2um, and the doping concentration is 1E17-5E18cm -2 .
4. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S200, the depth of the P+ region (4) is 0.4um-1.5um, and the doping concentration is 3E17-1E19cm -2 .
5. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S300, the thickness of the CSL layer (5) is 0.6um-2um, and the doping concentration is 1E17-5E17cm -2 .
6. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S400, the depth of the P-body region (6) is 0.6um-2um, and the doping concentration is 5E17-1E18cm -2 .
7. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S400, the depth of the NP region (7) is 0.3um-1.4um, and the doping concentration is 1E18-1E19cm -2 .
8. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: In step S400, the depth of the PP region (8) is 0.3um-1.6um, and the doping concentration is 1E18-1E19cm -2 .
9. A silicon carbide MOSFET device, prepared by the method for preparing a silicon carbide MOSFET device according to any one of claims 1 to 8, characterized in that: It includes an N+ Sub layer (1), an N- Drift layer (2) arranged from bottom to top, and a doping concentration of 1E17-5E18cm -2 An N+ region (3), a CSL layer (5), a gate oxide layer (9), a Poly layer (10), an isolation dielectric layer (11) and a front electrode metal layer (13); The top surface of the N+ region (3) is provided with a plurality of P+ regions (4) extending downward; the doping concentration of the P+ region (4) is 3E17-1E19 cm -2 ; The CSL layer (5) includes: The P-body region (6) extends downward from the top surface of the CSL layer (5) and is connected to the top surface of the P+ region (4); the doping concentration of the P-body region (6) is 5E17-1E18cm -2 ; A plurality of NP regions (7) are provided, each extending downward from the top surface of the P-body region (6); A plurality of PP regions (8) are provided, each extending downward from the top surface of the P-body region (6) and located between a pair of the NP regions (7); The bottom surface of the gate oxide layer (9) is respectively connected to the CSL layer (5), the P-body region (6) and the NP region (7); The side of the isolation dielectric layer (11) extends downward to connect with the NP region (7); An ohmic contact alloy layer (12) connected to the NP region (7) and the PP region (8) respectively is provided between adjacent isolation dielectric layers (11).
10. A silicon carbide MOSFET device according to claim 9, characterized in that: The bottom surface of the front electrode metal layer (13) is respectively connected to the isolation dielectric layer (11) and the ohmic contact alloy layer (12).