Ring gate field effect transistor and preparation method thereof, chip and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to a gate-all-around field effect transistor, a preparation method thereof, a chip and electronic equipment, and the preparation method comprises the steps: vertically growing a vertical nanowire on a substrate; after the vertical nanowire grows to a preset height, changing the growth direction of the nanowire, and transversely growing a source electrode, a channel and a drain electrode; and depositing a layer of gate dielectric material surrounding the vertical nanowire, the source electrode, the channel and the drain electrode, and etching to obtain a gate dielectric layer which surrounds the channel. According to the technical scheme, the manufacturing difficulty and the production cost can be reduced, and the method is mainly used for preparing the gate-all-around field effect transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a gate-all-around field effect transistor and a preparation method thereof, a chip and an electronic device. Background Art

[0002] As the integration of chips continues to increase, the size of semiconductor devices also needs to be continuously reduced according to the proportional scaling theory. At present, the gate-all-around field-effect transistor (GAAFET) has attracted much attention. Its characteristics are that the surface of the channel area is surrounded by the gate, which has stronger gate control ability and larger effective channel width. Because it has a steep subthreshold swing (SS), quasi-ballistic transmission and a one-dimensional channel structure, it is more conducive to further improving the device driving capability. Therefore, the gate-all-around field-effect transistor device is considered to be a new generation of mainstream devices for 3nm and below process nodes.

[0003] At present, the ring-gate structure of the ring-gate field effect transistor is usually to stack the channel material and other materials and then etch them to obtain a suspended channel, and then grow the dielectric material to obtain the ring-gate field effect transistor. For example, the nanosheet-type ring-gate field effect transistor is grown by stacking Si and SiGe, and then removing SiGe by an isotropic etching method, so as to obtain a suspended channel. It takes multiple steps of growth and etching to form a suspended channel, which greatly increases the complexity of the process and the difficulty of manufacturing, and also increases the production cost of the product. Summary of the invention

[0004] In order to solve the problems in the related art, the embodiments of the present disclosure provide a gate-all-around field effect transistor and a method for manufacturing the same, a chip and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for preparing a gate-all-around field effect transistor, comprising:

[0006] Growing vertical nanowires vertically on a substrate;

[0007] After the vertical nanowire grows to a predetermined height, the growth direction of the nanowire is changed to grow a source electrode, a channel electrode and a drain electrode laterally;

[0008] A layer of gate dielectric material surrounding the vertical nanowire, the source, the channel and the drain is deposited, and then etched to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

[0009] In a possible implementation manner, the vertically growing vertical nanowires on the substrate includes:

[0010] The vertical nanowires are grown vertically on the substrate using epitaxial technology;

[0011] The source, channel and drain are grown laterally, including:

[0012] The source, channel and drain are grown laterally using epitaxial technology.

[0013] In a possible implementation manner, the laterally growing a source, a channel, and a drain includes:

[0014] First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the channel drain electrode is grown laterally using the drain electrode material.

[0015] In a possible implementation, the material of the vertical nanowire, the source material, the channel material and the drain material all include Group III-V materials.

[0016] In a possible implementation, the source electrode material and the drain electrode material are one III-V group material, and the channel material is another different III-V group material.

[0017] In a possible implementation, the doping elements in the source material and the drain material are of a first conductivity type, and the doping elements in the channel material are of a second conductivity type, and when the first conductivity type is N-type, the second conductivity type is P-type; or, when the first conductivity type is P-type, the second conductivity type is N-type.

[0018] In a possible implementation manner, in the process of laterally growing the source electrode using the source electrode material, the doping concentration of the doping element in the source electrode material is adjusted;

[0019] In the process of continuing to grow the channel laterally using the channel material, adjusting the doping concentration of the doping element in the channel material;

[0020] In the process of continuing to grow the drain electrode laterally using the drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

[0021] In a possible implementation, the method further includes:

[0022] Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on one side of the source, and the drain sidewall is located on one side of the drain;

[0023] Depositing an insulating layer, wherein the insulating layer covers the structure on the substrate;

[0024] Etching the insulating layer in the regions corresponding to the source and the drain respectively by an etching process to form a source through hole and a drain through hole;

[0025] Interconnect lines are deposited at the source and drain vias.

[0026] In a second aspect, an embodiment of the present disclosure provides a gate-all-around field effect transistor, which is prepared by the method for preparing a gate-all-around field effect transistor according to any one of the first aspects, and the gate-all-around field effect transistor comprises:

[0027] substrate;

[0028] A nanowire located on the substrate, the nanowire comprising a vertical nanowire and a lateral nanowire, the lateral nanowire comprising three sections of a source, a channel and a drain;

[0029] The gate dielectric layer is located around the channel.

[0030] In a possible implementation manner, the gate-all-around field effect transistor further includes:

[0031] A source sidewall and a drain sidewall located on both sides of the gate dielectric layer, wherein the source sidewall is located on one side of the source, and the drain sidewall is located on one side of the drain;

[0032] An insulating layer, the insulating layer covers the structure on the substrate and is provided with a source through hole and a drain through hole in regions corresponding to the source and the drain;

[0033] The interconnection line is located at the source through hole and the drain through hole, and is connected to the source and the drain respectively.

[0034] In a third aspect, an embodiment of the present disclosure provides a chip including the above-mentioned ring-gate field effect transistor.

[0035] In a fourth aspect, an electronic device including the above-mentioned ring-gate field effect transistor is provided in an embodiment of the present disclosure.

[0036] According to the technical solution provided by the embodiment of the present disclosure, vertical nanowires can be grown vertically on a substrate; after the vertical nanowires grow to a predetermined height, the growth direction of the nanowires is changed, and a source, a channel and a drain are grown laterally; a layer of gate dielectric material surrounding the vertical nanowires, the source, the channel and the drain is deposited, and a gate dielectric layer is obtained by etching, wherein the gate dielectric layer is located around the channel, thereby forming a ring-gate structure of a ring-gate field effect transistor, and through the self-growth of the laterally suspended nanowires, the grown laterally nanowires can be directly used as suspended channels in the ring gate, thereby eliminating the repeated steps of etching after growth to manufacture suspended channels, thereby simplifying the preparation process and reducing the manufacturing difficulty and production cost; and because the surface of the nanowires has atomic-level smoothness that cannot be achieved by traditional etching methods, the carrier scattering caused by surface roughness can be greatly reduced.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0039] Figure 1 A flow chart of a method for preparing a gate-all-around field effect transistor provided by an embodiment of the present disclosure is shown.

[0040] Figure 2 A schematic diagram of the growth process of a nanowire provided by an embodiment of the present disclosure is shown.

[0041] Figure 3 A preparation flow chart of a gate-all-around field effect transistor provided by an embodiment of the present disclosure is shown.

[0042] Figure 4 A schematic structural diagram of a gate-all-around field effect transistor provided in an embodiment of the present disclosure is shown.

[0043] Figure 5 A schematic structural diagram of another gate-all-around field effect transistor provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0045] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0046] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] Figure 1 A flow chart of a method for preparing a gate-all-around field effect transistor provided by an embodiment of the present disclosure is shown. Figure 1 As shown, the preparation method comprises the following steps S101-S103:

[0048] In step S101, vertical nanowires are vertically grown on a substrate;

[0049] In step S102, after the vertical nanowire grows to a predetermined height, the nanowire growth direction is changed to grow a source, a channel and a drain laterally;

[0050] In step S103, a layer of gate dielectric material surrounding the vertical nanowire, the source, the channel and the drain is deposited, and then etched to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

[0051] In one possible implementation, the substrate of the ring-gate field effect transistor may be a silicon substrate, which may be made of silicon (Si) or silicon-based materials. In some cases, in order to improve the performance of the device, other materials such as silicon germanium (SiGe) or germanium nitride (GaN) may be used to prepare the substrate, which is not limited here.

[0052] In one possible embodiment, nanowires (NWs) are one-dimensional structures that are confined to less than 100 nanometers in the lateral direction (no confinement in the longitudinal direction), Figure 2 A schematic diagram of a nanowire growth process provided by an embodiment of the present disclosure is shown. Figure 2 The direction of the arrow in the figure is the growth direction of the nanowires, which can be grown on the substrate as shown in Figure 2 As shown in the figure, a vertical nanowire 11 is first grown vertically. After the vertical nanowire 11 grows to a predetermined height, the growth direction of the nanowire is changed to grow a horizontal nanowire laterally. The horizontal nanowire is divided into three sections: a source 12, a channel 13 and a drain 14. Among them, the channel 13 is located between the source 12 and the drain 14. The positions of the source and the drain can be as follows: Figure 2 As shown, they can also be interchanged, without limitation. Figure 2 The example of generating the source 12 first, and then generating the channel 13 and the drain 14 in sequence is used for explanation; in this way, through the self-growth of the lateral nanowires, the grown lateral nanowires can be directly used as the suspended channel 13 in the ring gate structure, so that the repeated steps of etching after growth in the prior art to manufacture the suspended channel can be omitted, thereby simplifying the manufacturing steps, thereby reducing the manufacturing difficulty and production cost. It should be noted here that the predetermined height of the vertical nanowire 11 can be set according to actual needs, and the vertical here refers to perpendicular to the substrate. The lateral nanowires are parallel to the substrate and perpendicular to the vertical nanowires.

[0053] In one possible implementation, Figure 3 A preparation flow chart of a gate-all-around field effect transistor provided by an embodiment of the present disclosure is shown, such as Figure 3As shown, after the vertical nanowire 11 and the lateral source 12, channel 13 and drain 14 are prepared on the substrate 10, a layer of gate dielectric material 15 such as a high dielectric constant (High-K) material surrounding the vertical nanowire 11, the source 12, the channel 13 and the drain 14 can be deposited, and the dielectric layer around the source 12 and the drain 14 is etched away, leaving only the gate dielectric material around the channel 13 to form a gate dielectric layer 150, as shown in FIG. Figure 3 As shown, the gate dielectric layer 150 is directly above and below the channel 13, as well as directly in front of and behind the channel 13 ( Figure 3 (Not shown in the figure, the left and right sides of the channel 13 are the source and the drain) thus forming a ring-gate structure of the ring-gate field effect transistor.

[0054] According to the present embodiment, a vertical nanowire 11 can be grown vertically on a substrate; after the vertical nanowire 11 grows to a predetermined height, the nanowire growth direction is changed, and a source 12, a channel 13 and a drain 14 are grown laterally; a layer of gate dielectric material surrounding the vertical nanowire 11, the source 12, the channel 13 and the drain 14 is deposited, and a gate dielectric layer 150 is obtained by etching, wherein the gate dielectric layer 150 is located around the channel 13, thereby forming a ring-gate structure of a ring-gate field effect transistor; through the self-growth of the lateral suspended nanowire, the grown lateral nanowire can be directly used as the suspended channel 13 in the ring gate, thereby eliminating the repeated steps of etching after growth to manufacture the suspended channel, thereby simplifying the preparation process and reducing the manufacturing difficulty and production cost; and because the surface of the nanowire has an atomic-level smoothness that cannot be achieved by traditional etching methods, the carrier scattering caused by the surface roughness can be greatly reduced.

[0055] In a possible implementation manner, the vertically growing vertical nanowires on the substrate includes:

[0056] The vertical nanowires are grown vertically on the substrate using epitaxial technology;

[0057] The source, channel and drain are grown laterally, including:

[0058] The source, channel and drain are grown laterally using epitaxial technology.

[0059] In this embodiment, epitaxy technology is a material growth technology that can accurately control the growth length, growth direction and doping concentration. The epitaxy technology can accurately grow a vertical nanowire 11 perpendicular to the substrate with a predetermined height. The material of the vertical nanowire 11 can be a material such as gallium arsenide, and no impurity doping is required. When growing the source 12, the channel 13 and the drain 14, the epitaxy technology can accurately grow a lateral source 12, the channel 13 and the drain 14 with a predetermined length and a predetermined doping concentration.

[0060] In a possible implementation manner, the laterally growing a source, a channel, and a drain includes:

[0061] First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the channel drain electrode is grown laterally using the drain electrode material.

[0062] In this embodiment, the lateral nanowires are grown little by little. During the growth process of the lateral nanowires, the growth material of the nanowires can be changed. First, the source material is used to grow the source laterally, then the channel material is used to continue to grow the channel laterally, and then the drain material is used to continue to grow the drain laterally.

[0063] In a possible implementation, the material of the vertical nanowire, the source material, the channel material and the drain material all include Group III-V materials.

[0064] In this embodiment, the III-V group material is a compound composed of Group III elements (such as boron, aluminum, gallium, indium, and thallium) and Group V elements (such as nitrogen, phosphorus, arsenic, antimony, and bismuth) in the periodic table, such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride.

[0065] When vertical and lateral nanowires are made of III-V materials, the carrier mobility of the nanowires is greatly improved, which can be 4-60 times higher than that of existing Si.

[0066] In a possible implementation, the source electrode material and the drain electrode material are one III-V group material, and the channel material is another different III-V group material.

[0067] In this embodiment, the growth material of the nanowire can be changed during its growth, so that the advantages of different materials can be simultaneously possessed, and a device with better performance and stronger comprehensive capabilities can be obtained. When the characteristics of one III-V group material are more suitable for the source 12 and the drain 14, and the characteristics of another III-V group material are more suitable for the channel 13, the two materials can be directly grown in appropriate positions by adjusting the growth material of the nanowire, so that the performance of the two materials can be maximized, so that the device has the advantages of two different materials, and a device with better comprehensive performance can be obtained.

[0068] For example, gallium arsenide can be used as the source material and the drain material, and indium phosphide can be used as the channel material. The source 12 is first grown using gallium arsenide, and then the channel 13 is grown using indium phosphide, and then the drain 14 is grown using gallium arsenide. Among them, the electron mobility of gallium arsenide is much higher than that of traditional semiconductor materials such as silicon, and the electron transmission speed in the material is faster, which helps to improve the performance of the device; indium phosphide has a high saturated electron drift velocity, which is very important for improving the response speed and frequency characteristics of the device. Using these two materials to prepare lateral nanowires can have the advantages of both materials and improve the overall performance of the device.

[0069] In a possible implementation, the doping elements in the source material and the drain material are of a first conductivity type, and the doping elements in the channel material are of a second conductivity type, and when the first conductivity type is N-type, the second conductivity type is P-type; or, when the first conductivity type is P-type, the second conductivity type is N-type.

[0070] In this embodiment, during the growth of the source 12, the channel 13 and the drain 14, the composition of the doping element in the growth material can be adjusted, so that the doping steps of the source 12, the channel 13 and the drain 14 can be achieved when the nanowires are grown. For example, P-type elements can be doped when the source 12 is grown, N-type elements can be doped when the channel 13 is grown, and the doping is switched back to P-type elements when the drain 14 is grown, so that a PNP transistor can be obtained; of course, N-type elements can also be doped when the source 12 is grown, P-type elements can be doped when the channel 13 is grown, and the doping is switched back to N-type elements when the drain 14 is grown, so that an NPN transistor can be obtained.

[0071] This embodiment can perform impurity doping while growing nanowires. Compared with the prior art that requires ion implantation for doping, the doping steps are simpler.

[0072] In one possible implementation, in the process of laterally growing a source electrode using a source electrode material, the doping concentration of the doping element in the source electrode material is adjusted; in the process of continuing to laterally grow a channel using a channel electrode material, the doping concentration of the doping element in the channel electrode material is adjusted; in the process of continuing to laterally grow a drain electrode using a drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

[0073] In this embodiment, during the growth of the source 12, the channel 13 and the drain 14, the concentration of the doping element can be adjusted as needed, so as to adjust the corresponding doping concentration. For example, in the process of growing the source 12, the concentration of the doping element can be configured as the first concentration first, so that after growing a section of the source, the concentration of the doping element is adjusted to a second concentration higher than the first concentration by a predetermined value, so that after growing a section of the source, the concentration of the doping element is further adjusted to a third concentration higher than the second concentration by a predetermined value, so as to grow a section of the source. Alternatively, in the process of growing the source 12, the concentration of the doping element can be configured as the first concentration first, so that after growing a section of the source, the concentration of the doping element can be adjusted to a second concentration higher than the first concentration by a predetermined value, so that after growing a section of the source, the concentration of the doping element is further adjusted to the first concentration, so as to grow a section of the source; and so on, the doping concentration of the doping element in the source material can be adjusted according to different requirements of the device. Similarly, in the process of growing the channel, the doping concentration of the doping element in the channel material can be adjusted; in the process of growing the drain, the doping concentration of the doping element in the drain material can be adjusted.

[0074] In this embodiment, impurity doping is performed while the nanowires are grown, so that the doping concentration and position can be controlled more accurately.

[0075] In a possible implementation, the method further includes:

[0076] Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on one side of the source, and the drain sidewall is located on one side of the drain;

[0077] Depositing an insulating layer, wherein the insulating layer covers the structure on the substrate;

[0078] Etching the insulating layer in the regions corresponding to the source and the drain respectively by an etching process to form a source through hole and a drain through hole;

[0079] Interconnect lines are deposited at the source and drain vias.

[0080] In this embodiment, if Figure 3 As shown, a source sidewall 161 and a drain sidewall 162 can be formed on both sides of the gate dielectric layer 150, wherein the source sidewall 161 is located on one side of the source 12, and the drain sidewall 162 is located on one side of the drain 14; the source sidewall 161 provides physical isolation between the gate and the source, and the drain sidewall 162 provides physical isolation between the gate and the drain, which can prevent current from leaking from the gate to the source / drain region, thereby reducing leakage current. At the same time, the sidewalls enhance the structural stability of the device, and prevent damage to the gate structure due to mechanical stress during the manufacturing process or during use.

[0081] In this embodiment, the source through hole 181 and the drain through hole 182 are located in the region of the insulating layer 17 corresponding to the source 12 and the drain 14, and are used to respectively connect the source 12 and the drain 14 regions with the metal interconnection lines of the upper layer, thereby realizing vertical transmission of current; the interconnection lines can be metal wires, which are used to connect the source 12 and the drain 14 to form a circuit network.

[0082] The present disclosure also provides a gate-all-around field effect transistor, which is prepared by using the above-mentioned method for preparing the gate-all-around field effect transistor. Figure 4 FIG. 4 shows a schematic diagram of a gate-all-around field effect transistor provided by an embodiment of the present disclosure. Figure 4 As shown, the gate-all-around field effect transistor comprises:

[0083] Substrate 10;

[0084] The nanowires are located on the substrate 10, and the nanowires include vertical nanowires 11 and lateral nanowires. The lateral nanowires include three sections of nanowires, namely, a source 12, a channel (not shown) and a drain 14. The channel is located between the source 12 and the drain 14. The positions of the source and the drain can be as follows: Figure 4 As shown, they can also be interchanged and are not limited here; the vertical here means perpendicular to the substrate, the lateral nanowires are parallel to the substrate and perpendicular to the vertical nanowires;

[0085] The gate dielectric layer 150 is located around the channel 13 .

[0086] In the present embodiment, the self-growth of lateral nanowires can be used directly as suspended channels in the ring gate, thus eliminating the repeated steps of etching after growth to produce suspended channels, thereby simplifying the preparation process and reducing the manufacturing difficulty and production cost; and because the surface of the nanowires has atomic-level smoothness that cannot be achieved by traditional etching methods, the carrier scattering caused by surface roughness can be greatly reduced.

[0087] In one possible implementation, Figure 5 FIG. 4 shows a schematic diagram of the structure of another gate-all-around field effect transistor provided by an embodiment of the present disclosure, such as Figure 5 As shown, the gate-all-around field effect transistor further includes:

[0088] A source sidewall 161 and a drain sidewall 162 located on both sides of the gate dielectric layer 150 , wherein the source sidewall 161 is located on one side of the source 12 , and the drain sidewall 162 is located on one side of the drain 14 ;

[0089] An insulating layer 171, the insulating layer covers the structure on the substrate and is provided with a source through hole 181 and a drain through hole 182 in the region corresponding to the source 12 and the drain 14;

[0090] Interconnection lines are located at the source through hole 181 and the drain through hole 182 , and are connected to the source 12 and the drain 14 respectively.

[0091] In this embodiment, if Figure 5 As shown, source sidewalls and drain sidewalls can be set on both sides of the gate dielectric layer 150, the source sidewall is located on the side of the source 12, and the drain sidewall is located on the side of the drain 14; the source sidewall provides physical isolation between the gate and the source level, and the drain sidewall provides physical isolation between the gate and the drain 14, which can prevent current from leaking from the gate to the source / drain area, thereby reducing leakage current. At the same time, the sidewalls enhance the structural stability of the device and prevent damage to the gate structure due to mechanical stress during the manufacturing process or during use.

[0092] In this embodiment, the through hole is used to connect the source 12 and drain 14 regions with the upper metal interconnection line, thereby realizing the vertical transmission of current; the interconnection line can be a metal wire, which is used to connect the source 12 and drain 14 to form a circuit network.

[0093] The embodiments of the present disclosure also provide a chip including the above-mentioned all-round gate field effect transistor, and an electronic device including the above-mentioned all-round gate field effect transistor.

[0094] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for preparing a gate-all-around field effect transistor, characterized in that: include: Growing vertical nanowires vertically on a substrate; After the vertical nanowire grows to a predetermined height, the growth direction of the nanowire is changed to grow a source electrode, a channel electrode and a drain electrode laterally; A layer of gate dielectric material surrounding the vertical nanowire, the source, the channel and the drain is deposited, and then etched to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

2. The preparation method according to claim 1, characterized in that: The step of vertically growing vertical nanowires on a substrate comprises: The vertical nanowires are grown vertically on the substrate using epitaxial technology; The source, channel and drain are grown laterally, including: The source, channel and drain are grown laterally using epitaxial technology.

3. The preparation method according to claim 1, characterized in that: The source, channel and drain are grown laterally, including: First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the channel drain electrode is grown laterally using the drain electrode material.

4. The preparation method according to claim 3, characterized in that: The materials of the vertical nanowires, the source electrode material, the channel electrode material and the drain electrode material all include III-V group materials.

5. The preparation method according to claim 4, characterized in that: The source electrode material and the drain electrode material are one III-V group material, and the channel material is another different III-V group material.

6. The preparation method according to claim 3, characterized in that: The doping elements in the source material and the drain material are of the first conductivity type, and the doping elements in the channel material are of the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; or when the first conductivity type is P-type, the second conductivity type is N-type.

7. The preparation method according to claim 6, characterized in that: In the process of laterally growing the source electrode using the source electrode material, adjusting the doping concentration of the doping element in the source electrode material; In the process of continuing to grow the channel laterally using the channel material, adjusting the doping concentration of the doping element in the channel material; In the process of continuing to grow the drain electrode laterally using the drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

8. The preparation method according to claim 1, characterized in that: The method further comprises: Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on one side of the source, and the drain sidewall is located on one side of the drain; Depositing an insulating layer, wherein the insulating layer covers the structure on the substrate; Etching the insulating layer in regions corresponding to the source and drain electrodes respectively by an etching process to form a source through hole and a drain through hole; Interconnect lines are deposited at the source and drain vias.

9. A gate-all-around field effect transistor, characterized in that: The method for preparing a gate-all-around field effect transistor according to any one of claims 1 to 8 is used for preparation, wherein the gate-all-around field effect transistor comprises: substrate; A nanowire located on the substrate, the nanowire comprising a vertical nanowire and a lateral nanowire, the lateral nanowire comprising three sections of a source, a channel and a drain; The gate dielectric layer is located around the channel.

10. The gate-all-around field effect transistor according to claim 9, characterized in that: Also includes: A source sidewall and a drain sidewall located on both sides of the gate dielectric layer, wherein the source sidewall is located on one side of the source, and the drain sidewall is located on one side of the drain; An insulating layer, the insulating layer covers the structure on the substrate and is provided with a source through hole and a drain through hole in regions corresponding to the source and the drain; The interconnection line is located at the source through hole and the drain through hole, and is connected to the source and the drain respectively.

11. A chip, characterized in that: The invention comprises the gate-all-around field effect transistor as claimed in claim 9 or 10.

12. An electronic device, characterized in that: The invention comprises the gate-all-around field effect transistor as claimed in claim 9 or 10.

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