Semiconductor power device and manufacturing method thereof

Abstract

The invention discloses a semiconductor power device, comprising: each device unit structure comprising a second conductivity type doped well region formed in a surface region of a drift region. And a trench gate passing through the well region. A heavily doped source region of the first conductive type is formed in the surface region of the well region. And a first ion implantation doped column doped in a second conduction type is formed at the bottom of the well region. The well region and the source region are connected to a source electrode composed of the front metal layer through a contact hole in the top of the source region. The well region extends into the terminal region, more than one second conductive type doped second ion implantation doped column is formed at the bottom of the well region in the terminal region, and the second ion implantation doped column is of an annular structure, surrounds the peripheral side of the primitive cell region and serves as a constituent part of the terminal protection structure. The invention further discloses a manufacturing method of the semiconductor power device. According to the invention, the withstand voltage same as that of an SGT device can be achieved, so that the wafer can be prevented from warping; and the breakdown voltage can be stabilized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor power device. The present invention also relates to a method for manufacturing a semiconductor power device. Background Art

[0002] Split shielded gate (SGT) power field effect transistors have extremely low specific on-resistance and are therefore widely used in energy conversion systems. However, the thick field oxide and deep trench process of existing traditional shielded gate MOSFETs can cause wafer warping, posing challenges to subsequent thinning and packaging processes, especially affecting the development of 12-inch wafer high-voltage platforms. In addition, the terminals of existing traditional shielded gate power MOSFETs are composed of field oxides. When the device undergoes repetitive avalanche drain-source current (IAR), part of the mobile charge generated by impact ionization will be captured by the silicon oxide interface at the terminal. As the IAR cycle increases, the device breakdown point will gradually move up from the bottom of the terminal to the top PN junction. The device breakdown voltage first rises, reaches a maximum value, and then drops sharply. The following is combined with Figure 1A and Figure 1B To explain in further detail:

[0003] like Figure 1A As shown in FIG. 1 , it is a three-dimensional diagram of the terminal structure of the existing SGT MOSFET; Figure 1B FIG. 1 is a cross-sectional view of a device unit structure of an existing SGTMOSFET; taking an N-type device as an example, the existing SGTMOSFET includes:

[0004] An N-type doped drift region 102 is formed on a semiconductor substrate. The drift region 102 is located in the primary cell region and the terminal region. The terminal region surrounds the primary cell region.

[0005] A plurality of parallel device unit structures are formed in the original cell region.

[0006] like Figure 1B As shown, each device unit structure includes:

[0007] A P-type doped well region 105 is formed in the surface region of the drift region 102 .

[0008] An N-type heavily doped source region 106 is formed in the surface region of the well region 105 .

[0009] The polysilicon gate 104 and the source polysilicon 113 are formed in a deep trench, the source polysilicon 113 and the inner surface of the deep trench are isolated by a field oxide layer 112, the polysilicon gate 104 and the side of the deep trench are isolated by a gate oxide layer 103, and the polysilicon gate 104 and the source polysilicon 113 are also isolated by a gate oxide layer 103.

[0010] The polysilicon gate 104 passes through the trench gate of the well region 105 , and the surface of the well region 105 covered by the side of the polysilicon gate 104 is used to form a conductive channel.

[0011] Both the well region 105 and the source region 106 are connected to a source electrode composed of a front metal layer 110 through a contact hole 107 penetrating through an interlayer film 108 at the top of the source region 106 .

[0012] like Figure 1A As shown, the well region 105 extends into the termination region, and the termination structure in the termination region includes a field oxide layer 113 filled in a deep trench and a source polysilicon 113. The well region 105 extending into the termination region is connected to the source through a contact hole 107 at the top.

[0013] An N-type heavily doped drain region 101 is formed at the bottom of the drift region 102. The semiconductor substrate is heavily doped with N-type, and the drain region 101 is composed of a thinned semiconductor substrate; or, the drain region 101 is composed of a back ion implantation region formed by back ion implantation of a thinned semiconductor substrate with heavily P-type doping.

[0014] Depend on Figure 1A As shown, as the IAR cycle increases, the device breakdown point will gradually move up from point A, i.e., the bottom corner of the deep trench, to point B, i.e., close to the PN junction formed by the drift region 102 and the well region 105. This will cause the device breakdown voltage to rise first, then drop sharply after reaching the maximum value. Summary of the invention

[0015] The technical problem to be solved by the present invention is to provide a semiconductor power device that can achieve the same withstand voltage as an SGT device, while avoiding the use of deep trenches and thick oxide layer processes, thereby preventing wafer warping; and simultaneously avoiding the capture of movable charges by the terminal structure and thereby stabilizing the breakdown voltage, thereby improving the performance of the device. The present invention also provides a method for manufacturing a semiconductor power device.

[0016] In order to solve the above technical problems, the semiconductor power device provided by the present invention comprises:

[0017] A drift region doped with a first conductivity type is formed on a semiconductor substrate, wherein the drift region is located in a primary cell region and a terminal region, and the terminal region surrounds a peripheral side of the primary cell region.

[0018] A plurality of parallel device unit structures are formed in the original cell region.

[0019] Each of the device unit structures comprises:

[0020] A well region doped with a second conductivity type is formed in a surface region of the drift region.

[0021] A trench gate passes through the well region, and a surface of the well region covered by a side surface of the trench gate is used to form a conductive channel.

[0022] A source region heavily doped with a first conductivity type is formed in a surface region of the well region.

[0023] A first ion implantation doped column doped with a second conductive type is formed at the bottom of the well region, and a bottom surface of the first ion implantation doped column is located below a bottom surface of the trench gate and above a bottom surface of the drift region.

[0024] The well region and the source region are both connected to a source electrode composed of a front metal layer through a contact hole on the top of the source region.

[0025] The well region extends into the terminal region, and one or more second ion implantation doping columns doped with a second conductive type are formed at the bottom of the well region in the terminal region. The second ion implantation doping columns are in a ring structure surrounding the periphery of the original cell region and serve as a component of the terminal protection structure. The bottom surface of the second ion implantation doping columns is located below the bottom surface of the trench gate and above the bottom surface of the drift region. The well region extending into the terminal region is connected to the source through a contact hole at the top.

[0026] A further improvement is that the semiconductor power device is a power MOSFET.

[0027] A drain region heavily doped with the first conductivity type is formed at the bottom of the drift region.

[0028] The semiconductor substrate is heavily doped with a first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with a second conductivity type.

[0029] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0030] A further improvement is that the first ion implantation doping column and the second ion implantation doping column are formed simultaneously using the same ion implantation process.

[0031] A further improvement is that the doping impurities of the first ion implantation doping column and the second ion implantation doping column are activated by rapid thermal annealing.

[0032] A further improvement is that the material of the semiconductor substrate includes silicon, SiC and gallium nitride.

[0033] A further improvement is that the drift region consists of a first epitaxial layer.

[0034] A further improvement is that the trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer, the gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer is filled in the gate trench.

[0035] A further improvement is that the operating voltage of semiconductor power devices is from tens of V to 200 V.

[0036] A further improvement is that the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semiconductor power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0037] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor power device, comprising the following steps:

[0038] A drift region doped with a first conductive type is formed on the surface of a semiconductor substrate; the drift region is located in a primary cell region and a terminal region, the primary cell region is a formation region for a plurality of parallel device unit structures, and the terminal region surrounds the peripheral side of the primary cell region.

[0039] A trench gate of each of the device unit structures is formed in a selected area of ​​the drift region.

[0040] A well region doped with a second conductive type is formed in the surface area of ​​the drift region, the well region is located in the original cell region and extends into the terminal region; the trench gate passes through the well region, and the surface of the well region covered by the side of the trench gate is used to form a conductive channel.

[0041] A source region heavily doped with a first conductivity type is formed in a surface region of the well region. The source region is located in the primary cell region and is self-aligned with a side surface of the corresponding trench gate.

[0042] The first ion implantation for second conductive type doping forms a first ion implantation doping column at the bottom of the well region in the original cell region and a second ion implantation doping column at the bottom of the well region in the terminal region; the bottom surface of the first ion implantation doping column is located below the bottom surface of the trench gate and above the bottom surface of the drift region, and the bottom surface of the second ion implantation doping column is located below the bottom surface of the trench gate and above the bottom surface of the drift region; the second ion implantation doping column is in an annular structure surrounding the periphery of the original cell region and serves as a component of the terminal protection structure.

[0043] The doping impurities of the first ion implantation doping column and the second ion implantation doping column are activated by rapid thermal annealing.

[0044] An interlayer film, contact holes and a front metal layer are formed, and the front metal layer is patterned to form a source electrode; in the primitive cell region, the well region and the source region are connected to the source electrode composed of the front metal layer through the contact hole at the top of the source region; in the terminal region, the well region is connected to the source electrode through the contact hole at the top.

[0045] A further improvement is that the semiconductor power device is a power MOSFET, and also includes the following back side processes:

[0046] The semiconductor substrate is thinned, and then a drain region heavily doped with the first conductivity type is formed on the back side of the drift region; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with the second conductivity type.

[0047] A back metal layer is formed on the back side of the drain region and a drain electrode is formed of the back metal layer.

[0048] A further improvement is that the material of the semiconductor substrate includes silicon, SiC and gallium nitride.

[0049] A further improvement is that the drift region consists of a first epitaxial layer.

[0050] A further improvement is that the trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer, the gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer is filled in the gate trench.

[0051] A further improvement is that the first ion implantation is achieved by multiple ion implantations with different implantation energies.

[0052] A further improvement is that the operating voltage of semiconductor power devices is from tens of V to 200 V.

[0053] A further improvement is that the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semiconductor power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0054] In order to eliminate the adverse effects of the deep trenches and thick oxide layers of the existing SGT devices on wafer warpage, the present invention eliminates the shielding polysilicon and thick oxide layer at the bottom of the trench gate, so the depth of the trench only needs to meet the requirements for forming the trench gate. Therefore, the present invention eliminates the deep trenches and thick oxide layers, thereby eliminating the adverse effects of the deep trenches and thick oxide layers of the existing SGT devices on wafer warpage. The influence of wafer warpage is particularly serious on large-sized wafers such as 12-inch wafers, so the present invention is conducive to the development of high-voltage platforms for large-sized wafers.

[0055] The present invention eliminates the shielding polysilicon and the thick oxide layer, adds a first ion implantation doping column doped with a second conductivity type at the bottom of the well region of the original cell region, and adds a second ion implantation doping column doped with a second conductivity type at the bottom of the well region of the terminal region. The first ion implantation doping column and the second ion implantation doping column can be realized by ion implantation and annealing activation, and the realization process is simple; in the original cell region, the first ion implantation doping column can laterally deplete the drift region at the bottom of the trench gate when reverse biased, thereby replacing the shielding polysilicon's lateral depletion function of the drift region, so that the withstand voltage in the original cell region and the efficiency of the existing SGT device are improved. The effect is the same; in the terminal region, the second ion implanted doping column can also laterally deplete the drift region when reverse biased, which can ensure that the depletion capacity of the terminal structure is the same as the depletion capacity of the existing shielding polysilicon that penetrates the deep trench, avoiding the capture of movable charges by the thick oxide layer in the existing deep trench, so that the terminal structure does not capture the movable charges, so that the withstand voltage of the terminal structure does not decrease with the increase of the captured movable charges, so that the withstand voltage of the terminal structure can be stabilized while ensuring the withstand voltage of the terminal structure, and finally the breakdown voltage of the device can be stabilized and the performance of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0057] Figure 1A This is a three-dimensional diagram of the terminal structure of the existing SGT MOSFET;

[0058] Figure 1B is a cross-sectional view of a device unit structure of an existing SGT MOSFET;

[0059] Figure 2 is a three-dimensional diagram of a terminal structure of a semiconductor power device according to an embodiment of the present invention;

[0060] Figure 3 is a cross-sectional view of a device unit structure of a semiconductor power device according to an embodiment of the present invention;

[0061] Figure 4A-4His a cross-sectional view of a device unit structure in each step of a method for manufacturing a semiconductor power device according to an embodiment of the present invention;

[0062] Figure 5 is a SEM image of a semiconductor power device formed by the method for manufacturing a semiconductor power device according to an embodiment of the present invention;

[0063] Figure 6 is a comparison curve of the breakdown voltage (BV) stability of the semiconductor power device according to the embodiment of the present invention and the existing SGT MOSFET after 1000 repetitions (Cycle) of the repeated avalanche drain-source current (IAR);

[0064] Figure 7 It is a comparison curve diagram of the high temperature reverse bias (HTRB) 1000h test results of the semiconductor power device according to the embodiment of the present invention and the existing SGT MOSFET. DETAILED DESCRIPTION

[0065] like Figure 2 , which is a three-dimensional diagram of the terminal structure of the semiconductor power device according to an embodiment of the present invention; Figure 3 FIG. 1 is a cross-sectional view of a device unit structure of a semiconductor power device according to an embodiment of the present invention; the semiconductor power device according to an embodiment of the present invention comprises:

[0066] A drift region 2 doped with a first conductivity type is formed on a semiconductor substrate. The drift region 2 is located in a primary cell region and a terminal region. The terminal region surrounds the primary cell region.

[0067] A plurality of parallel device unit structures are formed in the original cell region.

[0068] like Figure 3 As shown, each device unit structure includes:

[0069] A well region 5 doped with the second conductivity type is formed in the surface region of the drift region 2 .

[0070] A trench gate passes through the well region 5 , and a surface of the well region 5 covered by the side surface of the trench gate is used to form a conductive channel.

[0071] A source region 6 heavily doped with the first conductivity type is formed in the surface region of the well region 5 .

[0072] A first ion implantation doping column 7 doped with the second conductive type is formed at the bottom of the well region 5, and the bottom surface of the first ion implantation doping column 7 is located below the bottom surface of the trench gate and above the bottom surface of the drift region 2. In the embodiment of the present invention, the doping concentration of the well region 5 is greater than the doping concentration of the first ion implantation doping column 7. Figure 3In the overlapping region between the well region 5 and the first ion implantation doping column 7 , the doping concentration is dominated by the doping concentration of the well region 5 .

[0073] Both the well region 5 and the source region 6 are connected to the source electrode composed of the front metal layer 10 through the contact hole 10a passing through the interlayer film 8 at the top of the source region 6. A well contact region 9 heavily doped with the second conductivity type is also formed at the bottom of the contact hole 10a corresponding to the source region 6 to realize the well region 5 being led out to the source electrode through the contact hole 10a.

[0074] like Figure 2 As shown, the well region 5 extends into the terminal region, and at the bottom of the well region 5 in the terminal region, one or more second ion implantation doping columns 7a doped with a second conductive type are formed. The second ion implantation doping columns 7a are in a ring structure surrounding the periphery of the original cell region and serve as a component of the terminal protection structure. The bottom surface of the second ion implantation doping column 7a is located below the bottom surface of the trench gate and above the bottom surface of the drift region 2. The well region 5 extending into the terminal region is connected to the source through a contact hole 10a at the top. Figure 2 In the overlapping region between the well region 5 and the second ion implantation doping column 7 a , the doping concentration is dominated by the doping concentration of the well region 5 .

[0075] In the embodiment of the present invention, the semiconductor power device is a power MOSFET.

[0076] A drain region 1 heavily doped with a first conductivity type is formed at the bottom of the drift region 2 .

[0077] The semiconductor substrate is heavily doped with the first conductivity type, and the drain region 1 is composed of a thinned semiconductor substrate; or, the drain region 1 is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with the second conductivity type.

[0078] A drain electrode composed of a back metal layer 11 is formed on the back side of the drain region 1 .

[0079] In some embodiments, the material of the back metal layer 11 includes Al, and the material of the front metal layer 10 includes Al.

[0080] In the embodiment of the present invention, the first ion implantation doping column 7 and the second ion implantation doping column 7a are formed simultaneously by using the same ion implantation process.

[0081] The doping impurities of the first ion implantation doping column 7 and the second ion implantation doping column 7 a are activated by rapid thermal annealing.

[0082] Materials of the semiconductor substrate include silicon, SiC and gallium nitride.

[0083] The drift region 2 consists of a first epitaxial layer.

[0084] The trench gate comprises a gate trench, a gate dielectric layer 3 and a gate conductive material layer 4. The gate dielectric layer 3 is formed on the inner surface of the gate trench, and the gate conductive material layer 4 is filled in the gate trench.

[0085] In some embodiments, the gate dielectric layer 3 is a gate oxide layer; and the gate conductive material layer 4 is a polysilicon gate.

[0086] In the embodiment of the present invention, the operating voltage of the semiconductor power device is tens of V to 200 V, and the existing SGT device can be replaced.

[0087] In the embodiment of the present invention, the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the semiconductor power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0088] In order to eliminate the adverse effects of the deep trenches and thick oxide layers of the existing SGT devices on wafer warpage, the embodiments of the present invention eliminate the shielding polysilicon and thick oxide layers at the bottom of the trench gate, so the depth of the trench only needs to meet the requirements for forming the trench gate. Therefore, the embodiments of the present invention eliminate the deep trenches and thick oxide layers, thereby eliminating the adverse effects of the deep trenches and thick oxide layers of the existing SGT devices on wafer warpage. The influence of wafer warpage is particularly serious on large-sized wafers such as 12-inch wafers, so the embodiments of the present invention are conducive to the development of high-voltage platforms for large-sized wafers.

[0089] The embodiment of the present invention eliminates the shielding polysilicon and the thick oxide layer, and adds a first ion implantation doping column 7 doped with the second conductivity type at the bottom of the well region 5 in the original cell region and a second ion implantation doping column 7a doped with the second conductivity type at the bottom of the well region 5 in the terminal region. The first ion implantation doping column 7 and the second ion implantation doping column 7a can be realized by ion implantation plus annealing activation, and the realization process is simple; in the original cell region, the first ion implantation doping column 7 can laterally deplete the drift region 2 at the bottom of the trench gate when reverse biased, thereby replacing the shielding polysilicon's lateral depletion function of the drift region 2, so that the withstand voltage in the original cell region and the existing SG The effect is the same as that of the T device; in the terminal area, the second ion implanted doping column 7a can also laterally deplete the drift region 2 under reverse bias, which can ensure that the depletion capacity of the terminal structure is the same as the depletion capacity of the existing shielding polysilicon that penetrates the deep trench, avoiding the capture of movable charges by the thick oxide layer in the existing deep trench, so that the terminal structure does not capture the movable charges, so that the withstand voltage of the terminal structure does not decrease with the increase of the captured movable charges, so that the withstand voltage of the terminal structure can be stabilized while ensuring the withstand voltage of the terminal structure, and finally the breakdown voltage of the device can be stabilized and the performance of the device can be improved.

[0090] like 4A to 4H , which is a cross-sectional view of a device unit structure in each step of a method for manufacturing a semiconductor power device according to an embodiment of the present invention; the method for manufacturing a semiconductor power device according to an embodiment of the present invention comprises the following steps:

[0091] Step S101: Figure 4A As shown, a drift region 2 doped with a first conductive type is formed on the surface of a semiconductor substrate; the drift region 2 is located in a primary cell region and a terminal region, the primary cell region is a formation region for multiple parallel device unit structures, and the terminal region surrounds the primary cell region.

[0092] In the method of the embodiment of the present invention, the material of the semiconductor substrate includes silicon, SiC and gallium nitride.

[0093] The drift region 2 consists of a first epitaxial layer.

[0094] Step S102: Figure 4D As shown, trench gates of each device unit structure are formed in selected areas of the drift region 2 .

[0095] The trench gate comprises a gate trench, a gate dielectric layer 3 and a gate conductive material layer 4. The gate dielectric layer 3 is formed on the inner surface of the gate trench, and the gate conductive material layer 4 is filled in the gate trench.

[0096] The steps of forming the trench gate include:

[0097] like Figure 4B As shown, a gate trench is formed. Compared with the deep trench in the existing SGT device, the depth of the gate trench is shallower. At the same time, in the method of the embodiment of the present invention, it is not necessary to form a thick oxide layer on the bottom surface of the deep trench and the inner surface of the bottom area. This makes it difficult for the wafer to warp in the method of the embodiment of the present invention. The wafer is a single wafer formed by a semiconductor substrate.

[0098] like Figure 4C As shown, a gate dielectric layer 3 is formed on the inner surface of the gate trench. In some embodiments, the gate dielectric layer 3 is a gate oxide layer formed by a thermal oxidation process.

[0099] like Figure 4D As shown, a gate conductive material layer 4 is filled in the gate trench formed with the gate dielectric layer 3. In some embodiments, the gate conductive material layer 4 is a polysilicon gate.

[0100] Step S103: Figure 4E As shown, a well region 5 doped with a second conductive type is formed in the surface area of ​​the drift region 2, the well region 5 is located in the original cell region and extends into the terminal region; the trench gate passes through the well region 5, and the surface of the well region 5 covered by the side of the trench gate is used to form a conductive channel.

[0101] Step S104: Figure 4E As shown, a source region 6 heavily doped with the first conductivity type is formed in the surface region of the well region 5 . The source region 6 is located in the original cell region and is self-aligned with the side surface of the corresponding trench gate.

[0102] Step S105: Figure 4F As shown, the first ion implantation for second conductive type doping forms a first ion implantation doping column 7 at the bottom of the well region 5 in the original cell region and a second ion implantation doping column 7a at the bottom of the well region 5 in the terminal region; the bottom surface of the first ion implantation doping column 7 is located below the bottom surface of the trench gate and above the bottom surface of the drift region 2, and the bottom surface of the second ion implantation doping column 7a is located below the bottom surface of the trench gate and above the bottom surface of the drift region 2; the second ion implantation doping column 7a is in a ring structure surrounding the periphery of the original cell region and serves as a component of the terminal protection structure.

[0103] In the method of the embodiment of the present invention, the first ion implantation is implemented by multiple ion implantations with different implantation energies. Each ion implantation of the first ion implantation is a high-energy implantation with a relatively large implantation energy, so as to control the implantation depth.

[0104] In the method of the embodiment of the present invention, the operating voltage of the semiconductor power device is tens of V to 200 V, and is used to replace the existing SGT device.

[0105] The injection energy of each ion injection of the first ion injection can be set according to the operating voltage of the semiconductor power device. The greater the operating voltage, the thicker the drift region 2, the deeper the depth of the first ion injection doping column 7 and the second ion injection doping column 7a, and the greater the injection energy of the first ion injection.

[0106] Step S106: Figure 4F As shown, the doping impurities of the first ion implantation doping column 7 and the second ion implantation doping column 7 a are activated by rapid thermal annealing.

[0107] Step S107: Figure 4G As shown, an interlayer film 8 is formed.

[0108] The contact hole 10a is formed, including the following steps:

[0109] A contact hole opening is formed, and the contact hole opening at the top of the source region 6 passes through the source region 6 .

[0110] like Figure 4H As shown, a well contact region 9 heavily doped with the second conductivity type is formed at the bottom of the contact hole opening by self-alignment.

[0111] like Figure 3 As shown, a metal layer is filled in the contact hole opening to form a contact hole 10a.

[0112] Afterwards, a front metal layer 10 is formed and patterned to form a source electrode. In the method of the embodiment of the present invention, the front metal layer 10 is patterned to form a gate electrode, and the gate conductive material layer 4 is connected to the gate electrode through the contact hole 10a at the top. Figure 3 The gate is not shown in the corresponding cross section.

[0113] In the original cell region, both the well region 5 and the source region 6 are connected to the source electrode composed of the front metal layer 10 through the contact hole 10 a at the top of the source region 6 .

[0114] like Figure 2 As shown, in the terminal region, the well region 5 is connected to the source through a contact hole 10a at the top.

[0115] In the method of the embodiment of the present invention, the semiconductor power device is a power MOSFET, and further includes the following back side process:

[0116] The semiconductor substrate is thinned, and then a drain region 1 heavily doped with a first conductivity type is formed on the back side of the drift region 2; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region 1 is composed of the thinned semiconductor substrate; or, the drain region 1 is composed of a back ion implantation region formed by back ion implantation of a thinned semiconductor substrate heavily doped with a second conductivity type.

[0117] A back metal layer 11 is formed on the back side of the drain region 1 and a drain electrode composed of the back metal layer 11 is formed.

[0118] In some embodiment methods, the material of the back metal layer 11 includes Al, and the material of the front metal layer 10 includes Al.

[0119] In the method of the embodiment of the present invention, the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; the implanted impurities of the first ion implantation include boron. In other embodiments, the semiconductor power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0120] In the method of the embodiment of the present invention, only one additional mask needs to be added, and a P-type column is formed in the drift region through multiple high-energy boron injection and rapid annealing processes. No additional thermal process and deep trench process are required, which is fully compatible with the traditional BCD process, successfully eliminating the risk of wafer warpage of the existing traditional shielded gate power MOSFET, and providing a more stable solution for higher voltage resistance, high integration, large-size wafer production, and development of new processes. In addition, the terminal of the semiconductor power device of the embodiment of the present invention is composed of a P-type column, which avoids the phenomenon of movable charge capture, so its breakdown voltage is more stable after experiencing IAR, and at the same time, it also shows a more stable breakdown voltage after the high temperature reverse bias (HTRB) reliability assessment.

[0121] like Figure 5 , which is a SEM image of a semiconductor power device formed by the manufacturing method of a semiconductor power device according to an embodiment of the present invention; the drain region, i.e., the semiconductor substrate (sub), is indicated by the mark 1', the drift region is indicated by the mark 2', the gate conductive material layer is indicated by the mark 4', the well region is indicated by the mark 5', the source region is indicated by the mark 6', the first ion implantation doping column is indicated by the mark 7', the contact hole is indicated by the mark 10a', and the front metal layer is indicated by the mark 10'. Since the semiconductor power device according to the present invention is an N-type device, Figure 5 In the figure, the first ion implantation doping column 7' is also represented by P-pillar, that is, a P-type column, the well region 5' is also represented by P-body, that is, a P-type body region. The source is also represented by source metal, that is, a source metal, the contact hole 10a' is also represented by CT, the source region 6' is also represented by N+, the interlayer film is also represented by ILD, and the gate conductive material layer 4' is also represented by gate.

[0122] Figure 6 is a comparison curve of the IAR 1000Cycle BV stability of the semiconductor power device according to the embodiment of the present invention and the existing SGT MOSFET; Figure 6 The line corresponding to the semiconductor power device of the embodiment of the present invention is the line corresponding to New. These four curves are all located in the dotted circle 201 and basically overlap, which indicates that the BV stability of the semiconductor power device of the embodiment of the present invention is good.

[0123] Figure 6 In FIG. 2 , the line corresponding to the existing SGT MOSFET is the line corresponding to Old, and the four curves are all located in the dotted circle 202 .

[0124] The four curves of New and Old correspond to four test conditions: IAR 0C, IAR 100C, IAR 500C and IAR 1000C, respectively, indicating that the number of repetitive pulses applicable in the test process is 0 times, 100 times, 500 times and 1000 times.

[0125] It can be seen from the dotted circle 202 that the curves corresponding to IAR 0C, IAR 100C, IAR 500C and IAR 1000C are curves 202a, 202b, 202c and 202d respectively. Therefore, it can be known that the BV of the existing SGT MOSFET structure will gradually increase after experiencing IAR.

[0126] like Figure 7The figure shows the comparison curve of the HTRB 1000h test results of the semiconductor power device of the embodiment of the present invention and the existing SGT MOSFET; the horizontal axis is the corresponding sample number, that is, the breakdown voltage or BV data of the vertical axis is the data obtained by performing HTRB experiments on multiple samples. The temperature and bias conditions of HTRB are Figure 7 Similarly, the line corresponding to the semiconductor power device of the embodiment of the present invention is the line corresponding to New, and these four curves are all located in the dotted circle 203 and are basically overlapped, which indicates that the BV stability of the semiconductor power device of the embodiment of the present invention is good.

[0127] The line corresponding to the existing SGT MOSFET is the line corresponding to Old, and these four curves are all located in the dotted circle 204 .

[0128] The four curves of New and Old correspond to four test conditions: HTRB 0H, HTRB 168H, HTRB500H and HTRB 1000H, indicating that the time of experiencing the HTRB condition during the test process is 0 hours, 168 hours, 500 hours and 1000 hours respectively.

[0129] It can be seen from the dotted circle 204 that the curves corresponding to HTRB 0H, HTRB 168H, HTRB 500H and HTRB 1000H are curves 204a, 204b, 204c and 204d respectively. Therefore, it can be known that the BV of the existing SGT MOSFET structure is generally higher after undergoing HTRB tests of different time periods, and the longer the time, the greater the BV deviation. However, the BV of the semiconductor power device of the embodiment of the present invention tends to be stable before and after the test.

[0130] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A semiconductor power device, characterized in that: include: A drift region doped with a first conductivity type formed on a semiconductor substrate, the drift region being located in a primary cell region and a terminal region, the terminal region surrounding a peripheral side of the primary cell region; A plurality of parallel device unit structures are formed in the primitive cell region; Each of the device unit structures comprises: A well region doped with a second conductivity type is formed in a surface region of the drift region; A trench gate passing through the well region, wherein the surface of the well region covered by the side surface of the trench gate is used to form a conductive channel; A source region heavily doped with a first conductivity type is formed in a surface region of the well region; A first ion implantation doped column doped with a second conductive type is formed at the bottom of the well region, wherein a bottom surface of the first ion implantation doped column is located below a bottom surface of the trench gate and above a bottom surface of the drift region; The well region and the source region are both connected to a source electrode composed of a front metal layer through a contact hole at the top of the source region; The well region extends into the terminal region, and one or more second ion implantation doping columns doped with a second conductive type are formed at the bottom of the well region in the terminal region. The second ion implantation doping columns are in a ring structure surrounding the periphery of the original cell region and serve as a component of the terminal protection structure. The bottom surface of the second ion implantation doping columns is located below the bottom surface of the trench gate and above the bottom surface of the drift region. The well region extending into the terminal region is connected to the source through a contact hole at the top.

2. The semiconductor power device according to claim 1, characterized in that: The semiconductor power device is a power MOSFET; A drain region heavily doped with a first conductivity type is formed at the bottom of the drift region; The semiconductor substrate is heavily doped with a first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with a second conductivity type; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

3. The semiconductor power device according to claim 1, wherein: The first ion implantation doped column and the second ion implantation doped column are formed simultaneously by using the same ion implantation process.

4. The semiconductor power device according to claim 3, characterized in that: The doping impurities of the first ion implantation doping column and the second ion implantation doping column are activated by rapid thermal annealing.

5. The semiconductor power device according to claim 1, wherein: The materials of the semiconductor substrate include silicon, SiC and gallium nitride.

6. The semiconductor power device according to claim 1, wherein: The drift region consists of a first epitaxial layer.

7. The semiconductor power device according to claim 1, characterized in that: The trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer. The gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer is filled in the gate trench.

8. The semiconductor power device according to claim 1, wherein: The operating voltage of semiconductor power devices ranges from tens of V to 200 V.

9. The semiconductor power device according to any one of claims 1 to 8, characterized in that: The semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semiconductor power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

10. A method for manufacturing a semiconductor power device, characterized in that: The steps include: A drift region doped with a first conductive type is formed on the surface of the semiconductor substrate; the drift region is located in a primary cell region and a terminal region, the primary cell region is a formation region of a plurality of parallel device unit structures, and the terminal region surrounds the peripheral side of the primary cell region; forming a trench gate of each of the device unit structures in a selected area of ​​the drift region; A well region doped with a second conductive type is formed in the surface region of the drift region, the well region is located in the original cell region and extends into the terminal region; the trench gate passes through the well region, and the surface of the well region covered by the side of the trench gate is used to form a conductive channel; Forming a heavily doped source region of the first conductivity type in the surface area of ​​the well region, the source region being located in the original cell region and self-aligned with the side surface of the corresponding trench gate; The first ion implantation for second conductivity type doping forms a first ion implantation doping column at the bottom of the well region in the original cell region and a second ion implantation doping column at the bottom of the well region in the terminal region; the bottom surface of the first ion implantation doping column is located below the bottom surface of the trench gate and above the bottom surface of the drift region, and the bottom surface of the second ion implantation doping column is located below the bottom surface of the trench gate and above the bottom surface of the drift region; the second ion implantation doping column is in an annular structure surrounding the periphery of the original cell region and serves as a component of the terminal protection structure; Performing rapid thermal annealing to activate the doping impurities in the first ion implantation doping column and the second ion implantation doping column; forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode; In the primitive cell region, the well region and the source region are both connected to a source electrode composed of a front metal layer through a contact hole at the top of the source region; In the terminal region, the well region is connected to the source through a contact hole at the top.

11. The method for manufacturing a semiconductor power device according to claim 10, wherein: The semiconductor power device is a power MOSFET, which also includes the following back-side processes: The semiconductor substrate is thinned, and then a drain region heavily doped with a first conductivity type is formed on the back side of the drift region; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with a second conductivity type; A back metal layer is formed on the back side of the drain region and a drain electrode is formed of the back metal layer.

12. The method for manufacturing a semiconductor power device according to claim 10, wherein: The materials of the semiconductor substrate include silicon, SiC and gallium nitride.

13. The method for manufacturing a semiconductor power device according to claim 10, wherein: The drift region consists of a first epitaxial layer.

14. The method for manufacturing a semiconductor power device according to claim 10, wherein: The trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer. The gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer is filled in the gate trench.

15. The method for manufacturing a semiconductor power device according to claim 10, wherein: The first ion implantation is achieved by multiple ion implantations with different implantation energies.

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