Semiconductor device

Abstract

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device 1 according to one embodiment includes: a semiconductor substrate 11 of a first conductivity type; and a semiconductor layer 12 of the first conductivity type, and the semiconductor layer includes: a trench gate 14, a source region 15 of the first conductivity type; a contact region 16 of a second conductivity type, and a column region 17 of the second conductivity type. In the semiconductor layer, a plurality of trench gates 14 are discretely formed along a first direction X and a second direction Y; the source region 15 is in contact with the trench gates 14 and surrounds the trench gates 14; the contact region 16 is located between the source regions adjacent in the second direction Y; and the column region 17 extends from an end 16a of the contact region 16 closer to the semiconductor substrate toward the semiconductor substrate 11.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a superjunction structure as a semiconductor device. One type of cell structure of the semiconductor device disclosed in Patent Document 1 is a trench gate structure. Patent Document 2 discloses a semiconductor device including a trench gate MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a superjunction is formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-222710 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-115385

[0004] [overview] An embodiment of the present disclosure relates to a semiconductor device capable of reducing on-resistance.

[0005] a contact region of a second conductivity type formed on the main surface of the semiconductor layer and a column region of the second conductivity type; a semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type located on the semiconductor substrate and having a main surface located opposite the semiconductor substrate; a trench gate having a trench extending from the main surface toward the semiconductor substrate, a gate insulating film formed on an inner surface of the trench, and a gate electrode filled in the trench via the gate insulating film; a source region of the first conductivity type formed on the main surface; a contact region of a second conductivity type formed on the main surface; and a column region of the second conductivity type; a plurality of the trench gates are discretely formed in the semiconductor layer along a first direction and a second direction that intersect each other when viewed from a thickness direction of the semiconductor layer; the source region is in contact with the trench gate and surrounds the trench gate when viewed from the thickness direction; the contact region is located between the source regions adjacent to each other in the second direction; and the column region extends from an end of the contact region closer to the semiconductor substrate toward the semiconductor substrate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of an example of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram for explaining the internal structure of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a schematic diagram for explaining an example of a cross-sectional configuration taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic diagram for explaining an example of a cross-sectional configuration taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a schematic diagram for explaining an example of a cross-sectional configuration taken along line VV in FIG. [Figure 6] FIG. 6 is a diagram for explaining an example of the structure on the main surface of the epitaxial layer (semiconductor layer) in the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a plan view of the epitaxial layer (semiconductor layer) side as viewed from the position of line VII-VII in FIG. [Figure 8] FIG. 8 is a plan view of the epitaxial layer (semiconductor layer) side as viewed from the position of line VIII-VIII in FIG. [Figure 9] FIG. 9 is a plan view of an example of a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining another example of the structure on the main surface of the epitaxial layer (semiconductor layer) in the semiconductor device. [Figure 11] FIG. 11 is a plan view of the epitaxial layer (semiconductor layer) side as viewed from the position of line XI-XI in FIG.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The same or equivalent parts in each drawing will be designated by the same reference numerals, and duplicate explanations will be omitted. The dimensional proportions of the drawings do not necessarily correspond to those in the description.

[0008] (First embodiment) 1 is a plan view of a semiconductor device according to a first embodiment. The semiconductor device 1 includes a metal insulator semiconductor field effect transistor (MISFET). In the following description, the semiconductor device 1 includes a metal oxide semiconductor field effect transistor (MOSFET), which is a form of MISFET.

[0009] The semiconductor device 1 is, for example, a semiconductor switching device. The semiconductor device 1 has an outer shape of a chip that is approximately square in plan view, as shown in Fig. 1. The size of the chip-shaped semiconductor device 1 is about several millimeters in length in the thickness direction and in each of two directions perpendicular thereto. The shape of the semiconductor device 1 is not limited to the illustrated shape.

[0010] The semiconductor device 1 has an active region 2 and a peripheral region 3 surrounding the active region 2. The active region 2 is disposed, for example, in the center of the semiconductor device 1 in a plan view. A guard ring may be formed in the peripheral region 3.

[0011] A source pad 4 is formed on the surface of the semiconductor device 1. The source pad 4 is formed so as to cover almost the entire surface of the semiconductor device 1. In this embodiment, the source pad 4 is formed in the active region 2. The source pad 4 has a generally square shape in plan view with the four corners curved outward. A recess 4a is formed in the source pad 4 near the center of one side. The recess 4a is an area where the source pad 4 is not formed. The source pad 4 may be formed of aluminum, another metal, or the like.

[0012] A gate pad 5 is disposed in the recess 4a. The gate pad 5 may be made of aluminum or another metal. A gap is provided between the gate pad 5 and the source pad 4, and they are insulated from each other.

[0013] Examples of semiconductor materials constituting the semiconductor device 1 include silicon (Si) and compound semiconductors. Examples of compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Examples of III-V compound semiconductors include Ga-containing semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN). Examples of IV-IV compound semiconductors include Si-containing semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe).

[0014] Examples of N-type impurities used in the semiconductor device 1 include P (phosphorus), As (arsenic), and SB (antimony), and examples of P-type impurities include B (boron), Al (aluminum), and Ga (gallium).

[0015] The basic (or main) structure of the semiconductor device 1 will be described with reference to FIGS. 2 to 5. FIG. 2 is a diagram illustrating the internal structure of the semiconductor device 1. FIG. 2 is an enlarged view of region A shown in FIG. 1, showing an epitaxial layer (semiconductor layer) 12 (described later) viewed from the main surface 12a side. Region A is a region located in the active region 2. FIG. 3 is a schematic diagram illustrating an example of a cross-sectional configuration taken along line III-III in FIG. 2. FIG. 4 is a schematic diagram illustrating an example of a cross-sectional configuration taken along line IV-IV in FIG. 2. FIG. 5 is a schematic diagram illustrating an example of a cross-sectional configuration taken along line V-V in FIG. 2. A back electrode 13 is also illustrated in FIGS. 3 to 5.

[0016] In the following description, the X-axis direction, Y-axis direction, and Z-axis direction shown in Figures 1 to 5 may be used. The Z-axis direction corresponds to the stacking direction of the semiconductor substrate 11 and the epitaxial layer 12, the thickness direction of the epitaxial layer 12, or the thickness direction of the semiconductor substrate 11. The X-axis direction and the Y-axis direction are directions perpendicular to the Z-axis direction. The X-axis direction and the Y-axis direction are perpendicular to each other.

[0017] The semiconductor device 1 includes a semiconductor substrate 11 and a semiconductor layer formed on a first surface 11a of the semiconductor substrate 11. The semiconductor layer may be an epitaxial layer formed by epitaxial growth. In the following, a configuration in which the semiconductor layer formed on the semiconductor substrate 11 is an epitaxial layer 12 will be described.

[0018] The conductivity type of the semiconductor substrate 11 and the epitaxial layer 12 is N type as a first conductivity type. + The impurity concentration of the semiconductor substrate 11 is, for example, 1×10 18 cm -3 Above 1×10 21 cm -3 The epitaxial layer 12 is an N layer having a lower impurity concentration than the semiconductor substrate 11. - The impurity concentration of the epitaxial layer 12 is, for example, 1×10 15 cm -3 Above 1×10 17 cm -3The following is the result.

[0019] The thickness of the semiconductor substrate 11 is, for example, 30 μm or more and 400 μm or less, and the thickness of the epitaxial layer 12 is, for example, 3 μm or more and 100 μm or less.

[0020] 2, a plurality of trench gates 14 are formed in the epitaxial layer 12. The plurality of trench gates 14 may be formed in the active region 2 (see FIG. 1). The plurality of trench gates 14 are discretely arranged in a first direction and a second direction that intersect with each other when viewed from the thickness direction of the epitaxial layer 12.

[0021] In this embodiment, unless otherwise specified, the thickness direction of the epitaxial layer 12, the first direction, and the second direction are perpendicular to each other. Specifically, the thickness direction of the epitaxial layer 12 corresponds to the Z-axis direction, the first direction corresponds to the X-axis direction, and the second direction corresponds to the Y-axis direction. Therefore, hereinafter, the thickness direction of the epitaxial layer 12, the first direction, and the second direction may also be referred to as the Z-axis direction, the X-axis direction, and the Y-axis direction.

[0022] An example of the distance d1 between adjacent trench gates 14 among the multiple trench gates 14 arranged in the X-axis direction (first direction) is 0.1 μm or more and 0.6 μm or less. The distance d1 may be the length between adjacent trench gates 14 on an imaginary line passing through the center of each of the multiple trench gates 14 arranged in the X-axis direction. The multiple trench gates 14 arranged in the X-axis direction may be arranged at equal intervals. An example of the distance d2 between adjacent trench gates 14 among the multiple trench gates 14 arranged in the Y-axis direction (second direction) is 0.4 μm or more and 2 μm or less. The distance d2 may be the length between adjacent trench gates 14 on an imaginary line passing through the center of each of the multiple trench gates 14 arranged in the Y-axis direction. The multiple trench gates 14 arranged in the Y-axis direction may be arranged at equal intervals. The center of the trench gate 14 is the center of the trench gate 14 when viewed from the Z-axis direction. The distance d1 may be shorter than the distance d2.

[0023] The shape of the trench gate 14 when viewed from the Z-axis direction may be a quadrilateral (e.g., a rectangle, a square, a parallelogram, etc.), as shown in FIG. 2, or another polygon (e.g., an octagon, a hexagon), or may be a circle (including an ellipse).

[0024] The trench gate 14 includes a trench 141 , a gate insulating film 142 , and a gate electrode 143 .

[0025] The trench 141 extends from the main surface 12a of the epitaxial layer 12 toward the semiconductor substrate 11. The main surface 12a is the surface of the epitaxial layer 12 opposite the semiconductor substrate 11. The length of the trench 141 in the Z-axis direction is shorter than the thickness of the epitaxial layer 12. Therefore, the trench 141 does not reach the semiconductor substrate 11. The length of the trench 141 in the Z-axis direction corresponds to the depth of the trench gate 14. The trench 141 is formed, for example, by etching. The length of the trench 141 in the Z-axis direction is, for example, 0.6 μm or more and 3 μm or less.

[0026] The gate insulating film 142 is formed on the inner surface of the trench 141. The gate insulating film 142 is formed of, for example, silicon oxide. The gate insulating film 142 may be formed by a method appropriate for the material of the gate insulating film 142. For example, the gate insulating film 142 may be formed by thermal oxidation, a CVD method, or a combination thereof. An example thickness of the gate insulating film 142 is 50 Å or more and 1000 Å or less (5 nm or more and 100 nm or more).

[0027] The gate electrode 143 is buried in the trench 141. Specifically, the gate electrode 143 is buried in the trench 141 having a gate insulating film 142 formed on the inner surface thereof. The gate electrode 143 may be formed of a P-type semiconductor. Specifically, the gate electrode 143 is formed of a P + In this case, the impurity concentration of the gate electrode 143 is, for example, 1×10 18 cm -3Above 1×10 21 cm -3 The gate electrode 143 is P + The gate electrode 143 may be formed of polysilicon of the same type as the gate electrode 143. The gate electrode 143 may be formed by, for example, a CVD method.

[0028] As shown in FIG. 2, the semiconductor device 1 has a source region 15 and a contact region 16 on the main surface 12a of the epitaxial layer 12. In FIG. 2, the source region 15 is hatched to indicate the source region 15. The contact region 16 is a region for electrically connecting a column region 17 (described later) to the source pad 4. In one embodiment, the contact region 16 functions as a backgate contact region. Therefore, hereinafter, the contact region 16 will be referred to as the backgate contact region 16 unless otherwise specified.

[0029] The source region 15 is in contact with the trench gate 14 (specifically, the trench 141). The source region 15 is an N-type region. Specifically, the source region 15 is an N + The impurity concentration of the source region 15 is, for example, 1×10 18 cm -3 Above 1×10 21 cm -3 The depth of the source region 15 may be shallower than the depth of the trench gate 14. An example of the depth of the source region 15 is 0.1 μm or more and 0.6 μm or less.

[0030] The source region 15 surrounds each trench gate 14. In this embodiment, of the trench gates 14 adjacent along the X-axis direction, the source region 15 surrounding one trench gate 14 is in contact with the source region 15 surrounding the other trench gate 14. In other words, when viewed from the Z-axis direction, the source region 15 fills the space between the trench gates 14 adjacent along the X-axis direction. Of the trench gates 14 adjacent along the Y-axis direction, the source region 15 surrounding one trench gate 14 and the source region 15 surrounding the other trench gate 14 do not contact each other.

[0031] The back gate contact region 16 is formed on the main surface 12a of the epitaxial layer 12 between the source region 15 surrounding one of the trench gates 14 adjacent to each other along the Y-axis direction and the source region 15 surrounding the other of the trench gates 14. As shown in FIGS. 2 and 4, the back gate contact region 16 extends in the X-axis direction when viewed from the Z-axis direction. The back gate contact region 16 may extend from one end of the active region 2 to the other end in the X-axis direction when viewed from the Z-axis direction. The back gate contact region 16 is of the second conductivity type, P-type. In this embodiment, the back gate contact region 16 is P + An example of the impurity concentration of the back gate contact region 16 is 1×10 18 cm -3 Above 1×10 21 cm -3 The length of the back gate contact region 16 in the Z-axis direction is, for example, 0.1 μm or more and 1.0 μm or less. The depth of the back gate contact region 16 may be the same as the depth of the source region 15. The length of the back gate contact region 16 in the Y-axis direction is, for example, 0.2 μm or more and 2 μm or less.

[0032] As shown in FIGS. 3 and 4, the semiconductor device 1 has a column region 17 extending from a lower end 16a of the back gate contact region 16 toward the semiconductor substrate 11. The lower end 16a is the end of the back gate contact region 16 that is closer to the semiconductor substrate 11. When viewed from the Z-axis direction, the column region 17 extends in the X-axis direction, just like the back gate contact region 16. The length of the column region 17 in the Z-axis direction is shorter than the length between the lower end 16a and the semiconductor substrate 11. The lower end 17a of the column region 17 is not in contact with the semiconductor substrate 11. The length of the column region 17 in the Z-axis direction is, for example, 1 μm or more and 20 μm or less. The column region 17 is a P-type region. Specifically, the column region 17 is a P-type region having an impurity concentration lower than that of the back gate contact region 16. ― An example of the impurity concentration of the column region 17 is 1×10 15 cm -3Above 1×10 17 cm -3 The following is the result.

[0033] In one embodiment, the column region 17 may have multiple column portions 171 stacked in the Z-axis direction, as shown in FIGS. 3 and 4. In the embodiment shown in FIGS. 3 and 4, adjacent column portions 171 are in contact with each other in the Z-axis direction. Adjacent column portions 171 may be spaced apart in the Z-axis direction. When adjacent column portions 171 are spaced apart, the distance between the adjacent column portions 171 is, for example, 0.5 μm or more and 2 μm or less. The number of column portions 171 is not limited to three as shown in FIGS. 3 and 4, but may be two, four or more. The column region 17 having multiple column portions 171 is formed, for example, using a multi-epitaxial growth method in which a P-type impurity implantation process for forming the column region 17 and an epitaxial growth process are alternately performed.

[0034] The length of the column regions 17 in the Y-axis direction may be approximately the same as the interval d2 between adjacent trench gates 14 in the Y-axis direction. The column regions 17 are arranged at a predetermined pitch along the Y-axis direction. An example of the predetermined pitch is 5 μm or more and 20 μm or less. The column regions 17 may or may not be in contact with the source regions 15.

[0035] The semiconductor device 1 has column regions 17 arranged discretely along the Y-axis direction in the epitaxial layer 12, and thus the semiconductor device 1 has a superjunction structure.

[0036] The arrangement relationship of the above-described plurality of trench gates 14, source regions 15, back gate contact regions 16, and column regions 17 can also be expressed as follows, for example.

[0037] When viewed from the Z-axis direction, a plurality of source regions 15 are formed on the main surface 12a of the epitaxial layer 12 of the semiconductor device 1, discretely arranged along the Y-axis direction. Each source region 15 extends in the X-axis direction. A plurality of trench gates 14 are formed in each source region 15, discretely arranged along the X-axis direction. The length of each trench gate 14 in the Y-axis direction is shorter than the length of the source region 15 in the Y-axis direction. Therefore, each trench gate 14 formed in the source region 15 is in contact with and surrounded by the source region 15. On the main surface 12a, a back-gate contact region 16 is formed between adjacent source regions 15 in the Y-axis direction. The back-gate contact region 16 is in contact with the source region 15 and extends in the X-axis direction. A column region 17 extending from a lower end 16a of the back-gate contact region 16 toward the semiconductor substrate 11 is formed in the epitaxial layer 12.

[0038] 3 to 5, in the semiconductor device 1, a back surface electrode 13 is formed on the second surface 11b of the semiconductor substrate 11. The second surface 11b is the surface opposite to the first surface 11a, and the back surface electrode 13 may be formed to cover the entire second surface 11b. The back surface electrode 13 is an electrode that functions as a drain electrode in the semiconductor device 1. For example, an electrode having a layered structure (Ti / Ni / Au / Ag) in which titanium (Ti), nickel (Ni), gold (Au), and silver (Ag) are layered in this order from the semiconductor substrate 11 side can be used as the back surface electrode 13.

[0039] In the semiconductor device 1, the source region 15 and the back gate contact region 16 are electrically connected to the source pad 4, and the gate electrode 143 is electrically connected to the gate pad 5. An example of the wiring structure between the source region 15 and the back gate contact region 16 and the source pad 4, and the wiring structure between the gate electrode 143 and the gate pad 5 will be described with reference to FIGS. 6 to 8. However, the structure realizing the electrical connection between the source region 15 and the back gate contact region 16 and the source pad 4, and the structure realizing the electrical connection between the gate electrode 143 and the gate pad 5 are not limited to the forms described with reference to FIGS. 6 to 8.

[0040] FIG. 6 is a diagram illustrating an example of a structure on the main surface 12a of the semiconductor device 1. Similar to FIG. 3, FIG. 6 also schematically illustrates a cross-sectional configuration taken along line III-III in FIG. 2. FIG. 7 is a plan view of the epitaxial layer (semiconductor layer) 12 as viewed from line VII-VII in FIG. 6. FIG. 8 is a plan view of the epitaxial layer (semiconductor layer) 12 as viewed from line VIII-VIII in FIG. 6. The region illustrated in FIGS. 7 and 8 corresponds to region A in FIG. 1, similar to FIG. 2. Interlayer insulating films 21a and 21b are omitted from FIGS. 7 and 8. In other words, FIGS. 7 and 8 are schematic views of the semiconductor device 1 as viewed through the interlayer insulating films 21a and 21b. Similar to FIG. 2, the hatching in FIGS. 7 and 8 indicates the source region 15.

[0041] In the semiconductor device 1, an interlayer insulating film 21a is formed on the main surface 12a of the epitaxial layer 12. The material of the interlayer insulating film 21a is an insulating material such as silicon oxide or silicon nitride.

[0042] A gate wiring 22 is provided on the interlayer insulating film 21a and on the trench gate 14 (more specifically, on the gate electrode 143). The gate wiring 22 is a wiring for electrically connecting the gate pad 5 and the gate electrode 143, and is also known as a gate liner. The gate wiring 22 is made of a conductive material.

[0043] The gate wiring 22 is routed on the interlayer insulating film 21a so as to be electrically connected to the gate electrodes 143 of the multiple trench gates 14. For example, as shown in FIG. 7, in the region A shown in FIG. 1, multiple gate wirings 22 extending in the X-axis direction are arranged in the Y-axis direction. The multiple gate wirings 22 are connected outside the region shown in FIG. 7 and are further electrically connected to the gate pad 5.

[0044] The gate wiring 22 is electrically connected to the gate electrode 143 using gate contact vias 24 (see FIGS. 6 and 8) formed in the interlayer insulating film 21a. The gate contact vias 24 may be formed by filling a conductive material into a through-hole formed in the interlayer insulating film 21a. As shown in FIG. 8, the gate contact vias 24 are provided corresponding to each trench gate 14.

[0045] On the interlayer insulating film 21a, a source wiring 23 is provided on a region between adjacent trench gates 14 in the Y-axis direction (more specifically, on the source region 15 and the back gate contact region 16). The source wiring 23 is insulated from the gate wiring 22. The source wiring 23 is a wiring for electrically connecting the source region 15 and the back gate contact region 16 to the source pad 4. In this embodiment, as shown in FIGS. 6 and 7, a plurality of source wirings 23 extending in the X-axis direction are arranged along the Y-axis direction.

[0046] The source wiring 23 is electrically connected to the source region 15 and the back gate contact region 16 using source contact vias 25a (see FIGS. 6 and 8) formed in the interlayer insulating film 21a. The source contact vias 25a may be formed by filling a through hole formed in the interlayer insulating film 21a with a conductive material. The conductive material used for the source contact vias 25a may be the same as the conductive material used for the gate contact vias 24. In this embodiment, as shown in FIGS. 6 and 8, a plurality of source contact vias 25a extending in the X-axis direction are arranged along the Y-axis direction.

[0047] An interlayer insulating film 21b is formed on the interlayer insulating film 21a so as to fill the gate wiring 22 and the source wiring 23. The material of the interlayer insulating film 21b may be the same as the material of the interlayer insulating film 21a. In this case, the interlayer insulating films 21a and 21b can be regarded as a single interlayer insulating film. The gap between the gate wiring 22 and the source wiring 23 is also filled with the interlayer insulating film 21b. This more reliably ensures insulation between the gate wiring 22 and the source wiring 23.

[0048] On the interlayer insulating film 21b, a source pad 4 (see FIG. 7) and a gate pad 5 (not shown in FIGS. 7 and 8) are formed.

[0049] The source pad 4 is electrically connected to the source wiring 23 by a source contact via 25b formed in the interlayer insulating film 21b. In this embodiment, as shown in FIGS. 6 and 7, a plurality of source contact vias 25b extending in the X-axis direction are arranged along the Y-axis direction. As described above, the source wiring 23 is electrically connected to the source region 15 and the back gate contact region 16 by the source contact via 25a. Therefore, the source pad 4 is electrically connected to the source region 15 and the back gate contact region 16 using the source contact via 25b, the source wiring 23, and the source contact via 25a.

[0050] The gate pad 5 is electrically connected to the gate wiring 22 by a gate contact via (not shown) formed in the interlayer insulating film 21b. As described above, the gate wiring 22 is electrically connected to the gate electrode 143 by the gate contact via 24. Therefore, the gate pad 5 is electrically connected to the gate electrode 143 using the gate contact via (not shown) formed in the interlayer insulating film 21b, the gate wiring 22, and the gate contact via 24.

[0051] The semiconductor device 1 is manufactured, for example, as follows.

[0052] An epitaxial layer 12 including column regions 17 that are discretely arranged in the Y-axis direction and extend in the X-axis direction is formed on the first surface 11a of the semiconductor substrate 11 by epitaxial growth (semiconductor layer formation process). Specifically, the epitaxial layer 12 is formed by epitaxial growth while ion-implanting N-type impurities. In the process of forming the epitaxial layer 12, at the stage of forming the column regions 17, a multi-epitaxial growth method is performed in which a P-type impurity implantation process for forming the column regions 17 and an epitaxial growth process are alternately performed. In this manner, the epitaxial layer 12 including the column regions 17 is formed. The column regions 17 formed in this process have a plurality of column portions 171 stacked in the Z-axis direction. The column regions 17 are formed so that the main surface 12a of the epitaxial layer 12 and the column regions 17 are spaced apart.

[0053] Next, a back-gate contact region forming step (contact region forming step) for forming the back-gate contact region 16, a source region forming step for forming the source region 15, and a trench gate forming step for forming the trench gate 14 are performed. The order of the back-gate contact region forming step, source region forming step, and trench gate forming step is not limited. Here, as an example, a case where the back-gate contact region forming step, source region forming step, and trench gate forming step are performed in this order will be described.

[0054] In the back-gate contact region formation step, P-type impurities are selectively implanted from the main surface 12a side into the formation region of the back-gate contact region 16 to form the back-gate contact regions 16 that correspond to the multiple column regions 17 and extend in the X-axis direction. The back-gate contact regions 16 are formed so as to be in contact with the column regions 17. Because the epitaxial layer 12 has the multiple column regions 17 along the Y-axis direction, the back-gate contact region formation step results in the formation of multiple back-gate contact regions 16 along the Y-axis direction.

[0055] In the source region forming step, N-type impurities are selectively implanted from the main surface 12a into regions between adjacent back gate contact regions 16 among the plurality of back gate contact regions 16 arranged along the Y axis direction, thereby forming source regions 15 extending in the X axis direction. This results in a plurality of source regions 15 extending in the X axis direction along the Y axis direction.

[0056] In the trench gate forming step, trench gates 14 are selectively formed discretely along the X-axis direction in each of the plurality of source regions 15 along the Y-axis direction. The trench gates 14 are formed, for example, as follows.

[0057] A trench 141 is formed from the main surface 12a side of the epitaxial layer 12 by, for example, etching. Then, a gate insulating film 142 is formed on the inner surface of the trench 141. For example, the gate insulating film 142 is formed by thermally oxidizing the inner surface of the trench 141. After the gate insulating film 142 is formed, a gate electrode 143 is filled in the trench 141. For example, the gate electrode 143 is formed by a CVD method or the like.

[0058] The method for manufacturing the semiconductor device 1 may include a back surface electrode forming step, in which a back surface electrode 13 is formed on the second surface 11b of the semiconductor substrate 11 by a CVD method or the like.

[0059] After the source electrode forming step is performed, an upper wiring structure forming step and a pad forming step may be performed.

[0060] In the upper wiring structure forming step, an upper wiring structure is formed on the main surface 12a, which is a structure for electrical wiring between the source pad 4 and the source region 15 and the back gate contact region 16, and for electrical wiring between the gate pad 5 and the gate electrode 143. Here, a case where the wiring structure described with reference to FIGS. 7 and 8 is formed will be described.

[0061] An interlayer insulating film 21a is formed on the main surface 12a by a CVD method or the like. Next, the gate contact vias 24 and the source contact vias 25a described with reference to Figures 7 and 8 are formed in the interlayer insulating film 21a. The gate contact vias 24 and the source contact vias 25a can be formed by forming corresponding through holes in the interlayer insulating film 21a and then filling the through holes with a conductive material.

[0062] Next, a gate wiring 22 is formed on the interlayer insulating film 21a so as to be electrically connected to the gate contact via 24, and a source wiring 23 is formed so as to be electrically connected to the source contact via 25a. The gate wiring 22 and the source wiring 23 may be formed, for example, by forming a conductive layer on the interlayer insulating film 21a using a conductive material for forming the gate wiring 22 and the source wiring 23, and then patterning the conductive layer into the patterns of the gate wiring 22 and the source wiring 23. Alternatively, the gate wiring 22 and the source wiring 23 may be formed by forming a resist film on the interlayer insulating film 21a so as to have holes corresponding to the patterns of the gate wiring 22 and the source wiring 23, filling the holes with a conductive material, and then removing the resist film.

[0063] After the gate wiring 22 and the source wiring 23 are formed as described above, an interlayer insulating film 21b is formed on the interlayer insulating film 21a by a CVD method or the like so as to bury the gate wiring 22 and the source wiring 23 therein.

[0064] After the interlayer insulating film 21b is formed, a source contact via 25b (see FIG. 7) for electrically connecting the source pad 4 and the source wiring 23 and a gate contact via (not shown) for electrically connecting the gate pad 5 and the gate wiring 22 are formed in the interlayer insulating film 21b. The gate contact via and source contact via 25b for electrically connecting the gate pad 5 and the gate wiring 22 may be formed in the same manner as when the source contact via 25a and the gate contact via 24 are formed in the interlayer insulating film 21a.

[0065] In the pad formation step, a source pad 4 and a gate pad 5 are formed on the interlayer insulating film 21b. At this time, the source pad 4 is formed so as to be electrically connected to the source contact via 25b, and the gate pad 5 is formed so as to be electrically connected to the gate contact via b formed in the interlayer insulating film 21a.

[0066] By carrying out the above steps, the semiconductor device 1 is manufactured. In each step, when components (such as the source region 15 and the back gate contact region 16) are selectively formed in a certain region, for example, the source region 15 and the back gate contact region 16, a mask process or the like may be carried out in advance.

[0067] The semiconductor device 1 has a plurality of column regions 17 along the Y-axis direction. A superjunction structure is formed between the plurality of column regions 17 and the epitaxial layer 12. Because the semiconductor device 1 has a superjunction structure, it is easy to ensure a sufficient breakdown voltage even if the impurity concentration of the epitaxial layer 12 is relatively high. As a result, the resistance caused by the epitaxial layer 12 can be reduced, thereby reducing the on-resistance.

[0068] Furthermore, the semiconductor device 1 employs trench gates 14, and the trench gates 14 are arranged discretely along the first and second directions. In other words, the trench gates 14 are arranged two-dimensionally. With this configuration, the distance between adjacent trench gates 14 can be shortened when viewed from the Z-axis direction. This allows for an improvement in channel density per unit area, further reducing on-resistance.

[0069] In the semiconductor device 1, the source region 15 is formed to contact the trench gate 14 and surround the trench gate 14. A lower end 15a (see FIG. 5) of the source region 15, located between adjacent trench gates 14 in the X-axis direction, contacts the epitaxial layer 12. The lower end 15a is the end of the source region 15 closer to the semiconductor substrate 11. In this configuration, when the semiconductor device 1 is driven (in the on state), electrons flow from the source region 15, located between adjacent trench gates 14 in the X-axis direction, toward the semiconductor substrate 11, as indicated by the dashed arrow in FIG. 5. That is, the portion of the epitaxial layer 12 between the source region 15, located between adjacent trench gates 14 in the X-axis direction, and the semiconductor substrate 11 functions as a channel region. In this configuration, the on-resistance can be further reduced. This point will be described in detail.

[0070] In a MOSFET, the source region corresponding to the source region 15 is usually formed in a P-type body diffusion region (P-type diffusion region). In such a configuration, the source region is surrounded by the P-type body diffusion region, and the P-type body diffusion region also functions as a channel. The P-type body diffusion region has a certain high impurity concentration (for example, 1×10 16 cm -3 Above 1×10 17 cm -3 In particular, when SiC, which has large surface scattering, is used as the semiconductor material, the decrease in channel mobility causes an increase in on-resistance.

[0071] In contrast, the semiconductor device 1 according to this embodiment does not have a P-type body diffusion region. That is, in the semiconductor device 1, the source region 15 is formed in contact with and surrounds the trench gate 14. Even in the semiconductor device 1 without a P-type body diffusion region, a depletion layer can be generated near the trench gate 14 by adjusting the gate voltage Vgs (voltage between the gate and source) applied to the gate electrode 143. In the on-state, the depletion layer can be eliminated, allowing electrons (i.e., current) to flow from the source region 15 located between adjacent trench gates 14 in the X-axis direction toward the semiconductor substrate 11. In the semiconductor device 1 without a P-type body diffusion region, no resistance occurs when electrons flow through the P-type body diffusion region. Furthermore, in the semiconductor device 1, electrons (or current) flow through the epitaxial layer 12, which has a lower impurity concentration and is closer to the bulk than the P-type body diffusion region, thereby reducing channel resistance. As a result, the on-resistance is further reduced.

[0072] The gate electrode 143 is P + In a configuration in which the semiconductor device 1 is formed of a P-type semiconductor, even if the semiconductor device 1 does not have a P-type body diffusion region, due to the difference in work function, when no gate voltage Vgs is applied to the gate electrode 143 (Vgs=0), the vicinity of the trench gate 14 is depleted, and a depletion layer can be formed near the trench gate 14. In other words, a normally-off MOSFET can be realized. When a positive voltage is applied to the gate electrode 143 as the gate voltage Vgs, the depletion layer disappears and a current flows, turning the semiconductor device 1 into an on-state. In the on-state semiconductor device 1, the current does not flow through an inversion channel layer but flows through the epitaxial layer 12, which has a lower impurity concentration and is closer to the bulk than a P-type body diffusion region, thereby reducing the channel resistance. As a result, the on-resistance is further reduced.

[0073] When the distance between adjacent trench gates 14 in the X-axis direction is 0.1 μm or more and 0.6 μm or less, a depletion layer is formed near the trench gate 14, as described above, making it easy to turn it off.

[0074] In a configuration in which the space between adjacent trench gates 14 in the X-axis direction is filled with the source region 15, a larger channel can be formed, making it easier for current to flow.

[0075] In a MOSFET using SiC as the semiconductor material, the channel resistance is likely to increase due to relatively large surface scattering, and the on-resistance is likely to rise. In contrast, the semiconductor device 1 capable of reducing the channel resistance is more effective when SiC is used as the semiconductor material.

[0076] The semiconductor device 1 can be incorporated into a power module used in an inverter circuit that constitutes a drive circuit for driving an electric motor used as a power source for electric vehicles (including hybrid vehicles), trains, industrial robots, etc. The semiconductor device 1 can also be incorporated into a power module used in an inverter circuit that converts the power generated by a solar cell, a wind power generator, or other power generation device (particularly a private power generation device) so that it is compatible with the power of a commercial power source.

[0077] (Second embodiment) 9 is a plan view of a semiconductor device 1A according to the second embodiment. The semiconductor device 1A has, for example, a chip shape, specifically, for example, a rectangular parallelepiped or cubic shape. The semiconductor device 1A is an integrated semiconductor device including a plurality of device regions 100. The number, arrangement, and shape of the device regions 100 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0078] Each of the multiple device regions 100 includes a functional device formed using regions inside and outside the semiconductor device 1A. One of the functional devices is a semiconductor switching device. The semiconductor device 1A includes the semiconductor device 1 described in the first embodiment as a semiconductor switching device in at least one of the multiple device regions 100. In other words, at least one of the multiple device regions 100 has the configuration of the semiconductor device 1 according to the first embodiment.

[0079] The semiconductor device 1A may include, as an example of a functional device, a digital semiconductor device or an analog semiconductor device. The digital semiconductor device or the analog semiconductor device may include a MOS transistor or a bipolar transistor. An example of the functional device includes a semiconductor switching device as well as at least one of a semiconductor rectifying device and a passive device. The functional device in the semiconductor device 1A may include a circuit network that combines at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

[0080] The semiconductor device 1A may include, as a semiconductor switching device, other switching devices such as an IGBT (Insulated Gate Bipolar Junction Transistor) in addition to the semiconductor device 1 described in the first embodiment. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0081] In the semiconductor device 1A, the semiconductor substrate 11 and the epitaxial layer 12 of the semiconductor device 1 described in the first embodiment may be the semiconductor substrate 11 and the epitaxial layer 12 common to the other device regions 100. In the semiconductor device 1A, the back surface electrode 13 of the semiconductor device 1 described in the first embodiment may also be a common electrode to the other device regions 100. However, the regions of the back surface electrode corresponding to each device region 100 function as electrodes corresponding to the respective device regions 100.

[0082] At least one of the multiple device regions 100 of the semiconductor device 1A has the same configuration as the semiconductor device 1 according to the first embodiment. Therefore, the semiconductor device 1A has the same effects as the semiconductor device 1.

[0083] The semiconductor device 1A can also be incorporated into a power module used in an inverter circuit that constitutes a drive circuit for driving an electric motor used as a power source for electric vehicles (including hybrid vehicles), trains, industrial robots, etc. The semiconductor device 1A can also be incorporated into a power module used in an inverter circuit that converts power generated by solar cells, wind power generators, and other power generation devices (especially private power generation devices) so that it is compatible with the power of a commercial power source.

[0084] (Variation 1) Each embodiment has been described using an example in which the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type may be P-type and the second conductivity type may be N-type. In other words, a configuration in which the conductivity types of the semiconductor portions of the semiconductor devices 1 and 1A are reversed may be adopted. For example, in the semiconductor devices 1 and 1A, the P-type portions may be N-type and the N-type portions may be P-type.

[0085] (Variation 2) The material forming the gate electrode 143 is P + For example, the gate electrode 143 may be made of an N + In this case, for example, a depletion layer can be formed in the vicinity of the trench gate 14 by applying a negative gate voltage Vgs to the gate electrode 143.

[0086] (Variation 3) The space between adjacent trench gates 14 in the X-axis direction does not have to be filled with the source region 15. That is, a gap may be formed between the source region 15 surrounding one of the adjacent trench gates 14 and the source region 15 surrounding the other trench gate 14.

[0087] (Variation 4) The structure for electrically connecting the source region 15 and the back gate contact region 16 to the source pad 4 may be, for example, the form illustrated in FIGS.

[0088] FIG. 10 is a diagram for explaining another example of the structure on the main surface 12a of the semiconductor device 1. Like FIG. 3, FIG. 10 schematically shows a cross-sectional configuration taken along line III-III in FIG. 2. FIG. 11 is a plan view of the epitaxial layer (semiconductor layer) 12 side as viewed from line XI-XI in FIG. 10. As in FIGS. 7 and 8, the interlayer insulating films 21a and 21b are omitted from FIGS. 10 and 11. In other words, FIGS. 10 and 11 schematically show a perspective view of the interlayer insulating films 21a and 21b. As in FIG. 2, the hatching in FIGS. 10 and 11 indicates the source region 15.

[0089] The wiring structure illustrated in Figures 10 and 11 is the same as the wiring structure described using Figures 7 and 8, except that the source region 15 and back gate contact region 16 are electrically connected to the source pad 4 using a source contact via 25 instead of a source wiring 23.

[0090] The source contact via 25 penetrates the interlayer insulating film 21a and the interlayer insulating film 21b arranged between the main surface 12a and the source pad 4. The source contact via 25 corresponds to a via obtained by extending the source contact via 25a shown in FIG. 7 to the source pad 4. The wiring structure between the gate electrode 143 and the gate pad 5 may be the same as that described with reference to FIGS. 7 and 8.

[0091] The wiring structure illustrated in Figures 10 and 11 can be formed in the same manner as the upper wiring structure formation process described in the first embodiment, except that in the upper wiring structure formation process described in the first embodiment, a portion of the source contact via 25 located within the interlayer insulating film 21a is formed in the same way as when forming a source contact via 25a (see Figure 7) in the interlayer insulating film 21a, the source wiring 23 is not formed, and when forming a source contact via 25b (see Figure 7), a portion of the source contact via 25 located within the interlayer insulating film 21b is formed.

[0092] The source contact via 25 may be formed to penetrate the interlayer insulating films 21a and 21b after the interlayer insulating films 21a and 21b are formed.

[0093] (Variation 5) The method for manufacturing the semiconductor device 1 is not limited to the exemplified method. For example, the method for manufacturing the semiconductor device may include a semiconductor layer forming step of forming a first-conductivity-type semiconductor layer 12 having a main surface 12a on a first-conductivity-type semiconductor substrate 11, a column region forming step of forming a second-conductivity-type column region 17 in the semiconductor layer 12 so that the main surface 12a and the column region 17 are spaced apart, a trench gate forming step of forming a trench gate 14 having a trench 141, a gate insulating film 142, and a gate electrode 143 in the semiconductor layer 12 in which the column region 17 is formed, a source region forming step of forming a first-conductivity-type source region 15 in the main surface 12a of the semiconductor layer 12 in which the column region 17 is formed, and a back-gate contact region forming step of forming a second-conductivity-type back-gate contact region 16 in the main surface 12a of the semiconductor layer 12 in which the column region 17 is formed so that the back-gate contact region 16 is in contact with the column region 17. In the column region forming step of the manufacturing method described in Modification 5, the column regions 17 are formed to extend in the first direction out of a first direction (X-axis direction) and a second direction (Y-axis direction) that intersect with each other as viewed from the thickness direction (Z-axis direction) of the semiconductor layer 12, and multiple column regions 17 are formed discretely along the second direction. In the back-gate contact region forming step of the manufacturing method according to Modification 5, multiple back-gate contact regions 16 are formed by forming back-gate contact regions 16 corresponding to each of the multiple column regions 17. In the trench gate forming step of the manufacturing method according to Modification 5, multiple trench gates 14 are formed discretely along the first direction between adjacent column regions 17 among the multiple column regions 17 as viewed from the thickness direction. In the source region forming step of the manufacturing method according to Modification 5, a source region 15 is formed in contact with the trench gate 14 and surrounding the trench gate 14 as viewed from the thickness direction, or in contact with a trench gate formation region where the trench gate 14 is to be formed and surrounding the trench gate formation region as viewed from the thickness direction.

[0094] As can be understood from the above description, the semiconductor device according to the present disclosure can reduce the on-resistance.

[0095] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. In the various embodiments (including variations) described above, one or more elements of one embodiment may be combined with one or more elements of another embodiment. From the above description, it will be understood that the various embodiments of the present disclosure are illustrative in all respects, and that various changes may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

[0096] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0097] [A1] (Figures 2 to 5) a semiconductor substrate (11) of a first conductivity type; a semiconductor layer (12) of a first conductivity type located on the semiconductor substrate and having a main surface (12a) located opposite the semiconductor substrate; Equipped with The semiconductor layer is a trench gate (14) having a trench (141) extending from the main surface toward the semiconductor substrate, a gate insulating film (142) formed on the inner surface of the trench, and a gate electrode (143) filled in the trench via the gate insulating film; a first conductivity type source region (15) formed on the main surface; a second conductivity type contact region (16) formed on the main surface; A column region (17) of the second conductivity type; Including, a plurality of the trench gates are discretely formed in the semiconductor layer along a first direction (X) and a second direction (Y) that intersect with each other when viewed from a thickness direction (Z) of the semiconductor layer; the source region is in contact with the trench gate and surrounds the trench gate when viewed in the thickness direction; the contact region is located between the source regions adjacent in the second direction, The column region extends from an end (16a) of the contact region closer to the semiconductor substrate toward the semiconductor substrate. Semiconductor device (1).

[0098] [A2] the gate electrode is formed of a semiconductor of a second conductivity type; The semiconductor device according to [A1].

[0099] [A3] The source region is filled between the trench gates adjacent to each other in the first direction. The semiconductor device according to [A1] or [A2].

[0100] [A4] an end portion of the source region located between the trench gates adjacent in the first direction and closer to the semiconductor substrate is in contact with the semiconductor layer; The semiconductor device according to any one of [A1] to [A3].

[0101] [A5] The interval between the trench gates adjacent to each other in the first direction is not less than 0.1 μm and not more than 0.6 μm. The semiconductor device according to any one of [A1] to [A4].

[0102] [A6] the first direction and the second direction are perpendicular to each other; The semiconductor device according to any one of [A1] to [A5].

[0103] [B1] a semiconductor substrate (11) of a first conductivity type; a semiconductor layer (12) of a first conductivity type located on the semiconductor substrate and having a main surface located opposite the semiconductor substrate; Equipped with The semiconductor layer is a trench gate (14) having a trench (141) extending from the main surface toward the semiconductor substrate, a gate insulating film (142) formed on the inner surface of the trench, and a gate electrode (143) filled in the trench via the gate insulating film; a first conductivity type source region (15) formed on the main surface and extending in a first direction; a second conductivity type contact region (16) formed on the main surface and extending in the first direction; a column region (17) of a second conductivity type extending in the first direction; Including, a plurality of the source regions are discretely formed in the semiconductor layer along a second direction (Y) intersecting the first direction (X) when viewed from a thickness direction (Z) of the semiconductor layer; When viewed from the thickness direction, the trench gates are formed discretely in each of the plurality of source regions along the first direction, the contact region is located between the source regions adjacent in the first direction, the column region extends from an end of the contact region closer to the semiconductor substrate toward the semiconductor substrate; Semiconductor device.

[0104] [C1] a semiconductor layer forming step of forming a first conductivity type semiconductor layer (12) on a first conductivity type semiconductor substrate (11) and having a main surface (12a) located opposite to the semiconductor substrate; a column region forming step of forming a column region (17) of a second conductivity type in the semiconductor layer such that the column region is spaced apart from the main surface; a trench gate formation step of forming a trench gate (14) in the semiconductor layer in which the column region is formed, the trench gate (14) having a trench (141) extending from the main surface toward the semiconductor substrate, a gate insulating film (142) formed on the inner surface of the trench, and a gate electrode (143) filled in the trench via the gate insulating film; a source region forming step of forming a first conductivity type source region (15) on the main surface of the semiconductor layer in which the column region is formed; a contact region forming step of forming a second conductivity type contact region (16) on the main surface of the semiconductor layer in which the column region is formed so as to be in contact with the column region; Equipped with the column region extends in the first direction (X) of a first direction (X) and a second direction (Y) intersecting each other when viewed from a thickness direction (Z) of the semiconductor layer; In the column region forming step, a plurality of the column regions are discretely formed along the second direction (Y), In the contact region forming step, the contact regions are formed corresponding to the plurality of column regions, respectively, thereby forming the plurality of contact regions; In the trench gate forming step, a plurality of the trench gates are formed discretely along the first direction (X) between adjacent column regions among the plurality of column regions as viewed in the thickness direction (Z), In the source region forming step, the source region is formed so as to be in contact with the trench gate and surround the trench gate as viewed from the thickness direction (Z), or so as to be in contact with a trench gate formation region in which the trench gate is to be formed and surround the trench gate formation region as viewed from the thickness direction. A method for manufacturing a semiconductor device.

[0105] [C2] The column region forming step is performed while the semiconductor layer is being formed in the semiconductor layer forming step. [C1] A method for manufacturing a semiconductor device according to the present invention.

[0106] [C3] The source region forming step includes forming the source region between adjacent ones of the plurality of contact regions as viewed in the thickness direction (Z) in the semiconductor layer in which the plurality of column regions and the plurality of contact regions are formed, so as to extend in the first direction (X), thereby forming the plurality of source regions discretely along the second direction (Y); In the trench gate forming step, the trench gates are formed discretely in the first direction (X) in each of the source regions, thereby forming the trench gates. A method for manufacturing a semiconductor device according to [C1] or [C2]. [Explanation of symbols]

[0107] 1, 1A...Semiconductor device 2...Active area 3. Peripheral areas 4...Sauce pad 4a...recess 5...Gate pad 11...Semiconductor substrate 11a…First page 11b…Second side 12...Epitaxial layer (semiconductor layer) 12a…main surface 13...Back electrode 14...Trench gate 14a...lower end 141...Trench 142...Gate insulating film 143...gate electrode 15...Source region 16...Back gate contact area (contact area) 16a...lower end 17...Column area 17a...lower end 171...Column section 21a, 21b...Interlayer insulating film 22...Gate wiring 23...Source wiring 24...Gate contact via 25a, 25b, 25...Source contact vias 100...Device area

Claims

1. a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate and having a main surface located opposite the semiconductor substrate; Equipped with The semiconductor layer is a trench gate including a trench extending from the main surface toward the semiconductor substrate, a gate insulating film formed on an inner surface of the trench, and a gate electrode filled in the trench via the gate insulating film; a source region of a first conductivity type formed on the main surface; a second conductivity type contact region formed on the main surface; a column region of a second conductivity type; Including, a plurality of the trench gates are discretely formed in the semiconductor layer along a first direction and a second direction that intersect with each other when viewed from a thickness direction of the semiconductor layer; the source region is in contact with the trench gate and surrounds the trench gate when viewed in the thickness direction; the contact region is located between the source regions adjacent in the second direction, the column region extends from an end of the contact region closer to the semiconductor substrate toward the semiconductor substrate; Semiconductor device.

2. the gate electrode is formed of a semiconductor of a second conductivity type; The semiconductor device according to claim 1 .

3. The source region is filled between the trench gates adjacent to each other in the first direction.

3. The semiconductor device according to claim 1.

4. an end portion of the source region located between the trench gates adjacent to each other in the first direction and closer to the semiconductor substrate is in contact with the semiconductor layer; 3. The semiconductor device according to claim 1.

5. the interval between the trench gates adjacent to each other in the first direction is not less than 0.1 μm and not more than 0.6 μm; 3. The semiconductor device according to claim 1.

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