Semiconductor device and forming method thereof, vehicle-mounted chip and vehicle

Abstract

The invention relates to a semiconductor device and a forming method thereof, a vehicle-mounted chip and a vehicle. The semiconductor device includes a semiconductor layer, a first gate trench in the semiconductor layer, and a first trench gate structure. The semiconductor layer is provided with a first surface and a second surface which are oppositely arranged in a first direction. The first gate trench is recessed from the first surface to the second surface. The first trench gate structure is located in the first gate trench and comprises a first gate portion and a first shielding portion. The first gate portions and the first shielding portions are arranged at intervals in the second direction, and the first direction intersects with the second direction. The grid electrode in the first grid electrode groove is split into the first grid electrode part and the first shielding part which are arranged at intervals in the second direction, and stray capacitance between the first grid electrode part and the drain electrode is small. In addition, the first shielding part plays a role in shielding lateral parasitic capacitance between the first gate part and the drain, and the gate-drain capacitance can also be reduced. The small gate-drain capacitance can reduce the switching loss of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same, an on-board chip and a vehicle. Background Art

[0002] As a bipolar device, the Insulated Gate Bipolar Transistor (IGBT) combines the working mechanism of MOSFET and the working mechanism of bipolar transistor, and has the advantages of both. It is an improved power device. Compared with bipolar transistors, IGBT is a voltage-controlled device and has high gain under high current; compared with MOSFET, IGBT can withstand higher voltage, and has low on-state voltage drop and low power consumption under high current. At present, how to reduce the switching loss of IGBT is a technical problem that needs to be solved. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor device and a method for forming the same, an on-board chip and a vehicle to reduce the switching loss of the semiconductor device, so as to at least partially solve the above-mentioned technical problems.

[0004] In order to achieve the above object, according to a first aspect of the present application, a semiconductor device is provided, comprising:

[0005] The semiconductor layer has a first surface and a second surface arranged opposite to each other in a first direction;

[0006] A first gate trench located in the semiconductor layer, sunken from the first surface to the second surface;

[0007] The first trench gate structure is located in the first gate trench and includes a first gate portion and a first shielding portion. The first gate portion and the first shielding portion are arranged at intervals in a second direction, and the first direction intersects with the second direction.

[0008] According to a second aspect of the present application, a method for forming a semiconductor device is provided, the method comprising:

[0009] forming a semiconductor layer, wherein the semiconductor layer has a first surface and a second surface disposed opposite to each other in a first direction;

[0010] forming a first gate trench in the semiconductor layer, wherein the first gate trench is sunken from the first surface to the second surface;

[0011] A first trench gate structure is formed in the first gate trench, wherein the first trench gate structure includes a first gate portion and a first shielding portion, wherein the first gate portion and the first shielding portion are arranged at intervals in a second direction, and the first direction intersects with the second direction.

[0012] According to a third aspect of the present application, a vehicle-mounted chip is also provided, comprising the above-mentioned semiconductor device.

[0013] According to a fourth aspect of the present application, a vehicle is also provided, comprising the above-mentioned vehicle-mounted chip.

[0014] In the semiconductor device and its manufacturing method, on-board chip and vehicle of the embodiments of the present application, the gate in the first gate groove is split into a first gate portion and a first shielding portion arranged at intervals in the second direction. The design of the first shielding portion converts the parasitic capacitance between part of the gate and the drain in the traditional technology into the parasitic capacitance between the first shielding portion and the drain. In addition, the first shielding portion also shields the lateral parasitic capacitance between the first gate portion and the drain, reducing the parasitic capacitance between the first gate portion and the drain. Furthermore, the design of the first shielding portion makes the first gate portion a narrow gate structure. In the first direction, the first gate portion and the drain have a smaller facing area, and the parasitic capacitance between the first gate portion and the drain is smaller. The smaller gate-drain capacitance can reduce the switching loss of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0016] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0017] Figure 1 A schematic cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present disclosure;

[0018] Figure 2 A schematic cross-sectional view of another semiconductor device provided in an exemplary embodiment of the present disclosure;

[0019] Figure 3 is a schematic cross-sectional view of yet another semiconductor device provided in an exemplary embodiment of the present disclosure;

[0020] Figure 4 is a schematic cross-sectional view of yet another semiconductor device provided in an exemplary embodiment of the present disclosure;

[0021] Figure 5 A schematic flow chart of a process for forming a semiconductor device provided in an exemplary embodiment of the present disclosure;

[0022] Figures 6 to 18 It is a structural schematic diagram of a formation process of another semiconductor device provided in an exemplary embodiment of the present disclosure.

[0023] Description of reference numerals:

[0024] 100. Semiconductor devices;

[0025] 1. semiconductor layer; 1A1. first surface; 1A2. second surface;

[0026] 1B, collector region; 1C, buffer region; 1D, drift region; 1D1, first column region; 1D2, second column region;

[0027] 11. a first initial semiconductor layer; 12. a second initial semiconductor layer;

[0028] 131, a first gate trench; 132, a second gate trench; 133, a third gate trench;

[0029] 21, first trench gate structure; 211, first gate portion; 2111A, first initial gate doping portion; 2111, first gate doping portion; 2112A, second initial gate doping portion; 2112, second gate doping portion; 212, first shielding portion; 2121, first shielding doping portion; 2122, second shielding doping portion; 213A, second initial shielding portion; 213, second shielding portion; 214, first gate dielectric layer; 2141, first initial gate dielectric layer; 2142, fourth initial gate dielectric layer; 2143, fifth initial gate dielectric layer;

[0030] 22, second trench gate structure; 221, second gate portion; 2211A, third initial gate doping portion; 2211, third gate doping portion; 2212, fourth gate doping portion; 222, second gate dielectric layer;

[0031] 23. third trench gate structure; 231. third gate portion; 2311. fifth gate doping portion; 2312. sixth gate doping portion; 232. third gate dielectric layer;

[0032] 31. Body area;

[0033] 32, emitter region; 321, first emitter region; 322, second emitter region; 33, ohmic contact region; 34, depletion region; 35, carrier storage layer;

[0034] 36, floating area; 361, first floating area; 362, second floating area; 363, third floating area;

[0035] 4. Conductive layer; 41. First gate lead-out structure; 42. Second gate lead-out structure; 43. Third gate lead-out structure; 44. Emitter; 45. Conductive electrode; 46. Lead-out structure;

[0036] 5. Isolation dielectric layer;

[0037] 6. Collector;

[0038] Y, first direction; X, second direction. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] According to the first aspect of the embodiment of the present application, referring to Figure 1 , which is a cross-sectional schematic diagram of a semiconductor device 100 provided in an exemplary embodiment of the present disclosure. The semiconductor device 100 may be a power semiconductor device. The power semiconductor device includes, but is not limited to, any one of an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET).

[0041] The semiconductor device 100 includes a semiconductor layer 1, a first gate trench 131 located in the semiconductor layer 1, and a first trench gate structure 21. The semiconductor layer 1 has a first surface 1A1 and a second surface 1A2 arranged opposite to each other in a first direction Y. The first gate trench 131 is recessed from the first surface 1A1 to the second surface 1A2. The first trench gate structure 21 is located in the first gate trench 131 and includes a first gate portion 211 and a first shielding portion 212. The first gate portion 211 and the first shielding portion 212 are arranged at intervals in a second direction X, and the first direction Y intersects with the second direction X.

[0042] In the semiconductor device 100 of some embodiments of the present application, the gate in the first gate trench 131 is split into a first gate portion 211 and a first shielding portion 212 arranged at intervals in the second direction X. The design of the first shielding portion 212 converts the parasitic capacitance between part of the gate and the drain in the conventional technology into the parasitic capacitance between the first shielding portion 212 and the drain. In addition, the first shielding portion 212 also shields the lateral parasitic capacitance between the first gate portion 211 and the drain, thereby reducing the parasitic capacitance between the first gate portion 211 and the drain. Furthermore, the design of the first shielding portion 212 makes the first gate portion 211 a narrow gate structure. In the first direction Y, the first gate portion 211 has a smaller facing area with the drain, and the parasitic capacitance between the first gate portion 211 and the drain is smaller. The smaller gate-drain capacitance can reduce the switching loss of the semiconductor device 100.

[0043] In some embodiments, the first direction Y is perpendicular to the second direction X, but the present invention is not limited thereto. In other embodiments, the angle between the first direction Y and the second direction X may also be an acute angle or an obtuse angle.

[0044] In some embodiments, the semiconductor layer 1 includes a collector region 1B, a buffer region 1C, and a drift region 1D. In the first direction Y, the buffer region 1C is located between the collector region 1B and the drift region 1D. The collector region 1B is adjacent to the second surface 1A2, and the first gate trench 131 is located in the drift region 1D. In this way, the semiconductor device 100 is an IGBT device.

[0045] The collector region 1B has a first conductivity type, and the buffer region 1C has a second conductivity type, and the first conductivity type is opposite to the second conductivity type. Exemplarily, the first conductivity type is P type, and the second conductivity type is N type. It can be understood that when the first conductivity type can also be N type, the second conductivity type can also be P type.

[0046] In some embodiments, the semiconductor layer 1 may include at least one of silicon, a compound semiconductor material, and an alloy semiconductor material. The compound semiconductor material includes at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor material includes at least one of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.

[0047] In some embodiments, the semiconductor device 100 further includes a collector electrode 6 , which is located on the second surface 1A2 and in contact with the collector region 1B. In some embodiments, the collector electrode 6 includes a conductive material such as a metal material.

[0048] In some embodiments, the first shielding portion 212 may include a conductive material. In this way, the first shielding portion 212 has conductive properties. In some embodiments, the first shielding portion 212 may also include a conductive material and a doping material to improve the conductivity of the first shielding portion 212. Exemplarily, the first shielding portion 212 may include polysilicon and a doping material. In some embodiments, the first shielding portion 212 may include two shielding sub-portions of opposite conductivity types stacked in the first direction Y.

[0049] In some embodiments, the semiconductor device 100 further includes a conductive electrode 45, which is located on the first surface 1A1 and connected to the first shielding portion 212. In this way, the first shielding portion 212 can be connected to a fixed potential through the conductive electrode 45, and the first shielding portion 212 converts a portion of the parasitic capacitance between the gate and the drain in the related art into a parasitic capacitance between the first shielding portion 212 and the drain, thereby reducing the gate-drain capacitance.

[0050] In some embodiments, the semiconductor device 100 further includes an emitter 44, which is located on the first surface 1A1 of the semiconductor layer 1 and connected to the conductive electrode 45. In this way, the first shielding portion 212 is connected to the potential of the emitter 44, and the first shielding portion 212 converts a portion of the parasitic capacitance between the gate and the drain in the related art into a parasitic capacitance between the emitter 44 and the drain, thereby reducing the gate-drain capacitance.

[0051] In some embodiments, the first gate portion 211 includes a first gate doping portion 2111 and a second gate doping portion 2112 stacked in the first direction Y. The conductivity type of the doped ions in the first gate doping portion 2111 and the second gate doping portion 2112 is opposite. In this way, the first gate doping portion 2111 and the second gate doping portion 2112 constitute a first PN junction capacitor, and the gate-drain capacitor between the first gate portion 211 and the drain is in series with the first PN junction capacitor. The two capacitors are connected in series, the capacitance is reduced, the total gate-drain capacitance is reduced, and the switching loss of the semiconductor device 100 is further reduced.

[0052] In some embodiments, the first trench gate structure 21 may further include a first gate dielectric layer 214, and the first gate dielectric layer 214 is at least filled between the first gate portion 211, the first shielding portion 212, and the groove wall of the first gate trench 131. In this way, the first gate dielectric layer 214 is used to achieve insulation between the first gate portion 211, the first shielding portion 212, and the semiconductor layer 1.

[0053] In some embodiments, the first trench gate structure 21 further includes a second shielding portion 213. The second shielding portion 213 is located at the bottom of the first gate trench 131. The first gate portion 211 and the first shielding portion 212 are located on the side of the second shielding portion 213 away from the second surface 1A2. The first gate dielectric layer 214 is also filled between the second shielding portion 213 and the first gate portion 211, the first shielding portion 212 and the groove wall of the first gate trench 131. In this way, the design of the second shielding portion 213 plays a shielding role between the first gate portion 211 and the drain, further reducing the parasitic capacitance between the first gate portion 211 and the drain, and further reducing the switching loss of the semiconductor device 100.

[0054] In some embodiments, the second shielding portion 213 is connected to the low potential of the emitter 44. In this way, the second shielding portion 213 is connected to a fixed potential to play a shielding role. In other embodiments, the second shielding portion 213 can also be connected to other fixed potentials.

[0055] In some embodiments, the second shielding portion 213 may include a conductive material. In this way, the second shielding portion 213 has conductive properties. In some embodiments, the second shielding portion 213 may also include a conductive material and a doping material to improve the conductivity of the second shielding portion 213. Exemplarily, the second shielding portion 213 may include polysilicon and a doping material.

[0056] In some embodiments, the semiconductor device 100 further includes a first gate lead-out structure 41 , which is located on the first surface 1A1 and contacts the first gate portion 211 . Thus, the first gate portion 211 is connected to the gate potential through the first gate lead-out structure 41 .

[0057] In some embodiments, the semiconductor layer 1 further includes a first column region 1D1 of the first conductivity type and a second column region 1D2 of the second conductivity type. In the first direction Y, the first column region 1D1 and the second column region 1D2 are located on the side of the first surface 1A1 away from the first trench gate structure 21. The first column region 1D1 and the second column region 1D2 are adjacent to each other in the second direction X, and the first column region 1D1 and the second column region 1D2 extend along the first direction Y. In this way, the first column region 1D1 and the second column region 1D2 of opposite conductivity types form a super junction structure, which greatly reduces the conduction voltage drop of the semiconductor device 100. In addition, a better compromise between the forward conduction voltage drop and the turn-off loss can be achieved. At the same voltage level of 1200V, the drift region 1D length of the IGBT including the super junction structure can be reduced by 10% to 20% compared with the FS-IGBT (Field Stop, FS). During the turn-off process, the mutual depletion of the first column region 1D1 and the second column region 1D2 can accelerate the extraction of carriers, further reducing the turn-off loss of the semiconductor device 100.

[0058] The first stud region 1D1 of the first conductivity type and the second stud region 1D2 of the second conductivity type are located in the drift region 1D, and the first stud region 1D1 and the second stud region 1D2 are alternately arranged along the second direction X.

[0059] In some embodiments, the semiconductor device 100 further includes a second gate trench 132 and a body region 31 of the first conductivity type and a second trench gate structure 22 located in the semiconductor layer 1. The second gate trench 132 is recessed from the first surface 1A1 to the second surface 1A2 and extends toward the second column region 1D2. The second trench gate structure 22 is located in the second gate trench 132. The body region 31 is located between the first trench gate structure 21 and the second trench gate structure 22. In this way, when a voltage is applied to the gate in the second trench gate structure 22, a conductive channel can be formed on one side of the body region 31 close to the second trench gate structure 22.

[0060] In some embodiments, the second trench gate structure 22 includes a second gate portion 221, and the second gate portion 221 includes a third gate doping portion 2211 and a fourth gate doping portion 2212 stacked in the first direction Y, and the conductivity types of the doped ions in the third gate doping portion 2211 and the fourth gate doping portion 2212 are opposite. In this way, the third gate doping portion 2211 and the fourth gate doping portion 2212 constitute a second PN junction capacitor, and the gate-drain capacitor between the second gate portion 221 and the drain is in series with the second PN junction capacitor. The two capacitors are connected in series, the capacitance is reduced, the total gate-drain capacitance is reduced, and the switching loss of the semiconductor device 100 is further reduced.

[0061] In some other embodiments, the second gate portion 221 may also include a conductive material without doping ions or only doping ions of one conductive type.

[0062] In some embodiments, the second trench gate structure 22 further includes a second gate dielectric layer 222, and the second gate dielectric layer 222 is filled between the second gate portion 221 and the wall of the second gate trench 132. In this way, insulation between the second gate portion 221 and the semiconductor layer 1 is achieved.

[0063] The semiconductor device 100 further includes an emitter region 32 located in the semiconductor. The emitter region 32 is located between the first trench gate structure 21 and the second trench gate structure 22. The emitter region 32 is located between the body region 31 and the first surface 1A1 and is adjacent to the body region 31. The emitter 44 is located on the first surface 1A1 and is in contact with the emitter region 32. In some embodiments, the emitter region 32 includes a first emitter region 321 of a first conductivity type and a second emitter region 322 of a second conductivity type adjacent to each other along the second direction X. Exemplarily, the emitter region 32 includes two second emitter regions 322 and one first emitter region 321, and the first emitter region 321 is located between the two second emitter regions 322 in the second direction X.

[0064] In some embodiments, the semiconductor device 100 further includes a second conductivity type carrier storage layer 35 located inside the semiconductor. The carrier storage layer 35 is located between the first trench gate structure 21 and the second trench gate structure 22. In the second direction X, the carrier storage layer 35 is located between the body region 31 and the second column region 1D2. The concentration of doped ions in the carrier storage layer 35 is greater than the concentration of doped ions in the second column. In this way, a second conductivity type carrier storage layer 35 is added to the bottom of the first conductivity type body region 31, which prevents holes from flowing directly from the emitter 44. The higher concentration of the carrier storage layer 35 acts as an effective hole barrier, increases the carrier concentration on one side of the emitter 44, makes the conductivity modulation effect more intense, and further reduces the forward conduction voltage drop.

[0065] In some embodiments, the semiconductor device 100 further includes a second gate lead-out structure 42 , which is located on the first surface 1A1 and connected to the second gate portion 221 . Thus, the second gate portion 221 is connected to the gate potential through the second gate lead-out structure 42 .

[0066] In some embodiments, the semiconductor device 100 further includes a third gate trench 133 and a first conductivity type depletion region 34 and a third trench gate structure 23 located in the semiconductor layer 1. The third gate trench 133 is recessed from the first surface 1A1 to the second surface 1A2 and extends toward the first column region 1D1. The third trench gate structure 23 is located in the third gate trench 133. The depletion region 34 is located between the first trench gate structure 21 and the third trench gate structure 23. Thus, when the semiconductor device 100 is turned on, the majority carrier holes in the depletion region 34 will be depleted under the two positive voltages loaded on the gates in the first trench gate structure 21 and the third trench gate structure 23, which will repel the majority carrier holes and further allow the minority carrier electrons in the depletion region 34 to form an inversion layer, thereby preventing the majority carrier holes from flowing out. Therefore, when the semiconductor device 100 is turned on, a large number of holes will accumulate between the first trench gate structure 21 and the third trench gate structure 23, forcing the electron injection of the collector 6 region to be enhanced, which will aggravate the conductivity modulation effect and reduce the forward conduction voltage drop. At the same time, the sensitivity of the semiconductor device 100 to the doping concentration of the first column region 1D1 and the second column region 1D2 is also reduced, and the semiconductor device 100 can maintain the bipolar conduction mode within the doping range of the larger doping concentration of the first column region 1D1 and the second column region 1D2. In addition, when the semiconductor device 100 is turned off, the gate is not pressurized, the collector 6 is pressurized, and the depletion region 34 and the first column region 1D1 will form a normal hole channel, which accelerates the extraction of holes, reduces the forward conduction voltage drop while also reducing the turn-off loss, thereby achieving a compromise relationship between reducing the forward conduction voltage drop and the turn-off loss.

[0067] In some embodiments, the concentration of doping ions of the depletion region 34 is less than the concentration of doping ions of the first stud region 1D1 .

[0068] In some embodiments, the semiconductor device 100 further includes an ohmic contact region 33 of the first conductivity type and a lead-out structure 46. The ohmic contact region 33 is located between the first trench gate structure 21 and the third trench gate structure 23, and the ohmic contact region 33 is located between the depletion region 34 and the first surface 1A1 in the first direction Y and is adjacent to the depletion region 34. The lead-out structure 46 is located on the first surface 1A1 and contacts the ohmic contact region 33. The lead-out structure 46 is connected to the emitter 44. In this way, when the semiconductor device 100 is turned off, the holes in the depletion region 34 and the first column region 1D1 can be led out through the emitter 44.

[0069] In some embodiments, the concentration of doping ions in the ohmic contact region 33 is greater than the concentration of doping ions in the first stud region 1D1 and the concentration of doping ions in the depletion region 34 .

[0070] In some embodiments, the concentration of doping ions in the ohmic contact region 33 is the same as the concentration of doping ions in the first emitter region 321. In this way, the ohmic contact region 33 and the first emitter region 321 can be formed, simplifying the manufacturing process of the semiconductor device 100.

[0071] In other embodiments, the lead-out structure 46 may directly contact the depletion region 34 .

[0072] In some embodiments, in the second direction X, the first gate portion 211 is located between the depletion region 34 and the first shielding portion 212. Thus, the first gate portion 211 is disposed close to the depletion region 34, and when the semiconductor device 100 is turned on, the first gate portion 211 can better act on the depletion region 34 to reduce the forward conduction voltage drop.

[0073] In some embodiments, the third trench gate structure 23 includes a third gate portion 231, and the third gate portion 231 includes a fifth gate doping portion 2311 and a sixth gate doping portion 2312 stacked in the first direction Y, and the conductivity types of the doped ions in the fifth gate doping portion 2311 and the sixth gate doping portion 2312 are opposite. In this way, the fifth gate doping portion 2311 and the sixth gate doping portion 2312 constitute a third PN junction capacitor, and the gate-drain capacitor between the third gate portion 231 and the drain is in series with the third PN junction capacitor. When the two capacitors are connected in series, the capacitance is reduced, the total gate-drain capacitance is reduced, and the switching loss of the semiconductor device 100 is further reduced.

[0074] In some other embodiments, the third gate portion 231 may also include a conductive material without doping ions or only doping ions of one conductive type.

[0075] In some embodiments, the third trench gate structure 23 may further include a third gate dielectric layer 232 , and the third gate dielectric layer 232 is filled between the third gate portion 231 and the wall of the third gate trench 133 . In this way, the third gate portion 231 and the semiconductor layer 1 are electrically isolated.

[0076] In some embodiments, the first gate dielectric layer 214, the second gate dielectric layer 222, and the third gate dielectric layer 232 include an insulating material, and the insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0077] In some embodiments, the first gate trench 131 , the second gate trench 132 , and the third gate trench 133 may have the same depth along the first direction Y. Thus, the first gate trench 131 , the second gate trench 132 , and the third gate trench 133 may be formed in the same etching process, simplifying the manufacturing process of the semiconductor device 100 .

[0078] In some embodiments, the first gate portion 211 , the second gate portion 221 , and the third gate portion 231 include conductive materials such as polysilicon.

[0079] In some embodiments, when the first trench gate structure 21 includes the second shielding portion 213, the second gate portion 221 includes the third gate doping portion 2211 and the fourth gate doping portion 2212 stacked in the first direction Y, and the third gate portion 231 includes the fifth gate doping portion 2311 and the sixth gate doping portion 2312 stacked in the first direction Y, the fourth gate doping portion 2212 is located on the side of the third gate doping portion 2211 away from the second surface 1A2, and the sixth gate doping portion 2312 is located on the side of the fifth gate doping portion 2311 away from the second surface 1A2. The second shielding portion 213, the third gate doping portion 2211, and the fifth gate doping portion 2311 have doping ions of the same conductivity type. In this way, the second shielding portion 213, the third gate doping portion 2211, and the fifth gate doping portion 2311 can be formed at the same time, and the fourth gate doping portion 2212 and the sixth gate doping portion 2312 can be formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0080] In some implementations, the second shielding portion 213 , the third gate doping portion 2211 , and the fifth gate doping portion 2311 have doping ions of the first conductivity type, and the fourth gate doping portion 2212 and the sixth gate doping portion 2312 have doping ions of the second conductivity type.

[0081] In some implementations, the semiconductor device 100 further includes a floating region 36 located in the semiconductor layer 1, the floating region 36 has a conductivity type opposite to that of the second pillar region 1D2, and the bottom of at least one of the first gate trench 131, the second gate trench 132, and the third gate trench 133 extends to the inside of the floating region 36. In this way, the floating region 36 protects the gate dielectric layer located at the bottom of at least one of the first trench gate structure 21 to the third trench gate structure 23, reduces the risk of the gate dielectric layer being broken down, and improves the withstand voltage performance of the semiconductor device 100.

[0082] Exemplarily, the floating region 36 includes a first floating region 361 、 The first gate trench 131, the second gate trench 132 and the third gate trench 133 extend to the first floating region 361 respectively. 、 The inside of the second floating region 362 and the third floating region 363. In this way, the three floating regions 36 protect the gate dielectric layers at the bottoms of the three gate trenches, thereby better improving the withstand voltage performance of the semiconductor device 100.

[0083] In some embodiments, the first gate lead-out structure 41 , the second gate lead-out structure 42 , the third gate lead-out structure 43 , the emitter 44 , the conductive electrode 45 and the lead-out structure 46 may include the same material. In this way, these structures may be formed simultaneously, simplifying the manufacturing process of the semiconductor device 100 .

[0084] In other embodiments, please refer to Figure 2 , which is a schematic cross-sectional view of another semiconductor device provided in an exemplary embodiment of the present disclosure. Figure 2 The semiconductor device 100 is shown with Figure 1 The first gate portion 211 is basically similar to the first shield portion 212 and the body region 31 in the second direction X. In this way, when the semiconductor device 100 is turned on, the first gate portion 211 can act on the body region 31 to form a first conductive channel, and cooperate with the second gate portion 221 to also act on the body region 31 to form a second conductive channel. The first channel and the second channel form a double channel, which improves the current density when the semiconductor device 100 is turned on.

[0085] In some other embodiments, please refer to Figure 3 , which is a schematic cross-sectional view of yet another semiconductor device provided in an exemplary embodiment of the present disclosure. Figure 3 The semiconductor device 100 is shown with Figure 1The semiconductor device 100 shown is substantially similar, and the similarities are not repeated, and the differences include that the first shielding portion 212 and the first gate portion 211 have doping ions of the same conductivity type. In this way, the first shielding portion 212 and the first gate portion 211 are formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0086] In some other embodiments, please refer to Figure 4 , which is a schematic cross-sectional view of yet another semiconductor device provided in an exemplary embodiment of the present disclosure. Figure 4 The semiconductor device 100 is shown with Figure 1 The semiconductor device 100 shown is basically similar, and the similarities are not repeated here. The differences include that the first shielding portion 212 includes a first shielding doping portion 2121 and a second shielding doping portion 2122 stacked in the first direction Y, and the second shielding doping portion 2122 is located on the side of the first shielding doping portion 2121 away from the second surface 1A2. The second gate doping portion 2112 is located on the side of the first gate doping portion 2111 away from the second surface 1A2. The conductivity type of the doped ions in the second shielding doping portion 2122 and the second gate doping portion 2112 is the same. The conductivity type of the doped ions in the first shielding doping portion 2121 and the first gate doping portion 2111 is the same. In this way, the first shielding portion 212 and the first gate portion 211 can be formed simultaneously, simplifying the manufacturing process of the semiconductor device 100.

[0087] According to the second aspect of the embodiment of the present application, referring to Figure 5 As shown, the embodiment of the present application further provides a method for forming a semiconductor device 100. The method for forming the semiconductor device 100 includes steps S101 to S103.

[0088] Reference Figure 6 As shown, the above step S101 is performed to form a semiconductor layer 1 , wherein the semiconductor layer 1 has a first surface 1A1 and a second surface 1A2 that are oppositely arranged in a first direction Y.

[0089] In some embodiments, reference Figure 6 As shown, forming the semiconductor layer 1 includes:

[0090] Providing a first preliminary semiconductor layer 11 of a second conductivity type, wherein the first preliminary semiconductor layer 11 has a second surface 1A2;

[0091] A second initial semiconductor layer 12 of the second conductivity type is formed on a surface of the first initial semiconductor layer 11 away from the second surface 1A2 . The surface of the second initial semiconductor layer 12 away from the first initial semiconductor layer 11 is the first surface 1A1 .

[0092] In some embodiments, the first initial semiconductor layer 11 and the second initial semiconductor layer 12 each include a semiconductor material and a doping material. The semiconductor material includes at least one of silicon, a compound semiconductor material, and an alloy semiconductor material. Exemplarily, the first initial semiconductor layer 11 and the second initial semiconductor layer 12 include silicon and an N-type doping material.

[0093] In some embodiments, the second preliminary semiconductor layer 12 may be an epitaxial layer formed by an epitaxial process, but is not limited thereto.

[0094] In some embodiments, reference Figure 7 As shown, forming the semiconductor layer 1 further includes:

[0095] A first column region 1D1 of the first conductivity type and a second column region 1D2 of the second conductivity type are formed inside the semiconductor layer 1 . The first column region 1D1 and the second column region 1D2 are adjacent to each other in the second direction X, and extend from the inside of the semiconductor layer 1 along the first direction Y to the first surface 1A1 .

[0096] Illustratively, after forming the second initial semiconductor layer 12, a first implantation process of doped ions of the first conductive type can be performed on the second initial semiconductor layer 12, and annealing can be performed. The first implantation process and annealing steps can be repeated until the target first conductive type first column region 1D1 and second conductive type second column region 1D2 are obtained.

[0097] In some embodiments, the concentration of the first conductivity type doping ions of the first stud region 1D1 and the concentration of the second conductivity type doping ions of the second stud region 1D2 may be the same, and the first conductivity type is opposite to the second conductivity type, but is not limited thereto.

[0098] Step S102 : forming a first gate trench 131 in the semiconductor layer 1 , wherein the first gate trench 131 is sunken from the first surface 1A1 toward the second surface 1A2 .

[0099] In some embodiments, reference Figure 8 As shown, a first gate trench 131 is formed by an etching process, and the first gate trench 131 extends to the first stud region 1D1 and the second stud region 1D2.

[0100] In some embodiments, reference Fig. 9 As shown, the method for forming the semiconductor device 100 further includes: forming a first floating region 361 at the bottom of the first gate trench 131 in the semiconductor layer 1, wherein the conductivity type of the first floating region 361 is opposite to the conductivity type of the second column region 1D2.

[0101] Step S103 : forming a first trench gate structure 21 in the first gate trench 131 , wherein the first trench gate structure 21 includes a first gate portion 211 and a first shielding portion 212 . The first gate portion 211 and the first shielding portion 212 are arranged in a second direction X at intervals, and the first direction Y intersects the second direction X.

[0102] In some embodiments, reference Fig.10 As shown, a first trench gate structure 21 is formed in the first gate trench 131 , and further includes: forming a first initial gate dielectric layer 2141 on the wall of the first gate trench 131 .

[0103] In some embodiments, reference Fig.10 and Fig.11 As shown, a first trench gate structure 21 is formed in the first gate trench 131 , including: forming a second shielding portion 213 at the bottom of the first gate trench 131 .

[0104] Exemplarily, a second shielding portion 213 is formed at the bottom of the first gate trench 131, including: forming a second initial shielding portion 213A filling the remaining first gate trench 131, the first initial gate dielectric layer 2141 is located between the second initial shielding portion 213A and the wall of the first gate trench 131; and removing part of the second initial shielding portion 213A along the first direction Y, and the remaining second initial shielding portion 213A constitutes the second shielding portion 213.

[0105] In some embodiments, reference Fig.13 As shown, a first trench gate structure 21 is formed in the first gate trench 131 , and further includes: forming a fourth initial gate dielectric layer 2142 on the second shielding portion 213 .

[0106] In some embodiments, reference Figures 13 to 16 As shown, a first trench gate structure 21 is formed in the first gate trench 131, and further includes:

[0107] forming a first initial gate doping portion 2111A in the first gate trench 131;

[0108] A second initial gate doping portion 2112A is formed in the first gate trench 131 and is stacked on the first initial gate doping portion 2111A. The conductivity types of doped ions in the first initial gate doping portion 2111A and the second initial gate doping portion 2112A are opposite.

[0109] A first through groove is formed along the first direction Y, penetrating the first initial gate doping portion 2111A and the second initial gate doping portion 2112A. The remaining first initial gate doping portion 2111A and the second initial gate doping portion 2112A constitute the first gate portion 211 and the first shielding portion 212. In the second direction X, the first through groove is located between the first gate portion 211 and the first shielding portion 212. The first gate portion 211 includes a first gate doping portion 2111 and a second gate doping portion 2112 stacked along the first direction Y. The first shielding portion 212 includes a first shielding doping portion 2121 and a second shielding doping portion 2122 stacked along the first direction Y.

[0110] In some embodiments, reference Figure 13 to Figure 14 As shown, forming a first initial gate doping portion 2111A in the first gate trench 131 includes: forming a first initial gate doping portion 2111A in the first gate trench 131 and located on the fourth initial gate dielectric layer 2142 .

[0111] In some embodiments, reference Fig.16 As shown, a first trench gate structure 21 is formed in the first gate trench 131 , and further includes: forming a fifth initial gate dielectric layer 2143 between the first gate portion 211 and the first shielding portion 212 .

[0112] It should be noted that the fifth initial gate dielectric layer 2143 , the fourth initial gate dielectric layer 2142 , and the first initial gate dielectric layer 2141 in the first gate trench 131 constitute the first gate dielectric layer 214 .

[0113] In some other embodiments, forming the first trench gate structure 21 in the first gate trench 131 includes:

[0114] forming a first initial gate doping portion 2111A in the first gate trench 131;

[0115] A second through-groove is formed along the second direction X through the first initial gate doping portion 2111A. The remaining first initial gate doping portion 2111A constitutes a first gate portion 211 and a first shielding portion 212 spaced apart along the second direction X. The second through-groove is located between the first gate portion 211 and the first shielding portion 212 .

[0116] In some other embodiments, forming the first trench gate structure 21 in the first gate trench 131 includes:

[0117] forming a first initial gate doping portion 2111A in the bottom of the first gate trench 131;

[0118] A second initial gate doping portion 2112A is formed in the first gate trench 131 and is stacked on the first initial gate doping portion 2111A. The conductivity types of doped ions in the first initial gate doping portion 2111A and the second initial gate doping portion 2112A are opposite.

[0119] A first through-groove is formed that penetrates the first initial gate doping portion 2111A and the second initial gate doping portion 2112A along the first direction Y, and the remaining first initial gate doping portion 2111A and the second initial gate doping portion 2112A constitute a first gate portion 211, and the first gate portion 211 is adjacent to the first through-groove in the second direction X;

[0120] A first shielding portion 212 is formed in the first through-groove.

[0121] In some embodiments, reference Figures 8 to 12 As shown, the method of the semiconductor device includes: forming a second gate trench 132 in the semiconductor layer 1, the second gate trench 132 is recessed from the first surface 1A1 to the second surface 1A2 and extends toward the second column region 1D2; forming a second trench gate structure 22 in the second gate trench 132; and, forming a first conductive type body region 31 in the semiconductor layer 1, the body region 31 is located between the first trench gate structure 21 and the second trench gate structure 22.

[0122] In some embodiments, reference Figures 8 to 12 As shown, the method of the semiconductor device includes: forming a third gate trench 133 in the semiconductor layer 1, the third gate trench 133 is recessed from the first surface 1A1 to the second surface 1A2 and extends toward the first column region 1D1; forming a third trench gate structure 23 in the third gate trench 133; and forming a first conductive type depletion region 34 therein, the depletion region 34 is located between the first trench gate structure 21 and the third trench gate structure 23.

[0123] In some embodiments, reference Figure 8 As shown, in the process of forming the first gate trench 131 in the semiconductor layer 1, the second gate trench 132 is formed in the semiconductor layer 1, and the third gate trench 133 is formed in the semiconductor layer 1. In this way, the first gate trench 131 to the third gate trench 133 are formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0124] In some embodiments, reference Fig. 9 As shown, the method for forming the semiconductor device 100 further includes:

[0125] In the process of forming the first floating region 361 inside the semiconductor layer 1, the second floating region 362 is formed at the bottom of the second gate trench 132, and the third floating region 363 is formed at the bottom of the third gate trench 133. The bottom of the second gate trench 132 extends into the second floating region 362, and the bottom of the third gate trench 133 extends into the third floating region 363. The conductivity types of the second floating region 362 and the third floating region 363 are opposite to the conductivity type of the second column region 1D2.

[0126] In some embodiments, reference Fig.10 As shown, after forming the first gate trench 131 to the third gate trench 133, the method for forming the semiconductor device 100 further includes:

[0127] During the process of forming the first initial gate dielectric layer 2141 on the wall of the first gate trench 131 , the second gate dielectric layer 222 is formed on the wall of the second gate trench 132 , and the third gate dielectric layer 232 is formed on the wall of the third gate trench 133 .

[0128] In some embodiments, reference Figure 10 to Figure 11 As shown, the method for forming the semiconductor device 100 further includes: in the process of forming the second shielding portion 213 at the bottom of the first gate trench 131, forming the third gate doping portion 2211 at the bottom of the second gate trench 132, and forming the fifth gate doping portion 2311 in the bottom of the third gate trench 133, the second trench gate structure 22 includes the third gate doping portion 2211, the third trench gate structure 23 includes the fifth gate doping portion 2311, and the second shielding portion 213, the third gate doping portion 2211 and the fifth gate doping portion 2311 include doping ions of the same conductivity type. In this way, the second shielding portion 213, the third gate doping portion 2211 and the fifth gate doping portion 2311 having the same conductivity type and located at the bottom of the groove can be formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0129] Exemplarily, in the process of forming the second shielding portion 213 located on the first initial gate dielectric layer 2141 in the first gate trench 131, the third gate doping portion 2211 located on the second gate dielectric layer 222 is formed in the second gate trench 132, and the fifth gate doping portion 2311 located on the third gate dielectric layer 232 is formed in the third gate trench 133.

[0130] In some embodiments, reference Fig.12As shown, the method of the semiconductor device 100 further includes: in the process of forming the fourth gate doping portion 2212 stacked on the third gate doping portion 2211 in the second gate trench 132, forming the sixth gate doping portion 2312 stacked on the fifth gate doping portion 2311 in the third gate trench 133, the second trench gate structure 22 further includes the fourth gate doping portion 2212, the third trench gate structure 23 further includes the sixth gate doping portion 2312, the sixth gate doping portion 2312 and the fourth gate doping portion 2212 include doping ions of the same conductivity type, and the sixth gate doping portion 2312 and the fifth gate doping portion 2311 include doping ions of opposite conductivity types. In this way, the fourth gate doping portion 2212 and the sixth gate doping portion 2312 can be formed at the same time, further simplifying the manufacturing process of the semiconductor device 100.

[0131] In some embodiments, reference Fig.17 As shown, the method for forming the semiconductor device 100 further includes: forming a depletion region 34 of the first conductivity type in the semiconductor layer 1 , wherein the depletion region 34 is located between the first trench gate structure 21 and the third trench gate structure 23 .

[0132] In some embodiments, reference Fig.17 As shown, the method for forming the semiconductor device 100 also includes: forming an ohmic contact region 33 of a first conductivity type in the semiconductor layer 1, the ohmic contact region 33 is located between the first trench gate structure 21 and the third trench gate structure 23, and in the first direction Y, the ohmic contact region 33 is located between the depletion region 34 and the first surface 1A1 and is adjacent to the depletion region 34, and the concentration of doped ions in the ohmic contact region 33 is greater than the concentration of doped ions in the first column region 1D1 and the concentration of doped ions in the depletion region 34.

[0133] In some embodiments, reference Fig.17 As shown, the method for forming the semiconductor device 100 further includes: forming a carrier storage layer 35 in the semiconductor layer 1 , the carrier storage layer 35 is located between the first trench gate structure 21 and the second trench gate structure 22 , and the carrier storage layer 35 is adjacent to the second column region 1D2 .

[0134] In some embodiments, reference Fig.17 As shown, the method for forming the semiconductor device 100 further includes: forming an emitter region 32 in the semiconductor layer 1 , the emitter region 32 being located between the first trench gate structure 21 and the second trench gate structure 22 , and the emitter region 32 being located on a side of the body region 31 away from the second surface 1A2 and adjacent to the body region 31 .

[0135] In some embodiments, reference Fig.17 and Fig.18 As shown, the method for forming the semiconductor device 100 further includes:

[0136] An isolation dielectric layer 5 is formed on the first surface 1A1, the isolation dielectric layer 5 includes a first through hole, a second through hole, a third through hole, a fourth through hole, a fifth through hole and a sixth through hole penetrating the isolation dielectric layer 5 along the first direction Y, the first through hole exposing the first gate portion 211, the second through hole exposing the second gate portion 221, the third through hole exposing the third gate portion 231, the fourth through hole exposing the first shielding portion 212, the fifth through hole exposing the emitter 44, and the sixth through hole exposing the lead-out structure 46;

[0137] A conductive layer 4 is formed, and the conductive layer 4 includes an emitter 44, a first gate lead-out structure 41, a second gate lead-out structure 42, a third gate lead-out structure 43, a conductive electrode 45 and a lead-out structure 46. The first gate lead-out structure 41, the second gate lead-out structure 42 and the third gate lead-out structure 43 are connected to each other, and the emitter 44 is connected to the conductive electrode 45 and the lead-out structure 46. The first gate lead-out structure 41 is located in the first through hole and contacts the first gate portion 211, the second gate lead-out structure 42 is located in the second through hole and contacts the second gate portion 221, the third gate lead-out structure 43 is located in the third through hole and contacts the third gate portion 231, the conductive electrode 45 is located in the fourth through hole and contacts the first shielding portion 212, the emitter 44 is located in the fifth through hole and contacts the emitter region 32, and the lead-out structure 46 is located in the sixth through hole and contacts the ohmic through region.

[0138] Through the above steps, the emitter 44 , the first gate lead-out structure 41 , the second gate lead-out structure 42 , the third gate lead-out structure 43 , the conductive electrode 45 and the lead-out structure 46 are simultaneously formed, thereby simplifying the manufacturing process of the semiconductor device 100 .

[0139] In some embodiments, reference Fig.18 As shown, the method for forming the semiconductor device 100 further includes: thinning the semiconductor layer 1 from the second surface 1A2; injecting doping ions of the second conductivity type from the second surface obtained after the thinning process to form a heavily doped initial buffer zone of the second conductivity type; injecting doping ions of the first conductivity type from the second surface after the thinning process, and annealing to convert part of the initial buffer zone into a collector zone 1B of the first conductivity type, and the remaining initial buffer zone constitutes a buffer zone 1C. Annealing uses laser annealing to reduce the impact of high temperature on the conductive layer 4.

[0140] In some embodiments, the method for forming the semiconductor device 100 further includes: forming a collector electrode 6 on the collector region 1B.

[0141] In the formation method of the semiconductor device 100 of some embodiments of the present application, the gate in the first gate trench 131 is split into a first gate portion 211 and a first shielding portion 212 arranged at intervals in the second direction X. The design of the first shielding portion 212 converts the parasitic capacitance between part of the gate and the drain in the conventional technology into the parasitic capacitance between the first shielding portion 212 and the drain. In addition, the first shielding portion 212 also shields the lateral parasitic capacitance between the first gate portion 211 and the drain, thereby reducing the parasitic capacitance between the first gate portion 211 and the drain. Furthermore, the design of the first shielding portion 212 makes the first gate portion 211 a narrow gate structure. In the first direction Y, the first gate portion 211 has a smaller facing area with the drain, and the parasitic capacitance between the first gate portion 211 and the drain is smaller. The smaller gate-drain capacitance can reduce the switching loss of the semiconductor device 100.

[0142] According to a third aspect of the present disclosure, an embodiment of the present application further provides an on-vehicle chip. The on-vehicle chip includes the semiconductor device 100 described above. The reduced switching loss of the semiconductor device 100 can improve the performance of the on-vehicle chip.

[0143] According to a fourth aspect of the present disclosure, an embodiment of the present application further provides a vehicle. The vehicle may be a fuel vehicle, a plug-in hybrid vehicle, or a new energy vehicle. The vehicle includes the above-mentioned on-board chip. The performance improvement of the on-board chip can improve the performance of the vehicle.

[0144] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0145] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0147] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. Although the descriptions of various embodiments in the embodiments of the present application have different focuses, for the parts not described in detail in a certain embodiment, reference can be made to the relevant contents of other embodiments. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device (100), characterized in that: include: A semiconductor layer (1) having a first surface (1A1) and a second surface (1A2) arranged opposite to each other in a first direction (Y); A first gate trench (131) located in the semiconductor layer (1), recessed from the first surface (1A1) toward the second surface (1A2); A first trench gate structure (21) is located in the first gate trench (131) and comprises a first gate portion (211) and a first shielding portion (212), wherein the first gate portion (211) and the first shielding portion (212) are arranged at intervals in a second direction (X), and the first direction (Y) intersects with the second direction (X).

2. The semiconductor device (100) according to claim 1, characterized in that Also includes: A conductive electrode (45) is located on the first surface (1A1) and is in contact with the first shielding portion (212).

3. The semiconductor device (100) according to claim 2, characterized in that: Also includes: The emitter (44) is located on the first surface (1A1) of the semiconductor layer (1) and is connected to the conductive electrode (45).

4. The semiconductor device (100) according to claim 1, characterized in that Also includes: A body region (31) of the first conductivity type located in the semiconductor layer (1) is located on one side of the first trench gate structure (21) in the second direction (X), and the first gate portion (211) is located between the first shielding portion (212) and the body region (31) in the second direction (X).

5. The semiconductor device (100) according to claim 1, characterized in that The first shielding portion (212) includes a first shielding doping portion (2121) and a second shielding doping portion (2122) stacked in the first direction (Y), and the second shielding doping portion (2122) is located on a side of the first shielding doping portion (2121) away from the second surface (1A2).

6. The semiconductor device (100) according to claim 5, characterized in that The first gate portion (211) includes a first gate doping portion (2111) and a second gate doping portion (2112) stacked in the first direction (Y), and the conductivity types of doped ions in the first gate doping portion (2111) and the second gate doping portion (2112) are opposite.

7. The semiconductor device (100) according to claim 6, characterized in that The second gate doping portion (2112) is located on a side of the first gate doping portion (2111) away from the second surface (1A2), the conductivity type of the doped ions in the second shielding doping portion (2122) and the second gate doping portion (2112) is the same, and the conductivity type of the doped ions in the first shielding doping portion (2121) and the first gate doping portion (2111) is the same.

8. The semiconductor device (100) according to claim 1, characterized in that The first shielding portion (212) and the first gate portion (211) have doping ions of the same conductivity type.

9. The semiconductor device (100) according to claim 1, characterized in that: The semiconductor layer (1) further comprises a first column region (1D1) of a first conductivity type and a second column region (1D2) of a second conductivity type; the first column region (1D1) and the second column region (1D2) are located on a side of the first surface (1A1) away from the first trench gate structure (21) in the first direction (Y); the first column region (1D1) and the second column region (1D2) are adjacent to each other in the second direction (X); and the first column region (1D1) and the second column region (1D2) extend along the first direction (Y).

10. The semiconductor device (100) according to claim 9, characterized in that: Also includes: A second gate trench (132) located in the semiconductor layer (1), the second gate trench (132) being recessed from the first surface (1A1) toward the second surface (1A2) and extending toward the second column region (1D2); A second trench gate structure (22) located in the second gate trench (132); The body region (31) of the first conductivity type located in the semiconductor layer (1) is located between the first trench gate structure (21) and the second trench gate structure (22).

11. The semiconductor device (100) according to claim 10, characterized in that Also includes: A third gate trench (133) located in the semiconductor layer (1), the third gate trench (133) being recessed from the first surface (1A1) toward the second surface (1A2) and extending toward the first column region (1D1); A third trench gate structure (23), located in the third gate trench (133); A depletion region (34) of the first conductivity type located in the semiconductor layer (1) is located between the first trench gate structure (21) and the third trench gate structure (23).

12. The semiconductor device (100) according to claim 11, characterized in that In the second direction (X), the first gate portion (211) is located between the depletion region (34) and the first shielding portion (212).

13. The semiconductor device (100) according to claim 11, characterized in that The second trench gate structure (22) includes a second gate portion (221), the second gate portion (221) includes a third gate doping portion (2211) and a fourth gate doping portion (2212) stacked in the first direction (Y), and the conductivity types of the doped ions in the third gate doping portion (2211) and the fourth gate doping portion (2212) are opposite.

14. The semiconductor device (100) according to claim 13, characterized in that The third trench gate structure (23) includes a third gate portion (231), and the third gate portion (231) includes a fifth gate doping portion (2311) and a sixth gate doping portion (2312) stacked in the first direction (Y), and the conductivity types of the doped ions in the fifth gate doping portion (2311) and the sixth gate doping portion (2312) are opposite.

15. The semiconductor device (100) according to claim 14, characterized in that The first trench gate structure (21) further includes a second shielding portion (213), wherein the second shielding portion (213) is located at the bottom of the first gate trench (131), and the first gate portion (211) and the first shielding portion (212) are located on a side of the second shielding portion (213) that is away from the second surface (1A2).

16. The semiconductor device (100) according to claim 15, characterized in that The fourth gate doping portion (2212) is located on a side of the third gate doping portion (2211) away from the second surface (1A2), the sixth gate doping portion (2312) is located on a side of the fifth gate doping portion (2311) away from the second surface (1A2), and the second shielding portion (213), the third gate doping portion (2211) and the fifth gate doping portion (2311) have doping ions of the same conductivity type.

17. The semiconductor device (100) according to claim 11, characterized in that Also includes: A floating region (36) is located in the semiconductor layer (1), the floating region (36) has a conductivity type opposite to that of the second column region (1D2), and the bottom of at least one of the first gate trench (131), the second gate trench (132) and the third gate trench (133) extends to the interior of the floating region (36).

18. The semiconductor device (100) according to any one of claims 1 to 17, characterized in that: The first trench gate structure (21) further comprises a first gate dielectric layer (214), wherein the first gate dielectric layer (214) is at least filled between the first gate portion (211), the first shielding portion (212) and the wall of the first gate trench (131).

19. The semiconductor device (100) according to any one of claims 1 to 17, characterized in that: The semiconductor layer (1) comprises a collector region (1B), a buffer region (1C) and a drift region (1D); in the first direction (Y), the buffer region (1C) is located between the collector region (1B) and the drift region (1D), the collector region (1B) is adjacent to the second surface (1A2), and the first gate trench (131) is located in the drift region (1D).

20. A method for forming a semiconductor device (100), characterized in that: The method comprises: Forming a semiconductor layer (1), wherein the semiconductor layer (1) has a first surface (1A1) and a second surface (1A2) arranged opposite to each other in a first direction (Y); A first gate trench (131) is formed in the semiconductor layer (1), wherein the first gate trench (131) is recessed from the first surface (1A1) toward the second surface (1A2); A first trench gate structure (21) is formed in the first gate trench (131), the first trench gate structure (21) comprising a first gate portion (211) and a first shielding portion (212), the first gate portion (211) and the first shielding portion (212) being arranged at intervals in a second direction (X), and the first direction (Y) intersects with the second direction (X).

21. The method for forming a semiconductor device (100) according to claim 20, characterized in that: The forming of the semiconductor layer (1) comprises: A first column region (1D1) of a first conductivity type and a second column region (1D2) of a second conductivity type are formed inside the semiconductor layer (1), the first column region (1D1) and the second column region (1D2) are adjacent to each other in the second direction (X), and the first column region (1D1) and the second column region (1D2) extend from the inside of the semiconductor layer (1) along the first direction (Y) to the first surface (1A1).

22. The method for forming a semiconductor device (100) according to claim 21, characterized in that: The method comprises: A second gate trench (132) is formed in the semiconductor layer (1), wherein the second gate trench (132) is recessed from the first surface (1A1) toward the second surface (1A2) and extends toward the second column region (1D2); forming a second trench gate structure (22) in the second gate trench (132); A body region (31) of the first conductivity type is formed in the semiconductor layer (1), and the body region (31) is located between the first trench gate structure (21) and the second trench gate structure (22).

23. The method for forming a semiconductor device (100) according to claim 22, characterized in that: The method further comprises: A third gate trench (133) is formed in the semiconductor layer (1), wherein the third gate trench (133) is recessed from the first surface (1A1) toward the second surface (1A2) and extends toward the first column region (1D1); forming a third trench gate structure (23) in the third gate trench (133); A depletion region (34) of the first conductivity type is formed in the semiconductor layer (1), and the depletion region (34) is located between the first trench gate structure (21) and the third trench gate structure (23).

24. The method for forming a semiconductor device (100) according to claim 23, characterized in that: The method comprises: In the process of forming the second shielding portion (213) at the bottom of the first gate trench (131), a third gate doping portion (2211) is formed at the bottom of the second gate trench (132), and a fifth gate doping portion (2311) is formed in the bottom of the third gate trench (133), the first trench gate structure (21) also includes the second shielding portion (213), the first gate portion (211) and the first shielding portion (212) are located on the side of the second shielding portion (213) away from the second surface (1A2), the second trench gate structure (22) includes the third gate doping portion (2211), the third trench gate structure (23) includes the fifth gate doping portion (2311), and the second shielding portion (213), the third gate doping portion (2211) and the fifth gate doping portion (2311) include doping ions of the same conductivity type.

25. The method for forming a semiconductor device (100) according to claim 24, characterized in that: The method further comprises: In the process of forming a fourth gate doping portion (2212) stacked on the third gate doping portion (2211) in the second gate trench (132), a sixth gate doping portion (2312) stacked on the fifth gate doping portion (2311) is formed in the third gate trench (133), the second trench gate structure (22) also includes the fourth gate doping portion (2212), the third trench gate structure (23) also includes the sixth gate doping portion (2312), the sixth gate doping portion (2312) and the fourth gate doping portion (2212) include doping ions of the same conductivity type, and the sixth gate doping portion (2312) and the fifth gate doping portion (2311) include doping ions of opposite conductivity types.

26. A vehicle-mounted chip, characterized in that: A semiconductor device (100) comprising any one of claims 1 to 19.

27. A vehicle, characterized in that: Including the vehicle-mounted chip as described in claim 26.

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