A structure for improving integration of GaN n-channel and p-channel devices and a preparation method thereof

Abstract

The application discloses a structure and a preparation method for improving the integration of n-groove and p-groove devices, and relates to the technical field of semiconductor device preparation. A high-resistance buffer layer, a GaN channel layer, a barrier layer, a current transmission transition layer, a channel current expansion layer, a current blocking layer and a p-type ohmic contact layer are sequentially formed on a substrate. The current transmission transition layer, the channel current expansion layer, the current blocking layer and the p-type ohmic contact layer are etched and removed through an n-groove region etching mask, a doped gate control layer is made in an n-groove device preparation area, ohmic contact electrodes a and b are arranged on the left and right sides of the doped gate control layer, an ohmic contact electrode c is arranged on the p-type ohmic contact layer, the p-type ohmic contact layer and the current blocking layer and part of the channel current expansion layer are etched, a medium layer is regrown, and gate metal layers a and b are prepared in an n-groove device gate metal preparation area and a p-groove gate control area. The preparation precision requirement is low, and the current transmission capacity of the p-groove device is high.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a structure and fabrication method for improving the integration density of GaNn trench and p-trench devices. Background Technology

[0002] GaN power switching devices possess high switching speeds and low on-resistance, making them valuable for applications in efficient, miniaturized power supply systems. While GaN power switching devices can achieve high switching speeds, the high parasitic inductance of discrete drive schemes severely limits their operating speed. To address this issue, the current main approach is to integrate the GaN driver and power switch on a single chip. This approach effectively reduces the parasitic inductance between the driver and the power switch, thereby significantly improving the switching speed of GaN power switching devices.

[0003] Due to the difficulty of p-type doping in GaN materials, existing GaN HEMT devices are all n-channel conductive devices. Current GaN driver integration schemes mainly employ enhancement-mode GaN HEMT devices integrated with resistors, or enhancement-mode GaN HEMT devices integrated with depletion-mode GaN HEMT devices, to implement logic gate circuits such as inverters. Because of the lack of p-channel devices, it is impossible to form logic circuits similar to CMOS devices, resulting in high static power consumption in GaN driver integration schemes. To address this issue, many international research institutions are conducting research on GaN n-channel and p-channel device integration technologies, primarily using laterally conductive enhancement-mode n-channel GaN HEMT devices and laterally conductive enhancement-mode p-channel structures for integration. Due to the low hole mobility and low carrier concentration in GaN materials, the output current difference between GaN p-channel and GaN n-channel devices is large when using laterally conductive devices for integration. This necessitates the use of large-size GaN p-channel and n-channel devices for current matching, resulting in large chip area and low integration density. To improve the output current density and integration density of GaN p-channel devices, this invention adopts a structure that integrates vertically transmitted p-channel devices and n-channel devices to effectively realize a CMOS-like integrated structure. By using vertically transmitted p-channel devices and a structure that shares the source and drain of the two types of devices, the problem of large area ratio in p-channel device integration is further reduced, effectively improving the device integration density. Summary of the Invention

[0004] Technical problems to be solved:

[0005] The technical problem this application aims to solve is that high parasitic inductance severely restricts the operating speed of devices, resulting in problems such as high static power consumption, large chip area, and low integration density in GaN driver integration schemes. This application provides a structure and fabrication method to improve the integration density of GaN n-channel and p-channel devices.

[0006] Technical solution:

[0007] A method for fabricating structures that improve the integration density of GaNn trench and p-trench devices, comprising the following steps:

[0008] Step 1. Form a high-resistivity buffer layer on the substrate, form a GaN channel layer on the high-resistivity buffer layer, form a barrier layer on the GaN channel layer, form a current transport transition layer on the barrier layer, form a channel current extension layer on the current transport transition layer, form a current blocking layer on the channel current extension layer, and form a p-type ohmic contact layer on the current blocking layer; using an n-channel region etching mask, etch away the current transport transition layer, channel current extension layer, current blocking layer, and p-type ohmic contact layer above the barrier layer in the n-channel region to expose the n-channel device fabrication area;

[0009] Step 2. Fabricate a doped gate control layer in the n-channel device fabrication region using a selected regeneration process;

[0010] Step 3. Using an evaporation and lift-off process, ohmic contact electrodes a, b, and c are fabricated on the etched barrier layer and the p-type ohmic contact layer. Ohmic contact electrodes a and b are respectively disposed on the left and right sides of the doped gate control layer, and ohmic contact electrode c is disposed on the p-type ohmic contact layer. An ohmic contact is formed by alloying.

[0011] Step 4. Using the etching mask of the p-channel gate control region, etch the p-type ohmic contact layer, the current blocking layer, and part of the channel current extension layer;

[0012] Step 5. Form a gate control dielectric layer and a surface protective layer by growing a dielectric layer;

[0013] Step 6. Expose the gate metal fabrication region of the n-channel device above the doped gate control layer by dielectric etching;

[0014] Step 7. By evaporation and peeling, gate metal layer a and gate metal layer b are prepared in the gate metal fabrication region of the n-channel device and the gate control region of the p-channel device, respectively, to form the gate of the n-channel and p-channel devices;

[0015] Step 8. Expose the metal electrodes of ohmic contact electrode a, ohmic contact electrode b and ohmic contact electrode c through an etching process.

[0016] This application also discloses a structure for improving the integration density of GaNn trench and p-channel devices prepared by the above-mentioned method. The structure for improving the integration density of GaNn trench and p-channel devices includes a substrate, a high-resistivity buffer layer formed on the substrate, a GaN channel layer formed on the high-resistivity buffer layer, and a barrier layer formed on the GaN channel layer. An ohmic contact electrode a, a doped gate control layer, an ohmic contact electrode b, and a current transport transition layer are sequentially disposed on the barrier layer. A channel current extension layer, a current blocking layer, and a p-type ohmic contact layer are sequentially disposed on the current transport transition layer. An ohmic contact electrode c is disposed on the p-type ohmic contact layer. Then, a dielectric layer is disposed on the entire structure. A gate metal layer a is disposed on the doped gate control layer, and a gate metal layer b is disposed on the dielectric layer of the p-channel gate control region.

[0017] As a preferred technical solution of this application: an n-channel carrier transport structure is formed by a barrier layer and a GaN channel layer; the source and drain electrodes of the n-channel device are formed by ohmic contact electrodes a and b; the gate control structure of the n-channel device is formed by a gate metal layer a and a doped gate control layer; the source and drain electrodes of the p-channel device are formed by ohmic contact electrodes b and c; the gate control of the p-channel device is achieved by the gate metal layer b through a dielectric layer; and the p-channel carrier transport structure is composed of a current transport transition layer, a channel current extension layer, a current blocking layer, and a p-type ohmic contact layer arranged from bottom to top.

[0018] As a preferred technical solution of this application: the substrate and the GaN channel layer are separated by a high-resistivity buffer layer. The substrate is a substrate for realizing the epitaxy of GaN material, specifically one of doped or undoped silicon, silicon carbide, gallium nitride, aluminum nitride and gallium oxide.

[0019] As a preferred technical solution of this application: the high-resistivity buffer layer is carbon-doped AlGaN, carbon-doped GaN, a composite material of carbon-doped AlGaN and GaN, iron-doped AlGaN, iron-doped GaN, a composite material of iron-doped AlGaN and GaN, magnesium-doped AlGaN, magnesium-doped GaN, or a composite material of magnesium-doped AlGaN and GaN.

[0020] As a preferred technical solution of this application: the GaN channel layer is an n-type lightly doped GaN material with a doping concentration of 1E16cm⁻¹. -3 -1E17cm -3 .

[0021] As a preferred technical solution of this application: the current transport transition layer is a GaN material with gradually varying doping concentration. The doping concentration at the interface between the current transport transition layer and the channel current extension layer is the same as that of the channel current extension layer, and the doping concentration gradually decreases towards the interface between the current transport transition layer and the barrier layer.

[0022] As a preferred technical solution of this application: the channel current extension layer is a p-type doped GaN material with a hole concentration of 1E15cm⁻¹. -3 -3E17cm -3 The current blocking layer is made of carbon-doped AlGaN material with a thickness of 100-200 nm, and the p-type ohmic contact layer is made of p-type-doped GaN material with a hole concentration of 3E17 cm⁻¹. -3 -4E19cm -3 .

[0023] As a preferred technical solution of this application: the doped gate control layer is a p-type GaN or AlGaN doped gate control layer; the hole concentration in the doped gate control layer is 1E17cm⁻¹. -3 -7E18cm -3 .

[0024] As a preferred technical solution of this application: the ohmic contact electrode is a Ti monolayer, Al monolayer, Ti multilayer metal, Al multilayer metal, Ti nitride, Al nitride or Ti / Al multilayer metal.

[0025] Beneficial effects:

[0026] The structure and fabrication method for improving the integration density of GaNn-channel and p-channel devices described in this application have the following technical advantages compared with the prior art:

[0027] 1. The p-channel device of the present invention adopts a longitudinal transmission structure, and the transmission path is determined by the epitaxial structure. Compared with the transverse structure, the process fabrication precision requirements are low, and the p-channel device has high current transmission capability.

[0028] 2. The p-channel has a short current transmission path, which can achieve a large current density. At the same time, the source and drain electrodes of the n-channel and p-channel devices can be shared through the current transmission transition structure, which can effectively reduce the problems of high current mismatch ratio and large device size in the integration of n-channel and p-channel devices. This is conducive to achieving higher density monolithic integration of GaN n-channel and p-channel devices. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the epitaxial wafer material structure of this application;

[0030] Figure 2 This is a schematic diagram of the etching process used to remove material above the barrier layer in this application.

[0031] Figure 3 This is a schematic diagram showing the gate control layer of the n-channel device formed according to this application;

[0032] Figure 4 This is a schematic diagram showing the source and drain metal contacts of the device formed in this application;

[0033] Figure 5 This is a schematic diagram showing the etching of a portion of the current blocking layer and the p-type ohmic contact layer in this application;

[0034] Figure 6 This is a schematic diagram of the surface growth medium in this application;

[0035] Figure 7 This is a schematic diagram showing the gate control metal after it has been formed according to this application;

[0036] Figure 8 This is a schematic diagram of the GaN n-channel and p-channel integrated device with dielectric via etching completed according to this application.

[0037] Explanation of reference numerals in the attached figures: 1. Substrate; 2. High-resistivity buffer layer; 3. GaN channel layer; 4. Barrier layer; 5. Current transport transition layer; 6. Channel current spread layer; 7. Current blocking layer; 8. P-type ohmic contact layer; 9. Doped gate control layer; 10-a. Ohmic contact electrode a; 10-b. Ohmic contact electrode b; 10-c. Ohmic contact electrode c; 11. Dielectric layer; 12-a. Gate metal layer a; 12-b. Gate metal layer b. Detailed Implementation

[0038] To make the description more vivid and intuitive, the specific technical solution of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings are only one embodiment of the present invention and should not be construed as limiting the present invention.

[0039] Example 1:

[0040] A method for fabricating structures that improve the integration density of GaNn trench and p-trench devices, comprising the following steps:

[0041] Step 1. As Figure 1 As shown, a carbon-doped high-resistivity buffer layer 2 of 200 nm AlN / 1 μm GaN is grown on a p-type doped silicon substrate 1, and a 200 nm 1E16 cm⁻¹ layer is formed on the high-resistivity buffer layer 2. -3 A silicon-doped GaN channel layer 3 is formed, and a 10nm Al layer is formed on the GaN channel layer 3. 0.1 Ga 0.9 N-barrier layer 4, with a concentration of 100nm from 1E16cm on barrier layer 4. -3 Up to 1E18cm -3 A gradient magnesium-doped GaN current transport transition layer 5 is formed, and a 300 nm channel magnesium-doped 1E18 cm⁻¹ is formed on the current transport transition layer 5. -3 GaN channel current extension layer 6, and 200 nm carbon-doped Al formed on channel current extension layer 6. 0.05 Ga 0.95 N current blocking layer 7, a 100nm magnesium-doped 4E19cm layer is formed on the current blocking layer 7.-3 GaN p-type ohmic contact layer 8; using conventional photolithography, the n-channel etching region is photolithographically etched. Through a photoresist etching mask in the n-channel region, chlorine-based ICP etching technology is used to etch and remove the current transport transition layer 5, channel current extension layer 6, current blocking layer 7, and p-type ohmic contact layer 8 above the n-channel barrier layer 4, exposing the n-channel device fabrication area. Then, the photoresist mask is removed by organic cleaning, such as... Figure 2 As shown;

[0042] Step 2. SiO dielectric is grown on the surface of the n-channel device fabrication area using a selected regeneration process. A regeneration mask for the gate control region of the n-channel device is formed using photolithography and fluorine-based dry etching techniques. A 100nm 7E18cm layer is then grown using MOCVD. -3 Magnesium-doped p-type GaN-doped gate control layer 9 allows for easy removal of SiO and GaN material above SiO outside the gate control region of the n-channel device via BOE, as shown in the following results. Figure 3 As shown;

[0043] Step 3. Using an evaporation-lift process, 200 nm of Ti / Al / Ni / Au metal is evaporated and lifted from the etched barrier layer 4 and the n-channel and p-channel ohmic contact regions on the p-type ohmic contact layer 8 to prepare ohmic contact electrodes a 10-a, b 10-b, and c 10-c. Ohmic contact electrodes a 10-a and b 10-b are respectively positioned on the left and right sides of the doped gate control layer 9, while ohmic contact electrode c 10-c is positioned on the p-type ohmic contact layer 8. Rapid annealing at 800 degrees Celsius is then performed to form ohmic contacts in the n-channel and p-channel regions. The results are shown below. Figure 4 As shown;

[0044] Step 4. Using traditional photolithography, fabricate an etching mask for the p-channel gate control region. Utilize chlorine-based dry etching technology to etch the p-type ohmic contact layer 8, the current blocking layer 7, and part of the channel current extension layer 6 within the p-channel gate control region. Remove the photoresist mask using organic cleaning. Figure 5 As shown;

[0045] Step 5. Using the ALD growth method, grow a 20nm Al2O3 dielectric layer 11 to form the gate control dielectric layer and the surface protective layer, such as... Figure 6 As shown;

[0046] Step 6. Using traditional photolithography, an etching window is created on the doped gate control layer 9 by dielectric etching, and the dielectric layer 11 in this area is etched using a developer to expose the gate metal fabrication area of ​​the n-channel device.

[0047] Step 7. Gate metal layers a 12-a and b 12-b are prepared by evaporation and lift-off in the gate metal fabrication region of the n-channel device and the gate control region of the p-channel device, respectively, to form the gates of the n-channel and p-channel devices, as shown below. Figure 7 As shown;

[0048] Step 8. Define the window positions of the ohmic metal using standard photolithography. Etch the dielectric layer 11 with developer to expose the metal electrodes of ohmic contact electrodes a 10-a, b 10-b, and c 10-c, as shown. Figure 8 As shown.

[0049] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. There are many manufacturing methods that can actually be adopted. All equivalent changes and modifications made in accordance with the claims of the present invention are within the scope of the present invention.

Claims

1. A method for fabricating a structure to improve the integration density of GaNn-channel and p-channel devices, characterized in that, The steps are as follows: Step 1. Form a high-resistivity buffer layer (2) on the substrate (1), form a GaN channel layer (3) on the high-resistivity buffer layer (2), form a barrier layer (4) on the GaN channel layer (3), form a current transport transition layer (5) on the barrier layer (4), form a channel current extension layer (6) on the current transport transition layer (5), form a current blocking layer (7) on the channel current extension layer (6), and form a p-type ohmic contact layer (8) on the current blocking layer (7); use an n-channel region etching mask to etch and remove the current transport transition layer (5), channel current extension layer (6), current blocking layer (7), and p-type ohmic contact layer (8) above the n-channel barrier layer (4), exposing the n-channel device fabrication area; Step 2. Fabricate a doped gate control layer in the n-channel device fabrication region by selecting a regeneration process (9); Step 3. Using an evaporation stripping process, ohmic contact electrodes a (10-a), b (10-b), and c (10-c) are fabricated on the etched barrier layer (4) and the p-type ohmic contact layer (8). Ohmic contact electrodes a (10-a) and b (10-b) are respectively disposed on the left and right sides of the doped gate control layer (9), and ohmic contact electrode c (10-c) is disposed on the p-type ohmic contact layer (8). The ohmic contact is formed by alloying. Step 4. Using the etching mask of the p-channel gate control region, etch the p-type ohmic contact layer (8), the current blocking layer (7), and part of the channel current extension layer (6); Step 5. Form a gate control dielectric layer and a surface protective layer through the growth dielectric layer (11); Step 6. Expose the gate metal fabrication region of the n-channel device above the doped gate control layer (9) by dielectric etching; Step 7. By evaporation and stripping, gate metal layer a (12-a) and gate metal layer b (12-b) are prepared in the gate metal fabrication region of the n-channel device and the gate control region of the p-channel device, respectively, to form the gate of the n-channel and p-channel devices; Step 8. Expose the metal electrodes of ohmic contact electrode a (10-a), ohmic contact electrode b (10-b), and ohmic contact electrode c (10-c) through an etching process.

2. A structure for improving the integration density of GaNn-channel and p-channel devices prepared by the method of claim 1, characterized in that: The structure for improving the integration of GaN n-channel and p-channel devices includes a substrate (1), a high-resistivity buffer layer (2) formed on the substrate (1), a GaN channel layer (3) formed on the high-resistivity buffer layer (2), and a barrier layer (4) formed on the GaN channel layer (3). An ohmic contact electrode a (10-a), a doped gate control layer (9), an ohmic contact electrode b (10-b), and a current transport transition layer (5) are sequentially provided on the barrier layer (4). A channel current extension layer (6), a current blocking layer (7), and a p-type ohmic contact layer (8) are sequentially provided on the current transport transition layer (5). An ohmic contact electrode c (10-c) is provided on the p-type ohmic contact layer (8). Then, a dielectric layer (11) is provided on the entire structure. A gate metal layer a (12-a) is provided on the doped gate control layer (9), and a gate metal layer b (12-b) is provided on the dielectric layer (11) of the p-channel gate control region.

3. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: An n-channel carrier transport structure is formed by a barrier layer (4) and a GaN channel layer (3). The source and drain electrodes of the n-channel device are formed by ohmic contact electrodes a (10-a) and b (10-b). The gate control structure of the n-channel device is formed by a gate metal layer a (12-a) and a doped gate control layer (9). The source and drain electrodes of the p-channel device are formed by ohmic contact electrodes b (10-b) and c (10-c). The gate control of the p-channel device is achieved by the gate metal layer b (12-b) through the dielectric layer (11). The p-channel carrier transport structure is formed by a current transport transition layer (5), a channel current extension layer (6), a current blocking layer (7), and a p-type ohmic contact layer (8) arranged from bottom to top.

4. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The substrate (1) and the GaN channel layer (3) are separated by a high-resistivity buffer layer (2). The substrate (1) is a substrate for realizing the epitaxy of GaN material, specifically one of doped or undoped silicon, silicon carbide, gallium nitride, aluminum nitride and gallium oxide.

5. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The high-resistivity buffer layer (2) is a carbon-doped AlGaN, a carbon-doped GaN, a composite material of carbon-doped AlGaN and GaN, an iron-doped AlGaN, an iron-doped GaN, a composite material of iron-doped AlGaN and GaN, a magnesium-doped AlGaN, a magnesium-doped GaN, or a magnesium-doped AlGaN and GaN composite material.

6. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The GaN channel layer (3) is an n-type lightly doped GaN material with a doping concentration of 1E16cm⁻¹. -3 -1E17cm -3 .

7. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The current transport transition layer (5) is a GaN material with gradually varying doping concentration. The doping concentration at the interface between the current transport transition layer (5) and the channel current extension layer (6) is the same as that of the channel current extension layer (6), and the doping concentration gradually decreases towards the interface between the current transport transition layer (5) and the barrier layer (4).

8. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The channel current extension layer (6) is made of p-type doped GaN material with a hole concentration of 1E15 cm⁻¹. -3 -3E17m -3 The current blocking layer (7) is made of carbon-doped AlGaN material with a thickness of 100-200 nm, and the p-type ohmic contact layer (8) is made of p-type doped GaN material with a hole concentration of 3E17 cm⁻¹. -3 -4E19cm -3 .

9. The structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The doped gate control layer (9) is a p-type GaN or AlGaN doped gate control layer; the hole concentration in the doped gate control layer (9) is 1E17cm. -3 -7E18cm -3 .

10. A structure for improving the integration density of GaNn-channel and p-channel devices according to claim 2, characterized in that: The ohmic contact electrode (10-a) and the ohmic contact electrode (10-b) are Ti monolayer, Al monolayer, Ti multilayer metal, Al multilayer metal, Ti nitride, Al nitride or Ti / Al multilayer metal.

Images