A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor, so as to make the channel regions in the N-type ring gate transistor and the P-type ring gate transistor which are distributed along the thickness direction of the semiconductor substrate have different electrical conduction characteristics, and improve the yield of the semiconductor device. The semiconductor device comprises a first semiconductor substrate, an N-type ring gate transistor, a P-type ring gate transistor, a bonding isolation layer and an insulating layer. The bonding isolation layer is arranged between the first gate stack structure and the second gate stack structure. In the first channel region and the second channel region, one located above is bonded and interconnected above the other located below through the bonding isolation layer. The insulating layer is arranged between the first source / drain region included in the N-type ring gate transistor and the second source / drain region included in the P-type ring gate transistor. The insulating layer and the bonding isolation layer are adjacent. The materials and / or crystal orientations of the first channel region and the second channel region are different, and the first channel region and the second channel region are self-aligned.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Three-dimensional complementary field-effect transistors (CFETs) consist of vertically stacked N-type and P-type transistors to improve the integration density of CMOS devices. Furthermore, gate-around transistors (GOTMTs) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when both the N-type and P-type transistors in a CFET are GOTMTs, the operating performance of the CMOS device can be improved.

[0003] In some applications, the N-type gate-around transistors and P-type gate-around transistors in CFET devices need to have different channel conduction characteristics to meet the corresponding operating requirements. However, existing manufacturing methods are difficult to implement in the production of such CFET devices, resulting in poor actual performance of existing CFET devices, including both N-type and P-type gate-around transistors, and significant integration difficulties. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which enables the channel regions of N-type gate ring transistors and P-type gate ring transistors that are spaced apart along the thickness direction of the semiconductor substrate to have different electrical conduction characteristics, thereby improving the applicability of the semiconductor device in different application scenarios and increasing the yield of the semiconductor device.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: a first semiconductor substrate, an N-type gate-around transistor (GMT-AOT), a P-type GMT-AOT, a bonding isolation layer, and an insulating layer. The N-type GMT-AOT and the P-type GMT-AOT are disposed spaced apart on the first semiconductor substrate along its thickness direction. The bonding isolation layer is disposed between a first gate stack structure included in the N-type GMT-AOT and a second gate stack structure included in the P-type GMT-AOT. In the first channel region of the N-type GMT-AOT and the second channel region of the P-type GMT-AOT, the upper channel region is bonded and interconnected to the lower channel region via the bonding isolation layer. The insulating layer is disposed between a first source / drain region included in the N-type GMT-AOT and a second source / drain region included in the P-type GMT-AOT. The insulating layer and the bonding isolation layer are adjacent. The first channel region and the second channel region have different materials and / or crystal orientations, and the first channel region and the second channel region are self-aligned.

[0006] In the semiconductor device provided by the present invention, N-type gate-ring transistors and P-type gate-ring transistors are distributed at intervals along the thickness direction of the semiconductor substrate. In this case, the N-type gate-ring transistors and P-type gate-ring transistors can form a three-dimensional stacked complementary transistor device, which is beneficial for improving the integration density of the semiconductor device and for achieving miniaturization of the semiconductor device. Furthermore, since different semiconductor materials have different carrier conduction characteristics, when the materials of the first channel region included in the N-type gate-ring transistor and the second channel region included in the P-type gate-ring transistor are different, it is beneficial for the first channel region and the second channel region to have different electrical conduction characteristics. Channel regions with different crystal orientations also have different carrier conduction characteristics (e.g., the

[100] crystal orientation channel region is beneficial for electron transport, while the

[110] crystal orientation channel region is beneficial for hole transport). Therefore, when the crystal orientations of the first channel region included in the N-type gate-ring transistor and the second channel region included in the P-type gate-ring transistor are different, it is beneficial for the first channel region and the second channel region to have different electrical conduction characteristics. Therefore, the materials and / or crystal orientations of the first and second channel regions can be set according to different application scenarios, so that both N-type gate ring transistors and P-type gate ring transistors have driving performance that meets the corresponding working requirements, thereby improving the applicability of semiconductor devices in different application scenarios.

[0007] Furthermore, the aforementioned bonding isolation layer, disposed between the first gate stack structure of the N-type gate-around transistor and the second gate stack structure of the P-type gate-around transistor, not only reduces leakage current and interference between the N-type and P-type gate-around transistors, but also ensures that the upper channel region of the N-type gate-around transistor is bonded and interconnected with the lower channel region via the bonding isolation layer. Simultaneously, an insulating layer is disposed between the first source / drain region of the N-type gate-around transistor and the second source / drain region of the P-type gate-around transistor. Based on this, in the actual manufacturing process, in the first stack used to manufacture the first channel region and the second stack used to manufacture the second channel region, the upper layer is bonded and interconnected with the lower layer via the bonding isolation layer before the first and second source / drain regions are formed. At this point, the lower transistor has not yet been formed, and neither the N-type nor the P-type gate-around transistor is subject to the limitations of low-temperature processes, thus improving the yield of both types of transistors. After bonding to form a fin-like structure, the first and second source / drain regions, along with an insulating layer between them, can be formed separately through source / drain etching. This not only allows for different materials and / or crystal orientations of the first and second channel regions through bonding, but also solves the problem in existing sequential integration methods where the upper N-type gate ring transistor is limited by low-temperature processes, resulting in poor performance. This improves the operating performance and yield of semiconductor devices. Furthermore, the self-alignment of the first and second channel regions increases integration density and reduces the difficulty of subsequent interconnect processes.

[0008] In one example, the carrier mobility of the material in the second channel region is greater than that of the material in the first channel region.

[0009] In one example, the crystal orientation of the first channel region is

[100] and the crystal orientation of the second channel region is

[110] .

[0010] In one example, the material of the first or second channel region includes silicon, silicon germanium, or germanium. The germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

[0011] In one example, the aforementioned bonding isolation layer includes at least two bonding isolation sublayers stacked along the thickness direction of the first semiconductor substrate, wherein the material of at least one bonding isolation sublayer is different from the material of the other bonding isolation sublayers.

[0012] In one example, the thickness of the aforementioned bonded isolation layer is greater than or equal to 20 nm and less than or equal to 70 nm.

[0013] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: first, providing a first semiconductor substrate; next, forming an N-type gate-around transistor, a P-type gate-around transistor, a bonding isolation layer, and an insulating layer on the first semiconductor substrate. The N-type gate-around transistor and the P-type gate-around transistor are spaced apart on the first semiconductor substrate along its thickness direction. The bonding isolation layer is disposed between a first gate stack structure included in the N-type gate-around transistor and a second gate stack structure included in the P-type gate-around transistor. In the first channel region included in the N-type gate-around transistor and the second channel region included in the P-type gate-around transistor, the upper one is bonded and interconnected above the lower one through the bonding isolation layer. The insulating layer is disposed between a first source / drain region included in the N-type gate-around transistor and a second source / drain region included in the P-type gate-around transistor. The insulating layer and the bonding isolation layer are adjacent. The first channel region and the second channel region are made of different materials and / or have different crystal orientations, and the first channel region and the second channel region are self-aligned.

[0014] In one example, forming an N-type gate-around transistor, a P-type gate-around transistor, a bonding isolation layer, and an insulating layer on a first semiconductor substrate includes: forming a fin structure on the first semiconductor substrate. Along the thickness direction of the first semiconductor substrate, the fin structure includes a first stack and a second stack spaced apart, and a bonding isolation layer located between the first stack and the second stack. The first stack includes an alternately stacked first sacrificial layer and a first channel layer, wherein the top and bottom layers in the first stack are both first sacrificial layers. The second stack includes an alternately stacked second sacrificial layer and a second channel layer, wherein the top and bottom layers in the second stack are both second sacrificial layers. The materials of the first and second sacrificial layers are different from the materials of the first and second channel layers, respectively. Next, a first mask structure is formed across the fin structure. Next, the portion of the fin structure exposed outside the first mask structure is removed. Next, first source / drain regions are formed on both sides of the remaining first stack along the length direction of the fin structure. Next, an insulating layer is formed. Next, second source / drain regions are formed on both sides of the remaining second stack along the length direction of the fin structure. Next, at least a portion of the first mask structure is removed; and the remaining first sacrificial layer and the remaining second sacrificial layer are removed, so that the remaining first channel layer forms the first channel region and the remaining second channel layer forms the second channel region. Next, a first gate stack structure is formed around the outer periphery of the first channel region, and a second gate stack structure is formed around the outer periphery of the second channel region.

[0015] In one example, forming a fin structure on a first semiconductor substrate includes: providing a second semiconductor substrate. Next, on one of the first and second semiconductor substrates, a first stack and a first bonding interconnect layer are formed integrally; and on the other of the first and second semiconductor substrates, a second stack and a second bonding interconnect layer are formed integrally. A bonding isolation layer includes the first and second bonding interconnect layers. Next, the first and second stacks are bonded together via the first and second bonding interconnect layers. Next, the second semiconductor substrate is removed. Next, a second mask structure is formed on a portion of the upper portion of the first and second stacks. Next, under the protection of the second mask structure, at least the first stack, the second stack, and the bonding isolation layer are selectively etched to form a fin structure on the semiconductor substrate.

[0016] In one example, the materials of the first and second sacrificial layers are the same.

[0017] In one example, the materials of the first sacrificial layer and / or the second sacrificial layer include germanium silicon or germanium, the material of the second channel layer includes germanium silicon, and the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is at least 20% higher than the germanium content in the material of the second channel layer.

[0018] In one example, the second mask structure includes a first mask layer, a second mask layer, and a third mask layer disposed sequentially along the thickness direction of the semiconductor substrate.

[0019] The material of the third mask layer is different from the material of the upper one of the first and second stacks, the material of the first mask layer is different from the material of the lower one of the first and second stacks, and the material of the second mask layer is different from the material of the bonding isolation layer.

[0020] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0023] Figure 2A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0024] Figure 3 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 3 and indication Figure 4 ;

[0025] Figure 4 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 5 and indication Figure 6 ;

[0026] Figure 5 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 7 and indication Figure 8 ;

[0027] Figure 6 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 9 and indication Figure 10 ;

[0028] Figure 7 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 10 One and illustration Figure 10 two;

[0029] Figure 8 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 10 Three and diagram Figure 10 Four;

[0030] Figure 9 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 10 Five and diagram Figure 10 six;

[0031] Figure 10 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 10 Seven and symbol Figure 10 eight;

[0032] Figure 11Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 10 Nine Harmony Symbol Figure 2 ten;

[0033] Figure 12 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 2 11 and symbol Figure 2 twelve;

[0034] Figure 13 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 2 Thirteen and illustration Figure 2 fourteen;

[0035] Figure 14 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 2 Fifteen and indication Figure 2 sixteen;

[0036] Figure 15 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 2 Seventeen and indication Figure 2 eighteen;

[0037] Figure 16 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 2 Nineteen and indication Figure 3 ten;

[0038] Figure 17 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiments of the present invention during the manufacturing process. Figure 3 11 and symbol Figure 3 twelve.

[0039] Reference numerals: 11 is the first semiconductor substrate, 12 is an N-type gate-around transistor, 13 is a P-type gate-around transistor, 14 is the first gate stack structure, 15 is the second gate stack structure, 16 is a bonding isolation layer, 17 is the first channel region, 18 is the second channel region, 19 is the first source / drain region, 20 is the second source / drain region, 21 is an insulating layer, 22 is a bonding isolation sublayer, 23 is a shallow trench isolation structure, 24 is the gate sidewall, 25 is the inner sidewall, 26 is... Interlayer dielectric layer, 27 is a fin structure, 28 is a first stack, 29 is a second stack, 30 is a first sacrificial layer, 31 is a first channel layer, 32 is a second sacrificial layer, 33 is a second channel layer, 34 is a first mask structure, 35 is a sacrificial gate, 36 is a second semiconductor substrate, 37 is a first bonding interconnect layer, 38 is a second bonding interconnect layer, 39 is a second mask structure, 40 is a first mask layer, 41 is a second mask layer, and 42 is a third mask layer. Detailed Implementation

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0041] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0045] Three-dimensional complementary field-effect transistors (CFETs) consist of vertically stacked N-type and P-type transistors to improve the integration density of CMOS devices. Furthermore, gate-around transistors (GOTMTs) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when both the N-type and P-type transistors in a CFET are GOTMTs, the operating performance of the CMOS device can be improved.

[0046] In some applications, the N-type and P-type gate-around transistors in a CFET device need to have different channel conduction characteristics to meet the corresponding operating requirements. For example, since the channel carriers of the N-type gate-around transistor in a CFET device are electrons and the channel carriers of the P-type gate-around transistor are holes, when a gate-around transistor with a

[100] oriented channel is applied to the CFET device, the gate-around transistor only improves the electron mobility of the N-type gate-around transistor, but not the hole mobility of the P-type gate-around transistor, resulting in poor performance of the CFET device with the aforementioned gate-around transistor structure. In this case, the crystal orientation of the channel region of the P-type gate-around transistor can be set to

[110] , while the crystal orientation of the channel region of the N-type gate-around transistor remains

[100] , so that the CFET device has higher operating performance. For example, the P-type gate ring transistor can have higher operating performance by increasing the carrier mobility of the channel region material (e.g., using germanium-silicon or germanium materials with a higher germanium content than those used in the N-type gate ring transistor). Meanwhile, the N-type gate ring transistor still uses conventional silicon or germanium-silicon materials with lower germanium content to manufacture its channel region.

[0047] However, existing manufacturing methods struggle to produce the aforementioned CFET devices, resulting in poor actual performance and significant integration difficulties for existing CFET devices, including N-type and P-type gate-around transistors. Specifically, existing three-dimensional stacked complementary transistor manufacturing methods mainly employ the following two integration schemes:

[0048] The first method involves fabricating a three-dimensional stacked complementary transistor using a monolithic approach. Specifically, taking an example where both the N-type and P-type transistors are gate-around transistors, with the P-type transistor positioned above the N-type transistor, the process of fabricating a three-dimensional stacked complementary transistor using existing methods is explained: First, a fin structure is formed on a semiconductor substrate. This fin structure comprises at least two stacked layers. Each stack includes a sacrificial layer and a channel layer located on the sacrificial layer, and both the sacrificial layer and the channel layer are made of semiconductor materials. Next, a sacrificial gate and sidewalls are formed across a portion of the fin structure; using the sacrificial gate and sidewalls as a mask, the fin structure is selectively etched to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for fabricating the source and drain regions of the N-type transistor is formed on the semiconductor substrate. At this point, since the remaining portions of the sacrificial layers and channel layers corresponding to the N-type and P-type transistors are exposed after etching, these remaining portions can serve as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the N-type transistor, but also on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the P-type transistor. Next, the first semiconductor material located on both sides of the remaining portions of the sacrificial layers and channel layers corresponding to the P-type transistor needs to be removed, and the remaining portion of the first semiconductor material forms the source and drain regions included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the source and drain regions included in the N-type transistor away from the substrate surface; and the source and drain regions of the P-type transistor are formed on the epitaxial isolation layer using an epitaxial growth process. Finally, the sacrificial gate and the portion of the sacrificial layer located within the gate formation region are removed; and a gate stack structure surrounding the outer periphery of the channel region is formed to obtain a three-dimensional stacked complementary transistor.

[0049] The second method involves fabricating a three-dimensional stacked complementary transistor using a sequential approach. This method involves forming the bottom layer transistor using conventional semiconductor device manufacturing processes. After forming the corresponding contact electrodes of the bottom layer transistor, a semiconductor layer is deposited on top of the bottom layer transistor using wafer-to-wafer bonding technology and a wafer transfer method. Then, the top layer transistor is integrated based on this semiconductor layer, connecting the top and bottom gates to obtain the three-dimensional stacked complementary transistor.

[0050] As can be seen from the manufacturing process of the first method described above, the fin structure includes at least two stacked layers that are formed on the same semiconductor substrate through epitaxy and other processes. When the channel regions of the N-type gate-around transistor and the P-type gate-around transistor are made of different materials, the above-mentioned at least two stacked layers include semiconductor layers made of at least three semiconductor materials. However, there are lattice differences between semiconductor layers made of different materials. Furthermore, due to the limitation of the critical thickness of epitaxy, the selection of materials for the high-mobility channel region in the first method is limited, and the formation of channels with other crystal orientations is more difficult. In the second method of manufacturing three-dimensional stacked complementary transistors, the channel regions of the N-type gate-around transistor and the P-type gate-around transistor are not self-aligned, which makes subsequent processes more difficult. Moreover, the upper one of the N-type gate-around transistor and the P-type gate-around transistor needs to be manufactured at a low temperature, otherwise it will affect the yield of the lower one. Low-temperature processes are not conducive to improving the working performance of three-dimensional stacked complementary transistors.

[0051] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, the upper channel region of the N-type gate-around transistor (N-GMT) and the lower channel region of the P-type gate-around transistor (P-GMT) are bonded and interconnected via a bonding isolation layer. This not only allows for different materials and / or crystal orientations of the first and second channel regions through bonding, but also solves the problem in existing sequential integration methods where the upper N-GMT and P-GMT transistors suffer from poor performance due to low-temperature processing limitations, thus improving the operating performance and yield of the semiconductor device. Furthermore, the self-alignment of the first and second channel regions improves integration density and reduces the difficulty of subsequent interconnection processes.

[0052] Specifically, the first aspect, such as Figure 17As shown in sections (1) and (2) of this embodiment, the semiconductor device provided by this invention includes: a first semiconductor substrate 11, an N-type gate-around transistor 12, a P-type gate-around transistor 13, a bonding isolation layer 16, and an insulating layer 21. Along the thickness direction of the first semiconductor substrate 11, the N-type gate-around transistor 12 and the P-type gate-around transistor 13 are disposed at intervals on the first semiconductor substrate 11. The bonding isolation layer 16 is disposed between the first gate stack structure 14 included in the N-type gate-around transistor 12 and the second gate stack structure 15 included in the P-type gate-around transistor 13. In the first channel region 17 included in the N-type gate-around transistor 12 and the second channel region 18 included in the P-type gate-around transistor 13, the upper one is bonded and interconnected above the lower one through the bonding isolation layer 16. The insulating layer 21 is disposed between the first source / drain region 19 included in the N-type gate-around transistor 12 and the second source / drain region 20 included in the P-type gate-around transistor 13. The insulating layer 21 and the bonding isolation layer 16 are adjacent to each other. The first channel region 17 and the second channel region 18 are made of different materials and / or have different crystal orientations, and the first channel region 17 and the second channel region 18 are self-aligned.

[0053] When the above technical solution is adopted, such as Figure 17 As shown in sections (1) and (2) of the present invention, in the semiconductor device provided by the embodiments of the present invention, the N-type gate ring transistor 12 and the P-type gate ring transistor 13 are distributed at intervals along the thickness direction of the semiconductor substrate. At this time, the N-type gate ring transistor 12 and the P-type gate ring transistor 13 can form a three-dimensional stacked complementary transistor device, which is beneficial to improve the integration of the semiconductor device and to realize the miniaturization of the semiconductor device. In addition, since different semiconductor materials have different carrier conduction characteristics, when the materials of the first channel region 17 included in the N-type gate ring transistor 12 and the second channel region 18 included in the P-type gate ring transistor 13 are different, it is beneficial to make the first channel region 17 and the second channel region 18 have different electrical conduction characteristics. Different crystal orientations of the channel regions also have different carrier conduction characteristics (e.g., the

[100] crystal orientation channel region is conducive to electron transport, while the

[110] crystal orientation channel region is conducive to hole transport). Therefore, when the crystal orientations of the first channel region 17 of the N-type gate ring transistor 12 and the second channel region 18 of the P-type gate ring transistor 13 are different, it is beneficial to make the first channel region 17 and the second channel region 18 have different electrical conduction characteristics. It can be seen that the materials and / or crystal orientations of the first channel region 17 and the second channel region 18 can be set according to different application scenarios, so that both the N-type gate ring transistor 12 and the P-type gate ring transistor 13 have driving performance that meets the corresponding working requirements, thereby improving the applicability of semiconductor devices in different application scenarios.

[0054] In addition, such as Figures 1 to 17As shown in sections (1) and (2), the bonding isolation layer 16 is disposed between the first gate stack structure 14 of the N-type gate ring transistor 12 and the second gate stack structure 15 of the P-type gate ring transistor 13, which not only reduces leakage current and interference between the N-type gate ring transistor 12 and the P-type gate ring transistor 13, but also ensures that the upper channel region 17 of the N-type gate ring transistor 12 and the second channel region 18 of the P-type gate ring transistor 13 are bonded and interconnected above the lower channel region through the bonding isolation layer 16. Meanwhile, the insulating layer 21 is disposed between the first source / drain region 19 of the N-type gate ring transistor 12 and the second source / drain region 20 of the P-type gate ring transistor 13. Based on this, in the actual manufacturing process, in the first stack 28 used to manufacture the first channel region 17 and the second stack 29 used to manufacture the second channel region 18, the upper one is bonded and interconnected with the lower one through the bonding isolation layer 16 before the first source / drain region 19 and the second source / drain region 20 are formed. At this time, the lower layer transistor has not yet been formed, and the N-type gate ring transistor 12 and the P-type gate ring transistor 13 are not subject to the limitations of low temperature process, which is beneficial to improving the yield of the N-type gate ring transistor 12 and the P-type gate ring transistor 13. After bonding and forming the fin structure 27, the first source / drain region 19 and the second source / drain region 20, as well as the insulating layer 21 located between them, can be formed by source / drain etching. This not only enables bonding to achieve different materials and / or crystal orientations for the first channel region 17 and the second channel region 18, but also solves the problem in existing sequential integration methods where the upper N-type gate ring transistor 12 and P-type gate ring transistor 13 suffer from poor performance due to low-temperature process limitations, thus improving the operating performance and yield of semiconductor devices. Furthermore, the self-alignment of the first channel region 17 and the second channel region 18 not only improves integration density but also reduces the difficulty of subsequent interconnection processes.

[0055] In practical applications, the embodiments of the present invention do not specifically limit the material and structure of the semiconductor substrate, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. For example, the semiconductor substrate can be any semiconductor material such as a silicon substrate, a silicon-on-insulator substrate, a germanium-silicon substrate, or a germanium substrate.

[0056] For N-type gate-around transistors and P-type gate-around transistors, in terms of their formation location, such as Figure 17 As shown in part (1), along the thickness direction of the semiconductor substrate, the P-type gate ring transistor 13 can be disposed above the N-type gate ring transistor 12; or, as shown in part (1), the P-type gate ring transistor 13 can be disposed above the N-type gate ring transistor 12; or, as shown in part (2), the P-type gate ring transistor 13 can be disposed above the N-type gate ring transistor 12. Figure 17 As shown in part (2), the N-type gate ring transistor 12 can also be disposed above the P-type gate ring transistor 13.

[0057] It is understandable that the spacing between the N-type and P-type gate ring transistors along the thickness direction of the semiconductor substrate affects the thickness of the bonding isolation layer and the insulating layer. The thickness of the bonding isolation layer affects its ability to improve leakage and interference between the first and second gate stack structures, while the thickness of the insulating layer affects the isolation effect between the first and second source / drain regions. Therefore, the spacing between the N-type and P-type gate ring transistors can be determined based on the leakage and bonding requirements of the actual application scenario; no specific limitations are made here.

[0058] For example, along the thickness direction of the semiconductor substrate, the spacing between the N-type gate-around transistor and the P-type gate-around transistor can be greater than or equal to 20 nm and less than or equal to 70 nm. In this case, the thickness of the aforementioned bonding isolation layer and / or insulating layer can also be greater than or equal to 20 nm and less than or equal to 70 nm. In this scenario, while ensuring that the bonding isolation layer and insulating layer have a large thickness to reduce the risk of leakage, it also prevents the bonding between the N-type gate-around transistor and the P-type gate-around transistor from being affected by the large thickness of the bonding interconnect layer, ensuring high structural reliability of the semiconductor device.

[0059] From a structural perspective, such as Figure 17 As shown in sections (1) and (2), the aforementioned N-type gate-ring transistor 12 includes a first source / drain region 19, a first channel region 17, and a first gate stack structure 14. The first channel region 17 is located between the first source / drain regions 19, and both ends of the first channel region 17 along its length are in contact with the first source / drain regions 19, respectively. Furthermore, the first channel region 17 may include only one nanostructure, or it may include multiple nanostructures spaced apart along the thickness direction of the semiconductor substrate. The first gate stack structure 14 surrounds the outer periphery of each nanostructure included in the first channel region 17. Specifically, the first gate stack structure 14 may be formed on a gate dielectric layer around the outer periphery of the first channel region 17, and a gate located on the gate dielectric layer.

[0060] like Figure 17 As shown in sections (1) and (2), the aforementioned P-type gate-ring transistor 13 includes a second source / drain region 20, a second channel region 18, and a second gate stack structure 15. The second channel region 18 is located between the second source / drain regions 20, and both ends of the second channel region 18 along its length are in contact with the second source / drain regions 20, respectively. Furthermore, the second channel region 18 may include only one nanostructure, or it may include multiple nanostructures spaced apart along the thickness direction of the semiconductor substrate. The second gate stack structure 15 surrounds the outer periphery of each nanostructure included in the second channel region 18. Specifically, the second gate stack structure 15 may form a gate dielectric layer on the outer periphery of the second channel region 18, and a gate located on the gate dielectric layer.

[0061] In terms of materials, the materials of the first source / drain region, the first channel region, the second source / drain region, and the second channel region can include any semiconductor material such as silicon, silicon germanium, or germanium. The materials of the first channel region and the second channel region can be the same or different. The materials of the first channel region and the second channel region can be determined based on their crystal orientations. Specifically, when the crystal orientations of the first channel region and the second channel region are the same, their materials are different. Conversely, when the crystal orientations of the first channel region and the second channel region are different, their materials can be the same or different.

[0062] Specifically, when the materials of the first channel region and the second channel region are different, the carrier mobility of the material in the second channel region can be greater than that of the material in the first channel region. In this case, the driving performance of the P-type gate-around transistor can be improved, thereby enhancing the operating performance of the semiconductor device. The specific types of materials used in the first and second channel regions can be selected according to actual requirements.

[0063] For example, the material in the first or second channel region may include silicon, silicon germanium, or germanium. The germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region. The difference in germanium content between the materials of the first and second channel regions can be determined based on actual needs and the actual manufacturing process, and is not specifically limited here. For example, the germanium content in the material of the second channel region may be at least 10% higher than the germanium content in the material of the first channel region.

[0064] Of course, when the materials of the first channel region and the second channel region are different, the carrier mobility of the material in the second channel region can also be less than or equal to the carrier mobility of the material in the first channel region.

[0065] Furthermore, when the crystal orientations of the first channel region and the second channel region are different, the crystal orientation of the first channel region can be

[100] and the crystal orientation of the second channel region can be

[110] . In this case, since the

[100] crystal orientation of the channel region is conducive to electron transport, while the

[110] crystal orientation of the channel region is conducive to hole transport, setting the crystal orientation of the first channel region of the N-type gate ring transistor to

[100] facilitates electron transport and ensures that the N-type gate ring transistor has high driving performance. Similarly, setting the crystal orientation of the second channel region of the P-type gate ring transistor to

[110] facilitates hole transport and ensures that the P-type gate ring transistor has high driving performance.

[0066] Of course, if the crystal orientations of the first channel region and the second channel region are different, the first channel region can also be any crystal orientation other than

[100] , and the crystal orientation of the second channel region can also be any crystal orientation other than

[110] .

[0067] For the aforementioned bonding isolation layer, the bonding isolation layer is disposed between the first gate stack structure included in the N-type ring gate transistor and the second gate stack structure included in the P-type ring gate transistor. Furthermore, as... Figure 17 As shown in sections (1) and (2), in the first channel region 17 of the N-type gate ring transistor 12 and the second channel region 18 of the P-type gate ring transistor 13, the upper one is bonded and interconnected above the lower one by a bonding isolation layer 16.

[0068] Specifically, the bonding isolation layer can be a single-layer structure formed by a single insulating material. For example, the material of the bonding isolation layer can be SiO2, SiCO, SiCON, Y2O3, or HfO2, etc.

[0069] Or, such as Figure 17 As shown in sections (1) and (2), the bonding isolation layer 16 may also include at least two bonding isolation sub-layers 22 stacked along the thickness direction of the first semiconductor substrate 11, wherein the material of at least one bonding isolation sub-layer 22 is different from the material of the other bonding isolation sub-layers 22. Specifically, the number of bonding isolation sub-layers 22 included in the bonding isolation layer 16, the types of materials of different bonding isolation sub-layers 22 in the bonding isolation layer 16, and the distribution of bonding isolation sub-layers 22 with different materials can be set according to actual needs and are not specifically limited here.

[0070] The insulating layer described above is disposed between the first source / drain region of the N-type gate-ring transistor and the second source / drain region of the P-type gate-ring transistor, serving to isolate the first and second source / drain regions. This insulating layer is adjacent to the bonding isolation layer, meaning the sidewalls of the insulating layer and the bonding isolation layer are in contact. The material of the insulating layer can include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the insulating layer can be referred to the previous text and will not be repeated here.

[0071] In some cases, such as Figure 8 Parts (1) and (2) in the text, and Figure 17 As shown in sections (1) and (2) above, the semiconductor device may further include a shallow trench isolation structure 23. The shallow trench isolation structure 23 is disposed on the first semiconductor substrate 11 and is used to isolate different active regions on the first semiconductor substrate 11 to prevent leakage.

[0072] In some cases, such as Figure 17As shown in parts (1) and (2) above, the semiconductor device may further include a gate sidewall 24, which is provided at least on both sides of the first gate stack structure 14 and the second gate stack structure 15 along its own length direction, so as to isolate the first gate stack structure 14 and the second gate stack structure 15 from other adjacent conductive structures to prevent leakage or interference.

[0073] In some cases, such as Figure 17 As shown in sections (1) and (2) above, the N-type gate ring transistor 12 and / or the P-type gate ring transistor 13 may further include an inner sidewall 25. This inner sidewall 25 is disposed between the first gate stack structure 14 and the first source / drain region 19, and / or, the inner sidewall 25 is disposed between the second gate stack structure 15 and the second source / drain region 20, to define the length of the first gate stack structure 14 and / or the second gate stack structure 15, thereby improving the yield of the semiconductor device. It is possible that only the N-type gate ring transistor includes an inner sidewall, while the P-type gate ring transistor does not. Alternatively, it is also possible that the P-type gate ring transistor includes an inner sidewall, while the N-type gate ring transistor does not. Or, as... Figure 17 As shown in sections (1) and (2), both the N-type gate-around transistor 12 and the P-type gate-around transistor 13 include the aforementioned inner sidewall 25. In this case, during the actual manufacturing process, the inner sidewall 25 included in the N-type gate-around transistor 12 and the P-type gate-around transistor 13 can be integrally formed to improve the manufacturing efficiency of the semiconductor device and reduce the manufacturing cost of the semiconductor device. Alternatively, the inner sidewall 25 included in the N-type gate-around transistor 12 and the P-type gate-around transistor 13 can also be formed separately in different operating steps.

[0074] In some cases, such as Figure 17 As shown in sections (1) and (2), the semiconductor device may further include an interlayer dielectric layer 26 disposed on the first semiconductor substrate 11. The top of the interlayer dielectric layer 26 is flush with the top of the upper one of the first gate stack structure 14 and the second gate stack structure 15 to protect the first source / drain region 19 and the second source / drain region 20 from the effects of operations such as etching or cleaning, thereby improving the yield of the semiconductor device.

[0075] In terms of materials, the materials of the aforementioned shallow trench isolation structure, gate sidewall, inner sidewall, and interlayer dielectric layer can be set according to the actual manufacturing process and actual needs, and are not specifically limited here. For example, the materials of the shallow trench isolation structure, gate sidewall, inner sidewall, and interlayer dielectric layer may include any insulating material such as silicon oxide or silicon nitride.

[0076] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 17The illustrated cross-sectional or perspective view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0077] First, a first semiconductor substrate is provided.

[0078] Next, as Figure 17 As shown in sections (1) and (2), an N-type gate-around transistor 12, a P-type gate-around transistor 13, a bonding isolation layer 16, and an insulating layer 21 are formed on a first semiconductor substrate 11. The N-type gate-around transistor 12 and the P-type gate-around transistor 13 are spaced apart on the first semiconductor substrate 11 along its thickness direction. The bonding isolation layer 16 is disposed between the first gate stack structure 14 of the N-type gate-around transistor 12 and the second gate stack structure 15 of the P-type gate-around transistor 13. In the first channel region 17 of the N-type gate-around transistor 12 and the second channel region 18 of the P-type gate-around transistor 13, the upper one is bonded and interconnected above the lower one via the bonding isolation layer 16. The insulating layer 21 is disposed between the first source / drain region 19 of the N-type gate-around transistor 12 and the second source / drain region 20 of the P-type gate-around transistor 13. The insulating layer 21 and the bonding isolation layer 16 are adjacent to each other. The materials and / or crystal orientations of the first channel region 17 and the second channel region 18 are different, and the first channel region 17 and the second channel region 18 are self-aligned.

[0079] It is understood that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as the structure of the semiconductor device provided in the first aspect described above. Therefore, the specific structure and materials of the N-type gate ring transistor and the P-type gate ring transistor, the specific structure and materials of the bonding isolation layer, and the materials of the insulating layer in the semiconductor device formed by the manufacturing method provided in the second aspect can be referred to the above text and will not be repeated here.

[0080] For example, forming an N-type gate-around transistor, a P-type gate-around transistor, a bonding isolation layer, and an insulating layer on a first semiconductor substrate may include the following steps:

[0081] like Figure 7As shown in sections (1) and (2), a fin structure 27 is formed on a first semiconductor substrate 11. Along the thickness direction of the first semiconductor substrate 11, the fin structure 27 includes a first stack 28 and a second stack 29 disposed at intervals, and a bonding isolation layer 16 located between the first stack 28 and the second stack 29. The first stack 28 includes alternating layers of a first sacrificial layer 30 and a first channel layer 31, and the top and bottom layers in the first stack 28 are both first sacrificial layers 30. The second stack 29 includes alternating layers of a second sacrificial layer 32 and a second channel layer 33, and the top and bottom layers in the second stack 29 are both second sacrificial layers 32. The materials of the first sacrificial layer 30 and the second sacrificial layer 32 are different from the materials of the first channel layer 31 and the second channel layer 33, respectively.

[0082] Specifically, the first channel layer in the first stack is used to fabricate the nanostructures included in the first channel region, and the second channel layer in the second stack is used to fabricate the nanostructures included in the second channel region. Therefore, the positional relationship between the first and second stacks in the fin structure can be determined based on the positional relationship between the N-type gate-around transistors and the P-type gate-around transistors in the semiconductor substrate. For example, Figure 7 Part (1) of the text, and Figure 17 As shown in part (1), along the thickness direction of the semiconductor substrate, when the N-type gate ring transistor 12 is located below the P-type gate ring transistor 13, the first stack 28 in the fin structure 27 is located below the second stack 29. Figure 7 Part (2) of the text, and Figure 17 As shown in section (2), when the P-type gate ring transistor 13 is located below the N-type gate ring transistor 12, the second stack 29 in the fin structure 27 is located below the first stack 28. Furthermore, the number of layers and the material of the first channel layer 31 in the first stack 28 are the same as the number of layers and the material of the nanostructure in the first channel region 17, and the number of layers and the material of the second channel layer 33 in the second stack 29 are the same as the number of layers and the material of the nanostructure in the second channel region 18.

[0083] Regarding the aforementioned first and second sacrificial layers, their materials differ from those of the first and second channel layers, respectively. This facilitates selective etching of the first and second sacrificial layers relative to the first and second channel layers, allowing the nanostructures within the first and second channel regions to be suspended. Specifically, the materials of the first and second sacrificial layers can be the same or different. When the materials are the same, etching both layers improves the manufacturing efficiency of semiconductor devices. Furthermore, it reduces the variety of different semiconductor materials in the fin structure, mitigating the critical thickness limitations of each film layer in the first and second stacks during epitaxial growth and improving the yield of semiconductor devices.

[0084] For example, the materials of the first sacrificial layer and / or the second sacrificial layer include germanium-silicon or germanium, and the material of the second channel layer includes germanium-silicon. The germanium content in the materials of both the first and second sacrificial layers is at least 20% higher than the germanium content in the material of the second channel layer. For example, the material of the second channel layer is Si. 0.8 Ge 0.2 The material of the first sacrificial layer and / or the second sacrificial layer can be Si. 0.5 Ge 0.5 Si 0.4 Ge 0.6 Si 0.3 Ge 0.7 Si 0.2 Ge 0.8 or Si 0.1 Ge 0.9 wait.

[0085] In the actual manufacturing process, a second semiconductor substrate can be provided first. This second semiconductor substrate can be a substrate made of any semiconductor material, such as silicon, silicon germanium, or germanium. Next, as... Figure 1 and Figure 2 As shown, epitaxial growth and deposition processes can be used to form a first stacked layer 28 and a first bonding interconnect layer 37 on one of the first semiconductor substrate 11 and the second semiconductor substrate 36, respectively; as Figure 1 and Figure 2 As shown, a second stack 29, integrally formed, and a second bonding interconnect layer 38 located on the second stack 29 are formed on the other of the first semiconductor substrate 11 and the second semiconductor substrate 36. The bonding isolation layer 16 includes a first bonding interconnect layer 37 and a second bonding interconnect layer 38. Specifically, as... Figure 1 and Figure 17As shown in part (1), if the N-type gate ring transistor 12 is located below the P-type gate ring transistor 13, then a first stacked layer 28 and a first bonding interconnect layer 37 need to be formed on the first semiconductor substrate 11, and a second stacked layer 29 and a second bonding interconnect layer 38 need to be formed on the second semiconductor substrate 36. Figure 2 and Figure 17 As shown in part (2), if the P-type gate ring transistor 13 is located below the N-type gate ring transistor 12, a second stack 29 and a second bonding interconnect layer 38 need to be formed on the first semiconductor substrate 11, and a first stack 28 and a first bonding interconnect layer 37 need to be formed on the second semiconductor substrate 36. The structure and material of the first bonding interconnect layer 37 and the second bonding interconnect layer 38 can be determined with reference to the structure and material of the bonding isolation layer 16 described above. For example, when the bonding isolation layer 16 is a single-layer structure, the materials of the first bonding interconnect layer 37 and the second bonding interconnect layer 38 are the same. For another example, when the bonding isolation layer includes two bonding isolation sub-layers 22 with different materials, the first bonding interconnect layer 37 and the second bonding interconnect layer 38 can correspond to the corresponding bonding isolation sub-layers 22 respectively. Next, as Figure 3 As shown in sections (1) and (2), a bonding process is used to bond the first stack 28 and the second stack 29 together through the first bonding interconnect layer 37 and the second bonding interconnect layer 38. Specifically, the specific process parameters of this bonding process can be adjusted according to actual needs. Optionally, a low-temperature bonding process can be used to achieve the bonding interconnection of the first bonding interconnect layer 37 and the second bonding interconnect layer 38. Next, as... Figure 4 As shown in sections (1) and (2), the second semiconductor substrate can be removed using processes such as dry etching and / or wet etching. Specifically, the removal of the second semiconductor substrate can be achieved using only a single process (e.g., using only chemical mechanical polishing, dry etching, or wet etching). Alternatively, the thickness of the second semiconductor substrate can be reduced by a certain value (e.g., 1 μm to 10 μm) using processes such as chemical mechanical polishing and / or dry etching, and then the remaining second semiconductor substrate can be removed using a wet etching process with high selectivity. This setup not only enables rapid removal of the second semiconductor substrate but also ensures high formation quality of the first stack 28 and the second stack 29, preventing any residue of the second semiconductor substrate after the operation. Next, as... Figure 5 As shown in sections (1) and (2), a second mask structure 39 can be formed on a portion of the upper portion of the first stack 28 and the second stack 29 using processes such as deposition and photolithography. This second mask structure 39 can be a single-layer structure, and the material of the second mask structure 39 has a certain etching selectivity ratio among the materials of the first stack 28, the second stack 29, and the bonding isolation layer 16. Alternatively, as... Figure 5As shown in sections (1) and (2), the second mask structure 39 includes a first mask layer 40, a second mask layer 41, and a third mask layer 42 sequentially disposed along the thickness direction of the semiconductor substrate. The material of the third mask layer 42 is different from the material of the upper layer of the first stack 28 and the second stack 29, so as to achieve selective etching of the upper layer of the first stack 28 and the second stack 29 under the protection of the third mask layer 42; the material of the first mask layer 40 is different from the material of the lower layer of the first stack 28 and the second stack 29, so as to achieve selective etching of the lower layer of the first stack 28 and the second stack 29 under the protection of the first mask layer 40; the material of the second mask layer 41 is different from the material of the bonding isolation layer 16, so as to achieve selective etching of the bonding isolation layer 16 under the protection of the second mask layer 41. For example, the first mask layer 40 and the third mask layer 42 mentioned above can be dielectric layers (such as silicon oxide or silicon nitride), while the second mask layer 41 can be a dielectric layer (such as silicon nitride or silicon oxynitride) or a semiconductor layer (such as amorphous silicon). Next, as... Figure 6 As shown in sections (1) and (2), under the protection of the second mask structure 39, dry etching or wet etching processes can be used to selectively etch at least the first stack 28, the second stack 29, and the bonding isolation layer 16 to form a fin structure 27 on the semiconductor substrate. Where the manufactured semiconductor device does not include a shallow trench isolation structure, the first stack, the second stack, and the bonding isolation layer can be selectively etched. Figure 6 As shown in parts (1) and (2), when the manufactured semiconductor device also includes a shallow trench isolation structure 23, it is necessary to selectively etch the first stack 28, the second stack 29, the bonding isolation layer 16, and a portion of the first semiconductor substrate 11 to form fins; as Figure 7 As shown in parts (1) and (2), a shallow trench isolation structure 23 is then formed on the first semiconductor substrate 11 using processes such as deposition and etching. The top of the shallow trench isolation structure 23 is less than or equal to the bottom height of the bottom layer of the first sacrificial layer 30 and the second sacrificial layer 32 located at the bottom layer. The portion of the fin exposed outside the shallow trench isolation structure 23 is a fin structure 27.

[0086] Next, as Figure 8 As shown in parts (1) and (2), a first mask structure 34 spanning the fin structure 27 can be formed by processes such as deposition and etching.

[0087] In practical applications, the embodiments of the present invention do not specifically limit the material and structure of the first mask structure, as long as it can be applied to the manufacturing method provided by the embodiments of the present invention. For example, the above-mentioned first mask structure may include a sacrificial gate. Another example: Figure 8As shown in parts (1) and (2) of the document, the first mask structure may include a sacrificial gate 35 and gate sidewalls 24 located at least on both sides of the sacrificial gate 35 along its own length direction.

[0088] Next, as Figure 9 As shown in parts (1) and (2), dry etching or wet etching processes can be used to remove the portion of the fin structure exposed outside the first mask structure 34.

[0089] Next, as Figure 12 As shown in part (1), epitaxial and etching processes can be used to form the first source / drain region 19 on both sides of the remaining first stack along the length direction of the fin structure.

[0090] Next, as Figure 13 As shown in part (1), the insulating layer 21 can be formed by processes such as deposition.

[0091] Next, as Figure 14 As shown in part (1), epitaxial growth and etching processes can be used to form a second source / drain region 20 on both sides of the remaining second stack along the length direction of the fin structure.

[0092] It should be noted that the preceding description, assuming the N-type gate-around transistor is located below the P-type gate-around transistor along the thickness direction of the semiconductor substrate, illustrates the process of fabricating the first source / drain region, the insulating layer, and the second source / drain region. However, this does not mean that the N-type gate-around transistor in the semiconductor device formed by the manufacturing method provided in this embodiment can only be located below the P-type gate-around transistor. In practical applications, such as... Figure 17 As shown in section (2), the N-type gate ring transistor 12 can also be located above the P-type gate ring transistor 13. In this case, as... Figures 12 to 14 As shown in part (2), a second source / drain region 20 needs to be formed first, then an insulating layer 21 needs to be formed on the second source / drain region 20, and then a first source / drain region 19 needs to be formed on the insulating layer 21.

[0093] Additionally, after removing the portion of the fin structure exposed outside the first mask structure, and before forming the first source / drain region, the insulating layer, and the second source / drain region, as... Figure 10 As shown in parts (1) and (2), wet etching or dry etching processes can be used to remove the remaining edge portions of the first sacrificial layer 30 and / or the second sacrificial layer 32 along the length of the fin structure to form a notch. Next, as... Figure 11 As shown in sections (1) and (2), the inner sidewall 25 is filled into the notch using processes such as deposition and etching. Of course, the formation of the inner sidewall 25 may not be performed.

[0094] Furthermore, after forming the first source / drain region, the insulating layer, and the second source / drain region, before performing subsequent operations, such as Figure 15 As shown in sections (1) and (2), processes such as deposition and chemical mechanical polishing can also be used to form an interlayer dielectric layer 26 on the first semiconductor substrate 11. The top of the interlayer dielectric layer 26 is flush with the top of the first mask structure 34.

[0095] Next, dry etching or wet etching processes are used to remove at least part of the first mask structure.

[0096] Specifically, whether to remove part or all of the first mask structure depends on its specific structure; no specific limitation is made here. If the first mask structure only includes the sacrificial gate, then the entire first mask structure needs to be removed. For example... Figure 16 As shown in parts (1) and (2), if the first mask structure includes a sacrificial gate 35 and a gate sidewall 24, then only the sacrificial gate 35 included in the first mask structure needs to be removed.

[0097] Next, as Figure 16 As shown in parts (1) and (2), dry etching or wet etching processes are used to remove the remaining first sacrificial layer and the remaining second sacrificial layer so that the remaining first channel layer forms the first channel region 17 and the remaining second channel layer forms the second channel region 18.

[0098] Next, as Figure 17 As shown in parts (1) and (2) above, a first gate stack structure 14 surrounding the first channel region 17 and a second gate stack structure 15 surrounding the second channel region 18 can be formed using processes such as atomic layer deposition. The specific structure and materials of the first gate stack structure 14 and the second gate stack structure 15 can be referred to above and will not be repeated here.

[0099] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0100] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0101] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: First semiconductor substrate; Along the thickness direction of the first semiconductor substrate, N-type gate ring transistors and P-type gate ring transistors are disposed at intervals on the first semiconductor substrate; A bonding isolation layer is disposed between the first gate stack structure included in the N-type gate ring transistor and the second gate stack structure included in the P-type gate ring transistor; in the first channel region included in the N-type gate ring transistor and the second channel region included in the P-type gate ring transistor, the upper one is bonded and interconnected above the lower one through the bonding isolation layer; An insulating layer is disposed between the first source / drain region of the N-type gate ring transistor and the second source / drain region of the P-type gate ring transistor; the insulating layer and the bonding isolation layer are adjacent to each other; Wherein, the first channel region and the second channel region are made of different materials and / or have different crystal orientations, and the first channel region and the second channel region are self-aligned; The first gate stack structure surrounds the outer periphery of each nanostructure in the first channel region, and the second gate stack structure surrounds the outer periphery of each nanostructure in the second channel region.

2. The semiconductor device according to claim 1, characterized in that, The carrier mobility of the material in the second channel region is greater than that of the material in the first channel region; And / or, the crystal orientation of the first channel region is [100] crystal orientation, and the crystal orientation of the second channel region is [110] crystal orientation.

3. The semiconductor device according to claim 1, characterized in that, The material of the first trench region or the second trench region includes silicon, germanium-silicon, or germanium; The germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

4. The semiconductor device according to claim 1, characterized in that, The bonding isolation layer includes at least two bonding isolation sublayers stacked along the thickness direction of the first semiconductor substrate, wherein the material of at least one of the bonding isolation sublayers is different from the material of the other bonding isolation sublayers.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the bonding isolation layer is greater than or equal to 20 nm and less than or equal to 70 nm.

6. A method for manufacturing a semiconductor device, characterized in that, include: Provide a first semiconductor substrate; An N-type gate ring transistor, a P-type gate ring transistor, a bonding isolation layer, and an insulating layer are formed on the first semiconductor substrate; The N-type gate-around transistor and the P-type gate-around transistor are disposed spaced apart on the first semiconductor substrate along the thickness direction of the first semiconductor substrate; the bonding isolation layer is disposed between the first gate stack structure of the N-type gate-around transistor and the second gate stack structure of the P-type gate-around transistor; in the first channel region of the N-type gate-around transistor and the second channel region of the P-type gate-around transistor, the upper one is bonded and interconnected above the lower one through the bonding isolation layer; the insulating layer is disposed between the first source / drain region of the N-type gate-around transistor and the second source / drain region of the P-type gate-around transistor; the insulating layer and the bonding isolation layer are adjacent; the first channel region and the second channel region are made of different materials and / or have different crystal orientations, and the first channel region and the second channel region are self-aligned; The first gate stack structure surrounds the outer periphery of each nanostructure in the first channel region, and the second gate stack structure surrounds the outer periphery of each nanostructure in the second channel region.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The process of forming an N-type gate-around transistor, a P-type gate-around transistor, a bonding isolation layer, and an insulating layer on the first semiconductor substrate includes: A fin-like structure is formed on the first semiconductor substrate; along the thickness direction of the first semiconductor substrate, the fin-like structure includes a first stack and a second stack spaced apart, and a bonding isolation layer located between the first stack and the second stack; the first stack includes an alternately stacked first sacrificial layer and a first channel layer, and the top and bottom layers in the first stack are both the first sacrificial layer; the second stack includes an alternately stacked second sacrificial layer and a second channel layer, and the top and bottom layers in the second stack are both the second sacrificial layer; the materials of the first sacrificial layer and the second sacrificial layer are different from the materials of the first channel layer and the second channel layer, respectively; A first mask structure is formed across the fin-like structure; Remove the portion of the fin structure that is exposed outside the first mask structure; Along the length of the fin-like structure, the first source / drain regions are formed on both sides of the remaining first stack; Form the insulating layer; Along the length of the fin-like structure, the second source / drain regions are formed on both sides of the remaining second stack; At least a portion of the first mask structure is removed; and the remaining first sacrificial layer and the remaining second sacrificial layer are removed, so that the remaining first channel layer forms the first channel region and the remaining second channel layer forms the second channel region. A first gate stack structure is formed around the outer periphery of the first channel region, and a second gate stack structure is formed around the outer periphery of the second channel region.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The formation of the fin-like structure on the first semiconductor substrate includes: Provide a second semiconductor substrate; On one of the first semiconductor substrate and the second semiconductor substrate, a first stacked layer and a first bonding interconnect layer are formed integrally; and on the other of the first semiconductor substrate and the second semiconductor substrate, a second stacked layer and a second bonding interconnect layer are formed integrally; the bonding isolation layer includes the first bonding interconnect layer and the second bonding interconnect layer. The first stack and the second stack are bonded together through the first bonding interconnect layer and the second bonding interconnect layer; Remove the second semiconductor substrate; A second mask structure is formed on a portion of the uppermost of the first and second stacks; Under the protection of the second mask structure, at least the first stack, the second stack, and the bonding isolation layer are selectively etched to form the fin structure on the semiconductor substrate.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The first sacrificial layer and the second sacrificial layer are made of the same material; And / or, the materials of the first sacrificial layer and / or the second sacrificial layer include germanium silicon or germanium, the material of the second channel layer includes germanium silicon, and the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is at least 20% higher than the germanium content in the material of the second channel layer.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The second mask structure includes a first mask layer, a second mask layer, and a third mask layer sequentially disposed along the thickness direction of the semiconductor substrate; The material of the third mask layer is different from the material of the upper one of the first stack and the second stack, the material of the first mask layer is different from the material of the lower one of the first stack and the second stack, and the material of the second mask layer is different from the material of the bonding isolation layer.

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