Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell. The preparation method of the solar cell comprises the following steps: providing a semiconductor substrate; forming a first passivation structure on the back surface of the semiconductor substrate, wherein the first passivation structure comprises a first tunneling layer and a first intrinsic silicon layer which are stacked in sequence; performing patterning processing on the first passivation structure to form a groove exposing the semiconductor substrate; forming a second passivation structure on the semiconductor substrate exposed from the groove, wherein the second passivation structure comprises a second tunneling layer and a second doped silicon layer which are stacked in sequence; and forming doping source slurry on the first intrinsic silicon layer, and irradiating the first intrinsic silicon layer through laser to perform doping. According to the preparation method, the preparation process of the solar cell can be simplified, and the number of carriers which can be led out by the solar cell can be increased.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Back-contact solar cells refer to solar cells with both the positive and negative electrodes on the back. After the concept of back-contact cells was proposed in 1975, it has become one of the technical routes with high conversion efficiency recognized by the solar photovoltaic industry through continuous research and development and technical improvements. Its appearance not only has no grid lines blocking the front to maximize the light-receiving area, but also has a higher appearance. In addition, this structure can be used as a platform technology combined with a variety of battery routes to highlight the uniqueness of back-contact batteries.

[0003] In the preparation process of traditional back-contact solar cells, it is usually necessary to use a graphical processing method to form an isolation groove, which is located between two regions with different doping types to avoid the problem of large-scale recombination of carriers due to short circuit. This process still has the problem of high complexity of the preparation process, and the existence of the isolation groove also affects the area that can be occupied by the doping layer, resulting in a decrease in the number of carriers derived from the solar cell. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a solar cell in order to solve the problems in the above-mentioned background technology. The method can simplify the preparation process of the solar cell and is beneficial to increase the number of carriers that can be derived from the solar cell.

[0005] According to some embodiments of the present disclosure, a method for preparing a solar cell is provided, which comprises the following steps:

[0006] providing a semiconductor substrate;

[0007] forming a first passivation structure on the back side of the semiconductor substrate, wherein the first passivation structure comprises a first tunneling layer and a first intrinsic silicon layer which are stacked in sequence;

[0008] Performing a patterning process on the first passivation structure to form a groove exposing the semiconductor substrate;

[0009] forming a second passivation structure on the semiconductor substrate exposed from the groove, wherein the second passivation structure comprises a second tunneling layer and a second doped silicon layer which are sequentially stacked; and,

[0010] A doping source slurry is formed on the first intrinsic silicon layer, and the first intrinsic silicon layer is doped by irradiating it with a laser to form a first doped silicon layer having a doped region and a non-doped region, wherein the non-doped region is arranged on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the non-doped region.

[0011] In some embodiments of the present disclosure, the step of patterning the first passivation structure includes:

[0012] forming a protective layer on the surface of the first passivation structure;

[0013] The protective layer is patterned by laser etching; and

[0014] The first passivation structure exposed from the protective layer is removed by using a first etching solution containing alkali to form the groove.

[0015] In some embodiments of the present disclosure, the step of forming the second passivation structure includes:

[0016] Placing the semiconductor substrate in a deposition chamber of a chemical vapor deposition device, and sequentially depositing a second tunneling layer and a second intrinsic silicon layer on the back side of the semiconductor substrate, wherein the second tunneling layer is extended and deposited on the sidewall and top wall of the first intrinsic silicon layer;

[0017] placing the semiconductor substrate in a diffusion chamber, introducing a reaction gas containing a doping source into the diffusion chamber, and depositing a doping precursor material on the surface of the second intrinsic silicon layer; and

[0018] Annealing is performed to diffuse the doping elements in the doping precursor material into the second intrinsic silicon layer to form the second doped silicon layer and a doped oxide layer located on the second doped silicon layer.

[0019] In some embodiments of the present disclosure, the second passivation structure and the doped oxide layer are further extended and formed on the protective layer; before forming the doping source slurry on the first intrinsic silicon layer, the following steps are also included:

[0020] Selectively removing the doped oxide layer on the protective layer by laser etching;

[0021] selectively removing the second passivation structure on the protective layer using a second etching solution containing alkali; and

[0022] The front surface of the semiconductor substrate is subjected to a texturing treatment.

[0023] In some embodiments of the present disclosure, the step of forming the first passivation structure includes:

[0024] The semiconductor substrate is placed in a deposition chamber of a chemical vapor deposition device, and a first tunneling layer and a first intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate.

[0025] In some embodiments of the present disclosure, the doping type of the semiconductor substrate is the same as the doping type of the second doped silicon layer, and the doping type of the semiconductor substrate is different from the doping type of the first doped silicon layer.

[0026] In some embodiments of the present disclosure, the doping source slurry includes a boron-containing compound, and the solid content of the doping source slurry is 20% to 55%; and / or,

[0027] The viscosity of the doping source slurry is 20 Pa·s to 50 Pa·s.

[0028] In some embodiments of the present disclosure, in the step of forming the doping source slurry, the region where the doping source slurry is located is spaced apart from the edge of the first intrinsic silicon layer; and / or,

[0029] The line width of the region where the doping source slurry is located is 400 μm to 500 μm.

[0030] In some embodiments of the present disclosure, in the step of irradiating the first intrinsic silicon layer with laser for doping, the power of the laser used is 30W-60W, and the scanning width of the laser used is 300μm-600μm.

[0031] Furthermore, the present disclosure also provides a solar cell, the solar cell comprising a semiconductor substrate, a first tunneling layer, a second tunneling layer, a first doped silicon layer, and a second doped silicon layer;

[0032] The first tunneling layer and the first doped silicon layer are sequentially stacked on the back side of the semiconductor substrate, and the second tunneling layer and the second doped silicon layer are sequentially stacked on the back side of the semiconductor substrate; the first doped silicon layer includes a doped region and a non-doped region, the non-doped region is arranged on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the non-doped region.

[0033] In the preparation method of the solar cell disclosed in the present invention, a first patterned passivation structure is first formed, and then a second passivation structure is formed on the semiconductor substrate exposed from the groove, and then a doping source slurry is formed on the first intrinsic silicon layer, and a first doped silicon layer is formed by laser irradiation. The second tunneling layer in the second passivation structure can be used to separate the first intrinsic silicon layer and the second doped silicon layer, and the laser irradiation has a strong localization. When the first intrinsic silicon layer is doped, the doping element is difficult or will not diffuse laterally into the second doped silicon layer, so that the first doped silicon layer can have a doped area and a non-doped area, and the doped area and the second doped silicon layer are separated by the non-doped area. The preparation method can ensure the insulation interval between the first doped silicon layer and the second doped silicon layer, avoid a large number of carriers. Therefore, there is no need to prepare an additional isolation groove, which can simplify the preparation process of the solar cell. In addition, since the preparation method does not require the preparation of an additional isolation groove, the area on the back of the semiconductor substrate that can be occupied by the first doped silicon layer and the second doped silicon layer is increased, which is also conducive to increasing the number of carriers that can be derived by the solar cell.

[0034] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings used in the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of the steps of a method for preparing a solar cell disclosed in the present invention;

[0037] Figure 2 is a schematic cross-sectional structural diagram of forming a first passivation structure on a semiconductor substrate;

[0038] Figure 3 For Figure 2 A schematic diagram of a structure in which a patterned protective layer is formed on the basis of the structure shown;

[0039] Figure 4 For Figure 3 A schematic structural diagram of a first passivation structure being graphically processed based on the structure shown;

[0040] Figure 5 For Figure 4 A schematic diagram of a structure in which a second tunneling layer and a second intrinsic silicon layer are formed on the basis of the structure shown;

[0041] Figure 6 For Figure 5 A schematic diagram of a structure in which a second doped silicon layer and a doped oxide layer are formed on the basis of the structure shown;

[0042] Figure 7 For Figure 6 A schematic diagram of a structure in which the doped oxide layer and the second passivation structure located on the protective layer are removed based on the structure shown;

[0043] Figure 8 For Figure 7 A schematic diagram of a structure for forming a doping source slurry based on the structure shown;

[0044] Fig. 9 For Figure 8 A schematic diagram of a structure in which a first doped silicon layer is formed on the basis of the structure shown;

[0045] Fig.10 For Fig. 9 Schematic diagram of the structure in which the first surface functional layer and the second surface functional layer are formed on the basis of the structure shown.

[0046] The reference numerals and their meanings are as follows:

[0047] 100, semiconductor substrate; 110, first tunneling layer; 120, first doped silicon layer; 121, doped region; 122, non-doped region; 130, second tunneling layer; 140, second doped silicon layer; 150, first surface functional layer; 160, second surface functional layer; 170, first electrode; 180, second electrode; 210, first intrinsic silicon layer; 220, second intrinsic silicon layer; 230, protective layer; 240, doped oxide layer; 250, doping source slurry. DETAILED DESCRIPTION

[0048] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0050] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0053] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0054] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0055] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0056] The present disclosure provides a method for preparing a solar cell, which comprises the following steps: providing a semiconductor substrate; forming a first passivation structure on the back side of the semiconductor substrate, the first passivation structure comprising a first tunneling layer and a first intrinsic silicon layer which are sequentially stacked; patterning the first passivation structure to form a groove exposing the semiconductor substrate; forming a second passivation structure on the semiconductor substrate exposed from the groove, the second passivation structure comprising a second tunneling layer and a second doped silicon layer which are sequentially stacked; and forming a doping source slurry on the first intrinsic silicon layer, and irradiating the first intrinsic silicon layer with a laser to perform doping to form a first doped silicon layer.

[0057] In the preparation method of the solar cell disclosed in the present invention, a first patterned passivation structure is first formed, and then a second passivation structure is formed on the semiconductor substrate exposed from the groove, and then a doping source slurry is formed on the first intrinsic silicon layer, and a first doped silicon layer is formed by laser irradiation. Among them, the second tunneling layer in the second passivation structure can be used to separate the first intrinsic silicon layer and the second doped silicon layer, and the laser irradiation has a strong localization. When the first intrinsic silicon layer is doped, the doping element is difficult or will not diffuse laterally into the second doped silicon layer. Therefore, the method of forming the second passivation structure in the preparation method and then performing laser doping based on the doping source slurry can ensure the insulation spacing between the first doped silicon layer and the second doped silicon layer, avoid a large number of carriers. Therefore, there is no need to prepare an additional isolation groove, which can simplify the preparation process of the solar cell. In addition, since the preparation method does not require the preparation of an additional isolation groove, the area on the back of the semiconductor substrate that can be occupied by the first doped silicon layer and the second doped silicon layer is increased, which is also conducive to increasing the number of carriers that can be derived by the solar cell.

[0058] Figure 1 Schematic diagram of the steps of a method for preparing a solar cell disclosed in the present invention. Figure 1 As shown, the preparation method includes steps S1 to S5, which are specifically as follows.

[0059] Step S1 : providing a semiconductor substrate 100 .

[0060] As an example of this embodiment, the material of the semiconductor substrate 100 can be selected from one or more of silicon, germanium, gallium nitride, gallium arsenide and silicon carbide. In this embodiment, the material of the semiconductor substrate 100 can be silicon, such as a silicon wafer, and the silicon wafer can be a single crystal silicon wafer or a polycrystalline silicon wafer.

[0061] As an example of this embodiment, the semiconductor substrate 100 may contain doping elements, and the doping type of the semiconductor substrate 100 may be N-type or P-type. When the doping type of the semiconductor substrate 100 is N-type, the doping elements in the semiconductor substrate 100 may be one or more of phosphorus and arsenic. When the doping type of the semiconductor substrate 100 is P-type, the doping elements in the semiconductor substrate 100 may be one or more of aluminum, boron, gallium, and indium.

[0062] As an example of this embodiment, the step of providing the semiconductor substrate 100 includes alkali polishing the semiconductor substrate 100. Further, the semiconductor substrate 100 may be alkali polished using an alkali polishing liquid, and the alkali in the alkali polishing liquid may be selected from sodium hydroxide.

[0063] As a further example of this embodiment, the temperature of the alkali polishing treatment may be 60° C. to 80° C., and the time of the alkali polishing treatment may be 200 s to 400 s.

[0064] Step S2 , forming a first passivation structure on the back side of the semiconductor substrate 100 , wherein the first passivation structure includes a first tunneling layer 110 and a first intrinsic silicon layer 210 which are stacked in sequence.

[0065] Figure 2 FIG. 1 is a schematic cross-sectional view of a first passivation structure formed on a semiconductor substrate 100. Figure 2 As shown, the first tunneling layer 110 and the first intrinsic silicon layer 210 are sequentially stacked on the back side of the semiconductor substrate 100 .

[0066] As an example of this embodiment, the material of the first tunnel layer 110 includes silicon oxide or aluminum oxide. In this embodiment, the material of the first tunnel layer 110 includes silicon oxide.

[0067] As an example of this embodiment, the material of the first intrinsic silicon layer 210 is intrinsic amorphous silicon.

[0068] As an example of this embodiment, the step of forming the first passivation structure includes: placing the semiconductor substrate 100 in a deposition chamber of a chemical vapor deposition device, and sequentially depositing a first tunneling layer 110 and a first intrinsic silicon layer 210 on the back side of the semiconductor substrate 100. In this embodiment, the deposition chamber can be a deposition chamber of a low-pressure chemical vapor deposition device.

[0069] As an example of this embodiment, the thickness of the first tunneling layer 110 is 1 nm to 3 nm.

[0070] As an example of this embodiment, the thickness of the first intrinsic silicon layer 210 is 80 nm to 150 nm.

[0071] As an example of this embodiment, during the deposition of the first tunneling layer 110, silicon source gas and oxygen source gas may be introduced into the deposition chamber, wherein the silicon source gas may be selected from silicon hydride, such as silane (SiH4), and the oxygen source gas may be selected from oxygen or oxidizing gas.

[0072] As an example of this embodiment, during the deposition of the first intrinsic silicon layer 210, a silicon source gas, such as silane, may be introduced into the deposition chamber, and the flow rate of the silane may be 600 sccm to 2000 sccm.

[0073] As an example of this embodiment, during the deposition of the first tunneling layer 110 and / or the first intrinsic silicon layer 210 , the temperature in the deposition chamber may be controlled to be 480° C. to 680° C., and the pressure in the deposition chamber may be controlled to be 60 mTorr to 200 mTorr.

[0074] Step S3 , patterning the first passivation structure to form a groove exposing the semiconductor substrate 100 .

[0075] As an example of this embodiment, the step of patterning the first passivation structure includes: forming a protective layer 230 on the surface of the first passivation structure; patterning the protective layer 230 by laser etching; and using a first etching solution containing alkali to remove the first passivation structure exposed from the protective layer 230 to form a groove.

[0076] Figure 3 For Figure 2 A schematic diagram of a structure in which a patterned protective layer 230 is formed on the basis of the structure shown. Figure 3 As shown, the protection layer 230 is disposed on the first passivation structure and contacts the first intrinsic silicon layer 210. After the patterning process, the protection layer 230 has an opening exposing the first passivation structure.

[0077] The protective layer 230 is used as a mask for patterning the first passivation structure. The material of the protective layer 230 is different from the material of the first intrinsic silicon layer 210. As an example of this embodiment, the material of the protective layer 230 is selected from silicon oxide (SiO x )、Silicon Nitride(SiN x ) and silicon oxynitride (SiON x )

[0078] As an example of this embodiment, the method of forming the protective layer 230 on the surface of the first passivation structure can be selected from low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition or atomic layer deposition.

[0079] As an example of this embodiment, the thickness of the protection layer 230 is 2 nm to 50 nm.

[0080] As an example of this embodiment, in the process of patterning the protective layer 230 by laser etching, the power of the laser source is 20W-100W, and the spot size of the laser is 100 μm-300 μm.

[0081] Figure 4 For Figure 3 A schematic diagram of a structure in which the first passivation structure is graphically processed based on the structure shown. Figure 4 As shown, a groove exposing the semiconductor substrate 100 is formed in the first passivation structure.

[0082] As an example of this embodiment, the alkali in the first etching solution may be one or more of sodium hydroxide and potassium hydroxide.

[0083] As an example of this embodiment, the first etching solution includes sodium hydroxide and water. Further, a sodium hydroxide solution with a mass concentration of 45% to 55% can be mixed with water in a volume ratio of 1:20 to form the first etching solution.

[0084] As an example of this embodiment, in the process of removing the first passivation structure exposed from the protection layer 230 by using the first etching solution containing alkali, the etching time is 180s-420s, and the temperature of the first etching solution is 65°C-80°C.

[0085] As an example of this embodiment, the depth of the groove formed after etching is 1 μm to 5 μm.

[0086] In this embodiment, after the etching is completed and the grooves are formed, the protection layer 230 may be temporarily retained. The protection layer 230 may also protect the first intrinsic silicon layer 210 located therebelow in the subsequent preparation process.

[0087] Step S4 , forming a second passivation structure on the semiconductor substrate 100 exposed from the groove.

[0088] As an example of this embodiment, the steps of forming the second passivation structure include: placing the semiconductor substrate 100 in a deposition chamber of a chemical vapor deposition device, depositing the second tunneling layer 130 and the second intrinsic silicon layer 220 in sequence on the back of the semiconductor substrate 100, and the second tunneling layer 130 is also extended and deposited on the sidewalls and top wall of the first intrinsic silicon layer 210. Also, placing the semiconductor substrate 100 in a diffusion chamber, introducing a reaction gas containing a doping source into the diffusion chamber, and depositing a doping precursor material on the surface of the second intrinsic silicon layer 220; and, annealing so that the doping elements in the doping precursor material diffuse into the second intrinsic silicon layer 220 to form a second doped silicon layer 140 and a doped oxide layer 240.

[0089] Figure 5 For Figure 4 A schematic diagram of a structure in which a second tunneling layer 130 and a second intrinsic silicon layer 220 are formed on the basis of the structure shown in FIG. Figure 5 As shown, the second tunneling layer 130 and the second intrinsic silicon layer 220 are sequentially stacked on the semiconductor substrate 100 .

[0090] As an example of this embodiment, the thickness of the second tunneling layer 130 is 1 nm to 3 nm.

[0091] As an example of this embodiment, the thickness of the second intrinsic silicon layer 220 is 80 nm to 150 nm.

[0092] As an example of this embodiment, during the deposition of the second tunneling layer 130, silicon source gas and oxygen source gas may be introduced into the deposition chamber, wherein the silicon source gas may be selected from silicon hydride, such as silane, and the oxygen source gas may be selected from oxygen or oxidizing gas.

[0093] As an example of this embodiment, during the deposition of the second intrinsic silicon layer 220, a silicon source gas, such as silane, may be introduced into the deposition chamber, and the flow rate of the silane may be 600 sccm to 2000 sccm.

[0094] As an example of this embodiment, during the deposition of the second tunneling layer 130 and / or the second intrinsic silicon layer 220 , the temperature in the deposition chamber may be controlled to be 480° C. to 680° C., and the pressure in the deposition chamber may be controlled to be 60 mTorr to 200 mTorr.

[0095] Reference Figure 5 As shown, as an example of this embodiment, the second tunneling layer 130 is also extended and deposited on the side walls and top walls of the first intrinsic silicon layer 210 to separate the second intrinsic silicon layer 220 and the subsequently formed second doped silicon layer 140, and to prevent the doping elements from diffusing from the second doped silicon layer 140 into the first intrinsic silicon layer 210.

[0096] Figure 6 For Figure 5 A schematic diagram of a structure in which a second doped silicon layer 140 and a doped oxide layer 240 are formed on the basis of the structure shown in FIG. Figure 6 As shown, the second intrinsic silicon layer 220 is transformed into the second doped silicon layer 140, and a doped oxide layer 240 is formed on the surface of the second doped silicon layer 140. It can be understood that the second intrinsic silicon layer 220 can be used as a precursor material of the second doped silicon layer 140, and can form the second doped silicon layer 140 after being doped.

[0097] As an example of this embodiment, in the process of introducing the reaction gas containing the doping source into the diffusion chamber, the doping source can be selected according to the doping element in the second doped silicon layer 140. For example, in this embodiment, the doping type of the second doped silicon layer 140 is the same as the doping type of the semiconductor substrate 100, then the doping element in the second doped silicon layer 140 can be selected from phosphorus, and correspondingly, the doping source can include phosphorus oxychloride (POCl3). When introducing the reaction gas, nitrogen can be used as a carrier gas for phosphorus oxychloride.

[0098] As an example of this embodiment, during the process of introducing the reaction gas, the temperature in the diffusion chamber can be controlled to be 800° C. to 1000° C. At this time, the doping source can be deposited on the surface of the second intrinsic silicon layer 220 to form a doping precursor material. The concentration of the doping element in the doping precursor material can be 1×10 21 cm -3 ~5×10 21 cm -3 .

[0099] As an example of this embodiment, during the annealing process, the doping element in the doping precursor material diffuses into the second intrinsic silicon layer 220, so that the second intrinsic silicon layer 220 is converted into the second doped silicon layer 140. At the same time, a doped oxide layer 240 is formed on the surface of the second intrinsic silicon layer 220. In this embodiment, the doped oxide layer 240 is a phosphorus silicon glass layer (PSG). The doped oxide layer 240 can be temporarily retained and plays a protective role in the subsequent preparation process.

[0100] In step S5 , a doping source paste 250 is formed on the first intrinsic silicon layer 210 , and the first intrinsic silicon layer 210 is doped by laser irradiation to form a first doped silicon layer 120 .

[0101] Reference Figure 6 As shown, as an example of this embodiment, the second passivation structure and the doped oxide layer 240 are also extended and formed on the protective layer 230. Before forming the doping source slurry 250 on the first intrinsic silicon layer 210, the following steps are also included: selectively removing the doped oxide layer 240 located on the protective layer 230 by laser etching; selectively removing the second passivation structure located on the protective layer 230 by a second etching solution containing alkali; and performing a texturing treatment on the front surface of the semiconductor substrate 100.

[0102] Figure 7 For Figure 6 The structure diagram of the second passivation structure is shown in FIG. 1 , wherein the doped oxide layer 240 and the second passivation structure on the protective layer 230 are removed. Figure 7 As shown, the doped oxide layer 240 and the second passivation structure deposited on the protection layer 230 are removed, and the second passivation structure in the groove is retained.

[0103] As an example of this embodiment, in the process of selectively removing the doped oxide layer 240 located on the protective layer 230 , the power of the laser source is 50 W to 100 W, and the spot size of the laser is 100 μm to 300 μm.

[0104] As an example of this embodiment, in the process of selectively removing the second passivation structure located on the protective layer 230, the second etching solution includes sodium hydroxide and water. Further, a sodium hydroxide solution with a mass concentration of 45% to 55% can be mixed with water in a volume ratio of 1:10 to form the second etching solution.

[0105] As an example of this embodiment, in the process of selectively removing the second passivation structure on the protective layer 230, the temperature of the second etching solution can be controlled to be 60° C. to 80° C. Since the doped oxide layer 240 on the protective layer 230 is removed, the second etching solution can directly remove the second doped silicon layer 140 and the second tunneling layer 130 on the protective layer 230. The second passivation structure in the groove is retained.

[0106] As an example of this embodiment, in the process of texturing the front surface of the semiconductor substrate 100, a texturing agent containing alkali may be used for the texturing.

[0107] As a further example of this embodiment, a sodium hydroxide solution with a mass concentration of 45% to 55%, a texturing additive, and water may be mixed in a volume ratio of 3:1:20 to form a texturing agent.

[0108] As a further example of this embodiment, during the texturing process on the front side of the semiconductor substrate 100 , the temperature of the texturing agent is controlled to be 70° C. to 85° C., and the texturing time is controlled to be 300 s to 420 s.

[0109] Reference Figure 7 As shown, in this embodiment, after the texturing process, the front side of the semiconductor substrate 100 opposite to the back side has a texturing structure.

[0110] As an example of this embodiment, after the texturing process, a step of removing the remaining doped oxide layer 240 and the protective layer 230 is further included.

[0111] As an example of this embodiment, a cleaning agent containing hydrofluoric acid may be used to clean and remove the doped oxide layer 240 and the protective layer 230 .

[0112] As a further example of this embodiment, hydrofluoric acid and water may be mixed in a volume ratio of 1:15 to form a cleaning agent. In the process of cleaning and removing the doped oxide layer 240 and the protective layer 230, the cleaning time may be 30s to 200s to ensure that the doped oxide layer 240 and the protective layer 230 are completely removed and the damage to the first intrinsic silicon layer 210 and the second doped silicon layer 140 is reduced.

[0113] It can be understood that after removing the protection layer 230 , a doping source paste 250 may be formed on the first intrinsic silicon layer 210 . Figure 8 For Figure 7 The structure of the doping source paste 250 is formed on the basis of the structure shown in FIG. The doping source paste 250 may include a compound containing a doping element, and the compound containing a doping element may be selected corresponding to the doping type of the first doped silicon layer 120. In this embodiment, the doping type of the first doped silicon layer 120 is P type, and the compound containing a doping element may be a boron compound, such as boric acid.

[0114] As an example of this embodiment, the solid content of the doping source slurry 250 is 20% to 55%. In some examples, the solid content of the doping source slurry 250 can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, or the solid content of the doping source slurry 250 can also be between any two of the above solid contents.

[0115] As an example of this embodiment, the viscosity of the doping source slurry 250 is 20 Pa·s to 50 Pa·s. In some examples, the viscosity of the doping source slurry 250 can be 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s, 50 Pa·s, or the viscosity of the doping source slurry 250 can also be between any two of the above viscosities.

[0116] As an example of this embodiment, the doping source paste 250 may be formed on the first intrinsic silicon layer 210 by printing, such as screen printing or inkjet printing. After the doping source paste 250 is formed, it may be dried to remove the solvent therein and temporarily solidify the doping source paste 250.

[0117] Reference Figure 8 As shown, as an example of this embodiment, in the step of forming the doping source paste 250, the region where the doping source paste 250 is located is spaced from the edge of the first intrinsic silicon layer 210. This can reduce the doping concentration of the doping element at the edge of the first doped silicon layer 120 as much as possible, thereby reducing the recombination of carriers.

[0118] As an example of this embodiment, in the step of forming the doping source paste 250 , the line width of the region where the doping source paste 250 is located is 400 μm to 500 μm.

[0119] Fig. 9 For Figure 8 A schematic diagram of a structure in which a first doped silicon layer 120 is formed on the basis of the structure shown in FIG. Figure 8 and Fig. 9 As shown, the first intrinsic silicon layer 210 is transformed into the first doped silicon layer 120 .

[0120] It can be understood that in this embodiment, laser irradiation is a treatment method that can instantly heat the surface of the first intrinsic silicon layer 210 to an extremely high temperature, which can promote the diffusion of doping elements into the first intrinsic silicon layer 210 and form the first doped silicon layer 120 in a very short time. In addition, laser irradiation has a strong localization, and the doping elements are only doped in the area irradiated by the laser, and lateral diffusion rarely occurs. This, combined with the blocking effect of the second tunneling layer 130, can effectively avoid the contact between the first doped silicon layer 120 and the second doped silicon layer 140. Therefore, this embodiment can achieve the spacing between the first doped silicon layer 120 and the second doped silicon layer 140 without the need to prepare an additional isolation groove.

[0121] As an example of this embodiment, during the process of laser irradiation of the first intrinsic silicon layer 210 for doping, the laser power is 30W-60W and the laser scanning width is 300μm-600μm, which is conducive to making the doping elements more evenly distributed in the laser irradiated area.

[0122] Reference Fig. 9 As shown, in this embodiment, corresponding to the position of the doping source paste 250, the first doped silicon layer 120 formed includes a doped region 121 and a non-doped region 122, the non-doped region 122 is arranged on both sides of the doped region 121, and the doped region 121 and the second doped silicon layer 140 are separated by the non-doped region 122 to avoid short circuit between the doped region 121 and the second doped silicon layer 140. The doped region 121 of the first doped silicon layer 120 contains doping elements, and the non-doped region 122 of the first doped silicon layer 120 does not contain doping elements or the doping concentration of the doping elements is less than 1×10 18 .

[0123] As an example of this embodiment, after forming the first doped silicon layer 120 , a thermal annealing step is further included, which serves to improve the crystallization rate of the first doped silicon layer 120 and the second doped silicon layer 140 , thereby improving their electrical contact performance.

[0124] As an example of this embodiment, after forming the first doped silicon layer 120 , the step of forming the first surface functional layer 150 and the second surface functional layer 160 is further included. Fig.10 Shown in Fig. 9 The schematic diagram of the structure of forming the first surface functional layer 150 and the second surface functional layer 160 on the basis of the structure shown in FIG. Fig.10 As shown, the first surface functional layer 150 is stacked on the front side of the semiconductor substrate 100 , and the second surface functional layer 160 is stacked on the back side of the semiconductor substrate 100 and is located on the first doped silicon layer 120 and the second doped silicon layer 140 .

[0125] As an example of this embodiment, the first surface functional layer 150 includes at least one of a first passivation film and a first anti-reflection film, and the second surface functional layer 160 includes at least one of a second passivation film and a second anti-reflection film.

[0126] As a further example of this embodiment, the materials of the first passivation film and the second passivation film both include aluminum oxide (Al x O y ). The first passivation film and the second passivation film may be formed by atomic layer deposition, such as plasma enhanced atomic layer deposition or plate atomic layer deposition. When depositing the first passivation film and the second passivation film, an aluminum source and an oxygen source may be used as reaction gases, the aluminum source is selected from trimethylaluminum, and the oxygen source is selected from water or oxygen.

[0127] As a further example of this embodiment, the thickness of the first passivation film and the second passivation film is 3 nm to 10 nm.

[0128] As a further example of this embodiment, the materials of the first anti-reflection film and the second anti-reflection film include one or more of silicon nitride, silicon oxide and silicon oxynitride. The first anti-reflection film and the second anti-reflection film may be formed by plasma enhanced chemical vapor deposition.

[0129] As a further example of this embodiment, the thickness of the first anti-reflection film and the second anti-reflection film is 70 nm to 110 nm, and the refractive index is 2.0 to 2.4.

[0130] As an example of this embodiment, after forming the second surface functional layer 160 , the steps of forming the first electrode 170 and the second electrode 180 are further included. The first electrode 170 is in electrical contact with the first doped silicon layer 120 , and the second electrode 180 is in electrical contact with the second doped silicon layer 140 .

[0131] As a further example of this embodiment, the step of forming the first electrode 170 includes: printing aluminum paste on the first doped silicon layer 120 and sintering to form the first electrode 170 .

[0132] As a further example of this embodiment, the step of forming the second electrode 180 includes: printing silver paste on the second doped silicon layer 140 and sintering to form the second electrode 180 .

[0133] It can be understood that, through the above steps S1 to S5, the method for preparing a solar cell disclosed in the present invention can be completed, and a solar cell can be prepared.

[0134] Furthermore, the present disclosure also provides a solar cell, which can be prepared by the above preparation method, and the cross-sectional structure of the solar cell is as follows: Fig.10 See Fig.10 As shown, the solar cell includes a semiconductor substrate 100, a first tunneling layer 110, a second tunneling layer 130, a first doped silicon layer 120 and a second doped silicon layer 140. The first tunneling layer 110 and the first doped silicon layer 120 are sequentially stacked on the back of the semiconductor substrate 100, and the second tunneling layer 130 and the second doped silicon layer 140 are also sequentially stacked on the back of the semiconductor substrate 100. The first doped silicon layer 120 includes a doped region 121 and a non-doped region 122, and the non-doped region 122 is arranged on both sides of the doped region 121. The doped region 121 and the second doped silicon layer 140 are separated by the non-doped region 122 to avoid short circuit between the doped region 121 and the second doped silicon layer 140. The doped region 121 of the first doped silicon layer 120 contains doping elements, and the non-doped region 122 of the first doped silicon layer 120 does not contain doping elements or the doping concentration of the doping elements is lower than 1×10 18 .

[0135] As an example of this embodiment, the second tunneling layer is further extended between the first doped silicon layer and the second doped silicon layer, and spaces the first doped silicon layer and the second doped silicon layer.

[0136] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are only examples, and the embodiments having the same structure as the technical idea and exerting the same effect within the scope of the technical solution of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the main purpose of the present application, various modifications that can be thought of by those skilled in the art to the embodiments and other methods of combining some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: providing a semiconductor substrate; forming a first passivation structure on the back side of the semiconductor substrate, wherein the first passivation structure comprises a first tunneling layer and a first intrinsic silicon layer which are stacked in sequence; Performing a patterning process on the first passivation structure to form a groove exposing the semiconductor substrate; forming a second passivation structure on the semiconductor substrate exposed from the groove, wherein the second passivation structure comprises a second tunneling layer and a second doped silicon layer which are sequentially stacked; and, A doping source slurry is formed on the first intrinsic silicon layer, and the first intrinsic silicon layer is doped by irradiating it with a laser to form a first doped silicon layer having a doped region and a non-doped region, wherein the non-doped region is arranged on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the non-doped region.

2. The method for preparing a solar cell according to claim 1, characterized in that: The step of patterning the first passivation structure comprises: forming a protective layer on the surface of the first passivation structure; The protective layer is patterned by laser etching; and The first passivation structure exposed from the protective layer is removed by using a first etching solution containing alkali to form the groove.

3. The method for preparing a solar cell according to claim 2, characterized in that: The step of forming the second passivation structure comprises: Placing the semiconductor substrate in a deposition chamber of a chemical vapor deposition device, and sequentially depositing a second tunneling layer and a second intrinsic silicon layer on the back side of the semiconductor substrate, wherein the second tunneling layer is extended and deposited on the sidewall and top wall of the first intrinsic silicon layer; placing the semiconductor substrate in a diffusion chamber, introducing a reaction gas containing a doping source into the diffusion chamber, and depositing a doping precursor material on the surface of the second intrinsic silicon layer; and Annealing is performed to diffuse the doping elements in the doping precursor material into the second intrinsic silicon layer to form the second doped silicon layer and a doped oxide layer located on the second doped silicon layer.

4. The method for preparing a solar cell according to claim 3, characterized in that: The second passivation structure and the doped oxide layer are also extended and formed on the protective layer; before forming the doping source slurry on the first intrinsic silicon layer, the method further includes the following steps: Selectively removing the doped oxide layer on the protective layer by laser etching; selectively removing the second passivation structure on the protective layer using a second etching solution containing alkali; and The front surface of the semiconductor substrate is subjected to a texturing treatment.

5. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that: The step of forming the first passivation structure comprises: The semiconductor substrate is placed in a deposition chamber of a chemical vapor deposition device, and a first tunneling layer and a first intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate.

6. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that: The doping type of the semiconductor substrate is the same as the doping type of the second doped silicon layer, and the doping type of the semiconductor substrate is different from the doping type of the first doped silicon layer.

7. The method for preparing a solar cell according to claim 6, characterized in that: The doping source slurry comprises a boron-containing compound, and the solid content of the doping source slurry is 20% to 55%; and / or, The viscosity of the doping source slurry is 20 Pa·s to 50 Pa·s.

8. The method for preparing a solar cell according to any one of claims 1 to 4 and 7, characterized in that: In the step of forming the doping source slurry, the region where the doping source slurry is located is spaced apart from the edge of the first intrinsic silicon layer; and / or, The line width of the region where the doping source slurry is located is 400 μm to 500 μm.

9. The method for preparing a solar cell according to any one of claims 1 to 4 and 7, characterized in that: In the step of irradiating the first intrinsic silicon layer with laser to perform doping, the power of the laser used is 30W-60W, and the scanning width of the laser used is 300 μm-600 μm.

10. A solar cell, characterized in that: The solar cell comprises a semiconductor substrate, a first tunneling layer, a second tunneling layer, a first doped silicon layer and a second doped silicon layer; The first tunneling layer and the first doped silicon layer are sequentially stacked on the back side of the semiconductor substrate, and the second tunneling layer and the second doped silicon layer are sequentially stacked on the back side of the semiconductor substrate; the first doped silicon layer includes a doped region and a non-doped region, the non-doped region is arranged on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the non-doped region.

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