Organic light emitting diode display

Abstract

An organic light emitting diode display is provided, the organic light emitting diode display including: a flexible substrate; a semiconductor layer on the flexible substrate; and an overlay layer. The transistor includes: a driving transistor; a second transistor transmitting a data voltage transmitted through a data line to an input electrode of the driving transistor; and a third transistor including a gate electrode connected to the scan line, a first electrode connected to the output electrode of the driving transistor, and a second electrode connected to the gate electrode of the driving transistor. And a third transistor including two transistors connected to each other in series and connected to each other at a third node formed in the semiconductor layer, an additional capacitance portion formed in the semiconductor layer and in the vicinity of the third node, and a stack layer overlapping the third node of the semiconductor layer and the additional capacitance portion.

Description

[0001] This application is a divisional application of the invention patent application with the application date of April 3, 2019, application number "201910265312.8" and invention name "Organic Light Emitting Diode Display". Technical Field

[0002] Embodiments relate to an organic light emitting diode (OLED) display. Background Art

[0003] The display device displays images, and among the display devices, organic light emitting diode displays have attracted much attention.

[0004] Unlike liquid crystal display (LCD) devices, organic light emitting diode displays have self-luminous properties and do not require a separate light source, and thus can have reduced thickness and weight. In addition, organic light emitting diode displays can provide high quality properties of low power consumption, high brightness, and high response speed.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the above information may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0006] An embodiment relates to an organic light emitting diode display, which includes: a flexible substrate; a semiconductor layer located on the flexible substrate, the semiconductor layer including a channel of a transistor, a first electrode and a second electrode; and a stacked layer. The transistor may include: a driving transistor configured to apply a current to an organic light emitting element; a second transistor connected to a scan line and a data line, the second transistor transmitting a data voltage transmitted through the data line to an input electrode of the driving transistor; and a third transistor including a gate electrode connected to the scan line, a first electrode connected to an output electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor. The third transistor may include two transistors connected in series to each other and connected to each other at a third node, the third node may be formed in the semiconductor layer, an additional capacitance portion may be formed in the semiconductor layer and near the third node, and the stacked layer may overlap the third node of the semiconductor layer and the additional capacitance portion.

[0007] The semiconductor layer may extend in a first direction and be located within the third transistor, may be bent in a second direction, and then may extend in the second direction, wherein the second direction crosses the first direction.

[0008] The third node may be disposed at a bent portion of the semiconductor layer.

[0009] The additional capacitance portion may be a portion of the semiconductor layer protruding in an upward direction at the bent portion.

[0010] The additional capacitance portion may be a portion of the semiconductor layer protruding in the first direction at the bent portion.

[0011] The additional capacitance portion may be a portion of the semiconductor layer protruding in the first direction and in an upward direction at the bent portion.

[0012] The additional capacitance portion may be spaced apart from the semiconductor layer at the bent portion by a predetermined distance.

[0013] The stacking layer may be disposed between the flexible substrate and the semiconductor layer in a cross-sectional view.

[0014] The overlay layer may be floating.

[0015] The stacked layer may be applied with a driving voltage ELVDD.

[0016] The organic light emitting diode display may further include: a barrier layer located above the flexible substrate and below the stacked layer; a buffer layer located above the stacked layer and below the semiconductor layer; a first gate insulating layer covering the semiconductor layer; a first gate conductor located on the first gate insulating layer; a second gate insulating layer covering the first gate conductor and the first gate insulating layer; a second gate conductor located on the second gate insulating layer; an interlayer insulating layer covering the second gate conductor and the second gate insulating layer; a data conductor located on the interlayer insulating layer; and a passivation layer covering the data conductor and the interlayer insulating layer. The data conductor may include a driving voltage line to which a driving voltage ELVDD is applied, the driving voltage line and the second gate conductor may be electrically connected to each other through an opening in the interlayer insulating layer, and the second gate conductor may be electrically connected to the stacked layer through openings in the buffer layer, the first gate insulating layer, and the second gate insulating layer.

[0017] The second gate conductor may be a parasitic capacitor control pattern.

[0018] The data conductor may be a connecting member.

[0019] The stacking layer may be disposed over the semiconductor layer in a cross-sectional view.

[0020] The organic light emitting diode display may further include: a barrier layer located above the flexible substrate and below the stacked layer; a buffer layer located above the stacked layer and below the semiconductor layer; a first gate insulating layer covering the semiconductor layer; a first gate conductor located on the first gate insulating layer; a second gate insulating layer covering the first gate conductor and the first gate insulating layer; a second gate conductor located on the second gate insulating layer; an interlayer insulating layer covering the second gate conductor and the second gate insulating layer; a data conductor located on the interlayer insulating layer; and a passivation layer covering the data conductor and the interlayer insulating layer. The stacked layer may be located on the same layer as the first gate conductor or the second gate conductor.

[0021] The data conductor may include a driving voltage line to which a driving voltage ELVDD is applied, and the driving voltage line and the stacked layer may be electrically connected to each other through an opening in the interlayer insulating layer.

[0022] The stacked layer may be integrally formed with the parasitic capacitor control pattern, and the parasitic capacitor control pattern may be a second gate conductor.

[0023] Embodiments also relate to an organic light emitting diode display, the organic light emitting diode display comprising: a flexible substrate; a semiconductor layer located on the flexible substrate, the semiconductor layer comprising a channel of a transistor, a first electrode and a second electrode; a stacked layer located between the semiconductor layer and the flexible substrate; and a parasitic capacitor control pattern, which is arranged to be farther from the flexible substrate than the semiconductor layer. The transistor may include: a driving transistor configured to apply a current to the organic light emitting diode; a second transistor connected to a scan line and a data line, the second transistor transmitting a data voltage transmitted through the data line to an input electrode of the driving transistor; and a third transistor including a gate electrode connected to the scan line, a first electrode connected to an output electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor. The third transistor may include two transistors connected in series to each other and connected to each other at a third node, the third node may be formed in the semiconductor layer, and the stacked layer, the parasitic capacitor control pattern, and the third node of the semiconductor layer may be sequentially stacked.

[0024] The parasitic capacitor control pattern may be applied with a driving voltage ELVDD.

[0025] The additional capacitance portion may be formed in the semiconductor layer near the third node, and the stacked layer may overlap the third node of the semiconductor layer and the additional capacitance portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which: Figure 1 An equivalent circuit diagram showing one pixel of an organic light emitting diode display according to example embodiments; Figure 2 A timing diagram illustrating signals applied to one pixel of an organic light emitting diode display according to example embodiments; Figure 3 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Figure 4 Show Figure 3 an enlarged view of a portion of a pixel; Figure 5 Shown along Figure 4A cross-sectional view taken along line VV of ; Figure 6 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Figure 7 Show Figure 6 an enlarged view of a portion of a pixel; Figure 8 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig. 9 Show Figure 8 an enlarged view of a portion of a pixel; Fig.10 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig.11 Show Fig.10 an enlarged view of a portion of a pixel; Fig.12 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig.13 An equivalent circuit diagram showing one pixel of an organic light emitting diode display according to example embodiments; Fig.14 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig.15 Shown along Fig.14 A sectional view taken along line XV-XV of ; Fig.16 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig.17 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig.18 Shown along Fig.17 a sectional view taken along line XVIII-XVIII; Fig.19 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig. 20 Shown along Fig.19 A cross-sectional view taken along line XX-XX; Fig.21 A layout diagram showing one pixel region of an organic light emitting diode display according to example embodiments; Fig. 22 Show Fig.13 a portion of a circuit diagram of Fig.23The experimental results of brightness reduction are shown. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, these example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey example implementations to those skilled in the art. Like reference numerals refer to like elements throughout.

[0028] In order to clearly describe the present disclosure, parts irrelevant to the description may be omitted.

[0029] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, the words "on" or "above" mean disposed on or below an object portion, and do not necessarily mean disposed on the upper side of an object portion based on the direction of gravity.

[0030] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “have” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0031] Furthermore, throughout the specification, the phrase "on a plane" means observing a target portion from the top, and the phrase "on a cross section" means observing a cross section formed by vertically cutting the target portion from the side.

[0032] In the following, reference will be made to Figure 1 and Figure 2 An organic light emitting diode display according to example embodiments is described.

[0033] Figure 1 shows an equivalent circuit diagram of one pixel of an organic light emitting diode display according to example embodiments, Figure 2 A timing diagram illustrating signals applied to one pixel of an organic light emitting diode display according to example embodiments.

[0034] According to this exemplary embodiment, referring to Figure 1 , a pixel PX of the organic light emitting diode display includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to a number of signal lines 127, 151, 152, 153, 158, 171, 172 and 741, a storage capacitor Cst and an organic light emitting diode OLED.

[0035] Each of the third transistor T3 and the fourth transistor T4 is shown as a structure including two transistors connected in series. The structure including two transistors connected in series means a structure in which gate electrodes of the two transistors T3-1 and T3-2 are connected to each other to receive the same signal, and an output signal of one transistor is applied to the other transistor as an input signal.

[0036] According to the present exemplary embodiment, the third transistor T3 is formed to have a structure in which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected in series. The gate electrode G3-1 of the 3-1 transistor T3-1 and the gate electrode G3-2 of the 3-2 transistor T3-2 are connected to each other, and the first electrode S3-1 of the 3-1 transistor T3-1 and the second electrode D3-2 of the 3-2 transistor T3-2 are also connected to each other. The fourth transistor T4 is also formed to have a structure in which two transistors are connected in series, but in some exemplary embodiments, it may be formed as a single transistor.

[0037] Also, as an example, in Figure 1 The pixel PX shown in FIG. 1 further includes a stacked layer M1. The stacked layer M1 is stacked with a node (hereinafter, referred to as a "third node") N3, where a first electrode S3-1 of the third transistor T3-1 and a second electrode D3-2 of the third transistor T3-2 are connected to each other.

[0038] The stacked layer M1 may be disposed above or below the third node N3 stacked with the substrate with respect to the substrate.

[0039] According to the present example embodiment, a separate voltage may not be applied to the stacked layer M1. Therefore, the stacked layer M1 may be in a floating state. In another example embodiment, the stacked layer M1 may be electrically connected to another portion to receive a voltage, and the voltage that may be applied to the stacked layer M1 may be changed. Fig.13 A stacked layer M1 to which a voltage is applied is described.

[0040] According to the present example embodiment, an additional capacitor is formed between the third node N3 and the stacked layer M1 , and the additional capacitor serves to buffer a voltage change at the third node N3 .

[0041] According to the present exemplary embodiment, the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, a second transistor T2 and a third transistor T3 as switching transistors connected to the scan line 151, and the remaining transistors T4, T5, T6, and T7 (hereinafter referred to as compensation transistors) for operating the organic light emitting diode OLED. The compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0042] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a scan line 151, a front scan line 152, a light emitting control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be a part of the front scan line 152 or may be electrically connected to the front scan line 152.

[0043] According to the present exemplary embodiment, the scan line 151 is connected to the gate driver to transmit the scan signal Sn to the switching transistor (i.e., to the second transistor T2 and the third transistor T3). The front scan line 152 is connected to the gate driver to transmit the front scan signal Sn-1 to the fourth transistor T4, and the front scan signal Sn-1 is applied to the pixel PX disposed at the front side thereof. The fourth transistor T4 may include two transistors connected in series with each other. Therefore, the front scan signal Sn-1 may be applied to the gate electrode of each of the two transistors connected in series with each other included in the fourth transistor T4. The light emission control line 153 is connected to the light emission controller, and transmits the light emission control signal EM for controlling the time when the organic light emitting diode OLED emits light to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits the bypass signal GB to the seventh transistor T7, and in some exemplary embodiments, the bypass control line 158 may transmit the same signal as the front scan signal Sn-1 to the seventh transistor T7.

[0044] According to the present exemplary embodiment, the data line 171 is a wiring for transmitting a data voltage Dm generated by a data driver, and the light emission brightness of an organic light emitting diode (OLED; also referred to as an "organic light emitting element") changes according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD, the initialization voltage line 127 transmits an initialization voltage Vint for initializing the driving transistor T1, and the common voltage line 741 applies a common voltage ELVSS. A constant voltage may be applied to each of the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741.

[0045] Hereinafter, a plurality of transistors will be described.

[0046] According to the present exemplary embodiment, the driving transistor T1 is a transistor that adjusts the current output according to the applied data voltage Dm, and the output driving current Id is applied to the organic light emitting diode OLED. Therefore, the brightness of the organic light emitting diode OLED is adjusted according to the data voltage Dm. In an embodiment, the first electrode S1 of the driving transistor T1 is configured to be able to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. In the present exemplary embodiment, the first electrode S1 of the driving transistor T1 is connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 (output side electrode) is configured to be able to output current to the organic light emitting diode OLED and is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. The gate electrode G1 is connected to one electrode (the second storage electrode E2) of the storage capacitor Cst. Therefore, the voltage of the gate electrode G1 varies according to the voltage stored in the storage capacitor Cst, thereby changing the driving current Id output from the driving transistor T1.

[0047] According to the present exemplary embodiment, the second transistor T2 is a transistor for transmitting a data voltage Dm to the pixel PX. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0048] According to the present exemplary embodiment, the third transistor T3 is a transistor for transmitting a compensation voltage (voltage Dm+Vth) to the second storage electrode E2 of the storage capacitor Cst, and the compensation voltage changes when the data voltage Dm passes through the driving transistor T1. The third transistor T3 includes a 3-1 transistor T3-1 and a 3-2 transistor T3-2 connected in series to each other. The gate electrode G3-1 of the 3-1 transistor T3-1 and the gate electrode G3-2 of the 3-2 transistor T3-2 are connected to the scan line 151. The first electrode S3-2 of the 3-2 transistor T3-2 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3-1 of the 3-1 transistor T3-1 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. In the present exemplary embodiment, the first electrode S3-1 of the 3-1 transistor T3-1 and the second electrode D3-2 of the 3-2 transistor T3-2 are connected to each other at the third node N3. When the third transistor T3 is described as one transistor, the first electrode S3-2 of the 3-2 transistor T3-2 is the first electrode of the third transistor T3, and the second electrode D3-1 of the 3-1 transistor T3-1 is the second electrode of the third transistor T3. The third transistor T3 is turned on in response to the scan signal Sn received through the scan line 151 to connect the gate electrode G1 of the driving transistor T1 to the second electrode D1, and to connect the second electrode D1 of the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst.

[0049] According to the present exemplary embodiment, the fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the front scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The fourth transistor T4 also includes two transistors connected in series with each other. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the front scan signal Sn-1 received through the front scan line 152. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint can be a low voltage that can turn on the driving transistor T1.

[0050] According to the present exemplary embodiment, the fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the light emission control line 153, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0051] According to the present exemplary embodiment, the sixth transistor T6 is used to transmit the driving current Id output from the driving transistor T1 to the organic light emitting diode OLED. The gate electrode G6 is connected to the light emission control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0052] According to the present exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on by the light emission control signal EM received via the light emission control line 153, and when the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the organic light emitting diode OLED through the sixth transistor T6. The organic light emitting diode OLED emits light when the current Ioled flows therethrough.

[0053] According to the present exemplary embodiment, the seventh transistor T7 is used to initialize the anode of the organic light emitting diode OLED. The gate electrode G7 is connected to the bypass control line 158, the first electrode S7 is connected to the anode of the organic light emitting diode OLED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 158 may be connected to the front scan line 152, and the bypass signal GB is a signal of the same timing as the front scan signal Sn-1. The bypass control line 158 may not be connected to the front scan line 152, and a separate signal different from the front scan signal Sn-1 may be transmitted. When the seventh transistor T7 is turned on by the bypass signal GB, the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED to initialize the anode of the organic light emitting diode OLED.

[0054] According to the present example embodiment, the first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Therefore, the second storage electrode E2 may determine the voltage of the gate electrode G1 of the driving transistor T1, and may receive the data voltage Dm through the second electrode D3 of the third transistor T3, or receive the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0055] exist Figure 1 In the present exemplary embodiment, an additional storage capacitor is formed in the third transistor T3 by the third node N3 and the stacked layer M1. Therefore, a signal change at the third node N3 may be reduced, thereby improving the characteristics of the third transistor T3 as a whole.

[0056] According to the present example embodiment, an anode of the organic light emitting diode OLED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 , and a cathode of the organic light emitting diode OLED is connected to a common voltage line 741 for transmitting a common voltage ELVSS.

[0057] exist Figure 1 In the present exemplary embodiment, the pixel circuit includes seven transistors (T1 to T7) and one capacitor Cst, but the number of transistors and the number of capacitors and the connection between the transistors and the capacitors may be variously changed.

[0058] The organic light emitting diode display may include a display area displaying an image, and the pixels PX may be arranged in the display area in various forms such as a matrix.

[0059] Now refer to Figure 1 and Figure 2 An operation of one pixel of an organic light emitting diode display according to example embodiments is described.

[0060] During the initialization period, the low-level front scan signal Sn-1 is supplied to the pixel PX through the front scan line 152. The conductivity of the fourth transistor T4 applied with the low-level front scan signal Sn-1 increases, so that the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. Therefore, the driving transistor T1 and the storage capacitor Cst are initialized. The voltage of the initialization voltage Vint is low, so that the driving transistor T1 can be turned on.

[0061] In addition, during the initialization period, a low-level bypass signal GB is applied to the seventh transistor T7. The seventh transistor T7 applied with the low-level bypass signal GB is turned on, so that the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED through the seventh transistor T7. Therefore, the anode of the organic light emitting diode OLED is also initialized.

[0062] Thereafter, during a data writing period, a low-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 and the third transistor T3 are turned on by the low-level scan signal Sn.

[0063] When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 through the second transistor T2.

[0064] In addition, during the data writing period, the third transistor T3 is turned on, so that the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 and the second electrode D1 of the driving transistor T1 are diode-connected. In addition, during the initialization period, a low voltage (initialization voltage Vint) is applied to the gate electrode G1. Therefore, the driving transistor T1 is in a conducting state. Therefore, the data voltage Dm input to the first electrode S1 of the driving transistor T1 is output from the second electrode D1 through the channel of the driving transistor T1, and then stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3.

[0065] The voltage applied to the second storage electrode E2 changes according to the threshold voltage Vth of the driving transistor T1, the data voltage Dm is applied to the first electrode S1 of the driving transistor T1, and when the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output in the second electrode D1 may be "Vgs+Vth". Here, Vgs is the difference between the voltages applied to the gate electrode G1 of the driving transistor T1 and the first electrode S1, so it may be "Dm-Vint". Therefore, the voltage output from the second electrode D1 and stored in the second storage electrode E2 may be "Dm-Vint+Vth".

[0066] Compared with the case where the third transistor T3 is formed on a rigid substrate such as glass, the kickback voltage of the third transistor T3 increases when the third transistor T3 is formed on a flexible substrate. When black is displayed, the increase in the kickback voltage is significant, and when white and black are alternately displayed, a gray afterimage remains. When white and black are alternately displayed like a chessboard or a chessboard pattern, a gray afterimage remains, which is called a chess afterimage. This can be avoided by reducing the kickback voltage of the third transistor T3. In the present exemplary embodiment, an additional storage capacitor connected to the third transistor T3 is formed, and thus an overlapping layer M1 overlapping the third node N3 is included.

[0067] During the light emission period, the light emission control signal EM supplied from the light emission control line 153 is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. Therefore, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the organic light emitting diode OLED. The driving transistor T1 outputs a driving current Id according to the difference between the voltage of the gate electrode G1 and the voltage of the first electrode S1 (ie, the driving voltage ELVDD). The driving current Id of the driving transistor T1 may have a value proportional to the square value of "Vgs-Vth". Here, Vgs is the difference between the voltages applied to the two terminals of the storage capacitor Cst, and since Vgs is "Vg–Vs", it may be "Dm-Vint+Vth-ELVDD". Here, when "Vgs-Vth" is obtained by subtracting Vth, it is "Dm-Vint-ELVDD". Therefore, the driving current Id of the driving transistor T1 may be a current that is independent of the threshold voltage Vth of the driving transistor T1.

[0068] As described above, even if the driving transistors T1 disposed in the respective pixels PX have different threshold voltages Vth due to process dispersion, example embodiments may output the output current of the driving transistors T1 to be constant, thereby improving the uneven characteristics of the driving transistors T1 in the respective pixels PX.

[0069] In the above calculation formula, when the transistor is a p-type transistor using a polycrystalline semiconductor, Vth can be a value slightly greater than 0 or a negative value. In addition, the signs of "+" and "-" can be changed according to the direction of the calculated voltage. However, even in this case, the drive current Id as the output current of the drive transistor T1 can have a value that is independent of the threshold voltage Vth.

[0070] When the above-mentioned light emission period ends, the same operation can be repeated from the initialization period.

[0071] One of the first and second electrodes of each of the plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may be a source electrode and the other may be a drain electrode depending on a direction of applied voltage or current.

[0072] In an exemplary embodiment, when the seventh transistor T7 initializes the anode of the organic light emitting diode OLED during the initialization period, by discharging a small amount of current emitted under the condition that the driving transistor T1 is actually not turned on as a bypass current Ibp through the seventh transistor T7 to the terminal of the initialization voltage Vint, it can even prevent the small amount of current from flowing to the organic light emitting diode OLED. Therefore, the organic light emitting diode OLED can be prevented from emitting unnecessary light, so that the black gradient can be displayed more clearly and the contrast can be improved. The bypass signal GB can be a signal having a timing different from the timing of the front scanning signal Sn-1. In an exemplary embodiment, the seventh transistor T7 can be omitted.

[0073] In the pixel PX operated as described above, the stacked layer M1 may not operate and may remain in a floating state. However, an additional storage capacitor is formed between the third transistor T3 and the third node N3 by the stacked layer M1 to stabilize the voltage change at the third node N3. Therefore, it may be possible to prevent the residual image from remaining. In the present exemplary embodiment, the stacked layer M1 is stacked with the third transistor T3 and is disposed between the substrate and the third transistor T3. Therefore, when the third transistor T3 is manufactured, the third transistor T3 may have desired characteristics by preventing impurities from coming from a flexible substrate made of plastic or polyimide (PI).

[0074] In the following, reference will be made to Figures 3 to 5 Disposition of a pixel PX and an stacked layer M1 of an organic light emitting diode display according to example embodiments is described.

[0075] Figure 3 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Figure 4 Show Figure 3 A magnified image of a portion of the pixels, Figure 5 Shown along Figure 4 A cross-sectional view taken along line VV of FIG.

[0076] Reference Figures 3 to 5 The organic light emitting diode display according to the present exemplary embodiment includes a scan line 151, a front scan line 152, a light emitting control line 153, and an initialization voltage line 127 that extend mainly in a first direction and transmit a scan signal Sn, a front scan signal Sn-1, a light emitting control signal EM, and an initialization voltage Vint, respectively. The bypass signal GB is transmitted through the front scan line 152. The organic light emitting diode display includes a data line 171 and a driving voltage line 172 that extend in a second direction crossing the first direction and transmit a data voltage Dm and a driving voltage ELVDD, respectively.

[0077] According to the present exemplary embodiment, the organic light emitting diode display includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED. The stacking layer M1 is stacked with a portion (third node N3) where the 3-1 transistor T3-1 and the 3-2 transistor T3-2 of the third transistor T3 are connected, thereby forming an additional storage capacitor.

[0078] The stacked layer M1 may be formed of a metal having a conductive property or a semiconductor material corresponding to the metal. Figure 3 The stacking layer M1 of the present exemplary embodiment is disposed between the substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer. In the present exemplary embodiment, the stacking layer M1 is overlapped with the third node N3 at which two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may be overlapped with at least some of the other portions of the two transistors T3-1 and T3-2. The stacking layer M1 is in a floating state and is not electrically connected to the other portions. Figure 3 In order to clearly illustrate the stacked layer M1, the stacked layer M1 is represented by a thicker line than other parts.

[0079] The connection portion of the two transistors T3-1 and T3-2 stacked with the stacking layer M1 is disposed on the semiconductor layer, and the semiconductor layer also includes an additional capacitor portion. Figure 4 and Figure 5 Describe the Additional Capacitor section.

[0080] Figure 4 An enlarged view showing only the peripheral structure of the third transistor T3 is shown, showing the scan line 151, the stacked layer M1 and the semiconductor layer ACTIVE surrounding the third transistor T3, Figure 5 Shown along Figure 4 A cross-sectional view taken along line VV of FIG.

[0081] The scan line 151 extends in the first direction, and the gate electrode G3-1 of the 3-1 transistor T3-1 protrudes upward. In addition, the portion where the scan line 151 overlaps with the semiconductor layer ACTIVE is the gate electrode G3-2 of the 3-2 transistor T3-2, and unlike the gate electrode G3-1 of the 3-1 transistor T3-1, the gate electrode G3-2 of the 3-2 transistor T3-2 is not a protruding structure, but a portion of the scan line 151 extending in the first direction.

[0082] The semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The semiconductor layer ACTIVE has an upwardly protruding structure (additional capacitance portion) at the portion where the semiconductor layer ACTIVE bends in the second direction. Therefore, the sum of the widths of the portion where the semiconductor layer ACTIVE bends and the additional capacitance portion in the second direction is greater than the width of the semiconductor layer ACTIVE extending in the first direction in the second direction (see Figure 4 ). The portion where the semiconductor layer ACTIVE is bent corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected. Therefore, the additional capacitance portion is provided near the third node N3.

[0083] According to the present exemplary embodiment, the portion of the semiconductor layer ACTIVE where it is bent (and the additional capacitance portion) overlaps with the stacking layer M1 to form an additional storage capacitor. In the present exemplary embodiment, the stacking layer M1 is formed large enough to completely overlap with the portion of the semiconductor layer ACTIVE where it is bent (and the additional capacitance portion) in a plan view. Figures 3 to 5 In the present exemplary embodiment, the additional storage capacitor is formed by using the stacked layer M1, but in order to increase the capacitance of the additional storage capacitor, a protruding structure is added to the semiconductor layer ACTIVE. Therefore, the area where the stacked layer M1 overlaps the semiconductor layer ACTIVE (including the additional capacitance portion) increases, and thus the capacitance of the additional storage capacitor increases.

[0084] exist Figures 3 to 5 In the present example embodiment, the stacked layer M1 is disposed between the semiconductor layer ACTIVE and the substrate 110 , and the stacked layer M1 may be formed of a metal having conductivity or a semiconductor material corresponding to the metal.

[0085] Return to reference Figure 3 , an organic light emitting diode (OLED) includes a pixel electrode, an organic emission layer and a common electrode.

[0086] According to the present exemplary embodiment, the channel of each of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is disposed in the extended semiconductor layer 130 (also denoted by the reference numeral “ACTIVE”). In addition, at least some of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are also disposed in the semiconductor layer 130. Figure 3 In the figure, shading is added to the semiconductor layer 130 so that the semiconductor layer 130 is shown to be easily distinguished from other layers. Figure 3Unlike the structure shown in FIG. 1 , the semiconductor layer 130 may be variously curved. The semiconductor layer 130 may include a polycrystalline semiconductor such as polysilicon or an oxide semiconductor.

[0087] According to the present exemplary embodiment, the semiconductor layer 130 includes a channel doped with n-type impurities or p-type impurities, and a first doping region and a second doping region disposed at opposite sides of the channel have a doping concentration higher than the concentration of the impurities doped in the channel. The first doping region and the second doping region correspond to first electrodes and second electrodes of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, respectively, and when one of the first doping region and the second doping region is a source region, the other is a drain region. In the semiconductor layer 130, the region between the first electrode and the second electrode, respectively from two different transistors, is also doped so that the two different transistors can be electrically connected to each other.

[0088] According to the present exemplary embodiment, each of the channels of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7 overlaps the gate electrode of each of the transistors T1, T2, T3, T4, T5, T6 and T7, and is disposed between the first electrode and the second electrode of each of the transistors T1, T2, T3, T4, T5, T6 and T7. The plurality of transistors T1, T2, T3, T4, T5, T6 and T7 may have substantially the same stacking structure. Hereinafter, the driving transistor T1 will be mainly described in detail, and the other transistors T2, T3, T4, T5, T6 and T7 will be briefly described.

[0089] According to the present exemplary embodiment, the driving transistor T1 includes a channel, a gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is located between the first electrode S1 and the second electrode D1, and overlaps the gate electrode 155 in a plan view. The channel is curved so as to form a long channel in a limited area. The driving range of the gate voltage Vg applied to the gate electrode 155 of the driving transistor T1 widens as the length of the channel increases, and the driving current Id increases steadily according to the gate voltage Vg. Therefore, the grayscale of the light emitted from the organic light emitting diode OLED can be accurately controlled by changing the gate voltage Vg, and the display quality of the organic light emitting diode display can also be improved. In the present exemplary embodiment, the channel extends in several directions instead of in one direction. Therefore, the effect caused by the directivity is offset in the manufacturing process, which can help reduce the effect of process dispersion. Therefore, it can be possible to reduce or prevent the degradation of image quality such as point defects (for example, even if the same data voltage Dm is applied, brightness differences appear depending on the pixel) (which may occur due to the characteristics of the driving transistor T1 changing according to the area of ​​the display device due to process dispersion). The shape of the channel may have the illustrated Ω shape or various shapes.

[0090] According to the present example embodiment, the gate electrode 155 overlaps the channel in a plan view. The first electrode S1 and the second electrode D1 are disposed at opposite sides of the channel. The extended portion of the storage line 126 is separated and disposed on the gate electrode 155. The extended portion of the storage line 126 overlaps the gate electrode 155 in a plan view, and a second gate insulating layer is disposed between the extended portion of the storage line 126 and the gate electrode 155 to form a storage capacitor Cst. The extended portion of the storage line 126 is a first storage electrode ( Figure 1 E1), the gate electrode 155 is a second storage electrode ( Figure 1 The extension portion of the storage line 126 is provided with an opening 56 so that the gate electrode 155 can be connected to the first data connection member 71. In the opening 56, the upper surface of the gate electrode 155 and the first data connection member 71 are electrically connected through the opening 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0091] The gate electrode of the second transistor T2 may be a portion of the scan line 151. According to the present example embodiment, the data line 171 is connected to the first electrode S2 of the second transistor T2 through the opening 62, and the first electrode S2 and the second electrode D2 may be disposed on the semiconductor layer 130.

[0092] According to the present exemplary embodiment, the third transistor T3 is formed by two transistors T3-1 and T3-2 that are adjacent and connected in series to each other. The third transistor T3 may be connected in series to prevent leakage current from flowing. The structure in which two transistors are connected in series is described with reference to one third transistor T3, and the first electrode S3 of the third transistor T3 (corresponding to the first electrode S3-2 of the 3-2 transistor T3-2) is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. In the present exemplary embodiment, the second electrode D3 of the third transistor T3 (corresponding to the second electrode D3-1 of the 3-1 transistor T3-1) is connected to the first data connection member 71 through the opening 63.

[0093] According to the present exemplary embodiment, the fourth transistor T4 also includes two fourth transistors T4 connected in series to each other, and the two fourth transistors T4 are formed at the portion where the front scan line 152 and the semiconductor layer 130 intersect. The gate electrode G4 of the fourth transistor T4 may be a portion of the front scan line 152. The second electrode D4 of one fourth transistor T4 is connected to the second electrode D3 of the third transistor T3. As described above, the series connection structure may be used to block leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the opening 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through the opening 63.

[0094] The gate electrode G5 of the fifth transistor T5 may be part of the light emission control line 153. According to the present example embodiment, the driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the opening 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0095] The gate electrode G6 of the sixth transistor T6 may be part of the light emission control line 153. According to the present example embodiment, the third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the opening 69, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0096] The gate electrode G7 of the seventh transistor T7 may be a part of the front scan line 152. According to the present example embodiment, the third data connection member 73 is connected to the first electrode S7 of the seventh transistor T7 through the opening 81, and the second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0097] According to the present example embodiment, the storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 overlapped with each other, and a second gate insulating layer 142 is between the first storage electrode E1 and the second storage electrode E2. The second storage electrode E2 corresponds to the gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. According to the present example embodiment, the second gate insulating layer 142 (see Figure 5 ) becomes a dielectric, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the gate electrode 155 as the second storage electrode E2, a space for the storage capacitor Cst can be formed in a space narrowed due to the large area occupied by the channel of the driving transistor T1 in the pixel PX.

[0098] According to the present example embodiment, the driving voltage line 172 is connected to the first storage electrode E1 through the opening 68. Therefore, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the gate electrode 155.

[0099] According to the present example embodiment, the second data connection member 72 is connected to the initialization voltage line 127 through the opening 64. An electrode referred to as a pixel electrode is connected to the third data connection member 73 through the opening 81.

[0100] The parasitic capacitor control pattern 79 may be formed on the third node N3 of the third transistor T3. A parasitic capacitor exists in the pixel PX, and the image quality characteristics may change when the voltage applied to the parasitic capacitor changes. According to the present exemplary embodiment, the driving voltage line 172 is connected to the parasitic capacitor control pattern 79 through the opening 66. Therefore, the change of the image quality characteristics may be reduced or prevented by applying the driving voltage ELVDD (as a constant DC voltage) to the parasitic capacitor. The parasitic capacitor control pattern 79 may be formed in an area different from the area shown, and a voltage other than the driving voltage ELVDD may be applied. In an exemplary embodiment, the parasitic capacitor control pattern 79 may be omitted due to the stacking layer M1.

[0101] In the following, we will refer to Figure 5 An overall cross-sectional structure of an organic light emitting diode display according to example embodiments is described with reference to a stacking order of FIG.

[0102] In the organic light emitting diode display according to the present exemplary embodiment, the substrate 110 is flexible and is formed of a flexible material such as plastic or polyimide (PI). A barrier layer 111 is disposed on the substrate 110, and an overlay layer M1 formed of a conductive metal or a semiconductor material having the same conductive properties is disposed on the barrier layer 111. A buffer layer 112 is disposed on the overlay layer M1. The barrier layer 111 and the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, and may also include an organic insulating material such as polyimide (for example, epoxy resin added) and polyacrylic acid.

[0103] According to the present example embodiment, a semiconductor layer 130 including channels of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a first electrode, and a second electrode is disposed on the buffer layer 112. A first gate insulating layer 141 is disposed on the semiconductor layer 130 to cover the semiconductor layer 130.

[0104] According to the present example embodiment, a first gate conductor including gate electrodes (second storage electrode E2) of a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, a scan line 151, a front scan line 152 and a light emitting control line 153 is disposed on the first gate insulating layer 141.

[0105] According to the present example embodiment, the second gate insulating layer 142 covering the first gate conductor is disposed on the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide.

[0106] According to the present example embodiment, a second gate conductor including the storage line 126 , the first storage electrode E1 , the initialization voltage line 127 , and the parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142 .

[0107] According to the present example embodiment, an interlayer insulating layer 160 covering the second gate conductor is disposed on the second gate conductor. The interlayer insulating layer 160 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide, and may also be formed of an organic insulating material.

[0108] According to the present example embodiment, a data conductor including a data line 171 , a driving voltage line 172 , a first data connection member 71 , a second data connection member 72 , and a third data connection member 73 is disposed on the interlayer insulating layer 160 .

[0109] According to the present example embodiment, a passivation layer 180 covering the data conductor is disposed on the data conductor. The passivation layer 180, which may be a planarization layer, may include an organic insulating material.

[0110] According to the present exemplary embodiment, the pixel electrode is disposed on the passivation layer 180. The pixel electrode is connected to the third data connection member 73 through the opening 81 formed in the passivation layer 180. The partition wall is disposed on the passivation layer 180 and the pixel electrode. The partition wall is provided with an opening portion overlapping the pixel electrode, and the organic light emitting layer is disposed in the opening portion. The common electrode is disposed on the organic light emitting layer and the partition wall. The pixel electrode, the organic light emitting layer and the common electrode form an organic light emitting diode OLED.

[0111] In an example embodiment, the pixel electrode may be an anode as a hole injection electrode, and the common electrode may be a cathode as an electron injection electrode. Conversely, the pixel electrode may be a cathode, and the common electrode may be an anode. When holes and electrons are injected into the organic light emitting layer from the pixel electrode and the common electrode, respectively, when excitons in which the injected holes and electrons are recombined enter a ground state from an excited state, light is emitted.

[0112] According to the present exemplary embodiment, the scan line 151, the front scan line 152 and the light emitting control line 153 formed by the first gate conductor extend in the first direction, and the storage line 126 and the initialization voltage line 127 formed by the second gate conductor also extend in the first direction. The data line 171 and the driving voltage line 172 formed by the data conductor extend in the second direction.

[0113] According to the present example embodiment, the data line 171 is connected to the first electrode S2 of the second transistor T2 through the opening 62 formed in the first gate insulating layer 141 , the second gate insulating layer 142 , and the interlayer insulating layer 160 .

[0114] According to the present example embodiment, the driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through an opening 67 formed in the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 160, is connected to the extended portion of the storage line 126 (the first storage electrode E1) through an opening 68 formed in the interlayer insulating layer 160, and is connected to the parasitic capacitor control pattern 79 through an opening 66 formed in the interlayer insulating layer 160.

[0115] According to the present example embodiment, one end of the first data connection member 71 is connected to the gate electrode 155 through the opening 61 formed in the second gate insulating layer 142 and the interlayer insulating layer 160, and the other end of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the opening 63 formed in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160.

[0116] According to the present example embodiment, one end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through an opening 65 formed in the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 160, and the other end of the second data connection member 72 is connected to the initialization voltage line 127 through an opening 64 formed in the interlayer insulating layer 160.

[0117] According to the present example embodiment, the third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the opening 69 formed in the first gate insulating layer 141 , the second gate insulating layer 142 , and the interlayer insulating layer 160 .

[0118] According to the present exemplary embodiment, an encapsulation layer for protecting the organic light emitting diode OLED is disposed on the common electrode. The encapsulation layer may contact the common electrode, or may be spaced apart from the common electrode. The encapsulation layer may be a thin film encapsulation layer stacked with an inorganic film and an organic film, and may include three layers formed of an inorganic film, an organic film, and an inorganic film. A covering layer and a functional layer may be disposed between the common electrode and the encapsulation layer.

[0119] Figure 5 The structure of the electrical connection of the stacked layer M1 is shown in detail.

[0120] According to this exemplary embodiment, referring to Figure 5 , the barrier layer 111 is disposed on the substrate 110, and the stacking layer M1 is disposed on the barrier layer 111. Figure 3 As shown in FIG. 1 , the stacked layer M1 is located at a position overlapping with the third transistor T3 in a plan view. The stacked layer M1 is disposed on the buffer layer 112. The semiconductor layer 130 is disposed on the buffer layer 112. Figure 4 , the second electrode D3-1 and the first electrode S3-1 of the 3-1 transistor T3-1 and the second electrode D3-2 of the 3-2 transistor T3-2 are shown, and the channel of the 3-1 transistor T3-1 is provided between the second electrode D3-1 and the first electrode S3-1 of the 3-1 transistor T3-1.

[0121] According to the present exemplary embodiment, the first gate insulating layer 141 is disposed on the semiconductor layer ACTIVE of the third transistor T3 and the buffer layer 112. The gate electrode G3-1 of the 3-1 transistor T3-1 is disposed on the first gate insulating layer 141. The second gate insulating layer 142 is disposed on the gate electrode G3-1 of the 3-1 transistor T3-1.

[0122] According to the present example embodiment, the parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142. The interlayer insulating layer 160 is disposed on the parasitic capacitor control pattern 79. The passivation layer 180 is disposed on the interlayer insulating layer 160. The pixel electrode, the organic light emitting layer, the common electrode, and the encapsulation layer may be disposed on the passivation layer 180.

[0123] According to this exemplary embodiment, Figures 3 to 5 The stacked layer M1 is floated and overlaps a portion of the semiconductor layer ACTIVE at a bent portion in the third transistor T3, and is disposed above the substrate 110 and below the semiconductor layer 130 to be disposed between the barrier layer 111 and the buffer layer 112. The semiconductor layer ACTIVE overlapped with the stacked layer M1 to form an additional storage capacitor includes an upward protruding portion (additional capacitance portion).

[0124] According to this exemplary embodiment, Figures 3 to 5 In the structure, the stacked layer M1 and the parasitic capacitor control pattern 79 exist as a layer overlapping the third node N3 , the stacked layer M1 is floated, and the driving voltage ELVDD is applied to the parasitic capacitor control pattern 79 .

[0125] In example embodiments, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110 but may be disposed over the semiconductor layer ACTIVE and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0126] In an example embodiment, the additional capacitance portion of the semiconductor layer ACTIVE may have a Figure 6 and Figure 7 The structure shown in .

[0127] Figure 6 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Figure 7 Show Figure 6 An enlarged view of a portion of the pixels.

[0128] according to Figure 6 and Figure 7 The organic light emitting diode display of this exemplary embodiment is Figure 3 and Figure 4 The organic light emitting diode displays are similar in that they include an stacked layer M1 and in their overall structures, but are different in the difference between the shapes of the semiconductor layer ACTIVE stacked with the stacked layer M1.

[0129] In the following, reference will be made to Figure 6 and Figure 7 The main description is in addition to the previous Figures 3 to 5 Elements other than those described in .

[0130] Figure 7 An enlarged view showing the difference from the previously described example embodiment (the additional capacitance portion of the semiconductor layer ACTIVE), so that reference will be made mainly to Figure 7 The present example embodiments are described.

[0131] Figure 7 Example embodiments include Figure 4 The additional capacitance portion of the exemplary embodiment is different from the additional capacitance portion of the semiconductor layer ACTIVE. Figure 7 In the embodiment, the additional capacitance portion of the semiconductor layer ACTIVE protrudes in a first direction, for example, in a rightward direction.

[0132] Figure 7 As an enlarged view of only the peripheral structure of the third transistor T3 , the scan line 151 , the stacked layer M1 , and the semiconductor layer ACTIVE surrounding the third transistor T3 are shown.

[0133] The structure of the scanning line 151 is Figure 4 The structure of the scanning line 151 is the same.

[0134] According to the present exemplary embodiment, the semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The portion of the semiconductor layer ACTIVE bent in the second direction has a structure (additional capacitance portion) protruding in the first direction. Therefore, the sum of the widths of the portion of the semiconductor layer ACTIVE where the bend is located and the additional capacitance portion in the first direction is greater than the width of the gate electrode G3-1 of the 3-1 transistor T3-1 in the first direction (see FIG. 2 ). Figure 7 ). In the present exemplary embodiment, the sum of the widths of the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portion in the first direction is greater than the width of the semiconductor layer ACTIVE extending in the second direction in the first direction. The portion where the semiconductor layer ACTIVE is bent corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected. Therefore, the additional capacitance portion is disposed near the third node N3.

[0135] According to the present exemplary embodiment, the stacking layer M1 is disposed between the substrate 110 formed of plastic or polyimide (PI) and the semiconductor layer ACTIVE. The stacking layer M1 is formed to be large enough to completely overlap with the portion of the semiconductor layer ACTIVE where it is bent and the additional capacitance portion in a plan view. In the present exemplary embodiment, the stacking layer M1 overlaps with the third node N3 where the two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may overlap with at least some of the other portions of the two transistors T3-1 and T3-2. The stacking layer M1 has a floating state and is not electrically connected to other portions.

[0136] According to the present exemplary embodiment, the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portion overlap with the stacking layer M1 to form an additional storage capacitor. Therefore, the stacking layer M1 overlaps with the portion (third node N3) where the 3-1 transistor T3-1 and the 3-2 transistor T3-2 of the third transistor T3 are connected, thereby forming an additional storage capacitor.

[0137] exist Figure 6 and Figure 7In the present exemplary embodiment, an additional storage capacitor is formed by using the stacking layer M1, but in order to increase the capacitance of the additional storage capacitor, a protruding structure is added to the semiconductor layer ACTIVE. Therefore, the area where the stacking layer M1 overlaps the semiconductor layer ACTIVE (including the additional capacitance portion) increases, and as a result, the capacitance of the additional storage capacitor increases. Therefore, the voltage change at the third node N3 is buffered, and the kickback voltage of the third transistor T3 is reduced. Therefore, afterimages can be reduced or prevented. In the present exemplary embodiment, the stacking layer M1 overlaps the third transistor T3 and is disposed between the substrate 110 and the third transistor T3. Therefore, when the third transistor T3 is manufactured, the third transistor T3 can have desired characteristics by preventing impurities from coming from a flexible substrate made of plastic or polyimide (PI).

[0138] exist Figure 6 and Figure 7 In the present example embodiment, the stacked layer M1 is disposed between the semiconductor layer ACTIVE and the substrate 110, and the stacked layer M1 may be formed of a metal having conductivity or a semiconductor material corresponding to the metal. Figure 6 and Figure 7 In this example embodiment, the cross-sectional view and Figure 5 The cross-sectional views are the same.

[0139] According to this exemplary embodiment, Figure 6 and Figure 7 In the structure, the stacked layer M1 and the parasitic capacitor control pattern 79 exist as a layer overlapping the third node N3 , the stacked layer M1 is floated, and the driving voltage ELVDD is applied to the parasitic capacitor control pattern 79 .

[0140] In addition to the structure of the additional capacitance portion of the semiconductor layer ACTIVE stacked with the stacking layer M1, Figure 6 and Figure 7 Example embodiments and Figures 3 to 5 The exemplary embodiments of have the same characteristics. Therefore, Figure 6 and Figure 7 This example embodiment can be shown as Figure 1 The same circuit diagram as the circuit diagram, and can receive Figure 2 The timing signals shown in FIG. 1 are the same timing signals as those shown in FIG. 1 to perform the operation.

[0141] In example embodiments, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110 but may be disposed over the semiconductor layer ACTIVE and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0142] In an example embodiment, the additional capacitance portion of the semiconductor layer ACTIVE may have a Figure 8 and Fig. 9 The structure shown in .

[0143] Figure 8 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Fig. 9 Show Figure 8 An enlarged view of a portion of the pixels.

[0144] according to Figure 8 and Fig. 9 The organic light emitting diode display of this exemplary embodiment is Figure 3 and Figure 4 The organic light emitting diode displays are similar in that they include an stacked layer M1 and in their overall structures, but are different in the difference between the shapes of the semiconductor layer ACTIVE stacked with the stacked layer M1.

[0145] In the following, reference will be made to Figure 8 and Fig. 9 The main description is in addition to the previous Figures 3 to 5 Elements other than those described in .

[0146] Fig. 9 An enlarged view showing the difference from the previously described example embodiment (the additional capacitance portion of the semiconductor layer ACTIVE) is shown, so that reference will be made to Fig. 9 The present exemplary embodiment is mainly described.

[0147] Fig. 9 Example embodiments include having Figure 4 The structure of the additional capacitance portion of the exemplary embodiment is different from the structure of the semiconductor layer ACTIVE additional capacitance portion. Fig. 9 In the embodiment, the additional capacitance portion of the semiconductor layer ACTIVE extends in an upward direction and in the first direction.

[0148] Fig. 9 As an enlarged view of only the peripheral structure of the third transistor T3 , the scan line 151 , the stacked layer M1 , and the semiconductor layer ACTIVE surrounding the third transistor T3 are shown.

[0149] According to this exemplary embodiment, the structure of the scan line 151 is Figure 4 The structure of the scan line 151 in is the same.

[0150] According to the present exemplary embodiment, the semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The portion of the semiconductor layer ACTIVE that is bent in the second direction has a structure (additional capacitance portion) that protrudes in the upward direction as well as in the first direction. Therefore, the sum of the widths of the portion of the semiconductor layer ACTIVE where the bending occurs and the additional capacitance portion in the second direction is greater than the width of the semiconductor layer ACTIVE extending in the first direction in the second direction, and the sum of the widths of the portion of the semiconductor layer ACTIVE where the bending occurs and the additional capacitance portion in the first direction is greater than the width of the gate electrode G3-1 of the 3-1 transistor T3-1 in the first direction (see FIG. 1 ). Fig. 9 ). The portion where the semiconductor layer ACTIVE is bent corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected. Therefore, the additional capacitance portion is provided near the third node N3.

[0151] According to the present exemplary embodiment, the stacking layer M1 is disposed between the substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE. The stacking layer M1 is formed to be large enough to overlap with all of the additional capacitance portions in a plan view. In the present exemplary embodiment, the stacking layer M1 overlaps with the third node N3 at which the two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may overlap with at least some of the other portions of the two transistors T3-1 and T3-2. The stacking layer M1 has a floating state and is not electrically connected to the other portions.

[0152] According to the present exemplary embodiment, the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portion overlap with the stacking layer M1 to form an additional storage capacitor. Therefore, the stacking layer M1 overlaps with the portion (third node N3) where the 3-1 transistor T3-1 and the 3-2 transistor T3-2 of the third transistor T3 are connected, thereby forming an additional storage capacitor.

[0153] exist Figure 8 and Fig. 9In the present exemplary embodiment, an additional storage capacitor is formed by using the stacking layer M1, but in order to increase the capacitance of the additional storage capacitor, a protruding structure is added to the semiconductor layer ACTIVE. Therefore, the area where the stacking layer M1 overlaps the semiconductor layer ACTIVE (including the additional capacitance portion) increases, and as a result, the capacitance of the additional storage capacitor increases. Therefore, the voltage change at the third node N3 is buffered, and the kickback voltage of the third transistor T3 is reduced. Therefore, afterimages can be reduced or prevented. In the present exemplary embodiment, the stacking layer M1 overlaps the third transistor T3 and is disposed between the substrate 110 and the third transistor T3. Therefore, when the third transistor T3 is manufactured, the third transistor T3 can have desired characteristics by preventing impurities from coming from a flexible substrate made of plastic or polyimide (PI).

[0154] exist Figure 8 and Fig. 9 In the present example embodiment, the stacked layer M1 is disposed between the semiconductor layer ACTIVE and the substrate 110 , and the stacked layer M1 may be formed of a metal having conductivity or a semiconductor material corresponding to the metal. Figure 8 and Fig. 9 A cross-sectional view of this example embodiment and Figure 5 The cross-sectional views are the same.

[0155] exist Figure 8 and Fig. 9 In the structure, the stacked layer M1 and the parasitic capacitor control pattern 79 exist as a layer overlapping the third node N3 , the stacked layer M1 is floated, and the driving voltage ELVDD is applied to the parasitic capacitor control pattern 79 .

[0156] In addition to the structure of the additional capacitance portion of the semiconductor layer ACTIVE stacked with the stacking layer M1, Figure 8 and Fig. 9 Example embodiments and Figures 3 to 5 The exemplary embodiments of have the same characteristics. Therefore, Figure 8 and Fig. 9 This example embodiment can be shown as Figure 1 The circuit diagram of the exemplary embodiment is the same as the circuit diagram of the exemplary embodiment, and can receive Figure 2 The timing signals shown in FIG. 1 are the same timing signals as those shown in FIG. 1 to perform the operation.

[0157] In example embodiments, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110 but may be disposed over the semiconductor layer ACTIVE and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0158] In an example embodiment, the additional capacitance portion of the semiconductor layer ACTIVE may have a Fig.10and Fig.11 The structure shown in .

[0159] Fig.10 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Fig.11 Show Fig.10 An enlarged view of a portion of the pixels.

[0160] according to Fig.10 and Fig.11 The organic light emitting diode display of this exemplary embodiment is Figure 3 and Figure 4 The organic light emitting diode displays are similar in that they include an stacked layer M1 and in their overall structures, but are different in the difference between the shapes of the semiconductor layer ACTIVE stacked with the stacked layer M1.

[0161] In the following, reference will be made to Fig.10 and Fig.11 The main description is in addition to the previous Figures 3 to 5 Elements other than those described in .

[0162] Fig.11 An enlarged view showing the difference from the previously described example embodiment (the additional capacitance portion of the semiconductor layer ACTIVE) is shown, so that reference will be made to Fig.11 The present exemplary embodiments are mainly described.

[0163] Fig.11 Example embodiments include having Figure 4 The structure of the additional capacitance portion of the exemplary embodiment is different from the structure of the additional capacitance portions A1 and A2 of the semiconductor layer ACTIVE. Fig.11 In the embodiment, the additional capacitance parts A1 and A2 of the semiconductor layer ACTIVE do not extend and protrude in the semiconductor layer ACTIVE, but are spaced apart from the semiconductor layer ACTIVE by a predetermined distance. The additional capacitance parts A1 and A2 spaced apart by a predetermined distance may be formed of the same material as the semiconductor layer ACTIVE through the same process.

[0164] Fig.11 As an enlarged view of only the peripheral structure of the third transistor T3 , the scan line 151 , the stacked layer M1 , and the semiconductor layer ACTIVE surrounding the third transistor T3 are shown.

[0165] According to this exemplary embodiment, the structure of the scan line 151 is Figure 4 The structure of the scan line 151 in is the same.

[0166] According to the present exemplary embodiment, the semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The additional capacitance parts A1 and A2 spaced apart by a predetermined distance from the semiconductor layer ACTIVE are disposed at the portion bent in the second direction. The first additional capacitance part A1 is disposed to be spaced apart from the portion at the bend of the semiconductor layer ACTIVE by a predetermined distance in a direction opposite to the second direction. In the present exemplary embodiment, the second additional capacitance part A2 is disposed to be spaced apart from the portion at the bend of the semiconductor layer ACTIVE by a predetermined distance along the first direction. In the present exemplary embodiment, two additional capacitance parts A1 and A2 are included and the two additional capacitance parts A1 and A2 are spaced apart by a predetermined distance. In other embodiments, a single additional capacitance part may be included, or three additional capacitance parts may be included. The portion at the bend of the semiconductor layer ACTIVE corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected. Therefore, the additional capacitance part is disposed near the third node N3.

[0167] According to the present exemplary embodiment, the stacking layer M1 is disposed between the substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE. The stacking layer M1 is formed large enough to overlap a portion of the semiconductor layer ACTIVE where it is bent and all of the additional capacitance portions A1 and A2 in a plan view.

[0168] In the present example embodiment, the stacked layer M1 may overlap with the third node N3 at which two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may overlap with at least some of the other portions of the two transistors T3-1 and T3-2. According to the present example embodiment, the stacked layer M1 has a floating state and is not electrically connected to the other portions.

[0169] According to the present exemplary embodiment, the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portions A1 and A2 are overlapped with the stacking layer M1 to form an additional storage capacitor. Therefore, the stacking layer M1 is overlapped with the portion (third node N3) where the 3-1 transistor T3-1 and the 3-2 transistor T3-2 of the third transistor T3 are connected, thereby forming an additional storage capacitor.

[0170] exist Figure 10 to Figure 11In the present exemplary embodiment, an additional storage capacitor is formed by using the stacked layer M1, but in order to increase the capacitance of the additional storage capacitor, additional capacitance parts A1 and A2 are added to the semiconductor layer ACTIVE. Therefore, the area where the stacked layer M1 overlaps the semiconductor layer ACTIVE and the additional capacitance parts A1 and A2 increases, and as a result, the capacitance of the additional storage capacitor increases. Therefore, the voltage change at the third node N3 is buffered, and the kickback voltage of the third transistor T3 is reduced. Therefore, afterimages can be reduced or prevented. In the present exemplary embodiment, the stacked layer M1 overlaps the third transistor T3 and is disposed between the substrate 110 and the third transistor T3. Therefore, when the third transistor T3 is manufactured, the third transistor T3 can have desired characteristics by preventing impurities from coming from a flexible substrate made of plastic or polyimide (PI).

[0171] exist Fig.10 and Fig.11 In the present example embodiment, the stacked layer M1 is disposed between the semiconductor layer ACTIVE and the substrate 110 , and the stacked layer M1 may be formed of a metal having conductivity or a semiconductor material corresponding to the metal. Fig.10 and Fig.11 A cross-sectional view of this example embodiment and Figure 5 The cross-sectional views are the same.

[0172] According to this exemplary embodiment, Fig.10 and Fig.11 In the structure, the stacked layer M1 and the parasitic capacitor control pattern 79 exist as a layer overlapping the third node N3 , the stacked layer M1 is floated, and the driving voltage ELVDD is applied to the parasitic capacitor control pattern 79 .

[0173] In addition to the additional capacitance parts A1 and A2 structures of the semiconductor layer ACTIVE stacked with the stacking layer M1, Fig.10 and Fig.11 Example embodiments and Figures 3 to 5 The exemplary embodiments of have the same characteristics. Therefore, Fig.10 and Fig.11 This example embodiment can be shown as Figure 1 The same circuit diagram as the circuit diagram, and can receive Figure 2 The timing signals shown in FIG. 1 are the same timing signals as those shown in FIG. 1 to perform the operation.

[0174] In example embodiments, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110 but may be disposed over the semiconductor layer ACTIVE and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0175] In an example embodiment, if Fig.12In this case, the semiconductor layer ACTIVE may not include an additional capacitance portion of the semiconductor layer ACTIVE. This is a case where the change in the kickback voltage of the third transistor T3 can be sufficiently reduced by the capacitance additionally formed by the overlap of the stacked layer M1 and the bent portion of the semiconductor layer ACTIVE.

[0176] Fig.12 A layout diagram illustrating one pixel region of an organic light emitting diode display according to example embodiments.

[0177] according to Fig.12 The organic light emitting diode display of this exemplary embodiment is Figure 3 and Figure 4 The organic light emitting diode displays are similar in that they all include a stacking layer M1 and in their overall structures, but are different in the difference between the shapes of the semiconductor layer ACTIVE stacked with the stacking layer M1. Fig.12 In the embodiment, no additional capacitance portion is formed in the semiconductor layer ACTIVE.

[0178] In this example embodiment, referring to Fig.12 The semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The additional capacitance portion may be additionally omitted.

[0179] In the present example embodiment, a region of the stacked layer M1 overlapping the bent portion (third node N3 ) of the semiconductor layer ACTIVE is relatively narrow in both the first and second directions, compared to that of the stacked layer M1 of the previous example embodiments.

[0180] In the present example embodiment, the stacked layer M1 is disposed between the substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE. In the present example embodiment, the stacked layer M1 has a floating state and is not electrically connected to other portions.

[0181] and Figures 1 to 11 The capacitance of the additional storage capacitor of the example embodiment is compared with, Fig.12 The capacitance of the additional storage capacitor of this example embodiment is relatively small. Therefore, Fig.12 The present exemplary embodiment may be applicable to a case where a larger capacitance is not required to reduce a variation in the kickback voltage of the third transistor T3.

[0182] exist Fig.12In the present exemplary embodiment, due to the capacitance of the additional storage capacitor caused by overlapping the stacking layer M1 with the semiconductor layer ACTIVE, the voltage change at the third node N3 is buffered, and the kickback voltage of the third transistor T3 is reduced. Therefore, afterimages can be reduced or prevented. In the present exemplary embodiment, the stacking layer M1 overlaps the third transistor T3 and is disposed between the substrate 110 and the third transistor T3. Therefore, when the third transistor T3 is manufactured, the third transistor T3 can have desired characteristics by preventing impurities from coming from a flexible substrate made of plastic or polyimide (PI).

[0183] In this example embodiment, Fig.12 In the structure, the stacked layer M1 and the parasitic capacitor control pattern 79 exist as a layer overlapping the third node N3, the stacked layer M1 is floated, and the driving voltage ELVDD is applied to the parasitic capacitor control pattern 79.

[0184] Fig.12 The cross-sectional view of this example embodiment is Figure 5 In this example embodiment, Fig.12 This example embodiment can also be shown with Figure 1 The same circuit diagram as the circuit diagram, and can receive Figure 2 The timing signals shown in FIG. 1 are the same timing signals as those shown in FIG. 1 to perform the operation.

[0185] In example embodiments, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110 but may be disposed over the semiconductor layer ACTIVE and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0186] If the stacked layer M1 is formed of a second gate conductor, it may be connected to the parasitic capacitor control pattern 79 (eg, see Figure 3 , Figure 6 , Figure 8 , Fig.10 and Fig.12 ) are disposed on the same layer. In this case, a method may be considered in which the parasitic capacitor control pattern 79 is not formed, or the stacking layer M1 is omitted while the parasitic capacitor control pattern 79 is maintained.

[0187] First, relative to Figure 3 , Figure 6 , Figure 8 , Fig.10 and Fig.12 The parasitic capacitor control pattern 79 is removed so that the parasitic capacitor control pattern 79 may not be formed. In this case, since the opening 66 electrically connects the parasitic capacitor control pattern 79 and the driving voltage line 172, the opening 66 may also be omitted.

[0188] Furthermore, in order to omit the stacking layer M1 while maintaining the parasitic capacitor control pattern 79, the Figure 3 , Figure 6 , Figure 8 , Fig.10 and Fig.12 The stacking layer M1 is removed. The parasitic capacitor control pattern 79 serves as the stacking layer. In the present exemplary embodiment, the opening 66 is omitted and the stacking layer M1 is floated.

[0189] In the present example embodiment, the stacked layer M1 is not electrically connected to other portions and floats. In another embodiment, the stacked layer M1 may be electrically connected to other portions in the pixel PX to receive various voltages.

[0190] Hereinafter, an example embodiment to which a driving voltage ELVDD is applied as one of various voltages that may be applied to the stack layer M1 will be described.

[0191] Now refer to Fig.13 Describe its circuit structure.

[0192] Fig.13 An equivalent circuit diagram of one pixel of an organic light emitting diode display according to example embodiments is shown.

[0193] In addition to the stacked layer M1 being electrically connected to the driving voltage line 172 to which the driving voltage ELVDD is applied, Fig.13 In general, it corresponds to Figure 1 .

[0194] In this example embodiment, referring to Fig.13 When the driving voltage ELVDD is applied to the stacked layer M1, the voltage at one end of the additional storage capacitor is fixed so that the characteristics of the additional storage capacitor become constant, and thus the third node N3 of the third transistor T3 overlapping the stacked layer M1 can be further stabilized.

[0195] In the present exemplary embodiment, the threshold voltage Vth of the third transistor T3 is shifted in the negative direction due to a high voltage such as the driving voltage ELVDD applied to the stacked layer M1. When the threshold voltage Vth of the third transistor T3 is shifted in the negative direction, the kickback voltage of the third transistor T3 using a p-type semiconductor is further reduced, thereby reducing the brightness reduction.

[0196] Fig.13 Example embodiments of Figure 1 The same as the exemplary embodiment of is that when Figure 1 The same as in the present exemplary embodiment is applied Figure 2 When the signal Fig.13 The example embodiments operate as described herein.

[0197] In this example embodiment, Fig.13 The exemplary embodiment may also be applied to a semiconductor layer ACTIVE surrounding the third transistor T3 having a Figures 3 to 12 Thus, the capacitor portion may or may not protrude, or may be disposed to be spaced apart from the semiconductor layer ACTIVE by a predetermined distance.

[0198] In the present example embodiment, the driving voltage ELVDD is applied to the stacked layer M1.

[0199] In the following, reference will be made to Fig.14 and Fig.15 The structure of applying the driving voltage ELVDD to the stacked layer M1 is described. Here, among the structures of the various semiconductor layers ACTIVE, there are corresponding Figure 3 The exemplary embodiment of the structure of the semiconductor layer ACTIVE is used as a representative. The exemplary embodiment in which the driving voltage ELVDD is applied to the stacked layer M1 can also be applied to Figure 6 , Figure 8 , Fig.10 or Fig.12 .

[0200] Fig.14 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Fig.15 Shown along Fig.14 A sectional view taken along line XV-XV of FIG.

[0201] In this example embodiment, referring to Fig.14 The stacked layer M1 is formed of a metal having a conductive property or a semiconductor material corresponding to the metal, and is disposed between a substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE. In the present example embodiment, the stacked layer M1 overlaps a third node N3 at which two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may overlap at least some of the other portions of the two transistors T3-1 and T3-2.

[0202] exist Fig.14 In the present exemplary embodiment, the semiconductor layer ACTIVE stacked with the stacking layer M1 further includes an additional capacitance portion, and as shown in FIG. Figure 3 As shown in FIG.

[0203] In this exemplary embodiment, the semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. The semiconductor layer ACTIVE has a structure (additional capacitance portion) protruding upward at the portion where it bends in the second direction. Therefore, the sum of the widths of the portion where the semiconductor layer ACTIVE bends and the additional capacitance portion in the second direction is greater than the width of the semiconductor layer ACTIVE extending in the first direction in the second direction (see Figure 4 ). Fig.14 In the embodiment, the portion where the semiconductor layer ACTIVE is bent corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected. Therefore, the additional capacitance portion is provided near the third node N3.

[0204] In the present example embodiment, a portion of the semiconductor layer ACTIVE where it is bent and an additional capacitance portion overlap with the stacking layer M1 to form an additional storage capacitor.

[0205] In the present example embodiment, the stacked layer M1 is electrically connected to the parasitic capacitor control pattern 79 through the opening 57 and receives the driving voltage ELVDD, and the parasitic capacitor control pattern 79 is electrically connected to the driving voltage line 172 through the opening 66 .

[0206] Fig.15 Detailed description is given in FIG. 7A of the connection structure between the stacked layer M1 and the parasitic capacitor control pattern 79 .

[0207] Fig.15 The organic light emitting diode display shown in FIG. 1 uses a substrate 110 formed of a flexible material such as plastic or polyimide (PI). A barrier layer 111 is disposed on the substrate 110 , and an overlay layer M1 formed of a conductive metal or a semiconductor material having the same conductive property is disposed on the barrier layer 111 .

[0208] The buffer layer 112 is disposed on the stacked layer M1. The barrier layer 111 and the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, and may also include an organic insulating material such as polyimide (eg, epoxy resin added) and polyacrylic acid.

[0209] In the present example embodiment, a semiconductor layer 130 including channels of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a first electrode, and a second electrode is disposed on the buffer layer 112. Fig.15 , only a portion of the semiconductor layer 130 corresponding to the third transistor T3 is shown in the cross-sectional partial view.

[0210] In the present example embodiment, a first gate insulating layer 141 covering the semiconductor layer 130 is disposed on the semiconductor layer 130 .

[0211] In the present exemplary embodiment, a first gate conductor including gate electrodes (second storage electrodes E2) of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a scan line 151, a front scan line 152, and a light emitting control line 153 is disposed on the first gate insulating layer 141. Fig.15 In the cross-sectional partial view, only one of the gate electrodes G3-1 and G3-2 of the third transistor T3 is shown.

[0212] In the present example embodiment, the second gate insulating layer 142 covering the first gate conductor is disposed on the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide.

[0213] In the present example embodiment, a second gate conductor including the storage line 126 , the first storage electrode E1 , the initialization voltage line 127 , and the parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142 .

[0214] In the present exemplary embodiment, an opening 57 is formed in the buffer layer 112, the first gate insulating layer 141, and the second gate insulating layer 142 to expose a portion of the stacked layer M1. The parasitic capacitor control pattern 79 is electrically connected to the stacked layer M1 through the opening 57. The parasitic capacitor control pattern 79 is electrically connected to the driving voltage line 172 through the opening 66. Therefore, the stacked layer M1 is also electrically connected to the driving voltage line 172. Therefore, the driving voltage ELVDD is applied to the stacked layer M1. In an exemplary embodiment, the stacked layer M1 may be directly connected to the driving voltage line 172.

[0215] In the present example embodiment, an interlayer insulating layer 160 covering the second gate conductor is disposed on the second gate conductor. The interlayer insulating layer 160 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide, and may also be formed of an organic insulating material.

[0216] In the present example embodiment, the data conductors (including the data line 171 , the driving voltage line 172 , the first data connection member 71 , the second data connection member 72 , and the third data connection member 73 ) are disposed on the interlayer insulating layer 160 .

[0217] A passivation layer 180 covering the data conductor is disposed on the data conductor. The passivation layer 180 (also referred to as a planarization layer) may include an organic insulating material.

[0218] In the present example embodiment, a pixel electrode, an organic light emitting layer, a partition wall, and a common electrode may be formed on the passivation layer 180 .

[0219] Reference Fig.14 , in order to receive the driving voltage ELVDD, the stacked layer M1 may further include an extension portion for connection in addition to a portion (overlapping portion) overlapping the third node N3. In example embodiments, the length of the extension portion may be shorter.

[0220] In this example embodiment, referring to Fig.14 , the overlapping portion of the stacked layer M1 is formed to be large enough to completely overlap the portion of the semiconductor layer ACTIVE where it is bent and the additional capacitance portion in a plan view. Therefore, the area where the stacked layer M1 overlaps the semiconductor layer ACTIVE (including the additional capacitance portion) increases, and as a result, the capacitance of the additional storage capacitor increases. The voltage change at the third node N3 is reduced due to the additional storage capacitor, so that the kickback voltage of the third transistor T3 is also reduced.

[0221] In this example embodiment, Fig.14 and Fig.15 In the structure of FIG. 1 , the stacked layer M1 and the parasitic capacitor control pattern 79 exist as layers overlapping the third node N3, and the driving voltage ELVDD is applied to both the stacked layer M1 and the parasitic capacitor control pattern 79. In another embodiment, different voltages may be applied to the stacked layer M1 and the parasitic capacitor control pattern 79.

[0222] In the above description, a structure in which the stacked layer M1 receives the driving voltage ELVDD and the additional capacitance is partially provided in the semiconductor layer ACTIVE has been described.

[0223] In the following, reference will be made to Fig.16 An example embodiment is described in which the stacked layer M1 receives the driving voltage ELVDD but no additional capacitance portion is provided in the semiconductor layer ACTIVE.

[0224] Fig.16 A layout diagram illustrating one pixel region of an organic light emitting diode display according to example embodiments.

[0225] In this example embodiment, referring to Fig.16 The stacked layer M1 is formed of a metal having a conductive property or a semiconductor material corresponding to the metal, and is disposed between a substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE. In the present example embodiment, the stacked layer M1 overlaps a third node N3 at which two transistors T3-1 and T3-2 of the third transistor T3 are connected in a plan view, and may overlap at least some of the other portions of the two transistors T3-1 and T3-2.

[0226] exist Fig.16In the present exemplary embodiment, the semiconductor layer ACTIVE stacked with the stacked layer M1 does not include an additional capacitance portion. Therefore, the semiconductor layer ACTIVE disposed around the third transistor T3 extends in the first direction, passes through the gate electrode G3-1 of the 3-1 transistor T3-1, bends in the second direction, and then extends downward. Here, the portion where the semiconductor layer ACTIVE is bent corresponds to the third node N3 to which the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are connected.

[0227] A portion of the semiconductor layer ACTIVE where it is bent overlaps the stacking layer M1 to form an additional storage capacitor.

[0228] In the present example embodiment, the stacked layer M1 is electrically connected to the parasitic capacitor control pattern 79 through the opening 57 and receives the driving voltage ELVDD, and the parasitic capacitor control pattern 79 is electrically connected to the driving voltage line 172 through the opening 66 .

[0229] In this example embodiment, Fig.16 In the structure of FIG. 1 , the stacked layer M1 and the parasitic capacitor control pattern 79 exist as layers overlapping the third node N3, and the driving voltage ELVDD is applied to both the stacked layer M1 and the parasitic capacitor control pattern 79. In another embodiment, different voltages may be applied to the stacked layer M1 and the parasitic capacitor control pattern 79.

[0230] Combination Fig.16 A cross-sectional view of this example embodiment and Fig.15 Therefore, in Fig.16 In the present exemplary embodiment, the connection structure of the stacked layer M1 and the parasitic capacitor control pattern 79 may be as follows: Fig.15 Same as in.

[0231] In this example embodiment, referring to Fig.16 , in order to receive the driving voltage ELVDD, the stacked layer M1 may further include an extension portion for connection in addition to a portion (overlapping portion) overlapping the third node N3. In example embodiments, the length of the extension portion may be shorter.

[0232] exist Fig.16 In this exemplary embodiment, the additional capacitance portion of the semiconductor layer ACTIVE may be similar to Fig.12 For example, the change in the kickback voltage of the third transistor T3 can be sufficiently reduced by the capacitance additionally formed by the portion of the semiconductor layer ACTIVE where it is bent and the stacking layer M1.

[0233] In the above description, the case where the stacked layer M1 is disposed between the substrate 110 and the semiconductor layer ACTIVE has been mainly described. In another embodiment, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110, but may be disposed above the semiconductor layer ACTIVE, and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor.

[0234] Figures 14 to 16 A structure is shown in which the stacked layer M1 is applied with the driving voltage ELVDD through the opening 57 of the pixel PX close to the stacked layer M1, and the opening 57 may be provided in the pixel PX.

[0235] In the following, reference will be made to Fig.17 and Fig.18 An example embodiment in which the stacked layer M1 is formed of the second gate conductor is described.

[0236] In this example embodiment, Fig.17 and Fig.18 In the embodiment, the stacking layer M1 overlaps the parasitic capacitor control pattern 79 and is integrally formed with the parasitic capacitor control pattern 79 .

[0237] Fig.17 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Fig.18 Shown along Fig.17 A cross-sectional view taken along line XVIII-XVIII.

[0238] In this example embodiment, Fig.17 and Fig.18 The organic light emitting diode display shown in FIG. 1 uses a substrate 110 that may be flexible and may be formed of a flexible material such as plastic or polyimide (PI). A barrier layer 111 is disposed on the substrate 110, and a buffer layer 112 is disposed on the barrier layer 111. The barrier layer 111 and the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, and may also include an organic insulating material such as polyimide and polyacrylic acid (for example, epoxy resin added).

[0239] In the present example embodiment, a semiconductor layer 130 including channels of a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, first electrodes and second electrodes is disposed on the buffer layer 112. A first gate insulating layer 141 covering the semiconductor layer 130 is disposed on the semiconductor layer 130.

[0240] In the present example embodiment, a first gate conductor including gate electrodes (second storage electrode E2 ) of a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , a scan line 151 , a front scan line 152 , and a light emitting control line 153 is disposed on the first gate insulating layer 141 .

[0241] In the present example embodiment, the second gate insulating layer 142 covering the first gate conductor is disposed on the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide.

[0242] In the present exemplary embodiment, a second gate conductor including a storage line 126, a first storage electrode E1, and an initialization voltage line 127 is disposed on the second gate insulating layer 142. An stacked layer M1 integrally formed with the parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142. The parasitic capacitor control pattern 79 is electrically connected to the driving voltage line 172 through the opening 66. Therefore, the stacked layer M1 integrally formed with the parasitic capacitor control pattern 79 is applied with the driving voltage ELVDD.

[0243] In the present example embodiment, an interlayer insulating layer 160 covering the second gate conductor is disposed on the second gate conductor. The interlayer insulating layer 160 may be formed of a material such as silicon nitride, silicon oxide, and aluminum oxide, and may also be formed of an organic insulating material.

[0244] In the present example embodiment, a data conductor including a data line 171 , a driving voltage line 172 , a first data connection member 71 , a second data connection member 72 , and a third data connection member 73 is disposed on the interlayer insulating layer 160 .

[0245] In the present example embodiment, a passivation layer 180 covering the data conductor is disposed on the data conductor. The passivation layer 180 (also referred to as a planarization layer) may include an organic insulating material.

[0246] A pixel electrode, an organic light emitting layer, a partition wall, and a common electrode may be formed on the passivation layer 180 .

[0247] Fig.17 and Fig.18 The present exemplary embodiment shows that the stacked layer M1 is formed of a second gate conductor and receives the driving voltage ELVDD The stacked layer M1 disposed between the semiconductor layer ACTIVE and the substrate 110 is removed and is integrally formed with the parasitic capacitor control pattern 79 .

[0248] In example embodiments, the stacked layer M1 may be formed of a first gate conductor or a data conductor.

[0249] exist Fig.17 and Fig.18 In this example embodiment, the following is used: Figure 3 However, the additional capacitance portion may protrude differently, or may not exist, or the additional capacitance portion may be spaced apart from the semiconductor layer ACTIVE by a predetermined distance.

[0250] exist Figures 13 to 18 In the exemplary embodiment of , only the driving voltage ELVDD is described as a voltage applied to the stacked layer M1, but other voltages (e.g., initialization voltage Vint, common voltage ELVSS, scan signal Sn, front scan signal Sn-1, data voltage Dm, or light emitting control signal EM) may also be applied to the stacked layer M1, and the other voltages may be applied to one terminal of the plurality of transistors T1 to T7 or one terminal of the organic light emitting diode OLED. The threshold voltage Vth of the channel of the transistor overlapped with the stacked layer M1 may be shifted according to the voltage applied to the stacked layer M1. When the voltage applied to the stacked layer M1 is the driving voltage ELVDD and when the voltage applied to the transistor overlapped with the stacked layer M1 is the initialization voltage Vint, the threshold voltage Vth of the transistor may be shifted in the opposite direction. Therefore, by utilizing such characteristics, it is possible to compensate the transistor by applying various voltages to the stacked layer M1 according to the characteristics of the transistor to be compensated. In the exemplary embodiment, the voltage applied to the stacked layer M1 may be determined in consideration of whether the channel of the transistor is p-type or n-type.

[0251] In addition, various other modified embodiments are possible, and will be referred to below. Figures 19 to 21 Another modified embodiment will be described.

[0252] We will now describe Fig.19 and Fig. 20 An example embodiment is shown in FIG.

[0253] Fig.19 A layout diagram showing one pixel region of an organic light emitting diode display according to an example embodiment, Fig. 20 Shown along Fig.19 A sectional view taken along line XX-XX.

[0254] Fig.19 and Fig. 20 Example embodiments of Figures 14 to 18 The exemplary embodiments of the present invention are similar in that the stacked layer M1 is applied with the driving voltage ELVDD, and the difference therebetween is that Fig.19 and Fig. 20 The opening of the present exemplary embodiment that receives the driving voltage ELVDD is not provided in an adjacent pixel but is provided in an upper pixel.

[0255] We will now describe in detail Fig.19 and Fig. 20 An example embodiment is shown in FIG.

[0256] according to Fig.19 and Fig. 20 The stacked layer M1 of the present exemplary embodiment shown in FIG. 1 is disposed between the substrate 110 and the semiconductor layer ACTIVE, as shown in FIG. Figures 14 to 16 Therefore, the stacked layer M1 is disposed between the substrate 110 (which may be flexible and may be formed of plastic or polyimide (PI)) and the semiconductor layer ACTIVE, and is formed of a metal having conductive properties or a semiconductor material corresponding to the metal.

[0257] In the present example embodiment, the stacked layer M1 is applied with the driving voltage ELVDD, for example, the stacked layer M1 is applied with the driving voltage ELVDD through an opening provided in an upper pixel.

[0258] In the present exemplary embodiment, the stacked layer M1 overlaps the third node N3 where the two transistors T3-1 and T3-2 are connected in the third transistor T3 in a plan view, and may overlap at least some of the other portions of the two transistors T3-1 and T3-2. The third node N3 where the two transistors T3-1 and T3-2 are connected also includes an additional capacitance portion, and according to Fig.19 and Fig. 20 The additional capacitance portion of the present exemplary embodiment protrudes upward.

[0259] In this example embodiment, the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portion overlap with the stacking layer M1 to form an additional storage capacitor. The stacking layer M1 is formed to be large enough to completely overlap with the portion where the semiconductor layer ACTIVE is bent and the additional capacitance portion in a plan view. Therefore, the area where the stacking layer M1 overlaps with the semiconductor layer ACTIVE (including the additional capacitance portion) increases, and as a result, the capacitance of the additional storage capacitor increases.

[0260] In this example embodiment, Fig.19 and Fig. 20 As shown in FIG. 1 , when the driving voltage ELVDD is applied to the stacked layer M1, the voltage at one end of the additional storage capacitor is fixed, so that the characteristics of the additional storage capacitor become constant, and thus the third node N3 of the third transistor T3 overlapped with the stacked layer M1 can be further stabilized. Because a high voltage such as the driving voltage ELVDD is applied to the stacked layer M1, the threshold voltage Vth of the third transistor T3 shifts in the negative direction. When the threshold voltage Vth of the third transistor T3 shifts in the negative direction, the kickback voltage of the third transistor T3 using a p-type semiconductor is further reduced, thereby reducing the brightness reduction.

[0261] In the following, Fig.19 and Fig. 20 As shown in FIG. 5 , a structure in which the stacked layer M1 is electrically applied with the driving voltage ELVDD through the opening 57 - 2 provided in the upper pixel will be described in detail.

[0262] For reference, in Fig.19 In FIG. 1 , the stacked layer M1 is shown with thicker lines than other parts so as to more clearly show the structure of the stacked layer M1 .

[0263] according to Fig.19 and Fig. 20 The stacked layer M1 of the present exemplary embodiment includes an extension portion 31-3 overlapping the third node N3 of the third transistor T3 in a plan view, a contact portion 31-1 receiving the driving voltage ELVDD, and a connection portion 31-2 for connecting the extension portion 31-3 and the contact portion 31-1. Fig.19 In the embodiment, the stacked layer M1 is bent to be connected to the driving voltage line 172 .

[0264] according to Fig.19 In the present exemplary embodiment, the driving voltage line 172 further includes a protrusion protruding laterally to be connected to the contact portion 31 - 1 of the stacked layer M1 . The driving voltage line 172 and the stacked layer M1 are electrically connected to each other through a connection member 78 .

[0265] In this example embodiment, referring to Fig. 20 The protrusion of the driving voltage line 172 is connected to one end of a connection member 78 formed of a second gate conductor through the opening 57-1. The other end of the connection member 78 is connected to the contact portion 31-1 of the stacking layer M1 through the opening 57-2 and receives the driving voltage ELVDD.

[0266] exist Fig.19 and Fig. 20 In the present exemplary embodiment, the connection portion 31-2 of the stacking layer M1 overlaps the seventh transistor T7. The portion receiving the driving voltage ELVDD (contact portion 31-1) additionally overlaps the seventh transistor T7 while extending to the third node N3 of the third transistor T3. Depending on the characteristics of the pixel PX, such an additional stacking structure may be omitted.

[0267] Fig.21 A structure is shown in which a portion (contact portion 31 - 1 ) receiving the driving voltage ELVDD while extending to the third node N3 of the third transistor T3 is small, wherein the portion is additionally overlapped with the seventh transistor T7 .

[0268] Fig.21 A layout diagram illustrating one pixel region of an organic light emitting diode display according to example embodiments.

[0269] according to Fig.21 of this example embodiment, with Fig.19 Unlike the exemplary embodiment of FIG. 1 , the connection portion 31 - 2 of the stacked layer M1 is formed along the periphery of the pixel PX to minimize the overlap of the stacked layer M1 with other transistors.

[0270] exist Fig.21 In the present exemplary embodiment, the connection portion 31 - 2 of the stacked layer M1 is formed along a boundary line (indicated by a dotted line) of the pixel PX and does not overlap the channel region of the seventh transistor T7 .

[0271] Fig.21 The example embodiments may have the advantage that undesirable parasitic capacitance may be eliminated.

[0272] In an example embodiment, the stacked layer M1 may not be disposed between the semiconductor layer ACTIVE and the substrate 110, but may be disposed on the semiconductor layer ACTIVE, and may be formed of one of a first gate conductor, a second gate conductor, and a data conductor. In addition, a voltage other than the driving voltage ELVDD may be applied to the stacked layer M1. In addition, the additional capacitance portion formed in the semiconductor layer ACTIVE may not protrude in an upward direction, but may protrude in a lateral direction or in another direction. In addition, the additional capacitance portion may not exist, or the additional capacitance portion may be spaced apart from the semiconductor layer ACTIVE by a predetermined distance.

[0273] exist Figures 19 to 21 In the embodiment, although the stacked layer M1 is applied with the driving voltage ELVDD through the opening 57 - 2 of the pixel adjacent to the pixel PX, the opening 57 - 2 may be provided in a portion of the pixel.

[0274] In the following, reference will be made to Fig. 22 and Fig.23 Effects according to the exemplary embodiment are described.

[0275] Fig. 22 Show Fig.13 Part of the circuit diagram.

[0276] Fig. 22 An additional storage capacitor C2 and a parasitic capacitor C1 are shown in connection with the third transistor T3.

[0277] In this exemplary embodiment, one end of the additional storage capacitor C2 is applied with the driving voltage ELVDD, and the other end of the additional storage capacitor C2 is the node N3. One end of the parasitic capacitor C1 is the node N3, and the other end of the parasitic capacitor C1 is the gate electrode G3-1 of the third transistor T3. Fig. 22The other end of the parasitic capacitor C1 is shown to be only the gate electrode G3 - 1 of the 3 - 1 transistor T3 - 1 , but the other end of the parasitic capacitor C1 may include the gate electrode G3 - 2 of the 3 - 2 transistor T3 - 2 .

[0278] In this structure, Fig. 22 The change (ΔVn3) of the kickback voltage of the third transistor T3 shown in is expressed by Equation 1.

[0279] [Equation 1] ΔVn3=[C1 / (C1+C2)]×ΔV In Equation 1, C1 is the capacitance value of the parasitic capacitor C1, and C2 is the capacitance value of the additional storage capacitor C2.

[0280] The capacitance value of the parasitic capacitor C1 is a value determined when the structure of the third transistor T3 is determined, and therefore, does not change. However, the capacitance value of the additional storage capacitor C2 changes according to the size of the semiconductor layer ACTIVE overlapped with the overlapped layer M1.

[0281] According to Equation 1, it can be seen that the change (ΔVn3) of the kickback voltage of the third transistor T3 decreases as the value of C2 increases. Therefore, the width of the change (ΔVn3) of the kickback voltage of the third transistor T3 can be reduced by increasing the capacitance value of the additional storage capacitor C2, and in an embodiment, an additional capacitance portion may be provided in the semiconductor layer ACTIVE. Therefore, according to example embodiments, the change (ΔVn3) of the kickback voltage of the third transistor T3 is reduced, thereby improving display quality.

[0282] although Fig. 22 Shows Fig.13 part of the circuit diagram, but because Fig.13 A state in which only one electrode of the additional storage capacitor is floated is shown, so the variation (ΔVn3) of the kickback voltage of the third transistor T3 does not differ in Equation 1. Therefore, the same effect is obtained also in the present exemplary embodiment in which the stacked layer M1 is floated.

[0283] In the following, reference will be made to Fig.23 The degree of brightness reduction is compared using various comparative examples (Ref) and example embodiments.

[0284] Fig.23 The experimental results of brightness reduction are shown.

[0285] exist Fig.23 , the extent of brightness reduction in two comparative examples (Ref and T4 leakage) and two example embodiments (DY+N3 shielding and EG+N3 shielding) is compared.

[0286] Comparative Example 1 (Ref) has a structure in which there is no layer overlapping the third transistor T3, and neither the overlapping layer M1 nor the parasitic capacitor control pattern 79 is formed. In Comparative Example 1 (Ref), although the third transistor T3 is formed of two transistors connected in series, the fourth transistor T4 is formed of one transistor and is not formed of two transistors connected in series.

[0287] In Comparative Example 2 (T4 Leakage), the fourth transistor T4 of Comparative Example 1 (Ref) is also formed of two transistors connected in series, and the channel length of the third transistor T3 and the channel length of the fourth transistor T4 are equal to each other. This is a case where only the leakage current in the third transistor T3 and the fourth transistor T4 is reduced.

[0288] Example Embodiment 1 (DY+N3 Shielding) further includes a layer stacked with the third transistor T3 in Comparative Example 1 (Ref), wherein a stacked layer M1 and a parasitic capacitor control pattern 79 are formed.

[0289] Example Embodiment 2 (EG+N3 shielding) further includes a layer stacked with the third transistor T3 in Comparative Example 2 (T4 leakage), wherein a stacked layer M1 and a parasitic capacitor control pattern 79 are formed.

[0290] like Fig.23 As shown in , it can be confirmed that the brightness reduction is reduced by including a layer overlapping the third transistor T3. In addition, it can be seen that by reducing the leakage current of the third transistor T3 and the fourth transistor T4, the brightness reduction effect is further enhanced. In an embodiment, the third transistor T3 and the fourth transistor T4 may include two transistors connected in series to each other.

[0291] By way of summary and review, generally, an organic light emitting diode display includes a substrate, a plurality of thin film transistors disposed on the substrate, a plurality of insulating layers disposed between wirings for constructing the thin film transistors, and an organic light emitting element connected to the thin film transistor. A flexible organic light emitting diode display has been developed, which includes a flexible substrate containing a polymer material as a substrate and capable of being fully bent. The organic light emitting diode display includes a plurality of pixels, and a plurality of transistors included in each pixel may include a polycrystalline semiconductor or an oxide semiconductor.

[0292] As described above, the embodiment relates to a flexible organic light emitting diode display. The embodiment can provide a flexible organic light emitting diode display in which even if a transistor is formed on a flexible substrate, a change in a kickback voltage of the transistor can be reduced and display quality can be not degraded. The embodiment can provide an organic light emitting diode display that can prevent residual afterimages from remaining when white and black are alternately displayed by increasing the storage capacitance of a specific transistor to reduce a change in a characteristic (e.g., kickback voltage) of the corresponding transistor, thereby improving the display quality of the organic light emitting diode display.

[0293] <Description of symbols> 110: base 111: barrier layer M1: stacking layer 112: buffer layer 130: semiconductor layer 141: first gate insulating layer 142: second gate insulating layer 160: interlayer insulating layer 180: passivation layer N3: third node 56: Opening 57, 61-69, 81: Opening A1, A2: Additional capacitance section 79: Parasitic capacitor control pattern 126: storage line 127: initialization voltage line 151: Scan line 152: Front scan line 153: Light emission control line 155: Gate electrode 158: bypass control line 171: data line 172: driving voltage line 71, 72, 73: data connection line 741: common voltage lines E1, E2: storage electrodes 78: Connecting member 31-1: Contact portion 31-2: Connecting part 31-3: Extending part T1, T2, T3, T4, T5, T6, T7: transistors.

[0294] Example embodiments have been disclosed herein, and although specific terms are employed, the specific terms are used and will be interpreted only in a general and descriptive sense, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, as of the date of filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. An organic light emitting diode display, comprising: A first transistor is disposed on a substrate, wherein the first transistor comprises a gate electrode, an input electrode and an output electrode; a second transistor electrically connected to a scan line, a data line and the input electrode of the first transistor; a third transistor including a gate electrode, a first electrode electrically connected to the output electrode of the first transistor, and a second electrode electrically connected to the gate electrode of the first transistor; a fourth transistor connected to an initialization voltage line and initializing the gate electrode of the first transistor; as well as a stacking layer, stacked with the gate electrode of the third transistor in a plan view, in, The stacked layer is disposed between the substrate and the semiconductor layer of the third transistor, and The stacking layer overlaps the initialization voltage line in a plan view.

2. The organic light emitting diode display according to claim 1, wherein: At an overlapping portion of the stacking layer and the initialization voltage line, an extending direction of the stacking layer and an extending direction of the initialization voltage line are substantially perpendicular.

3. The organic light emitting diode display according to claim 1, wherein: The stacked layers include a metal having conductive properties or a semiconductor material having conductive properties.

4. The organic light emitting diode display according to claim 1, wherein: The stacking layer overlaps a channel of the semiconductor layer of the third transistor in a plan view.

5. The organic light emitting diode display according to claim 4, wherein: The semiconductor layer of the third transistor includes an oxide semiconductor.

6. The organic light emitting diode display according to claim 4, wherein: An area of ​​the stacked layer is larger than an area of ​​the channel of the semiconductor layer of the third transistor.

7. The organic light emitting diode display according to claim 1, wherein: An area of ​​the stacked layer is larger than an area of ​​the gate electrode of the third transistor.

8. The organic light emitting diode display according to claim 1, wherein: The stacked layers are electrically connected to an element having a voltage level of a driving voltage.

9. The organic light emitting diode display according to claim 1, further comprising a storage capacitor storing a voltage of the gate electrode of the first transistor, in, The fourth transistor initializes the storage capacitor. 10 . The organic light emitting diode display of claim 1 , further comprising a fifth transistor transmitting a driving voltage to the input electrode of the first transistor. 11 . The organic light emitting diode display of claim 1 , further comprising a sixth transistor transmitting a driving current from the first transistor to a light emitting diode. 12 . The organic light emitting diode display according to claim 11 , further comprising a seventh transistor that initializes an anode of the light emitting diode.

13. The organic light emitting diode display according to claim 1, wherein: The stacked layers provide a buffer capacitance that buffers voltage changes to reduce an afterimage effect of the organic light emitting diode display.

14. An organic light emitting diode display, comprising: A light emitting diode having an anode; a first transistor, outputting a driving current to the anode of the light emitting diode and disposed on a substrate, wherein the first transistor includes a gate electrode, an input electrode and an output electrode; a second transistor electrically connected to a scan line, a data line and the input electrode of the first transistor; a third transistor including a gate electrode, a first electrode electrically connected to the output electrode of the first transistor, and a second electrode electrically connected to the gate electrode of the first transistor; a seventh transistor connected to an initialization voltage line and initializing the anode of the light emitting diode; as well as a stacking layer, stacked with the gate electrode of the third transistor in a plan view, in, The stacked layer is disposed between the substrate and the semiconductor layer of the third transistor, and The stacking layer overlaps the initialization voltage line in a plan view.

15. The organic light emitting diode display according to claim 14, wherein: At an overlapping portion of the stacking layer and the initialization voltage line, an extending direction of the stacking layer and an extending direction of the initialization voltage line are substantially perpendicular.

16. The organic light emitting diode display according to claim 14, wherein: The stacked layers include a metal having conductive properties or a semiconductor material having conductive properties.

17. The organic light emitting diode display according to claim 14, wherein: The stacking layer overlaps a channel of the semiconductor layer of the third transistor in a plan view.

18. The organic light emitting diode display according to claim 17, wherein: The semiconductor layer of the third transistor includes an oxide semiconductor.

19. The organic light emitting diode display according to claim 14, wherein: The stacked layers are electrically connected to an element having a voltage level of a driving voltage.

20. The organic light emitting diode display according to claim 14, further comprising: a storage capacitor storing a voltage of the gate electrode of the first transistor; a fourth transistor, initializing the gate electrode of the first transistor and the storage capacitor; a fifth transistor, transmitting a driving voltage to the input electrode of the first transistor; as well as A sixth transistor transmits the driving current from the first transistor to the anode of the light emitting diode.

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