Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer, the driving structure layer comprises a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit, the light-emitting structure layer comprises a first light-emitting device, a second light-emitting device and a third light-emitting device, the first light-emitting device is connected with the first pixel driving circuit, and the second light-emitting device is connected with the third pixel driving circuit. The second light-emitting device is connected with the second pixel driving circuit, and the third light-emitting device is connected with the third pixel driving circuit; the driving structure layer further comprises a first power line, a second power line, a third power line and a connecting line, the first power line is connected with the first pixel driving circuit, the second power line is connected with the second pixel driving circuit, and the third power line is connected with the third pixel driving circuit; the connecting line is connected with the first power line, the second power line or the third power line, and a grid communication structure for transmitting power signals is formed on the display substrate. The power consumption is effectively reduced.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing display devices have problems such as high power consumption. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a method for preparing the same, and a display device, so as to solve the problems of high power consumption in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, comprising a display area and a binding area arranged on at least one side of the display area, the display area comprising a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the circuit unit at least comprising a pixel driving circuit, the light-emitting structure layer comprising a plurality of light-emitting units, the light-emitting units at least comprising light-emitting devices; the plurality of circuit units at least comprising a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit, the plurality of light-emitting units at least comprising a first light-emitting unit provided with a first light-emitting device, a second light-emitting unit provided with a second light-emitting device, and a third light-emitting unit provided with a third light-emitting device, the first light-emitting device, the second light-emitting device, the second light-emitting device, the third light-emitting device, The device and the third light-emitting device emit light of different colors; the first light-emitting device is connected to the first pixel driving circuit, the second light-emitting device is connected to the second pixel driving circuit, and the third light-emitting device is connected to the third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along the first direction, and a first power line, a second power line and a third power line extending at least partially along the second direction, the first direction and the second direction intersect, and the first power line, the second power line and the third power line have different potentials; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line or the third power line, forming a grid connection structure for transmitting power signals on the display substrate.

[0007] In an exemplary embodiment, the first power line and the third power line are disposed in the same unit column, or the first power line and the third power line are disposed in different unit columns.

[0008] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer includes a plurality of conductive layers, and any one or more of the first power line, the second power line, and the third power line are disposed in at least one conductive layer.

[0009] In an exemplary embodiment, at least one connecting line includes any one or more of a first connecting line, a second connecting line and a third connecting line; the first connecting line is connected to the first power line to form a grid connection structure for transmitting a first power signal on the display substrate; the second connecting line is connected to the second power line to form a grid connection structure for transmitting a second power signal on the display substrate; the third connecting line is connected to the third power line to form a grid connection structure for transmitting a third power signal on the display substrate.

[0010] In an exemplary embodiment, any one or more of the first connection line, the second connection line, and the third connection line are disposed in at least one cell row.

[0011] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer includes a plurality of conductive layers, and any one or more of the first connecting line, the second connecting line and the third electrical connection are disposed in at least one conductive layer.

[0012] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer includes multiple conductive layers, and the first power line and the first connecting line are arranged in different conductive layers; or, the second power line and the second connecting line are arranged in different conductive layers; or, the third power line and the third connecting line are arranged in different conductive layers.

[0013] In an exemplary embodiment, the multiple circuit units also include a fourth circuit unit provided with a fourth pixel driving circuit, the multiple light-emitting units also include a fourth light-emitting unit provided with a fourth light-emitting device, the fourth light-emitting unit and the second light-emitting device emit light of the same color, the driving structure layer also includes a fourth power line and a fourth connecting line, the fourth power line is connected to the fourth pixel driving circuit, and the fourth connecting line is connected to the fourth power line, forming a grid connection structure for transmitting a fourth power signal on the display substrate.

[0014] In an exemplary embodiment, the second connection line is further connected to the fourth power line, and the fourth connection line is further connected to the second power line.

[0015] In an exemplary embodiment, the driving structure layer also includes a first data signal line, a second data signal line and a third data signal line, the first data signal line is connected to the first pixel driving circuit, the second data signal line is connected to the second pixel driving circuit, and the third data signal line is connected to the third pixel driving circuit; any one or more of the first data signal line, the second data signal line and the third data signal line are arranged in at least one unit column.

[0016] In an exemplary embodiment, the driving structure layer further includes a fifth power line, a sixth power line and a seventh power line, the fifth power line being connected to the cathode of the first light-emitting device, the sixth power line being connected to the cathode of the second light-emitting device, and the seventh power line being connected to the cathode of the third light-emitting device.

[0017] In an exemplary embodiment, in a direction perpendicular to the base, the display substrate includes a plurality of conductive layers, an anode switch line is provided in any one or more of the conductive layers, the first power line and the third power line are arranged in different unit columns, the first pixel driving circuit is connected to the first light-emitting device through the anode switch line, and / or the third pixel driving circuit is connected to the third light-emitting device through the anode switch line.

[0018] In an exemplary embodiment, the first light-emitting device includes at least a first anode, the first anode includes at least a main body and a connecting portion, and an orthographic projection of at least part of the main body of the first anode on the substrate plane does not overlap with an orthographic projection of the first pixel driving circuit on the substrate plane, a first end of the anode adapter is connected to the main body of the first anode, a second end of the anode adapter is connected to the connecting portion of the first anode, and the connecting portion of the first anode is connected to the first pixel driving circuit; and / or, the third light-emitting device includes at least a third anode, the third anode includes at least a main body and a connecting portion, and an orthographic projection of at least part of the main body of the third anode on the substrate plane does not overlap with an orthographic projection of the third pixel driving circuit on the substrate plane, a first end of the anode adapter is connected to the main body of the third anode, a second end of the anode adapter is connected to the connecting portion of the third anode, and the connecting portion of the third anode is connected to the third pixel driving circuit.

[0019] In an exemplary embodiment, the orthographic projection of at least part of the main body of the first anode on the substrate plane at least partially overlaps with the orthographic projection of the third pixel driving circuit on the substrate plane; and / or, the orthographic projection of at least part of the main body of the third anode on the substrate plane at least partially overlaps with the orthographic projection of the first pixel driving circuit on the substrate plane.

[0020] In an exemplary embodiment, the orthographic projection of the anode switching line on the substrate plane at least partially overlaps with the orthographic projection of the second pixel driving circuit on the substrate plane; and / or, the orthographic projection of the anode switching line on the substrate plane at least partially overlaps with the orthographic projection of the fourth pixel driving circuit on the substrate plane.

[0021] In an exemplary embodiment, the first light-emitting device includes at least a first anode, the first anode includes at least a main body and a connecting portion, a first end of the connecting portion of the first anode is connected to the main body of the first anode, a second end of the connecting portion of the first anode is connected to the first pixel driving circuit, and an orthographic projection of at least part of the main body of the first anode on the substrate plane at least partially overlaps with an orthographic projection of the first pixel driving circuit on the substrate plane; and / or, the third light-emitting device includes at least a third anode, the third anode includes at least a main body and a connecting portion, a first end of the connecting portion of the third anode is connected to the main body of the third anode, a second end of the connecting portion of the third anode is connected to the third pixel driving circuit, and an orthographic projection of at least part of the main body of the third anode on the substrate plane at least partially overlaps with an orthographic projection of the third pixel driving circuit on the substrate plane.

[0022] In an exemplary embodiment, the binding area includes at least a first high potential power lead, a second high potential power lead and a third high potential power lead, the first power lead is connected to the first high potential power lead, the second power lead is connected to the second high potential power lead, and the third power lead is connected to the third high potential power lead.

[0023] In an exemplary embodiment, the display substrate further includes a flexible circuit board bound and connected to the binding area, the flexible circuit board at least including a control circuit, a plurality of circuit board pads and a plurality of power transmission lines, the control circuit at least including a first control circuit providing a first power signal, a second control circuit providing a second power signal and a third control circuit providing a third power signal, the plurality of circuit board pads at least include a first pad, a second pad and a third pad, and the plurality of power transmission lines at least include a first transmission line, a second transmission line and a third transmission line; the first control circuit is connected to a first high potential power lead of the binding area through the first transmission line and the first pad, the second control circuit is connected to a second high potential power lead of the binding area through the second transmission line and the second pad, and the third control circuit is connected to a third high potential power lead of the binding area through the third transmission line and the third pad.

[0024] In an exemplary embodiment, the display substrate further includes a flexible circuit board bound and connected to the binding area, the flexible circuit board at least including a control circuit, a plurality of circuit board pads and a plurality of power transmission lines, the control circuit at least including a management integrated circuit, the management integrated circuit at least including a first signal channel providing a first power signal, a second signal channel providing a second power signal and a third signal channel providing a third power signal, the plurality of circuit board pads at least including a first pad, a second pad and a third pad, and the plurality of power transmission lines at least including a first transmission line, a second transmission line and a third transmission line; the first signal channel is connected to a first high potential power lead of the binding area through the first transmission line and the first pad, the second signal channel is connected to a second high potential power lead of the binding area through the second transmission line and the second pad, and the third signal channel is connected to a third high potential power lead of the binding area through the third transmission line and the third pad.

[0025] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0026] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising a display area and a binding area disposed on at least one side of the display area, the preparation method comprising:

[0027] A driving structure layer is formed on the substrate of the display area, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of circuit units at least include a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along a first direction, and a first power line, a second power line, and a third power line extending at least partially along a second direction, the first direction intersects with the second direction, and the first power line, the second power line, and the third power line have different potentials; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line, or the third power line, to form a grid connection structure for transmitting a power signal on the display substrate;

[0028] A light-emitting structure layer is formed on the driving structure layer, the light-emitting structure layer includes a plurality of light-emitting units, the plurality of light-emitting units include at least a first light-emitting unit provided with a first light-emitting device, a second light-emitting unit provided with a second light-emitting device, and a third light-emitting unit provided with a third light-emitting device, the first light-emitting device, the second light-emitting device, and the third light-emitting device emit light of different colors; the first light-emitting device is connected to the first pixel driving circuit, the second light-emitting device is connected to the second pixel driving circuit, and the third light-emitting device is connected to the third pixel driving circuit.

[0029] The embodiments of the present disclosure provide a display substrate and a preparation method thereof, and a display device. Through the independent design of high-potential power lines, a first power line, a second power line, and a third power line are used to provide different power signals to a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit, respectively, so that the saturation region margin voltages of the first light-emitting device, the second light-emitting device, and the third light-emitting device are basically the same, thereby effectively reducing power consumption.

[0030] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0032] Figure 1 is a structural schematic diagram of a display device;

[0033] Figure 2 It is a structural schematic diagram of a display substrate;

[0034] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0035] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0036] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0037] FIG. 6A to FIG. 6C A schematic diagram of the connection between a circuit unit and a light-emitting unit disclosed in the present invention;

[0038] Figure 7 This is a schematic diagram of connecting power lines and connecting lines in a display substrate disclosed in the present invention;

[0039] Fig. 8A and Figure 8BThis is a schematic diagram of a display substrate after a first semiconductor layer pattern is formed on the display substrate of the present disclosure;

[0040] 9A to 9C This is a schematic diagram of a display substrate after a first conductive layer pattern is formed on the display substrate of the present disclosure;

[0041] FIG. 10A to FIG. 10C This is a schematic diagram of a display substrate after a second conductive layer pattern is formed on the display substrate of the present disclosure;

[0042] FIG. 11A to FIG. 11C This is a schematic diagram of a display substrate disclosed herein after a second semiconductor layer pattern is formed;

[0043] FIG. 12A to FIG. 12C This is a schematic diagram of a display substrate after a third conductive layer pattern is formed on the display substrate of the present disclosure;

[0044] Fig.13A and Fig. 13B This is a schematic diagram of a display substrate after a sixth insulating layer pattern is formed on the display substrate of the present disclosure;

[0045] FIG. 14A to FIG. 14C This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed on the display substrate of the present disclosure;

[0046] Fig.15A and Fig. 15B This is a schematic diagram of a display substrate after a first flat layer pattern is formed in the present disclosure;

[0047] FIG. 16A to FIG. 16C It is a schematic diagram of a display substrate after a fifth conductive layer pattern is formed on the display substrate of the present disclosure;

[0048] FIG. 16D to FIG. 16F This is a connection diagram of data signal lines according to an embodiment of the present disclosure;

[0049] Fig.17A and Fig. 17B This is a schematic diagram of a display substrate after a second flat layer pattern is formed on the display substrate of the present disclosure;

[0050] 18A to 18C This is a schematic diagram of a display substrate disclosed in the present invention after a sixth conductive layer pattern is formed;

[0051] Fig.18D This is a connection diagram of a connection line according to an embodiment of the present disclosure;

[0052] Fig.19A and Fig.19B This is a schematic diagram of a display substrate after a third flat layer pattern is formed on the display substrate of the present disclosure;

[0053] Fig. 20A and Fig. 20B This is a schematic diagram of a display substrate after an anode conductive layer pattern is formed in the present disclosure;

[0054] FIG. 21A to FIG. 21C This is a schematic diagram of another connection between a circuit unit and a light-emitting unit disclosed in the present invention;

[0055] Fig. 22 This is another schematic diagram of connecting power lines and connecting lines in a display substrate disclosed in the present invention;

[0056] FIG. 23A to FIG. 23C It is a schematic diagram of another display substrate of the present disclosure after a fourth conductive layer pattern is formed;

[0057] Fig.24A and Fig. 24B It is a schematic diagram of another display substrate of the present disclosure after a first flat layer pattern is formed;

[0058] FIG. 25A to FIG. 25C It is a schematic diagram of another display substrate of the present disclosure after a fifth conductive layer pattern is formed;

[0059] Fig.26A and Fig.26B It is a schematic diagram of another display substrate of the present disclosure after forming a second flat layer pattern;

[0060] FIG. 27A to FIG. 27C It is a schematic diagram of another display substrate of the present disclosure after a sixth conductive layer pattern is formed;

[0061] Fig.28A and Fig.28B It is a schematic diagram of another display substrate of the present disclosure after a third flat layer pattern is formed;

[0062] Fig.29A and Fig.29B It is a schematic diagram of another display substrate after forming an anode conductive layer pattern in the present disclosure;

[0063] Fig.29C This is a connection diagram of an anode adapter cable according to an embodiment of the present disclosure;

[0064] FIG. 30A to FIG. 30C This is a schematic diagram of connection between another circuit unit and a light-emitting unit disclosed in the present invention;

[0065] Fig.31 This is a schematic diagram showing the connection between power lines and connecting lines in another display substrate disclosed in the present invention;

[0066] FIG. 32A to FIG. 32C This is a schematic diagram of connection between another circuit unit and a light-emitting unit disclosed in the present invention;

[0067] Fig.33 This is a schematic diagram showing the connection between power lines and connecting lines in another display substrate disclosed in the present invention;

[0068] FIG. 34A to FIG. 34C A schematic diagram of a connection between a circuit unit and a light-emitting unit disclosed in the present invention

[0069] Fig.35 This is a wiring diagram of power lines and connecting lines in another display substrate disclosed in the present invention;

[0070] Fig.36 A schematic diagram of a power supply routing in a binding area of ​​an exemplary embodiment of the present disclosure;

[0071] Fig.37 A schematic diagram of a power supply line in a flexible circuit board according to an exemplary embodiment of the present disclosure;

[0072] Fig.38 A schematic diagram of power routing in another flexible circuit board according to an exemplary embodiment of the present disclosure;

[0073] Fig.39 A schematic diagram of the connection between a low potential power supply line and a low potential connection line in a display substrate disclosed in the present invention;

[0074] Fig.40 The diagram is a schematic diagram of a power supply line in a border area of ​​an exemplary embodiment of the present disclosure.

[0075] Description of reference numerals:

[0076] 11—first active layer; 12—second active layer; 13—third active layer;

[0077] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0078] 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line;

[0079] 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line;

[0080] 25—luminous signal line; 26—shielding line; 31—first initial signal line;

[0081] 32—second initial signal line; 33—third initial signal line; 41—first initial connection line;

[0082] 42—second initial connection line; 43—first initial connection bar; 44—second initial connection bar;

[0083] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0084] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0085] 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode;

[0086] 61—eleventh connecting electrode; 62—data signal line; 63—anode connecting electrode;

[0087] 71—first electrode plate; 72—second electrode plate; 73—opening;

[0088] 81—first power line; 82—second power line; 83—third power line;

[0089] 84—fourth power line; 85—fifth power line; 86—sixth power line;

[0090] 87—seventh power line; 90A—first anode; 90B—second anode;

[0091] 90C—third anode; 90D—fourth anode; 91—first connecting line;

[0092] 92—second connecting line; 93—third connecting line; 94—fourth connecting line;

[0093] 95—fifth connecting line; 96—sixth connecting line; 97—seventh connecting line;

[0094] 100—display area; 101—substrate; 102—driving circuit layer;

[0095] 103—light emitting structure layer; 104—encapsulation structure layer; 110—main body;

[0096] 120—connection part; 130—anode adapter wire; 200—binding area;

[0097] 201—a first high potential power lead; 202—a second high potential power lead; 203—a third high potential power lead;

[0098] 210—control circuit; 211—first control circuit; 212—second control circuit;

[0099] 213—third control circuit; 214—management integrated circuit; 214A—first signal channel;

[0100] 214B—second signal channel; 214C—third signal channel; 221—first pad;

[0101] 222—second pad; 223—third pad; 231—first transmission line;

[0102] 232—second transmission line; 233—third transmission line; 300—border area;

[0103] 301—a first low-potential power lead; 302—a second low-potential power lead; 303—a third low-potential power lead;

[0104] 310 - first cathode line; 320 - second cathode line; 330 - third cathode line. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0106] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0107] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0108] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0109] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0110] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0111] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0112] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0113] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0114] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0115] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0116] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0117] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines DATA1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0118] Figure 2 FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels being configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled up.

[0119] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead lines. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include at least an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include at least a plurality of binding pads (Bonding Pad), which are configured to be bound and connected to an external flexible printed circuit (FPC).

[0120] In an exemplary embodiment, the frame region 300 may include at least a circuit region connected to the display region 100 , and may include at least a gate driving circuit connected to a pixel driving circuit in the display region 100 .

[0121] In an exemplary embodiment, at least one isolation dam may be provided in the binding area 200 and the border area 300. The isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area or the border area.

[0122] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a light-emitting signal line, a data signal line, and a high-potential power line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0123] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a first green sub-pixel (G1) emitting green light, the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light, and the fourth sub-pixel P4 may be a second green sub-pixel (G2) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In some other exemplary embodiments, the four sub-pixels may be arranged in horizontal parallel, vertical parallel or square manner, etc., which is not limited in the present disclosure.

[0124] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or in a triangle arrangement, etc., which is not limited in the present disclosure.

[0125] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0126] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, and the light-emitting device may include at least an anode, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode and the cathode respectively, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0127] Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, fourth scanning signal line S4, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and high potential power line VDD).

[0128] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fourth node N4 is also connected to the anode of the light emitting device EL.

[0129] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the high potential power line VDD.

[0130] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor, the gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The fourth transistor T4 may be referred to as a data writing transistor, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fifth transistor T5 can be called a first light emission control transistor, the gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is connected to the high potential power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The sixth transistor T6 can be called a second light emission control transistor, the gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. The seventh transistor T7 can be called a second initialization transistor, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The eighth transistor T8 can be called a third initialization transistor, the gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0131] In an exemplary embodiment, the light emitting device EL may be an OLED including a stacked anode (first pole), an organic light emitting layer and a cathode (second pole), or may be a QLED including a stacked anode (first pole), a quantum dot light emitting layer and a cathode (second pole).

[0132] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the low potential power line VSS.

[0133] In an exemplary embodiment, the signal of the high potential power line VDD is a high level signal that is continuously provided, and the signal of the low potential power line VSS is a low level signal that is continuously provided.

[0134] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0135] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Low-temperature polysilicon transistors and metal oxide transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0136] In an exemplary embodiment, the second transistor T2 may be an N-type transistor of metal oxide, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be a P-type transistor of low temperature polysilicon.

[0137] In an exemplary embodiment, Figure 5 The working process of the pixel driving circuit shown may include:

[0138] The first stage is called the reset stage of the second node N2 and the fourth node N4. The signal of the second scanning signal line S2 is a low level signal, and the signals of the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line EM are high level signals.

[0139] The signal of the second scanning signal line S2 is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8. The signal of the second initial signal line INIT2 is provided to the fourth node N4, and the first electrode of the light-emitting device EL is initialized (reset), and the original charge in the first electrode of the light-emitting device EL is cleared, so that the potential of the fourth node N4 is Vinit2. The signal of the third initial signal line INIT3 is provided to the second node N2, and the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared, so that the potential of the second node N2 is Vinit3. In this stage, the third transistor T3 is turned on. The signal of the fourth scanning signal line S4 is a high-level signal, and the second transistor T2 is turned on. The signal of the second node N2 is provided to the first node N1 and the third node N3, and the first node N1 and the third node N3 are initialized. The signals of the first scanning signal line S1, the third scanning signal line S3 and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0140] The second stage is called the first node N1 reset stage. The signal of the third scan signal line S3 is a low level signal, and the signals of the first scan signal line S1, the second scan signal line S2, the fourth scan signal line S4 and the light emitting signal line EM are high level signals.

[0141] The signal of the third scan signal line S3 becomes a low-level signal, turning on the first transistor T1. Since the signal of the fourth scan signal line S4 is a high-level signal at this stage, the second transistor T2 is turned on. Therefore, the signal of the first initial signal line INIT1 is provided to the first node N1 through the third node N3, and the first node N1 is reset again. The potential of the first node N1 is Vinit1. The signals of the first scan signal line S1, the second scan signal line S2 and the light-emitting signal line EM are high-level signals, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0142] The third stage is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, and the signals of the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4 and the luminous signal line EM are high level signals.

[0143] The signal of the first scanning signal line S1 is a low-level signal to turn on the fourth transistor T4. Since the third transistor T3 is continuously turned on at this stage, the signal of the fourth scanning signal line S4 is a high-level signal to turn on the second transistor T2. Therefore, the data voltage output by the data signal line DATA is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line DATA, and Vth is the threshold voltage of the third transistor T3. The signals of the second scanning signal line S2, the third scanning signal line S3 and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0144] The fourth stage is called the continuous compensation stage. The signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line EM are high level signals.

[0145] The signal of the fourth scan signal line S4 is a high level signal, the second transistor T2 is continuously turned on, the signals of the first scan signal line S1, the third scan signal line S3, the second scan signal line S2 and the light emitting signal line EM are high level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. Although the signal of the data signal line DATA stops writing, the second node N2 is still provided to the first node N1 through the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the threshold voltage of the third transistor T3 is continuously compensated.

[0146] The fifth stage is called the second node N2 and the fourth node N4 point reset stage. The signals of the second scanning signal line S2 and the fourth scanning signal line S4 are low level signals, and the signals of the first scanning signal line S1, the third scanning signal line S3 and the light emitting signal line EM are high level signals.

[0147] The signals of the first scanning signal line S1, the third scanning signal line S3 and the light emitting signal line EM are high level signals, the signal of the fourth scanning signal line S4 is a low level signal, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all turned off. The signal of the second scanning signal line S2 is a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and since the third transistor T3 is continuously turned on at this stage, the signal of the third initial signal line INIT3 is written into the second node N2 and the third node N3, and the signal of the second initial signal line INIT2 is written into the fourth node N3, and the second node N2, the third node N3 and the fourth node N4 are reset respectively, and the potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3 and the fourth node N4 can eliminate the hysteresis deviation caused by the grayscale difference between adjacent pixels, reduce the hysteresis deviation, and can also reset the OLED anode periodically to improve low-frequency flicker.

[0148] The sixth stage is called the light-emitting stage. The signals of the light-emitting signal line EM and the fourth scanning signal line S4 are low-level signals, and the signals of the first scanning signal line S1, the second scanning signal line S2 and the third scanning signal line S3 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the high-potential power supply line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting device EL to emit light.

[0149] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0150] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0151] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the high potential power supply line VDD.

[0152] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, which can ensure the uniform display brightness of the display product and improve the display effect of the entire display product.

[0153] An exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting device, the light-emitting device is connected to a pixel driving circuit of a corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to a current output by the connected pixel driving circuit.

[0154] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0155] In an exemplary embodiment, a display substrate provided by an exemplary embodiment of the present disclosure includes a display area and a binding area arranged on at least one side of the display area, the display area includes a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the circuit unit includes at least a pixel driving circuit, the light-emitting structure layer includes a plurality of light-emitting units, the light-emitting units include at least a light-emitting device; the plurality of circuit units include at least a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit, the plurality of light-emitting units include at least a first light-emitting unit provided with a first light-emitting device, a second light-emitting unit provided with a second light-emitting device, and a third light-emitting unit provided with a third light-emitting device, the first light-emitting device, the second light-emitting device, the second light-emitting device, and the third light-emitting device. The first light emitting device and the third light emitting device emit light of different colors; the first light emitting device is connected to the first pixel driving circuit, the second light emitting device is connected to the second pixel driving circuit, and the third light emitting device is connected to the third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along the first direction, and a first power line, a second power line and a third power line extending at least partially along the second direction, the first direction and the second direction intersect, the first power line, the second power line and the third power line have different potentials, and are all high-potential power lines; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line or the third power line, forming a grid connection structure for transmitting power signals on the display substrate.

[0156] In an exemplary embodiment, the first power line and the third power line are disposed in the same unit column, or the first power line and the third power line are disposed in different unit columns.

[0157] In an exemplary embodiment, at least one connecting line includes any one or more of a first connecting line, a second connecting line and a third connecting line; the first connecting line is connected to the first power line to form a grid connection structure for transmitting a first power signal on the display substrate; the second connecting line is connected to the second power line to form a grid connection structure for transmitting a second power signal on the display substrate; the third connecting line is connected to the third power line to form a grid connection structure for transmitting a third power signal on the display substrate.

[0158] In an exemplary embodiment, the multiple circuit units also include a fourth circuit unit provided with a fourth pixel driving circuit, the multiple light-emitting units also include a fourth light-emitting unit provided with a fourth light-emitting device, the fourth light-emitting unit and the second light-emitting device emit light of the same color, the driving structure layer also includes a fourth power line and a fourth connecting line, the fourth power line is connected to the fourth pixel driving circuit, and the fourth connecting line is connected to the fourth power line, forming a grid connection structure for transmitting a fourth power signal on the display substrate.

[0159] In an exemplary embodiment, the second connection line is further connected to the fourth power line, and the fourth connection line is further connected to the second power line.

[0160] In an exemplary embodiment, the first power line and the third power line are arranged in different unit columns, the driving structure layer also includes an anode switching line, the first pixel driving circuit is connected to the first light-emitting device through the anode switching line, and / or the third pixel driving circuit is connected to the third light-emitting device through the anode switching line.

[0161] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer includes a plurality of conductive layers, and the anode switching wire is disposed in any one of the conductive layers or in the plurality of conductive layers.

[0162] Fig. 6A FIG. 1 is a schematic diagram of an arrangement of a circuit unit according to an exemplary embodiment of the present disclosure. Figure 6B is a schematic diagram of the arrangement of a light-emitting unit according to an exemplary embodiment of the present disclosure, Figure 6C FIG. 1 is a schematic diagram showing the connection between a circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure. Fig. 6A , Figure 6B and Figure 6C As shown, on a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, the plurality of circuit units may constitute a plurality of unit rows and a plurality of unit columns, the unit rows may include a plurality of circuit units sequentially arranged along a first direction X, the unit columns may include a plurality of circuit units sequentially arranged along a second direction Y, and the circuit units may include at least a pixel driving circuit. The light-emitting structure layer may include a plurality of light-emitting units, the plurality of light-emitting units may constitute a plurality of light-emitting rows and a plurality of light-emitting columns, the light-emitting rows may include a plurality of light-emitting units sequentially arranged along a first direction X, the light-emitting columns may include a plurality of light-emitting units sequentially arranged along a second direction Y, and the light-emitting units may include at least light-emitting devices. In an exemplary embodiment, the first direction X intersects with the second direction Y. In an exemplary embodiment, the direction of the unit rows may be the first direction X, and the direction of the unit columns may be the second direction Y.

[0163] In an exemplary embodiment, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, a third circuit unit Q3, and a fourth circuit unit Q4. In a unit row, the first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 may be periodically arranged in a first direction X, and the corresponding circuit units of the odd unit rows and the even unit rows are staggered. In a unit column, the first circuit unit Q1 and the third circuit unit Q3 are alternately arranged in a second direction Y, and in another unit column, the second circuit unit Q2 and the fourth circuit unit Q4 are alternately arranged in the second direction Y.

[0164] In an exemplary embodiment, the plurality of light emitting units may include a first light emitting unit F1, a second light emitting unit F2, a third light emitting unit F3, and a fourth light emitting unit F4. In a light emitting row, the first light emitting unit F1, the second light emitting unit F2, the third light emitting unit F3, and the fourth light emitting unit F4 may be periodically arranged in the first direction X, and the corresponding light emitting units of the odd light emitting rows and the even light emitting rows are staggered. In one light emitting column, the first light emitting unit F1 and the third light emitting unit F3 are alternately arranged in the second direction Y, and in another light emitting column, the second light emitting unit F2 and the fourth light emitting unit F4 are alternately arranged in the second direction Y.

[0165] In an exemplary embodiment, the first circuit unit Q1 may include a first pixel driving circuit, the second circuit unit Q2 may include a second pixel driving circuit, the third circuit unit Q3 may include a third pixel driving circuit, and the fourth circuit unit Q4 may include a fourth pixel driving circuit. The first light emitting unit F1 may include a first light emitting device emitting a first color light, the second light emitting unit F2 may include a second light emitting device emitting a second color light, the third light emitting unit F3 may include a third light emitting device emitting a third color light, and the fourth light emitting unit F4 may include a fourth light emitting device emitting a fourth color light.

[0166] In an exemplary embodiment, the first color light may be a red light, the second color light may be a green light, the third color light may be a blue light, and the fourth color light may be a green light.

[0167] In an exemplary embodiment, the first light-emitting device of the first light-emitting unit F1 is connected to the first pixel driving circuit of the first circuit unit Q1, and the position of the orthogonal projection of the first light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the first pixel driving circuit on the substrate. The second light-emitting device of the second light-emitting unit F2 is connected to the second pixel driving circuit of the second circuit unit Q2, and the position of the orthogonal projection of the second light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the second pixel driving circuit on the substrate. The third light-emitting device of the third light-emitting unit F3 is connected to the third pixel driving circuit of the third circuit unit Q3, and the position of the orthogonal projection of the third light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the third pixel driving circuit on the substrate. The fourth light-emitting device of the fourth light-emitting unit F4 is connected to the fourth pixel driving circuit of the fourth circuit unit Q4, and the position of the orthogonal projection of the fourth light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the fourth pixel driving circuit on the substrate.

[0168] In an exemplary embodiment, the shape of the circuit unit may include any one or more of triangle, rectangle, rhombus, pentagon and hexagon, and the shape of the light emitting unit may include any one or more of triangle, rectangle, rhombus, pentagon and hexagon.

[0169] Figure 7 FIG. 1 is a schematic diagram showing the connection of power lines and connection lines in a display substrate according to an exemplary embodiment of the present disclosure. Figure 7 As shown, in an exemplary embodiment of the present disclosure, the power line may include a first power line 81, a second power line 82, a third power line 83 and a fourth power line 84, and the connection line may include a first connection line 91, a second connection line 92, a third connection line 93 and a fourth connection line 94.

[0170] In an exemplary embodiment, the shapes of the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 may be straight lines or broken lines extending at least partially along the second direction Y, or straight lines or broken lines with the main part extending along the second direction Y, and the shapes of the first connection line 91, the second connection line 92, the third connection line 93 and the fourth connection line 94 may be straight lines or broken lines extending at least partially along the first direction X, or straight lines or broken lines with the main part extending along the first direction X. In the present disclosure, A extends along the B direction, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. In the following description, "A extends along the B direction" means "the main part of A extends along the B direction".

[0171] In an exemplary embodiment, the first power line 81 and the third power line 83 may be disposed together in a cell column including the first circuit unit Q1 and the third circuit unit Q3 to form a cell column with a dual power line structure. The second power line 82 may be disposed alone in a cell column including the second circuit unit Q2 and the fourth circuit unit Q4, and the fourth power line 84 may be disposed alone in a cell column including the second circuit unit Q2 and the fourth circuit unit Q4 to form a cell column with a single power line structure.

[0172] In an exemplary embodiment, the first power line 81 is respectively connected to the first pixel driving circuits of the plurality of first circuit units Q1 in the unit column, and the first power line 81 is configured to provide a first power signal to the plurality of first pixel driving circuits in the unit column. The second power line 82 is respectively connected to the second pixel driving circuits of the plurality of second circuit units Q2 in the unit column, and the second power line 82 is configured to provide a second power signal to the plurality of second pixel driving circuits in the unit column. The third power line 83 is respectively connected to the third pixel driving circuits of the plurality of third circuit units Q3 in the unit column, and the third power line 83 is configured to provide a third power signal to the plurality of third pixel driving circuits in the unit column. The fourth power line 84 is respectively connected to the fourth pixel driving circuits of the plurality of fourth circuit units Q4 in the unit column, and the fourth power line 84 is configured to provide a fourth power signal to the plurality of fourth pixel driving circuits in the unit column.

[0173] In an exemplary embodiment, any one or more of the first connection line 91 , the second connection line 92 , the third connection line 93 , and the fourth connection line 94 may be disposed in at least one cell row.

[0174] In an exemplary embodiment, the first connection lines 91 can be arranged in a unit row and respectively connected to multiple first power lines 81, so that the first connection lines 91 extending along the first direction X of the main body are connected to the first power lines 81 extending along the second direction Y of the main body, so that the first power lines 81 and the first connection lines 91 form a grid connection structure on the display substrate for transmitting the first power signal.

[0175] In an exemplary embodiment, the second connecting lines 92 can be arranged in another unit row and respectively connected to multiple second power lines 82, so that the second connecting lines 92 extending from the main body along the first direction X and the second power lines 82 extending from the main body along the second direction Y are interconnected, so that the second power lines 82 and the second connecting lines 92 form a grid connection structure for transmitting the second power signal on the display substrate.

[0176] In an exemplary embodiment, the third connection line 93 can be arranged in another unit row and connected to multiple third power lines 83 respectively, so that the third connection line 93 extending along the first direction X of the main body and the third power line 83 extending along the second direction Y of the main body are connected to each other, so that the third power lines 83 and the third connection lines 93 form a grid connection structure for transmitting the third power signal on the display substrate.

[0177] In an exemplary embodiment, the fourth connection line 94 can be arranged in another unit row and connected to multiple fourth power lines 84 respectively, so as to realize the mutual connection between the fourth connection line 94 extending along the first direction X of the main body and the fourth power line 84 extending along the second direction Y of the main body, so that the fourth power lines 84 and the fourth connection lines 94 constitute a grid connection structure for transmitting the fourth power signal on the display substrate.

[0178] In an exemplary embodiment, the first power signal, the second power signal, the third power signal and the fourth power signal may be different, that is, the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 have different potentials.

[0179] In another exemplary embodiment, the first power line 81 , the second power line 82 , and the third power line 83 have different potentials, and the second power line 82 and the fourth power line 84 have the same potential.

[0180] In an exemplary embodiment, the second power line 82 is also connected to the fourth pixel driving circuits of the fourth circuit units Q4 in the same unit column, and the fourth power line 84 is also connected to the second pixel driving circuits of the second circuit units Q2 in the same unit column.

[0181] In an exemplary embodiment, in at least one unit row, the second connection line 92 is simultaneously connected to multiple second power lines 82 and multiple fourth power lines 84, and the fourth connection line 94 is simultaneously connected to multiple second power lines 82 and multiple fourth power lines 84, so that the second power lines 82 and the fourth power lines 84 are interconnected through the second connection line 92 and the fourth connection line 94, and the second power lines 82 and the fourth power lines 84 have the same potential.

[0182] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer may include a plurality of conductive layers, and the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 may be arranged in the same conductive layer, or may be arranged in different conductive layers. The first connection line 91, the second connection line 92, the third connection line 93, and the fourth connection line 94 may be arranged in the same conductive layer, or may be arranged in different conductive layers.

[0183] In an exemplary embodiment, the first power line 81 and the first connection line 91 may be disposed in different conductive layers, and the first connection line 91 may be connected to the first power line 81 through a via. The second power line 82 and the second connection line 92 may be disposed in different conductive layers, and the second connection line 92 may be connected to the second power line 82 through a via. The third power line 83 and the third connection line 93 may be disposed in different conductive layers, and the third connection line 93 may be connected to the third power line 83 through a via. The fourth power line 84 and the fourth connection line 94 may be disposed in different conductive layers, and the fourth connection line 94 may be connected to the fourth power line 84 through a via.

[0184] In an exemplary embodiment, the multiple conductive layers in the driving structure layer may include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in sequence along a direction away from the substrate, the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 may be arranged in the second source-drain metal layer, and the first connection line 91, the second connection line 92, the third connection line 93, and the fourth connection line 94 may be arranged in the third source-drain metal layer.

[0185] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0186] In an exemplary embodiment, taking 32 circuit units (4 unit rows and 8 unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations. Among them, in the Mth unit row and the M+2th unit row, the circuit units of the Nth unit column to the N+3th unit column and the N+4th unit column to the N+7th unit column are respectively the first circuit unit, the second circuit unit, the third circuit unit and the fourth circuit unit; in the M+1th unit row and the M+3th unit row, the circuit units of the Nth unit column to the N+3th unit column and the N+4th unit column to the N+7th unit column are respectively the third circuit unit, the fourth circuit unit, the first circuit unit and the second circuit unit.

[0187] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process, forming a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A Schematic diagram of the structures of the four circuit units.

[0188] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integral structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0189] In an exemplary embodiment, in the second direction Y, the first active layer 11 and the fourth active layer 14 can be located on the side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be located on the side of the second direction Y of the third active layer 13 in the present circuit unit.

[0190] In an exemplary embodiment, the third active layer 13 may be shaped like an inverted "Ω", the first active layer 11, the fourth active layer 14, and the sixth active layer 16 may be shaped like an "I", and the fifth active layer 15, the seventh active layer 17, and the eighth active layer 18 may be shaped like an "L".

[0191] In example embodiments, the first active layer 11 and the third active layer 13 to the eighth active layer 18 may each include a first region, a second region, and a channel region between the first region and the second region.

[0192] In an exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, that is, the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer.

[0193] In exemplary embodiments, the first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be separately provided.

[0194] In an exemplary embodiment, in a unit row, the first regions 18-1 of the eighth active layers in two adjacent circuit units may be connected to each other, and the eighth active layers 18 in the two adjacent circuit units may be an integrated structure connected to each other. For example, the eighth active layer 18 of the N+1th unit column and the eighth active layer 18 of the N+2th unit column may be an integrated structure connected to each other. For another example, the eighth active layer 18 of the N+3th unit column and the eighth active layer 18 of the N+4th unit column may be an integrated structure connected to each other. For another example, the eighth active layer 18 of the N+5th unit column and the eighth active layer 18 of the N+6th unit column may be an integrated structure connected to each other. Since the first area 18-1 of the eighth active layer in each circuit unit is configured to be connected to the third initial signal line formed subsequently, by forming the eighth active layers of adjacent circuit units into an interconnected integrated structure, not only can the number of signal lines and the number of corresponding vias be reduced, and the occupied area of ​​the pixel driving circuit be reduced, which is beneficial to improving the resolution, but also it can ensure that the first electrodes of the eighth transistors of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0195] In an exemplary embodiment, the first active layer 11 may span two adjacent unit rows, the second region 11 - 2 of the first active layer may be located in the present circuit unit, and the first region 11 - 1 of the first active layer may be located in the circuit unit of the previous unit row.

[0196] In an exemplary embodiment, the first semiconductor layers of adjacent unit columns may be mirror-symmetrical with respect to a column boundary, and the column boundary may be a straight line located between adjacent unit columns and extending along the second direction Y. For example, the first semiconductor layer of the Nth unit column and the first semiconductor layer of the N+1th unit column may be mirror-symmetrical with respect to the column boundary. For another example, the first semiconductor layer of the N+1th unit column and the first semiconductor layer of the N+2th unit column may be mirror-symmetrical with respect to the column boundary. For another example, the first semiconductor layer of the N+2th unit column and the first semiconductor layer of the N+3th unit column may be mirror-symmetrical with respect to the column boundary.

[0197] In example embodiments, shapes of the first semiconductor layers in a plurality of cell rows may be substantially the same.

[0198] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor T1, the third transistor T3 to the eighth transistor T8 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and performing a crystallization treatment on the amorphous silicon film after the dehydrogenation treatment to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.

[0199] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on a substrate having the aforementioned pattern, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig. 9A , Fig. 9B and Fig. 9C As shown, Fig. 9B for Fig. 9A The structural diagram of the four circuit units in the figure is as follows: Fig. 9C for Fig. 9A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0200] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 25 , and a first electrode 71 of a storage capacitor.

[0201] In an exemplary embodiment, the shape of the first electrode plate 71 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 71 may simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0202] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line with the main part extending along the first direction X. The first scan signal line 21 can be located on the side of the first electrode 71 in the opposite direction of the second direction Y, and the area where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0203] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line with the main part extending along the first direction X. The second scan signal line 22 can be located on one side of the second direction Y of the first electrode 71. The area where the second scan signal line 22 overlaps with the seventh active layer can be used as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 22 overlaps with the eighth active layer can be used as the gate electrode of the eighth transistor T8.

[0204] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main part extending along the first direction X. The third scan signal line 23 can be located on the side of the first scan signal line 21 away from the first electrode plate 71, and the area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0205] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 25 can be located between the first electrode 71 and the second scanning signal line 22. The area where the light-emitting signal line 25 overlaps with the fifth active layer can be used as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 25 overlaps with the sixth active layer can be used as the gate electrode of the sixth transistor T6.

[0206] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 25 can be designed with unequal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0207] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 may include an overlapping area with the first semiconductor layer and a non-overlapping area with the first semiconductor layer, and the width of the signal line in the overlapping area with the first semiconductor layer may be greater than the width of the signal line in the non-overlapping area with the first semiconductor layer.

[0208] In an exemplary embodiment, the first conductive layers of adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the first conductive layer of the Nth unit column and the first conductive layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the first conductive layer of the N+1th unit column and the first conductive layer of the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the first conductive layer of the N+2th unit column and the first conductive layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0209] In example embodiments, shapes of the first conductive layers in a plurality of cell rows may be substantially the same.

[0210] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are both conductorized.

[0211] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Fig. 10A , Fig. 10B and Fig. 10C As shown, Fig. 10B for Fig. 10A The structural diagram of the four circuit units in the figure is as follows: Fig. 10C for Fig. 10A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0212] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a shielding line 26 , a first initial signal line 31 , and a second electrode plate 72 of a storage capacitor.

[0213] In an exemplary embodiment, the shape of the shielding line 26 can be a straight line or a broken line with the main part extending along the first direction X. The shielding line 26 can be located between the first scanning signal line 21 and the first electrode 71. The shielding line 26 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and is configured as a bottom gate electrode of the second transistor T2.

[0214] In an exemplary embodiment, the shape of the first initial signal line 31 can be a straight line or a broken line with the main part extending along the first direction X. The first initial signal line 31 can be located on the side of the third scanning signal line 23 away from the first electrode plate 71. The first initial signal line 31 is configured to be connected to the first region of the first active layer through the seventh connecting electrode formed subsequently, and the first initial signal is written into the first electrode of the first transistor T1.

[0215] In an exemplary embodiment, a first initial connection block 31-1 is disposed on the first initial signal line 31 of each circuit unit. The first initial connection block 31-1 may be in a block shape and may be disposed on a side of the first initial signal line 31 away from the second electrode plate 72. The first initial connection block 31-1 is configured to be connected to the first region of the first active layer through a subsequently formed seventh connection electrode.

[0216] In an exemplary embodiment, the shielding line 26 and the first initial signal line 31 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0217] In an exemplary embodiment, the outline of the second electrode plate 72 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 72 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate. The second electrode plate 72 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 71 and the second electrode plate 72 constitute the storage capacitor of the pixel driving circuit.

[0218] In an exemplary embodiment, an opening 73 is provided on the second electrode plate 72. The opening 73 may be rectangular and may be located in the middle of the second electrode plate 72, so that the second electrode plate 72 forms a ring structure. The opening 73 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the opening 73 on the substrate. In an exemplary embodiment, the opening 73 is configured to accommodate a thirteenth via hole formed subsequently. The thirteenth via hole is located in the opening 73 and exposes the first electrode plate 71, so that the first connection electrode formed subsequently is connected to the first electrode plate 71.

[0219] In an exemplary embodiment, the second conductive layers of adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the second conductive layer of the Nth unit column and the second conductive layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the second conductive layer of the N+1th unit column and the second conductive layer of the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the second conductive layer of the N+2th unit column and the second conductive layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0220] In example embodiments, shapes of the second conductive layers in a plurality of cell rows may be substantially the same.

[0221] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, such as Fig.11A , Fig. 11B and Fig. 11C As shown, Fig. 11B for Fig.11A The structural diagram of the four circuit units in the figure is as follows: Fig. 11C for Fig.11A Schematic plan view of the second semiconductor layer in FIG.

[0222] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0223] In an exemplary embodiment, the second active layer 12 may be shaped like a fold line, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the shielding line 26 on the substrate.

[0224] In an exemplary embodiment, the second active layer 12 may include a first region, a second region, and a channel region between the first region and the second region. The first region 12-1 of the second active layer may be located on a side of the shielding line 26 away from the second electrode plate 72, and the second region 12-2 of the second active layer may be located on a side of the shielding line 26 close to the second electrode plate 72.

[0225] In an exemplary embodiment, the second semiconductor layers of adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the second semiconductor layer of the Nth unit column and the second semiconductor layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the second semiconductor layer of the N+1th unit column and the second semiconductor layer of the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the second semiconductor layer of the N+2th unit column and the second semiconductor layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0226] In example embodiments, shapes of the second semiconductor layers in a plurality of cell rows may be substantially the same.

[0227] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0228] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, such as Fig. 12A , Fig. 12B and Fig. 12C As shown, Fig. 12B for Fig. 12A The structural diagram of the four circuit units in the figure is as follows: Fig. 12C for Fig. 12A In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0229] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a fourth scan signal line 24 , a second preliminary signal line 32 , and a third preliminary signal line 33 .

[0230] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main part extending along the first direction X. The fourth scan signal line 24 can be located between the first scan signal line 21 and the second electrode 72. The positive projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the positive projection of the shielding line 26 on the substrate. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0231] In an exemplary embodiment, the fourth scan signal line 24 and the shielding line 26 can be connected to the same signal source, so that the shielding line 26 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0232] In an exemplary embodiment, the shape of the second initial signal line 32 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 32 can be located on the side of the first initial signal line 31 close to the second electrode plate 72. The second initial signal line 32 is configured to be connected to the first region of the seventh active layer through the subsequently formed eighth connecting electrode, and write the second initial signal into the first electrode of the seventh transistor T7.

[0233] In an exemplary embodiment, a second initial connection block 32-1 is disposed on the second initial signal line 32 of each circuit unit. The second initial connection block 32-1 may be in a block shape and may be disposed on a side of the second initial signal line 32 away from the second electrode plate 72. The second initial connection block 32-1 is configured to be connected to the first region of the seventh active layer through an eighth connection electrode formed subsequently.

[0234] In an exemplary embodiment, the positive projection of the second initial signal line 32 on the substrate at least partially overlaps with the positive projection of the third scanning signal line 23 on the substrate, so that the second initial signal line 32 with a constant potential can effectively shield the influence of the scanning signal on the pixel driving circuit, thereby improving the driving performance of the pixel driving circuit.

[0235] In an exemplary embodiment, the shape of the third initial signal line 33 can be a straight line or a broken line with the main part extending along the first direction X. The third initial signal line 33 can be located on the side of the light-emitting signal line 25 away from the second electrode plate 72. The third initial signal line 33 is configured to be connected to the first area of ​​the eighth active layer through a ninth connecting electrode formed subsequently, and the third initial signal is written into the first electrode of the eighth transistor T8.

[0236] In an exemplary embodiment, a third initial connection block 33-1 is disposed on the third initial signal line 33 of each circuit unit. The third initial connection block 33-1 may be in a block shape and may be disposed on a side of the third initial signal line 33 away from the second electrode plate 72. The third initial connection block 33-1 is configured to be connected to the first region of the eighth active layer through a subsequently formed ninth connection electrode.

[0237] In an exemplary embodiment, since the eighth active layers in some adjacent circuit units in a unit row are interconnected as an integrated structure, the third initial connection block 33-1 can be located between adjacent circuit units, so that some adjacent circuit units can share one third initial connection block 33-1.

[0238] In an exemplary embodiment, the orthographic projection of the third initial signal line 33 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate, so that the third initial signal line 33 with a constant potential can effectively shield the influence of the scanning signal on the pixel driving circuit, thereby improving the driving performance of the pixel driving circuit.

[0239] In an exemplary embodiment, the third conductive layers of adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the third conductive layer of the Nth unit column and the third conductive layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the third conductive layer of the N+1th unit column and the third conductive layer of the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the third conductive layer of the N+2th unit column and the third conductive layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0240] In example embodiments, shapes of the third conductive layers in a plurality of cell rows may be substantially the same.

[0241] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, and providing a plurality of vias on the sixth insulating layer, such as Fig.13A and Fig. 13B As shown, Fig. 13B for Fig.13A Schematic diagram of the structures of the four circuit units.

[0242] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0243] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0244] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0245] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0246] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0247] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fifth via hole V5 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0248] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer, and the sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0249] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0250] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer), and the eighth via hole V8 is configured to connect the subsequently formed fifth connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) through the via hole.

[0251] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect a subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect a subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0253] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a ninth connection electrode formed subsequently to the first region of the eighth active layer through the via hole. In an exemplary embodiment, since the first regions of the eighth active layers of some adjacent circuit units in a unit row are connected to each other, some adjacent circuit units can share one eleventh via hole V11.

[0254] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer, and the twelfth via hole V12 is configured to connect a subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0255] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 73 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode plate 71, and the thirteenth via hole V13 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 71 through the via hole.

[0256] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second electrode plate 72 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second electrode plate 72, and the fourteenth via hole V14 is configured to connect a subsequently formed fourth connecting electrode to the second electrode plate 72 through the via hole.

[0257] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 31-1 of the first initial signal line 31 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first initial connection block 31-1, and the fifteenth via hole V15 is configured to connect the subsequently formed seventh connection electrode to the first initial connection block 31-1 through the via hole.

[0258] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 32-1 of the second initial signal line 32 on the substrate, the sixth insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the second initial connection block 32-1, and the sixteenth via hole V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 32-1 through the via hole.

[0259] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 33-1 of the third initial signal line 33 on the substrate, the sixth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the third initial connection block 33-1, and the seventeenth via hole V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 33-1 through the via hole.

[0260] In an exemplary embodiment, the plurality of via holes in adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the shapes of the plurality of via holes in the plurality of cell rows may be substantially the same.

[0261] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Fig.14A , Fig. 14B and Fig. 14C As shown, Fig. 14B for Fig.14A The structural diagram of the four circuit units in the figure is as follows: Fig. 14C for Fig.14A In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0262] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0263] In an exemplary embodiment, the shape of the first connection electrode 51 may be a zigzag shape with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the first region of the second active layer through the third via hole V3. The second end of the first connection electrode 51 is connected to the first electrode plate 71 through the thirteenth via hole V13 after extending along the second direction Y. In an exemplary embodiment, since the first electrode plate 71 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first electrode plate 71 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0264] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip whose main part extends along the second direction Y. The first end of the second connection electrode 52 is connected to the second region of the first active layer through the second via hole V2. After the second end of the second connection electrode 52 extends along the second direction Y, it is connected to the second region of the third active layer (also the first region of the sixth active layer) through the fifth via hole V5. The portion between the first end and the second end of the second connection electrode 52 is connected to the second region of the second active layer through the fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 enables the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0265] In an exemplary embodiment, the shape of the third connection electrode 53 may be a block shape (such as a rectangle), and the third connection electrode 53 is connected to the first region of the fourth active layer through the sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4, and the third connection electrode 53 is configured to be connected to a data signal line formed subsequently.

[0266] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be a zigzag shape with the main part extending along the second direction Y. The first end of the fourth connection electrode 54 is connected to the first area of ​​the fifth active layer through the seventh via hole V7. The second end of the fourth connection electrode 54 extends in the opposite direction of the second direction Y and is connected to the second electrode plate 72 through the fourteenth via hole V14, thereby achieving the same potential for the first electrode of the fifth transistor T5 and the second electrode plate 72 of the storage capacitor in each circuit unit.

[0267] In an exemplary embodiment, the fourth connection electrode 54 can be used as the first electrode of the fifth transistor T5. A power connection block 54-1 is disposed on the fourth connection electrode 54 in each circuit unit, and the power connection block 54-1 is configured to be connected to a power line formed later in the circuit unit.

[0268] In an exemplary embodiment, the position of the power connection block 54-1 in the first circuit unit, the second circuit unit and the fourth circuit unit can be the same, and the shape of the power connection block 54-1 in the first circuit unit, the second circuit unit and the fourth circuit unit can be block-shaped (such as rectangular) and can be arranged between the first end and the second end of the fourth connection electrode 54.

[0269] In an exemplary embodiment, the position of the power connection block 54-1 in the third circuit unit may be different from the position of the power connection block 54-1 in other circuit units, and the shape of the power connection block 54-1 in the third circuit unit may be block-shaped (such as rectangular) and may be arranged on the side of the second end of the fourth connection electrode 54 away from the first end of the fourth connection electrode 54.

[0270] In an exemplary embodiment, the fifth connection electrode 55 may be in a zigzag shape with a main portion extending along the second direction Y. The first end of the fifth connection electrode 55 is connected to the first region of the third active layer through the eighth via hole V8. The second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through the twelfth via hole V12 after extending along the second direction Y. In an exemplary embodiment, since the first region of the third active layer serves as the second region of the fourth active layer and the second region of the fifth active layer at the same time, the fifth connection electrode 55 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming the second node N2 of the pixel driving circuit.

[0271] In an exemplary embodiment, the shape of the sixth connection electrode 56 may be a block shape (such as a rectangle), and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to the eleventh connection electrode formed subsequently.

[0272] In an exemplary embodiment, the seventh connection electrode 57 may be in a strip shape, a first end of the seventh connection electrode 57 is connected to the first region of the first active layer through a first via hole V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 31-1 through a fifteenth via hole V15. In an exemplary embodiment, the seventh connection electrode 57 may serve as a first electrode of the first transistor T1, and since the first initial connection block 31-1 is connected to the first initial signal line 31, the seventh connection electrode 57 enables the first initial signal transmitted by the first initial signal line 31 to be written into the first electrode of the first transistor T1.

[0273] In an exemplary embodiment, the eighth connection electrode 58 may be in a strip shape with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 32-1 through a sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as a first electrode of the seventh transistor T7. Since the second initial connection block 32-1 is connected to the second initial signal line 32, the eighth connection electrode 58 writes the second initial signal transmitted by the second initial signal line 32 into the first electrode of the seventh transistor T7.

[0274] In an exemplary embodiment, since in the circuit unit, the second initial signal line 32 is arranged on the side of the first scanning signal line 21 away from the second electrode plate 72, and the second initial connection block 32-1 is arranged on the side of the second initial signal line 32 away from the second electrode plate 72, the second initial signal line 32 of this circuit unit is connected to the first area of ​​the seventh active layer of the circuit unit in the previous unit row through the eighth connection electrode 58, that is, the second initial signal line 32 in this unit row writes the second initial signal to the first electrode of the seventh transistor T7 in the previous unit row.

[0275] In an exemplary embodiment, the ninth connection electrode 59 may be in a strip shape with a main portion extending along the second direction Y. A first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through an eleventh via hole V11, and a second end of the eighth connection electrode 58 is connected to the third initial connection block 33-1 through a seventeenth via hole V17. In an exemplary embodiment, the ninth connection electrode 59 may serve as a first electrode of the eighth transistor T8. Since the third initial connection block 33-1 is connected to the third initial signal line 33, the ninth connection electrode 59 enables the third initial signal transmitted by the third initial signal line 33 to be written into the first electrode of the eighth transistor T8.

[0276] In an exemplary embodiment, since the eighth active layers in some adjacent circuit units in a unit row are interconnected as an integrated structure, some adjacent circuit units share a third initial connection block 33-1, and thus some adjacent circuit units share a ninth connection electrode 59, it can be ensured that the first electrodes of the eighth transistors T8 of the adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0277] In an exemplary embodiment, the fourth conductive layer may further include a first preliminary connection line 41 , a second preliminary connection line 42 , a first preliminary connection bar 43 , and a second preliminary connection bar 44 .

[0278] In an exemplary embodiment, the shape of the first preliminary connection line 41 may be a straight line or a zigzag line with a main portion extending along the second direction Y. In at least one circuit unit, the first preliminary connection line 41 may be disposed on a side of the second connection electrode 52 away from the first connection electrode 51. The shape of the first preliminary connection bar 43 may be a straight line or a zigzag line with a main portion extending along the first direction X. The first preliminary connection bar 43 may be disposed between the first preliminary connection line 41 and the seventh connection electrode 57. The first end of the first preliminary connection bar 43 is connected to the first preliminary connection line 41, and the second end of the first preliminary connection bar 43 is connected to the seventh connection electrode 57.

[0279] In an exemplary embodiment, since the seventh connection electrode 57 is connected to the first initial signal line 31 through the first initial connection block 31-1, the first initial signal line 31 extending along the first direction X of the main part and the first initial connection line 41 extending along the second direction Y of the main part are connected to each other, so that the first initial signal line 31 and the first initial connection line 41 form a grid connection structure for transmitting the first initial signal on the display substrate, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0280] In an exemplary embodiment, the second initial connection line 42 may be in the shape of a straight line or a zigzag line with a main portion extending along the second direction Y. In at least one circuit unit, the second initial connection line 42 may be disposed on a side of the second connection electrode 52 in the circuit unit away from the first connection electrode 51. The second initial connection bar 44 may be in the shape of a straight line or a zigzag line with a main portion extending along the first direction X. The second initial connection bar 44 may be disposed between the second initial connection line 42 and the eighth connection electrode 58. A first end of the second initial connection bar 44 is connected to the second initial connection line 42, and a second end of the second initial connection bar 44 is connected to the eighth connection electrode 58.

[0281] In the exemplary embodiment, since the eighth connection electrode 58 is connected to the second initial signal line 32 through the second initial connection block 32-1, the second initial signal line 32 extending along the first direction X and the second initial connection line 42 extending along the second direction Y are connected to each other, so that the second initial signal line 32 and the second initial connection line 42 form a grid connection structure for transmitting the first initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0282] In an exemplary embodiment, in the first direction X, the first initial connection lines 41 and the second initial connection lines 42 may be alternately arranged, that is, one second initial connection line 42 may be arranged between two adjacent first initial connection lines 41 in the first direction X, and one first initial connection line 41 may be arranged between two adjacent second initial connection lines 42 in the first direction X.

[0283] In an exemplary embodiment, adjacent cell columns may share one first initial connection line 41 or one second initial connection line 42. For example, multiple circuit units in the Nth cell column and the N+1th cell column may share one second initial connection line 42, and multiple circuit units in the N+4th cell column and the N+5th cell column may share one second initial connection line 42. For another example, multiple circuit units in the N+2th cell column and the N+3th cell column may share one first initial connection line 41, and multiple circuit units in the N+6th cell column and the N+7th cell column may share one first initial connection line 41.

[0284] In an exemplary embodiment, in at least one unit row, the fourth conductive layers of some adjacent circuit units may be mirror-symmetric with respect to the column boundary. For example, in the Mth unit row and the M+2th unit row, the fourth conductive layers of the two circuit units of the Nth unit column and the N+1th unit column may be mirror-symmetric with respect to the column boundary, and the fourth conductive layers of the two circuit units of the N+4th unit column and the N+5th unit column may be mirror-symmetric with respect to the column boundary. For another example, in the M+1th unit row and the M+3th unit row, the fourth conductive layers of the two circuit units of the N+2th unit column and the N+3th unit column may be mirror-symmetric with respect to the column boundary, and the fourth conductive layers of the two circuit units of the N+6th unit column and the N+7th unit column may be mirror-symmetric with respect to the column boundary.

[0285] In an exemplary embodiment, in at least one unit column, the shape of the fourth conductive layer of some circuit units may be substantially the same. For example, in the Nth unit column, the N+1th unit column, the N+4th unit column, and the N+5th unit column, the shape of the fourth conductive layer of two circuit units in the Mth unit row and the M+2th unit row may be substantially the same. For another example, in the N+2th unit column, the N+3th unit column, the N+6th unit column, and the N+7th unit column, the shape of the fourth conductive layer of two circuit units in the M+1th unit row and the M+3th unit row may be substantially the same.

[0286] In an exemplary embodiment, except for the fourth conductive layer of the fourth connection electrode 54, the fourth conductive layers of some adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the fourth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+2th unit column and the fourth conductive layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+4th unit column and the fourth conductive layer of the N+5th unit column may be mirror-symmetric with respect to the column boundary.

[0287] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of via holes are disposed on the first planar layer, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A Schematic diagram of the structures of the four circuit units.

[0288] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0289] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the sixth connecting electrode 56 through the via hole.

[0290] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0291] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the power connection block 54-1, and the twenty-third via hole V23 is configured to connect a subsequently formed high-potential power line to the power connection block 54-1 through the via hole.

[0292] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Fig.16A , Fig. 16B and Fig. 16C As shown, Fig. 16B for Fig.16A The structural diagram of the four circuit units in the figure is as follows: Fig. 16C for Fig.16A In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0293] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least an eleventh connection electrode 61 and a data signal line 62 .

[0294] In an exemplary embodiment, the eleventh connection electrode 61 may be in the shape of a strip having a main portion extending along the second direction Y, the eleventh connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-first via hole V21, and the eleventh connection electrode 61 is configured to be connected to a subsequently formed anode connection electrode.

[0295] In an exemplary embodiment, the data signal line 62 may be in a zigzag shape with a main portion extending along the second direction Y, and the data signal line 62 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 62 is connected to the first electrode of the fourth transistor T4, and the data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0296] In an exemplary embodiment, the fifth conductive layer of the first circuit unit may further include a first power line 81, the fifth conductive layer of the second circuit unit may further include a second power line 82, the fifth conductive layer of the third circuit unit may further include a third power line 83, and the fifth conductive layer of the fourth circuit unit may further include a fourth power line 84. The first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 are all high-potential power lines.

[0297] In an exemplary embodiment, the shape of the first power line 81 can be a zigzag shape with the main part extending along the second direction Y. The first power line 81 is connected to the power connection block 54-1 of the circuit unit through the twenty-third via V23 in the first circuit unit, that is, the first power line 81 is connected to the first pixel driving circuit in the first circuit unit.

[0298] In an exemplary embodiment, the shape of the second power line 82 can be a zigzag shape with the main part extending along the second direction Y. The second power line 82 is connected to the power connection block 54-1 of the circuit unit through the twenty-third via V23 in the second circuit unit, that is, the second power line 82 is connected to the second pixel driving circuit in the second circuit unit.

[0299] In an exemplary embodiment, the shape of the third power line 83 can be a zigzag shape with the main part extending along the second direction Y. The third power line 83 is connected to the power connection block 54-1 of the circuit unit through the twenty-third via V23 in the third circuit unit, that is, the third power line 83 is connected to the third pixel driving circuit in the third circuit unit.

[0300] In an exemplary embodiment, the shape of the fourth power line 84 can be a zigzag shape with the main part extending along the second direction Y. The fourth power line 84 is connected to the power connection block 54-1 of the circuit unit through the twenty-third via V23 in the fourth circuit unit, that is, the fourth power line 84 is connected to the fourth pixel driving circuit in the fourth circuit unit.

[0301] In an exemplary embodiment, since the power connection block 54-1 of each circuit unit is connected to the fourth connection electrode 54 of the circuit unit, and the fourth connection electrode 54 is respectively connected to the first area of ​​the fifth active layer of the circuit unit and the second plate 72 of the storage capacitor, the first power line 81 writes the first power signal into the first electrode of the fifth transistor T5 in the first pixel driving circuit and the second plate 72 of the storage capacitor, the second power line 82 writes the second power signal into the first electrode of the fifth transistor T5 in the second pixel driving circuit and the second plate 72 of the storage capacitor, the third power line 83 writes the third power signal into the first electrode of the fifth transistor T5 in the third pixel driving circuit and the second plate 7 of the storage capacitor, and the fourth power line 84 writes the fourth power signal into the first electrode of the fifth transistor T5 in the fourth pixel driving circuit and the second plate 72 of the storage capacitor.

[0302] In an exemplary embodiment, the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 can be zigzag lines of unequal width, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the power lines and the data signal lines.

[0303] In an exemplary embodiment, any one or more of the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 are arranged in at least one unit column. For example, the four power lines can be arranged in different unit columns, respectively. For another example, two of the four power lines can be arranged in the same unit column.

[0304] In an exemplary embodiment, since the first circuit unit and the third circuit unit are arranged at intervals in a unit column, the first power line 81 and the third power line 83 can be arranged together in a unit column, the first power line 81 is connected to the first pixel driving circuit of multiple first circuit units in the unit column, and the third power line 83 is connected to the third pixel driving circuit of multiple third circuit units in the unit column.

[0305] In an exemplary embodiment, the second power line 82 and the fourth power line 84 may be connected to the same signal source, that is, the second power line 82 and the fourth power line 84 have the same potential. Since the second circuit unit and the fourth circuit unit are arranged in one unit column, the second power line 82 may be arranged alone in one unit column, and the second power line 82 is connected to the pixel driving circuits of the plurality of second circuit units and the plurality of fourth circuit units in the unit column, and the fourth power line 84 may be arranged alone in one unit column, and the second power line 82 is connected to the pixel driving circuits of the plurality of second circuit units and the plurality of fourth circuit units in the unit column.

[0306] In an exemplary embodiment, the third power line 83 may be disposed on one side of the data signal line 62 of the present circuit unit in the first direction X, and the first power line 81 may be disposed on one side of the third power line 83 of the present circuit unit in the first direction X. The second power line 82 may be disposed on one side of the data signal line 62 of the present circuit unit in the opposite direction of the first direction X, and the fourth power line 84 may be disposed on one side of the data signal line 62 of the present circuit unit in the opposite direction of the first direction X.

[0307] In an exemplary embodiment, the first power line 81 and the third power line 83 may be arranged in the Nth unit column, the N+2th unit column, the N+4th unit column, and the N+6th unit column, forming a dual power line structure in these unit columns. The second power line 82 may be arranged in the N+1th unit column and the N+5th unit column, forming a single power line structure in these unit columns. The fourth power line 84 may be arranged in the N+3th unit column and the N+7th unit column, forming a single power line structure in these unit columns. In this way, along the first direction X, the unit columns of the dual power line structure and the unit columns of the single power line structure are alternately arranged.

[0308] In an exemplary embodiment, the odd-numbered cell columns in the display substrate are cell columns with a dual power line structure, and the even-numbered cell columns are cell columns with a single power line structure. Alternatively, the even-numbered cell columns in the display substrate are cell columns with a dual power line structure, and the odd-numbered cell columns are cell columns with a single power line structure.

[0309] In an exemplary embodiment, in a cell column of a dual power line structure, a plurality of first circuit units may be located in odd cell rows, a plurality of third circuit units may be located in even cell rows, a first power line 81 may be connected to pixel driving circuits of circuit units in all odd cell rows in the cell column, and a third power line 83 may be connected to pixel driving circuits of circuit units in all even cell rows in the cell column.

[0310] In an exemplary embodiment, in a cell column of a dual power line structure, multiple first circuit units may be located in even-numbered cell rows, multiple third circuit units may be located in odd-numbered cell rows, the first power line 81 may be connected to the pixel driving circuits of the circuit units in all even-numbered cell rows in the cell column, and the third power line 83 may be connected to the pixel driving circuits of the circuit units in all odd-numbered cell rows in the cell column.

[0311] In an exemplary embodiment, in a unit column of a single power line structure, the second power line 82 can be connected to the pixel driving circuits of multiple second circuit units and multiple fourth circuit units in the unit column, that is, the second power line 82 can be connected to the pixel driving circuits of the circuit units in all odd unit rows and all even unit rows in the unit column.

[0312] In an exemplary embodiment, in a unit column of a single power line structure, the fourth power line 84 can be connected to the pixel driving circuits of multiple second circuit units and multiple fourth circuit units in the unit column, that is, the fourth power line 84 can be connected to the pixel driving circuits of the circuit units in all odd unit rows and all even unit rows in the unit column.

[0313] In an exemplary embodiment, at least one of the first power line, the second power line, the third power line and the fourth power line may extend to the binding area or the frame area, and the power lines of the same potential are connected together through power routing in the binding area or the frame area.

[0314] In an exemplary embodiment, the orthographic projection of at least one of the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the power line with a constant potential can effectively shield the influence of the data voltage jump and other signals on the first node N1 in the pixel driving circuit, avoid the data voltage jump and other signals affecting the potential of the first node N1, and improve the driving performance of the pixel driving circuit.

[0315] In an exemplary embodiment, the orthographic projection of at least one of the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the power line can block the second active layer, thereby blocking the light emission of the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, preventing the oxide transistor from drifting in characteristics due to light, and improving the electrical characteristics of the oxide transistor.

[0316] In an exemplary embodiment, an orthographic projection of at least one of the first power line 81 , the second power line 82 , the third power line 83 , and the fourth power line 84 on the substrate at least partially overlaps an orthographic projection of the second connection electrode 52 on the substrate.

[0317] In an exemplary embodiment, in at least one unit row, the eleventh connection electrode 61 and the data signal line 62 of the adjacent circuit units may be mirror-symmetric with respect to the column boundary. For example, the eleventh connection electrode 61 and the data signal line 62 of the two circuit units of the Nth unit column and the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the eleventh connection electrode 61 and the data signal line 62 of the two circuit units of the N+1th unit column and the N+2th unit column may be mirror-symmetric with respect to the column boundary.

[0318] In an exemplary embodiment, in at least one unit column, the shapes of the fourth conductive layers of some circuit units may be substantially the same. For example, the shapes of the fourth conductive layers of two circuit units in the Mth unit row and the M+2th unit row may be substantially the same. For another example, the shapes of the fourth conductive layers of two circuit units in the M+1th unit row and the M+3th unit row may be substantially the same.

[0319] Fig.16D , Fig.16E and Fig.16F Schematic diagram of the connection of the data signal line of the embodiment of the present disclosure. In an exemplary embodiment, the data signal line 62 may include a first data signal line 62-1, a second data signal line 62-2, a third data signal line 62-3 and a fourth data signal line 62-4, each of which is connected to the first region of the fourth active layer through a third connecting electrode, thereby realizing that the data signal line writes the data signal to the first electrode of the fourth transistor T4. Any one or more of the first data signal line 62-1, the second data signal line 62-2, the third data signal line 62-3 and the fourth data signal line 62-4 may be set in at least one unit column.

[0320] In an exemplary embodiment, each data signal line can be separately arranged in a unit column. For a unit column including a first circuit unit and a third circuit unit, a first data signal line 62-1 arranged in the unit column is connected not only to the fourth transistor T4 of the first pixel driving circuit in the unit column, but also to the fourth transistor T4 of the third pixel driving circuit in the unit column, and a third data signal line 62-3 arranged in the unit column is connected not only to the fourth transistor T4 of the third pixel driving circuit in the unit column, but also to the fourth transistor T4 of the first pixel driving circuit in the unit column. Fig.16D shown.

[0321] In another exemplary embodiment, the first data signal line 62-1 and the third data signal line 62-3 may be arranged together in one unit column. For a unit column including a first circuit unit and a third circuit unit, the first data signal line 62-1 arranged in the unit column is connected only to the fourth transistor T4 of the first pixel driving circuit in the unit column, and the third data signal line 62-3 arranged in the unit column is connected only to the fourth transistor T4 of the third pixel driving circuit in the unit column. Fig.16E shown.

[0322] In another exemplary embodiment, each data signal line may be separately provided in a unit column. For a unit column including the first circuit unit and the third circuit unit, the first data signal line 62-1 is connected only to the fourth transistor T4 of the first pixel driving circuit in the unit column, and is connected to the fourth transistor T4 of the first pixel driving circuit in another unit column through the data transfer line 62-5. For another unit column including the first circuit unit and the third circuit unit, the third data signal line 62-3 is connected only to the fourth transistor T4 of the third pixel driving circuit in the unit column, and is connected to the fourth transistor T4 of the third pixel driving circuit in another unit column through the data transfer line 62-5. Fig.16F shown.

[0323] In an exemplary embodiment, since the first pixel driving circuit is connected to the light-emitting units of the same color (such as red), the first data signal line 62-1 is connected to the pixel driving circuit of the same color sub-pixel. Since the third pixel driving circuit is connected to the light-emitting units of the same color (such as blue), the third data signal line 62-3 is connected to the pixel driving circuit of the same color sub-pixel. Since the second pixel driving circuit and the fourth pixel driving circuit are connected to the light-emitting units of the same color (such as green), the second data signal line 62-2 and the fourth data signal line 62-4 are connected to the pixel driving circuit of the same color sub-pixel. The present disclosure can save power consumption of the driving circuit when a pure color picture is displayed by connecting a single data signal line to the pixel driving circuit of the same color sub-pixel.

[0324] (10) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of via holes are disposed on the second planar layer, such as Fig.17A and Fig. 17B As shown, Fig. 17B for Fig.17A Schematic diagram of the structures of the four circuit units.

[0325] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a thirty-first via V31 .

[0326] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the eleventh connecting electrode 61 on the substrate, the second flat layer in the thirty-first via hole V31 is etched away to expose the surface of the eleventh connecting electrode 61, and the thirty-first via hole V31 is configured to connect a subsequently formed anode connecting electrode to the eleventh connecting electrode 61 through the via hole.

[0327] In an exemplary embodiment, a forty-first via hole V41 , a forty-second via hole V42 , a forty-third via hole V43 , or a forty-fourth via hole V44 may be further disposed on the second planar layer of at least one circuit unit.

[0328] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the first power line 81 on the substrate, the second flat layer in the forty-first via V41 is etched away to expose the surface of the first power line 81, and the forty-first via V41 is configured to connect a subsequently formed first connecting line to the first power line 81 through the via.

[0329] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the second power line 82 on the substrate, the second flat layer in the forty-second via V42 is etched away to expose the surface of the second power line 82, and the forty-second via V42 is configured to connect a subsequently formed second connecting line to the second power line 82 through the via.

[0330] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the third power line 83 on the substrate, the second flat layer in the forty-third via V43 is etched away to expose the surface of the third power line 83, and the forty-third via V43 is configured to connect a subsequently formed third connecting line to the third power line 83 through the via.

[0331] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the fourth power line 84 on the substrate, the second flat layer in the forty-fourth via V44 is etched away to expose the surface of the fourth power line 84, and the forty-fourth via V44 is configured to connect a subsequently formed fourth connecting line to the fourth power line 84 through the via.

[0332] In an exemplary embodiment, only the 41st via hole V41 or only the 43rd via hole V43 may be provided in the multiple circuit units of at least one unit row. For example, only the 41st via hole V41 may be provided in the multiple circuit units of the Mth unit row, and only the 43rd via hole V43 may be provided in the multiple circuit units of the M+2th unit row.

[0333] In an exemplary embodiment, the 42nd via V42 and the 44th via V44 may be simultaneously disposed in a plurality of circuit units of at least one unit row. For example, the 42nd via V42 and the 44th via V44 may be simultaneously disposed in a plurality of circuit units of the M+1th unit row, and the 42nd via V42 and the 44th via V44 may be simultaneously disposed in a plurality of circuit units of the M+3th unit row.

[0334] In an exemplary embodiment, only the 41st via hole V41, the 42nd via hole V42, the 43rd via hole V43, or the 44th via hole V44 may be provided in the multiple circuit units of at least one unit column. For example, only the 41st via hole V41 may be provided in the multiple circuit units of the Nth unit column and the N+4th unit column, only the 42nd via hole V42 may be provided in the multiple circuit units of the N+1th unit column and the N+5th unit column, only the 43rd via hole V43 may be provided in the multiple circuit units of the N+2th unit column and the N+6th unit column, and only the 44th via hole V44 may be provided in the multiple circuit units of the N+3th unit column and the N+7th unit column.

[0335] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second planar layer, such as Fig.18A , Fig.18B and Fig. 18C As shown, Fig.18B for Fig.18A The structural diagram of the four circuit units in the figure is as follows: Fig. 18C for Fig.18A In an exemplary embodiment, the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer.

[0336] In an exemplary embodiment, the sixth conductive layer of each circuit unit includes at least an anode connection electrode 63 .

[0337] In an exemplary embodiment, the shape of the anode connection electrode 63 may be a block shape (such as a rectangle), and the anode connection electrode 63 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31, and the anode connection electrode 63 is configured to be connected to the subsequently formed anode. Since the eleventh connection electrode 61 is connected to the sixth connection electrode 56 through the via hole, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0338] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may be further provided with a first connection line 91 , a second connection line 92 , a third connection line 93 , or a fourth connection line 94 .

[0339] In an exemplary embodiment, in at least one circuit unit, the shape of the first connection line 91 can be a straight line or a broken line extending along the first direction X, and the first connection line 91 is connected to the first power line 81 through the forty-first via V41, thereby realizing the mutual connection between the first connection line 91 extending along the first direction X of the main part and the first power line 81 extending along the second direction Y of the main part, so that the first power line 81 and the first connection line 91 form a grid connection structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0340] In an exemplary embodiment, in at least one circuit unit, the shape of the second connection line 92 can be a straight line or a broken line extending along the first direction X, and the second connection line 92 is connected to the second power line 82 through the forty-second via V42, thereby realizing the mutual connection between the second connection line 92 extending along the first direction X of the main part and the second power line 82 extending along the second direction Y of the main part, so that the second power line 82 and the second connection line 92 form a grid connection structure for transmitting the second power signal on the display substrate, which can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0341] In an exemplary embodiment, in at least one circuit unit, the shape of the third connection line 93 can be a straight line or a broken line extending along the first direction X, and the third connection line 93 is connected to the third power line 83 through the forty-third via V43, thereby realizing the interconnection between the third connection line 93 extending along the first direction X of the main part and the third power line 83 extending along the second direction Y of the main part, so that the third power line 83 and the third connection line 93 form a grid connection structure for transmitting the third power signal on the display substrate, which can not only effectively reduce the resistance of the third power line and reduce the voltage drop of the third power signal, but also effectively improve the uniformity of the third power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0342] In an exemplary embodiment, in at least one circuit unit, the shape of the fourth connection line 94 can be a straight line or a broken line extending along the first direction X, and the fourth connection line 94 is connected to the fourth power line 84 through the forty-fourth via V44, thereby realizing the mutual connection between the fourth connection line 94 extending along the first direction X of the main body and the fourth power line 84 extending along the second direction Y of the main body, so that the fourth power line 84 and the fourth connection line 94 form a grid connection structure for transmitting the fourth power signal on the display substrate, which can not only effectively reduce the resistance of the fourth power line and reduce the voltage drop of the fourth power signal, but also effectively improve the uniformity of the fourth power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0343] In an exemplary embodiment, in at least one unit row, the second connection line 92 is not only connected to the multiple second power lines 82 through the multiple forty-second vias V42, but also connected to the multiple fourth power lines 84 through the multiple forty-fourth vias V44, so that the second power lines 82 and the fourth power lines 84 are interconnected through the second connection line 92, and the second power lines 82 and the fourth power lines 84 have the same potential.

[0344] In an exemplary embodiment, in at least one cell row, the fourth connecting line 94 is not only connected to the multiple fourth power lines 84 through the multiple forty-fourth vias V44, but also connected to the multiple second power lines 82 through the multiple forty-second vias V42, so that the second power lines 82 and the fourth power lines 84 are interconnected through the fourth connecting line 94, and the second power lines 82 and the fourth power lines 84 have the same potential.

[0345] In an exemplary embodiment, any one or more of the first connection line 91, the second connection line 92, the third connection line 93, or the fourth connection line 94 are arranged in at least one unit row. For example, the four connection lines can be arranged in different unit rows, respectively. For another example, two, three, or four of the four connection lines can be arranged in the same unit row.

[0346] In an exemplary embodiment, only one connection line may be provided in a cell row. For example, only the first connection line 91 may be provided in the Mth cell row. For another example, only the third connection line 93 may be provided in the M+2th cell row. For another example, only the second connection line 92 may be provided in the M+1th cell row, and only the fourth connection line 94 may be provided in the M+3th cell row.

[0347] In an exemplary embodiment, since the power line is arranged in the second source-drain metal (SD2) layer and the connecting line is arranged in the third source-drain metal (SD3) layer, the power line and the connecting line only need one flat layer via to achieve connection, thereby minimizing the occupied space and facilitating the realization of high-resolution display.

[0348] In an exemplary embodiment, at least one of the first to fourth connection lines may extend to the frame region, and the connection lines with the same potential may be connected together through a power supply line in the frame region.

[0349] In the exemplary embodiment, although the present embodiment is described by taking the first to fourth connection lines as an example in which they are all arranged in the sixth conductive layer, the first to fourth connection lines may be arranged in any one conductive layer or multiple conductive layers in the driving circuit layer. For example, one or more of the first to fourth connection lines may be arranged in the fifth conductive layer, and the first to fourth power supply lines may be arranged in the sixth conductive layer, which is not limited in the present disclosure.

[0350] In some possible exemplary embodiments, one or more of the first to fourth connection lines may be disposed in the first conductive layer. For another example, one or more of the first to fourth connection lines may be disposed in the second conductive layer. For another example, one or more of the first to fourth connection lines may be disposed in the third conductive layer. Since the plurality of signal lines in these conductive layers are in the shape of lines extending along the first direction X, it is advantageous to dispose one or more connection lines.

[0351] In the exemplary embodiment, although the present embodiment is described by taking the example that the first to fourth connection lines are all arranged continuously in the display area, one or more of the first to fourth connection lines may be arranged at intervals.

[0352] Fig.18D This is a connection diagram of a connection line of an embodiment of the present disclosure. In an exemplary embodiment, the power line may include a first power line 81, a second power line 82, and a third power line 83, and the connection line may include a first connection line 91, a second connection line 92, and a third connection line 93. The first connection line 91 is connected to the first power line 81, the first power line 81 is connected to the first pixel driving circuit, the second connection line 92 is connected to the second power line 82, the second power line 82 is respectively connected to the second pixel driving circuit and the fourth pixel driving circuit, the third connection line 93 is connected to the third power line 83, and the third power line 83 is connected to the third pixel driving circuit.

[0353] In an exemplary embodiment, in at least one unit row, the first connection line 91, the second connection line 92 and the third connection line 93 can be periodically arranged in the first direction X, and the first connection line 91, the second connection line 92 and the third connection line 93 in adjacent unit rows are staggered to form a staggered stepped structure.

[0354] In an exemplary embodiment, in each unit row, the first connection line 91 is respectively connected to two first power lines 81 adjacent to the first direction X, the second connection line 92 is respectively connected to two second power lines 82 adjacent to the first direction X, and the third connection line 93 is respectively connected to two third power lines 83 adjacent to the first direction X.

[0355] In an exemplary embodiment, the first power line 81, the second power line 82 and the third power line 83 can extend to the binding area or the border area, and the power lines with the same potential are connected together through power lines in the binding area or the border area, so that the connection lines with the same potential in the display area form a mesh structure.

[0356] In an exemplary embodiment, the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in the same conductive layer, or may be disposed in different conductive layers.

[0357] (12) Forming a third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of anode vias are disposed on the third planar layer, such as Fig.19A and Fig.19B As shown, Fig.19B for Fig.19A Schematic diagram of the structures of the four circuit units.

[0358] In an exemplary embodiment, the orthographic projection of the anode via V40 of each circuit unit on the substrate is located within the range of the orthographic projection of the anode connecting electrode 63 on the substrate, the third flat layer in the anode via V40 is removed to expose the surface of the anode connecting electrode 63, and the anode via V40 is configured to connect a subsequently formed anode to the anode connecting electrode 63 through the via.

[0359] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a data signal line, a power line, a first initial signal line, a second initial signal line, and a third initial signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer sequentially arranged on the substrate. The first semiconductor layer may include at least the active layers of the first transistor, the third transistor to the eighth transistor, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the shielding line, the first initial signal line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the fourth scanning signal line, the second initial signal line and the third initial signal line, the fourth conductive layer may include at least a plurality of connection electrodes, the fifth conductive layer may include at least the data signal line and the power line, and the sixth conductive layer may include at least the anode connection electrode and the connection line. The power line may include the first power line, the second power line, the third power line and the fourth power line, and the connection line may include the first connection line, the second connection line, the third connection line and the fourth connection line.

[0360] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0361] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first planar layer, the second planar layer and the third planar layer may be made of organic materials, such as resin, etc.

[0362] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0363] (13) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on the third flat layer, such as Fig. 20A and Fig. 20B As shown, Fig. 20B for Fig. 20A Schematic diagram of the plan view of the anode conductive layer.

[0364] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0365] In an exemplary embodiment, the anode conductive layer may include a first anode 90A located in a red light-emitting unit, a second anode 90B located in a first green light-emitting unit, a third anode 90C located in a blue light-emitting unit, and a fourth anode 90D located in a second green light-emitting unit. The first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be respectively connected to the anode connecting electrode 63 of the circuit unit through the anode via V40.

[0366] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include a main body portion 110 and a connecting portion 120 that are connected to each other. The main body portion 110 may be circular or elliptical, and the connecting portion 120 may be strip-shaped. The first end of the connecting portion 120 is directly connected to the main body portion 110, and the second end of the connecting portion 120 extends in a direction away from the main body portion 110 and is connected to the anode connecting electrode 63 through the anode via V40.

[0367] In an exemplary embodiment, the first anode 90A of the red light emitting unit is connected to the first pixel driving circuit of the first circuit unit, the second anode 90B of the first green light emitting unit is connected to the second pixel driving circuit of the second circuit unit, the third anode 90C of the blue light emitting unit is connected to the third pixel driving circuit of the third circuit unit, and the fourth anode 90D of the second green light emitting unit is connected to the fourth pixel driving circuit of the fourth circuit unit.

[0368] In an exemplary embodiment, the main body 110 of the first anode 90A in the red light-emitting unit is at least partially overlapped with the main body 110 of the connected first pixel driving circuit on the substrate. For example, the main body 110 of the first anode 90A in an odd-numbered light-emitting row is at least partially overlapped with the first pixel driving circuit of the Nth unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the Nth unit column. The main body 110 of the first anode 90A in another odd-numbered light-emitting row is at least partially overlapped with the first pixel driving circuit of the N+4th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the N+4th unit column. For another example, the main body 110 of the first anode 90A in an even-numbered light-emitting row at least partially overlaps with the first pixel driving circuit of the N+2th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the N+2th unit column. The main body 110 of the first anode 90A in another even-numbered light-emitting row at least partially overlaps with the first pixel driving circuit of the N+6th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the N+6th unit column.

[0369] In an exemplary embodiment, the main body 110 of the second anode 90B of the first green light-emitting unit is at least partially overlapped with the orthographic projection of the second pixel driving circuit connected to it on the substrate. For example, the main body 110 of the second anode 90B in an odd-numbered light-emitting row is at least partially overlapped with the second pixel driving circuit of the N+1th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+1th unit column. The main body 110 of the second anode 90B in another odd-numbered light-emitting row is at least partially overlapped with the second pixel driving circuit of the N+5th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+5th unit column. For another example, the main body 110 of the second anode 90B in an even-numbered light-emitting row at least partially overlaps with the second pixel driving circuit of the N+4th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+4th unit column. The main body 110 of the second anode 90B in another even-numbered light-emitting row at least partially overlaps with the second pixel driving circuit of the N+7th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+7th unit column.

[0370] In an exemplary embodiment, the main body 110 of the third anode 90C in the blue light-emitting unit is at least partially overlapped with the main body 110 of the connected third pixel driving circuit in the substrate. For example, the main body 110 of the third anode 90C in an odd-numbered light-emitting row is at least partially overlapped with the third pixel driving circuit of the N+2th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+3th unit column. The main body 110 of the third anode 90C in another odd-numbered light-emitting row is at least partially overlapped with the third pixel driving circuit of the N+6th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+6th unit column. For another example, the main body 110 of the third anode 90C in an even-numbered light-emitting row at least partially overlaps with the third pixel driving circuit of the Nth unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the Nth unit column. The main body 110 of the third anode 90C in another even-numbered light-emitting row at least partially overlaps with the third pixel driving circuit of the N+4th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+4th unit column.

[0371] In an exemplary embodiment, the main body 110 of the fourth anode 90D of the second green light-emitting unit is at least partially overlapped with the main body 110 of the fourth pixel driving circuit connected to it in the substrate. For example, the main body 110 of the fourth anode 90D in an odd-numbered light-emitting row is at least partially overlapped with the fourth pixel driving circuit of the N+3th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+3th unit column. The main body 110 of the fourth anode 90D in another odd-numbered light-emitting row is at least partially overlapped with the fourth pixel driving circuit of the N+7th unit column in the Mth unit row (or the M+2th unit row), and the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+7th unit column. For another example, the main body 110 of the fourth anode 90D in an even-numbered light-emitting row at least partially overlaps with the fourth pixel driving circuit of the N+1th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+1th unit column. The main body 110 of the fourth anode 90D in another even-numbered light-emitting row at least partially overlaps with the fourth pixel driving circuit of the N+5th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+5th unit column.

[0372] In an exemplary embodiment, the subsequent preparation process may include: forming a pixel definition layer pattern, a plurality of pixel openings are provided on the pixel definition layer, and the plurality of pixel openings may respectively expose the surfaces of the first anode, the second anode, the third anode and the fourth anode. Subsequently, an organic light-emitting layer is formed by evaporation or inkjet printing, and then a cathode is formed on the organic light-emitting layer to complete the preparation of the light-emitting structure layer. Subsequently, an encapsulation structure layer is formed, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0373] Fig.21A FIG. 1 is a schematic diagram of another arrangement of circuit units of an exemplary embodiment of the present disclosure. Fig.21B FIG. 1 is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Fig. 21C FIG. 2 is a schematic diagram showing another connection between a circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure. Fig.21A , Fig.21B and Fig. 21C As shown, on a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, a third circuit unit Q3 and a fourth circuit unit Q4, and the plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, a third light-emitting unit F3 and a fourth light-emitting unit F4.

[0374] In an exemplary embodiment, in each unit row, the first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 may be periodically arranged in the first direction X, that is, the circuit units of the odd unit rows and the even unit rows are arranged in the same manner, and the same circuit units are arranged in each unit column. For example, the first unit column is provided with a plurality of first circuit units Q1, the second unit column is provided with a plurality of second circuit units Q2, the third unit column is provided with a plurality of third circuit units Q3, and the fourth unit column is provided with a plurality of fourth circuit units Q4.

[0375] In an exemplary embodiment, in one light-emitting row, the first light-emitting unit F1, the second light-emitting unit F2, the third light-emitting unit F3 and the fourth light-emitting unit F4 may be periodically arranged in the first direction X, and the corresponding light-emitting units in the odd-numbered light-emitting rows and the even-numbered light-emitting rows are staggered. In one light-emitting column, the first light-emitting unit F1 and the third light-emitting unit F3 are alternately arranged in the second direction Y, and in another light-emitting column, the second light-emitting unit F2 and the fourth light-emitting unit F4 are alternately arranged in the second direction Y.

[0376] In an exemplary embodiment, the first light-emitting device of the first light-emitting unit F1 is connected to the first pixel driving circuit of the first circuit unit Q1. In one light-emitting row (for example, an odd-numbered light-emitting row), the position of the positive projection of the first light-emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected first pixel driving circuit on the substrate. In another light-emitting row (for example, an even-numbered light-emitting row), the position of the positive projection of the first light-emitting device on the substrate is not corresponding to the position of the positive projection of the connected first pixel driving circuit on the substrate, and the position of the positive projection of the first light-emitting device on the substrate is substantially corresponding to the position of the positive projection of the third pixel driving circuit of the third circuit unit Q3 on the substrate, and the first light-emitting device is connected to the first pixel driving circuit of the first circuit unit Q1 through the anode adapter 130.

[0377] In an exemplary embodiment, the third light-emitting device of the third light-emitting unit F3 is connected to the third pixel driving circuit of the third circuit unit Q3. In one light-emitting row (for example, an odd-numbered light-emitting row), the position of the positive projection of the third light-emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected third pixel driving circuit on the substrate. In another light-emitting row (for example, an even-numbered light-emitting row), the position of the positive projection of the third light-emitting device on the substrate is not corresponding to the position of the positive projection of the connected third pixel driving circuit on the substrate, and the position of the positive projection of the third light-emitting device on the substrate is substantially corresponding to the position of the positive projection of the first pixel driving circuit of the first circuit unit Q1 on the substrate, and the third light-emitting device is connected to the third pixel driving circuit of the third circuit unit Q3 through the anode adapter 130.

[0378] In an exemplary embodiment, the second light-emitting device of the second light-emitting unit F2 is connected to the second pixel driving circuit of the second circuit unit Q2 or the fourth pixel driving circuit of the fourth circuit unit Q4. In one light-emitting row (e.g., an odd-numbered light-emitting row), the position of the positive projection of the second light-emitting device on the substrate substantially corresponds to the position of the positive projection of the connected second pixel driving circuit on the substrate. In another light-emitting row (e.g., an even-numbered light-emitting row), the position of the positive projection of the second light-emitting device on the substrate substantially corresponds to the position of the positive projection of the connected fourth pixel driving circuit on the substrate.

[0379] In an exemplary embodiment, the fourth light-emitting device of the fourth light-emitting unit F4 is connected to the second pixel driving circuit of the second circuit unit Q2 or the fourth pixel driving circuit of the fourth circuit unit Q4. In one light-emitting row (e.g., an odd-numbered light-emitting row), the position of the positive projection of the fourth light-emitting device on the substrate substantially corresponds to the position of the positive projection of the connected fourth pixel driving circuit on the substrate. In another light-emitting row (e.g., an even-numbered light-emitting row), the position of the positive projection of the fourth light-emitting device on the substrate substantially corresponds to the position of the positive projection of the connected second pixel driving circuit on the substrate.

[0380] Fig. 22 FIG. 1 is another schematic diagram showing the connection of power lines and connection lines in a display substrate according to an exemplary embodiment of the present disclosure. Fig. 22 As shown, in an exemplary embodiment of the present disclosure, the power line may include a first power line 81, a second power line 82, a third power line 83 and a fourth power line 84, and the connection line may include a first connection line 91, a second connection line 92, a third connection line 93 and a fourth connection line 94.

[0381] In an exemplary embodiment, any one or more of the first power line 81 , the second power line 82 , the third power line 83 , and the fourth power line 84 may be disposed in at least one cell column.

[0382] In an exemplary embodiment, the shapes of the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 can be straight lines or broken lines with the main body extending along the second direction Y, and the shapes of the first connection line 91, the second connection line 92, the third connection line 93 and the fourth connection line 94 can be straight lines or broken lines with the main body extending along the first direction X.

[0383] In an exemplary embodiment, the first power line 81 can be separately set in a unit column including the first circuit unit Q1, the second power line 82 can be separately set in a unit column including the second circuit unit Q2, the third power line 83 can be separately set in a unit column including the third circuit unit Q3, and the fourth power line 84 can be separately set in a unit column including the fourth circuit unit Q4, respectively forming unit columns of single power line structure.

[0384] In an exemplary embodiment, the first power line 81 is respectively connected to the first pixel driving circuit of multiple first circuit units Q1 in the unit column, the second power line 82 is respectively connected to the second pixel driving circuit of multiple second circuit units Q2 in the unit column, the third power line 83 is respectively connected to the third pixel driving circuit of multiple third circuit units Q3 in the unit column, and the fourth power line 84 is respectively connected to the fourth pixel driving circuit of multiple fourth circuit units Q4 in the unit column.

[0385] In an exemplary embodiment, any one or more of the first connection line 91 , the second connection line 92 , the third connection line 93 , and the fourth connection line 94 may be disposed in at least one cell row.

[0386] In an exemplary embodiment, the first connection line 91 can be arranged in one unit row and connected to the plurality of first power lines 81, respectively, so that the first connection line 91 extending along the first direction X of the main body part and the first power line 81 extending along the second direction Y of the main body part are connected to each other, forming a grid connection structure. The second connection line 92 can be arranged in another unit row and connected to the plurality of second power lines 82 and the plurality of fourth power lines 84, respectively, so that the second connection line 92 extending along the first direction X of the main body part and the second power line 82 and the fourth power line 84 extending along the second direction Y of the main body part are connected to each other, forming a grid connection structure. The third connection line 93 can be arranged in another unit row and connected to the plurality of third power lines 83, respectively, so that the third connection line 93 extending along the first direction X of the main body part and the third power line 83 extending along the second direction Y of the main body part are connected to each other, forming a grid connection structure. The fourth connecting line 94 can be arranged in another unit row and connected to multiple second power lines 82 and multiple fourth power lines 84 respectively, thereby realizing the mutual connection between the fourth connecting line 94 extending along the first direction X of the main body and the second power lines 82 and fourth power lines 84 extending along the second direction Y of the main body, forming a grid connection structure.

[0387] In an exemplary embodiment, the potentials of the first power line 81 , the second power line 82 , and the third power line 83 may be different, and the potentials of the second power line 82 and the fourth power line 84 may be the same.

[0388] In an exemplary embodiment, the first power line 81 , the second power line 82 , the third power line 83 , and the fourth power line 84 may be disposed in the same conductive layer, or in different conductive layers.

[0389] In an exemplary embodiment, the first connection line 91 , the second connection line 92 , the third connection line 93 , and the fourth connection line 94 may be disposed in the same conductive layer, or in different conductive layers.

[0390] In an exemplary embodiment, the multiple conductive layers may include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in sequence along a direction away from the substrate, the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 may be arranged in the second source-drain metal layer, and the first connection line 91, the second connection line 92, the third connection line 93, and the fourth connection line 94 may be arranged in the third source-drain metal layer.

[0391] In an exemplary embodiment, taking 32 circuit units (4 unit rows and 8 unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0392] (21) A first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a sixth insulating layer pattern are sequentially formed, and the process and the formed structure are substantially the same as steps (1) to (6) of the aforementioned embodiment.

[0393] (22) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Fig.23A , Fig. 23B and Fig.23C As shown, Fig. 23B for Fig.23A The structural diagram of the four circuit units in the figure is as follows: Fig.23C for Fig.23A Schematic plan view of the fourth conductive layer in FIG.

[0394] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58 and a ninth connecting electrode 59. The positions and shapes of the above-mentioned connecting electrodes are basically the same as those in the aforementioned embodiments. The difference is that the position and shape of the power connection block 54-1 in the first circuit unit, the second circuit unit, the third circuit unit and the fourth circuit unit can be basically the same, and are all arranged between the first end and the second end of the fourth connecting electrode 54.

[0395] In an exemplary embodiment, the fourth conductive layer may further include a first preliminary connection line 41 , a second preliminary connection line 42 , a first preliminary connection bar 43 , and a second preliminary connection bar 44 , and the positions and shapes of the connection electrodes are substantially the same as those of the aforementioned embodiment.

[0396] In an exemplary embodiment, the fourth conductive layers of some adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the fourth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+2th unit column and the fourth conductive layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+4th unit column and the fourth conductive layer of the N+5th unit column may be mirror-symmetric with respect to the column boundary.

[0397] In example embodiments, shapes of the fourth conductive layers in a plurality of cell rows may be substantially the same.

[0398] (23) forming a first planar layer pattern, the process and the formed via structure are substantially the same as those in step (8) of the aforementioned embodiment, the plurality of vias in each circuit unit at least include a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23, the via structure being substantially the same as that in the aforementioned embodiment, such as Fig.24A and Fig. 24B As shown, Fig. 24B for Fig.24A Schematic diagram of the structures of the four circuit units.

[0399] (24) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Fig.25A , Fig.25B and Fig.25C As shown, Fig.25B for Fig.25A The structural diagram of the four circuit units in the figure is as follows: Fig.25C for Fig.25A Schematic plan view of the fifth conductive layer in FIG.

[0400] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least an eleventh connection electrode 61 and a data signal line 62 , and the structures of the eleventh connection electrode 61 and the data signal line 62 are substantially the same as those of the aforementioned embodiment.

[0401] In an exemplary embodiment, the fifth conductive layer may further include a first power line 81, a second power line 82, a third power line 83 and a fourth power line 84. The shape of each power line may be a zigzag line with a main body extending along the second direction Y, and each of the power lines may be connected to the power connection block 54-1 through the twenty-third via hole V23 of the corresponding circuit unit, thereby enabling the power line to write the power signal into the first electrode of the fifth transistor T5 in the corresponding circuit unit and the second electrode plate 72 of the storage capacitor.

[0402] In an exemplary embodiment, the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 can be zigzag lines of unequal width, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the power lines and the data signal lines.

[0403] In an exemplary embodiment, any one or more of the first power line 81, the second power line 82, the third power line 83, and the fourth power line 84 are arranged in at least one unit column. For example, the four power lines can be arranged in different unit columns, respectively. For another example, two of the four power lines can be arranged in the same unit column.

[0404] In an exemplary embodiment, since the same first circuit unit is set in one unit column, the first power line 81 can be set in one unit column alone, and the first power line 81 is connected to the pixel driving circuits of all the first circuit units in the unit column. Since the same second circuit unit is set in one unit column, the second power line 82 can be set in one unit column alone, and the second power line 82 is connected to the pixel driving circuits of all the second circuit units in the unit column. Since the same third circuit unit is set in one unit column, the third power line 83 can be set in one unit column alone, and the third power line 83 is connected to the pixel driving circuits of all the third circuit units in the unit column. Since the same fourth circuit unit is set in one unit column, the fourth power line 84 can be set in one unit column alone, and the fourth power line 84 is connected to the pixel driving circuits of all the fourth circuit units in the unit column.

[0405] In an exemplary embodiment, the first power line 81 can be arranged in the Nth unit column and the N+4th unit column, the second power line 82 can be arranged in the N+1th unit column and the N+5th unit column, the third power line 83 can be arranged in the N+2th unit column and the N+6th unit column, and the fourth power line 84 can be arranged in the N+3th unit column and the N+7th unit column, and a single power line structure is formed in the above unit columns. In this way, the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 are periodically arranged along the first direction X.

[0406] In an exemplary embodiment, the positive projection of at least one of the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 on the substrate at least partially overlaps with the positive projection of the first connecting electrode 51 on the substrate. The power line with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node N1, and improve the driving performance of the pixel driving circuit.

[0407] In an exemplary embodiment, the orthographic projection of at least one of the first power line 81, the second power line 82, the third power line 83 and the fourth power line 84 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the power line can block the second active layer, thereby blocking the light emission of the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, preventing the oxide transistor from drifting in characteristics due to light, and improving the electrical characteristics of the oxide transistor.

[0408] In an exemplary embodiment, an orthographic projection of at least one of the first power line 81 , the second power line 82 , the third power line 83 , and the fourth power line 84 on the substrate at least partially overlaps an orthographic projection of the second connection electrode 52 on the substrate.

[0409] In an exemplary embodiment, the fifth conductive layer of the adjacent unit column can be mirror-symmetric with respect to the column boundary. For example, the fourth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column can be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+1th unit column and the fourth conductive layer of the N+2th unit column can be mirror-symmetric with respect to the column boundary. For another example, the fourth conductive layer of the N+2th unit column and the fourth conductive layer of the N+3th unit column can be mirror-symmetric with respect to the column boundary.

[0410] In example embodiments, shapes of the fourth conductive layers in a plurality of cell rows may be substantially the same.

[0411] (25) forming a second flat layer pattern, the process and the formed via structure are substantially the same as those in step (10) of the aforementioned embodiment, the plurality of vias in each circuit unit includes at least a thirty-first via V31, and the second flat layer of at least one circuit unit may further be provided with a forty-first via V41, a forty-second via V42, a forty-third via V43 or a forty-fourth via V44, and the above via structure is substantially the same as that in the aforementioned embodiment, such as Fig.26A and Fig.26B As shown, Fig.26B for Fig.26A Schematic diagram of the structures of the four circuit units.

[0412] In an exemplary embodiment, only the forty-first via V41 or only the forty-third via V43 may be set in the multiple circuit units of at least one unit row, the forty-second via V42 and the forty-fourth via V44 may be simultaneously set in the multiple circuit units of at least another unit row, and only the forty-first via V41, the forty-second via V42, the forty-third via V43 or the forty-fourth via V44 may be set in the multiple circuit units of at least one unit column.

[0413] (26) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second planar layer, such as Fig.27A , Fig.27B and Fig.27C As shown, Fig.27B for Fig.27A The structural diagram of the four circuit units in the figure is as follows: Fig.27C for Fig.27ASchematic plan view of the sixth conductive layer in FIG.

[0414] In an exemplary embodiment, the sixth conductive layer of each circuit unit includes at least an anode connecting electrode 63, and the shape and position of the anode connecting electrode 63 are basically the same as those in the aforementioned embodiment. The difference is that the length of the anode connecting electrode 63 in some circuit units is greater than the length of the anode connecting electrode 63 in other circuit units, and the length is the dimension of the anode connecting electrode 63 in the second direction Y.

[0415] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may also be provided with a first connecting line 91, a second connecting line 92, a third connecting line 93 or a fourth connecting line 94, and the positions, shapes and connection structures of the above connecting lines are substantially the same as those in the aforementioned embodiments. The first power line 81 and the first connecting line 91 constitute a grid connection structure for transmitting a first power signal on the display substrate, the second power line 82 and the second connecting line 92 constitute a grid connection structure for transmitting a second power signal on the display substrate, the third power line 83 and the third connecting line 93 constitute a grid connection structure for transmitting a third power signal on the display substrate, and the fourth power line 84 and the fourth connecting line 94 constitute a grid connection structure for transmitting a fourth power signal on the display substrate.

[0416] In an exemplary embodiment, in at least one unit row, the second connection line 92 is also connected to multiple fourth power lines 84 through multiple forty-fourth vias V44, and the fourth connection line 94 is also connected to multiple second power lines 82 through multiple forty-second vias V42, so that the second power line 82 and the fourth power line 84 have the same potential.

[0417] In an exemplary embodiment, only one connection line may be provided in a cell row, or two connection lines may be provided in a cell row. For example, a first connection line 91 and a third connection line 93 may be provided in the Mth cell row. For another example, a first connection line 91 and a third connection line 93 may be provided in the M+2th cell row.

[0418] (27) A third planar layer pattern is formed. The process and the formed via structure are substantially the same as step (12) of the aforementioned embodiment. A plurality of anode vias V40 are provided on the third planar layer. Fig.28A and Fig.28B As shown, Fig.28B for Fig.28A Schematic diagram of the structures of the four circuit units.

[0419] (28) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on the third flat layer, such as Fig.29A and Fig.29B As shown, Fig.29B for Fig.29A Schematic plan view of the sixth conductive layer in FIG.

[0420] In an exemplary embodiment, the anode conductive layer may include a first anode 90A located in a red light-emitting unit, a second anode 90B located in a first green light-emitting unit, a third anode 90C located in a blue light-emitting unit, and a fourth anode 90D located in a second green light-emitting unit. The first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be respectively connected to the anode connecting electrode 63 of the circuit unit through the anode via V40.

[0421] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include a main body 110 and a connecting portion 120, the shape of the main body 110 may be circular or elliptical, the shape of the connecting portion 120 may be strip-shaped, the first end of the connecting portion 120 is directly connected to the main body 110, or the first end of the connecting portion 120 is connected to the main body 110 via an anode transfer line 130, and the second end of the connecting portion 120 is connected to the anode connecting electrode 63 via an anode via V40.

[0422] In an exemplary embodiment, the first anode 90A of the red light emitting unit is connected to the first pixel driving circuit of the first circuit unit.

[0423] In an exemplary embodiment, in an emitting row (e.g., an odd-numbered emitting row), the main body 110 of at least part of the first anode 90A overlaps at least partially with the main body 110 of the connected first pixel driving circuit on the substrate in its orthographic projection on the substrate. For example, the main body 110 of the first anode 90A in an odd-numbered emitting row overlaps at least partially with the first pixel driving circuit of the Nth unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the Nth unit column. For another example, the main body 110 of the first anode 90A in an odd-numbered emitting row overlaps at least partially with the first pixel driving circuit of the N+4th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the first anode 90A is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the N+4th unit column.

[0424] In an exemplary embodiment, in another light-emitting row (e.g., an even-numbered light-emitting row), the main body 110 of at least part of the first anode 90A does not overlap with the main body 110 of the connected first pixel driving circuit in the substrate in the orthographic projection on the substrate. For example, the main body 110 of the first anode 90A in an even-numbered light-emitting row does not overlap with the first pixel driving circuit of the Nth unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the first anode 90A is connected to the main body 110 through the anode adapter 130, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the Nth unit column. The first end of the anode adapter 130 is connected to the main body 110, and after the anode adapter 130 extends from the N+2th unit column to the Nth unit column, the second end of the anode adapter 130 is connected to the first end of the connecting portion 120. For another example, the main body 110 of the first anode 90A in an even-numbered light-emitting row does not overlap with the first pixel driving circuit of the N+4th unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the first anode 90A is connected to the main body 110 through the anode adapter 130, and the second end of the connecting portion 120 is connected to the first pixel driving circuit of the N+4th unit column. The first end of the anode adapter 130 is connected to the main body 110, and after the anode adapter 130 extends from the N+6th unit column to the N+4th unit column, the second end of the anode adapter 130 is connected to the first end of the connecting portion 120.

[0425] In an exemplary embodiment, an orthographic projection of at least a portion of the main body 110 of the first anode 90A on the substrate at least partially overlaps an orthographic projection of the third pixel driving circuit of the third circuit unit on the substrate.

[0426] In an exemplary embodiment, an orthographic projection of the anode jumper wire 130 to which the first anode 90A is connected on the substrate at least partially overlaps with an orthographic projection of the second pixel driving circuit of the second circuit unit on the substrate.

[0427] In an exemplary embodiment, the third anode 90C of the blue light emitting unit is connected to the third pixel driving circuit of the third circuit unit.

[0428] In an exemplary embodiment, in one light-emitting row (e.g., an odd-numbered light-emitting row), the main body 110 of at least part of the third anode 90C overlaps at least partially with the main body 110 of the connected third pixel driving circuit on the substrate in its orthographic projection on the substrate. For example, the main body 110 of the third anode 90C in an odd-numbered light-emitting row overlaps at least partially with the third pixel driving circuit of the N+2th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+3th unit column. For another example, the main body 110 of the third anode 90C in an odd-numbered light-emitting row overlaps at least partially with the third pixel driving circuit of the N+6th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the third anode 90C is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+6th unit column.

[0429] In an exemplary embodiment, in another light-emitting row (e.g., an even-numbered light-emitting row), the main body 110 of at least part of the third anode 90C does not overlap with the main body 110 of the connected third pixel driving circuit in the substrate in the orthographic projection on the substrate. For example, the main body 110 of the third anode 90C in an even-numbered light-emitting row does not overlap with the third pixel driving circuit of the N+2th unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the third anode 90C is connected to the main body 110 through the anode adapter 130, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+2th unit column. The first end of the anode adapter 130 is connected to the main body 110, and after the anode adapter 130 extends from the Nth unit column to the N+2th unit column, the second end of the anode adapter 130 is connected to the first end of the connecting portion 120. For another example, the main body 110 of the third anode 90C in an even-numbered light-emitting row does not overlap with the third pixel driving circuit of the N+6th unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the third anode 90C is connected to the main body 110 through the anode adapter 130, and the second end of the connecting portion 120 is connected to the third pixel driving circuit of the N+6th unit column. The first end of the anode adapter 130 is connected to the main body 110, and after the anode adapter 130 extends from the N+4th unit column to the N+6th unit column, the second end of the anode adapter 130 is connected to the first end of the connecting portion 120.

[0430] In an exemplary embodiment, an orthographic projection of the main body portion 110 of the third anode 90C on the substrate at least partially overlaps an orthographic projection of the first pixel driving circuit of the first circuit unit on the substrate.

[0431] In an exemplary embodiment, an orthographic projection of the anode jumper wire 130 to which the third anode 90C is connected on the substrate at least partially overlaps with an orthographic projection of the fourth pixel driving circuit of the fourth circuit unit on the substrate.

[0432] In an exemplary embodiment, the second anode 90B of the first green light emitting unit is connected to the second pixel driving circuit of the second circuit unit or the fourth pixel driving circuit of the fourth circuit unit.

[0433] In an exemplary embodiment, in one light-emitting row (e.g., an odd-numbered light-emitting row), the main body 110 of at least part of the second anode 90B overlaps at least partially with the main body 110 of the connected second pixel driving circuit on the substrate in its orthographic projection on the substrate. For example, the main body 110 of the second anode 90B in one odd-numbered light-emitting row overlaps at least partially with the second pixel driving circuit of the N+1th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+1th unit column. For another example, the main body 110 of the second anode 90B in another odd-numbered light-emitting row overlaps at least partially with the second pixel driving circuit of the N+5th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+5th unit column.

[0434] In an exemplary embodiment, in another light-emitting row (e.g., an even-numbered light-emitting row), the main body 110 of at least part of the second anode 90B overlaps at least partially with the main body 110 of the connected fourth pixel driving circuit on the substrate in the positive projection on the substrate. For example, the main body 110 of the second anode 90B in an even-numbered light-emitting row overlaps at least partially with the fourth pixel driving circuit of the N+4th unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+4th unit column. For another example, the main body 110 of the second anode 90B in an even-numbered light-emitting row overlaps at least partially with the fourth pixel driving circuit of the N+7th unit column in the M+1th unit row (or the M+3th unit row), and the first end of the connecting portion 120 of the second anode 90B is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+7th unit column.

[0435] In an exemplary embodiment, the fourth anode 90D of the second green light emitting unit is connected to the second pixel driving circuit of the second circuit unit or the fourth pixel driving circuit of the fourth circuit unit.

[0436] In an exemplary embodiment, in one light-emitting row (e.g., an odd-numbered light-emitting row), the main body 110 of at least part of the fourth anode 90D overlaps at least partially with the main body 110 of the connected fourth pixel driving circuit on the substrate in an orthographic projection on the substrate. For example, the main body 110 of the fourth anode 90D in an odd-numbered light-emitting row overlaps at least partially with the fourth pixel driving circuit of the N+3th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+3th unit column. For another example, the main body 110 of the fourth anode 90D in an odd-numbered light-emitting row overlaps at least partially with the fourth pixel driving circuit of the N+7th unit column in the Mth unit row (or the M+2th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the fourth pixel driving circuit of the N+7th unit column.

[0437] In an exemplary embodiment, in an even-numbered light-emitting row (e.g., an even-numbered light-emitting row), the main body 110 of at least part of the fourth anode 90D overlaps at least partially with the main body 110 of the connected second pixel driving circuit on the substrate. For example, the main body 110 of the fourth anode 90D in an even-numbered light-emitting row overlaps at least partially with the second pixel driving circuit of the N+1th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+1th unit column. For another example, the main body 110 of the fourth anode 90D in an even-numbered light-emitting row overlaps at least partially with the second pixel driving circuit of the N+5th unit column in the M+1th unit row (or the M+3th unit row), the first end of the connecting portion 120 of the fourth anode 90D is directly connected to the main body 110, and the second end of the connecting portion 120 is connected to the second pixel driving circuit of the N+5th unit column.

[0438] Fig.29C FIG. 1 is a schematic diagram of a connection of an anode adapter cable according to an embodiment of the present disclosure. Fig.29C As shown, the connection structure between the anode and the pixel driving circuit in this embodiment is similar to Fig.29A and Fig.29B The structures shown are substantially the same, except that the anode transition wires extend in the same direction.

[0439] In an exemplary embodiment, for the first anode located in the M+1th unit row and the N+2th unit column, the main body of the first anode does not overlap with the first pixel driving circuit. The first end of the anode adapter line 130 is connected to the main body of the first anode, and after the anode adapter line 130 extends from the N+2th unit column to the N+4th unit column, the second end of the anode adapter line 130 is connected to the connecting portion of the first anode, and the connecting portion of the first anode is connected to the first pixel driving circuit of the M+1th unit row and the N+4th unit column.

[0440] In an exemplary embodiment, for the third anode located in the M+1th unit row and the Nth unit column, the main body of the third anode does not overlap with the third pixel driving circuit. The first end of the anode adapter line 130 is connected to the main body of the third anode, and after the anode adapter line 130 extends from the Nth unit column to the N+2th unit column, the second end of the anode adapter line 130 is connected to the connecting portion of the third anode, and the connecting portion of the third anode is connected to the third pixel driving circuit of the M+1th unit row and the N+2th unit column.

[0441] The present invention arranges multiple anode adapter lines to extend in the same direction, thereby avoiding the crossing of the anode adapter lines and increasing the distance between the anode adapter lines, which can effectively reduce the difficulty of layout and improve the process quality.

[0442] In an exemplary embodiment, although the present embodiment is described by taking the anode switching line disposed in the anode conductive layer as an example, the anode switching line may be disposed in any conductive layer or multiple conductive layers in the display substrate, and the present disclosure is not limited thereto.

[0443] In a possible exemplary embodiment, the anode connection line can be arranged in the sixth conductive layer, and the anode connection line and the anode connection electrode are arranged in the same layer and are formed synchronously through the same patterning process. For the first circuit unit of the M+1th unit row and the Nth unit column, the anode connection electrode of the circuit unit can be connected to the eleventh connection electrode of the third circuit unit of the M+1th unit row and the N+2th unit column through the anode connection line. For the third circuit unit of the M+1th unit row and the N+2th unit column, the anode connection electrode of the circuit unit can be connected to the eleventh connection electrode of the first circuit unit of the M+1th unit row and the N+2th unit column through the anode connection line.

[0444] In another possible exemplary embodiment, the anode connection line can be arranged in the fifth conductive layer, and the anode connection line and the eleventh connection electrode are arranged in the same layer and are formed synchronously through the same patterning process. For the first circuit unit of the M+1th unit row and the Nth unit column, the eleventh connection electrode of the circuit unit can be connected to the sixth connection electrode of the third circuit unit of the M+1th unit row and the N+2th unit column through the anode connection line. For the third circuit unit of the M+1th unit row and the N+2th unit column, the eleventh connection electrode of the circuit unit can be connected to the sixth connection electrode of the first circuit unit of the M+1th unit row and the N+2th unit column through the anode connection line.

[0445] In an exemplary embodiment, the subsequent preparation process may include: forming a pixel definition layer pattern, a plurality of pixel openings are provided on the pixel definition layer, and the plurality of pixel openings may respectively expose the surfaces of the first anode, the second anode, the third anode and the fourth anode. Subsequently, an organic light-emitting layer is formed by evaporation or inkjet printing, and then a cathode is formed on the organic light-emitting layer to complete the preparation of the light-emitting structure layer. Subsequently, an encapsulation structure layer is formed, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0446] Fig. 30A FIG. 1 is a schematic diagram of another arrangement of a circuit unit according to an exemplary embodiment of the present disclosure. Fig. 30B FIG. 1 is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Fig. 30C FIG. 2 is a schematic diagram showing the connection between another circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure. Fig. 30A , Fig. 30B and Fig. 30C As shown, on a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3, and the plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, and a third light-emitting unit F3.

[0447] In an exemplary embodiment, in each unit row, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be periodically arranged in the first direction X, that is, the circuit units of the odd unit rows and the even unit rows are arranged in the same manner. In each unit column, the same circuit unit is arranged. For example, the first unit column is provided with a plurality of first circuit units Q1, the second unit column is provided with a plurality of second circuit units Q2, and the third unit column is provided with a plurality of third circuit units Q3.

[0448] In an exemplary embodiment, in each light-emitting row, the first light-emitting unit F1, the second light-emitting unit F2, and the third light-emitting unit F3 may be periodically arranged in the first direction X, that is, the light-emitting units of the odd-numbered unit rows and the even-numbered unit rows are arranged in the same manner. In each light-emitting column, the same light-emitting unit is arranged. For example, the first light-emitting column is provided with a plurality of first light-emitting units F1, the second light-emitting column is provided with a plurality of second light-emitting units F2, and the third light-emitting column is provided with a plurality of third light-emitting units F3.

[0449] In an exemplary embodiment, the first light emitting device of the first light emitting unit F1 is connected to the first pixel driving circuit of the first circuit unit Q1. In each light emitting row, the position of the positive projection of the first light emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected first pixel driving circuit on the substrate.

[0450] In an exemplary embodiment, the second light emitting device of the second light emitting unit F2 is connected to the second pixel driving circuit of the second circuit unit Q2. In each light emitting row, the position of the second light emitting device projected on the substrate substantially corresponds to the position of the connected second pixel driving circuit projected on the substrate.

[0451] In an exemplary embodiment, the third light emitting device of the third light emitting unit F3 is connected to the third pixel driving circuit of the third circuit unit Q3. In each light emitting row, the position of the positive projection of the third light emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected third pixel driving circuit on the substrate.

[0452] Fig.31 FIG. 1 is another schematic diagram showing the connection of power lines and connection lines in a display substrate according to an exemplary embodiment of the present disclosure. Fig.31 As shown, in an exemplary embodiment of the present disclosure, the power line may include a first power line 81 , a second power line 82 , and a third power line 83 , and the connection line may include a first connection line 91 , a second connection line 92 , and a third connection line 93 .

[0453] In an exemplary embodiment, the shapes of the first power line 81, the second power line 82 and the third power line 83 can be straight lines or broken lines with the main body extending along the second direction Y, and the shapes of the first connection line 91, the second connection line 92 and the third connection line 93 can be straight lines or broken lines with the main body extending along the first direction X.

[0454] In an exemplary embodiment, any one or more of the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in at least one cell column.

[0455] In an exemplary embodiment, the first power line 81 can be separately set in a unit column including a first circuit unit Q1, and the first power line 81 is respectively connected to the first pixel driving circuits of multiple first circuit units Q1 in the unit column. The second power line 82 can be separately set in a unit column including a second circuit unit Q2, and the second power line 82 is respectively connected to the second pixel driving circuits of multiple second circuit units Q2 in the unit column. The third power line 83 can be separately set in a unit column including a third circuit unit Q3, and the third power line 83 is respectively connected to the third pixel driving circuits of multiple third circuit units Q3 in the unit column, forming unit columns with single power line structures.

[0456] In an exemplary embodiment, any one or more of the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in at least one cell row.

[0457] In an exemplary embodiment, the first connection line 91 can be arranged in one unit row and connected to the plurality of first power lines 81, respectively, so that the first connection line 91 extending along the first direction X of the main part and the first power line 81 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure. The second connection line 92 can be arranged in another unit row and connected to the plurality of second power lines 82, respectively, so that the second connection line 92 extending along the first direction X of the main part and the second power line 82 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure. The third connection line 93 can be arranged in another unit row and connected to the plurality of third power lines 83, respectively, so that the third connection line 93 extending along the first direction X of the main part and the third power line 83 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure.

[0458] In an exemplary embodiment, the potentials of the first power line 81 , the second power line 82 , and the third power line 83 may be different.

[0459] In an exemplary embodiment, the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in the same conductive layer, or in different conductive layers.

[0460] In an exemplary embodiment, the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in the same conductive layer, or in different conductive layers.

[0461] Fig.32A FIG. 1 is a schematic diagram of another arrangement of a circuit unit according to an exemplary embodiment of the present disclosure. Fig.32B FIG. 1 is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Fig.32CFIG. 2 is a schematic diagram showing the connection between another circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure. Fig.32A , Fig.32B and Fig.32C As shown, on a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3, and the plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, and a third light-emitting unit F3.

[0462] In an exemplary embodiment, in each unit column, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 can be arranged periodically in the second direction Y, that is, the circuit units of the odd unit columns and the even unit columns are arranged in the same manner. In each unit row, the same circuit unit is arranged. For example, the first unit row is provided with a plurality of first circuit units Q1, the second unit row is provided with a plurality of second circuit units Q2, and the third unit row is provided with a plurality of third circuit units Q3.

[0463] In an exemplary embodiment, in each light-emitting column, the first light-emitting unit F1, the second light-emitting unit F2, and the third light-emitting unit F3 may be periodically arranged in the second direction Y, that is, the light-emitting units of the odd-numbered unit columns and the even-numbered unit columns are arranged in the same manner. In each light-emitting row, the same light-emitting unit is arranged. For example, the first light-emitting row is provided with a plurality of first light-emitting units F1, the second light-emitting row is provided with a plurality of second light-emitting units F2, and the third light-emitting row is provided with a plurality of third light-emitting units F3.

[0464] In an exemplary embodiment, the first light emitting device of the first light emitting unit F1 is connected to the first pixel driving circuit of the first circuit unit Q1. In each light emitting column, the position of the positive projection of the first light emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected first pixel driving circuit on the substrate.

[0465] In an exemplary embodiment, the second light emitting device of the second light emitting unit F2 is connected to the second pixel driving circuit of the second circuit unit Q2. In each light emitting column, the position of the positive projection of the second light emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected second pixel driving circuit on the substrate.

[0466] In an exemplary embodiment, the third light emitting device of the third light emitting unit F3 is connected to the third pixel driving circuit of the third circuit unit Q3. In each light emitting column, the position of the positive projection of the third light emitting device on the substrate is substantially corresponding to the position of the positive projection of the connected third pixel driving circuit on the substrate.

[0467] Fig.33FIG. 1 is another schematic diagram showing the connection of power lines and connection lines in a display substrate according to an exemplary embodiment of the present disclosure. Fig.33 As shown, in an exemplary embodiment of the present disclosure, the power line may include a first power line 81 , a second power line 82 , and a third power line 83 , and the connection line may include a first connection line 91 , a second connection line 92 , and a third connection line 93 .

[0468] In an exemplary embodiment, the shapes of the first power line 81, the second power line 82 and the third power line 83 can be straight lines or broken lines with the main body extending along the first direction X, and the shapes of the first connecting line 91, the second connecting line 92 and the third connecting line 93 can be straight lines or broken lines with the main body extending along the second direction Y.

[0469] In an exemplary embodiment, any one or more of the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in at least one cell row.

[0470] In an exemplary embodiment, the first power line 81 can be separately set in a unit row including the first circuit unit Q1, and the first power line 81 is respectively connected to the first pixel driving circuits of the multiple first circuit units Q1 in the unit row. The second power line 82 can be separately set in a unit row including the second circuit unit Q2, and the second power line 82 is respectively connected to the second pixel driving circuits of the multiple second circuit units Q2 in the unit row. The third power line 83 can be separately set in a unit row including the third circuit unit Q3, and the third power line 83 is respectively connected to the third pixel driving circuits of the multiple third circuit units Q3 in the unit row, forming unit rows with single power line structures.

[0471] In an exemplary embodiment, any one or more of the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in at least one cell column.

[0472] In an exemplary embodiment, the first connection line 91 can be arranged in one unit column and respectively connected to the plurality of first power lines 81 to form a grid connection structure. The second connection line 92 can be arranged in another unit column and respectively connected to the plurality of second power lines 82 to form a grid connection structure. The third connection line 93 can be arranged in another unit column and respectively connected to the plurality of third power lines 83 to form a grid connection structure.

[0473] In an exemplary embodiment, the potentials of the first power line 81 , the second power line 82 , and the third power line 83 may be different.

[0474] In an exemplary embodiment, the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in the same conductive layer, or in different conductive layers.

[0475] In an exemplary embodiment, the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in the same conductive layer, or in different conductive layers.

[0476] Fig.34A FIG. 1 is a schematic diagram of another arrangement of a circuit unit according to an exemplary embodiment of the present disclosure. Fig.34B FIG. 1 is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Fig.34C FIG. 2 is a schematic diagram showing the connection between another circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure. Fig.34A , Fig.34B and Fig.34C As shown, on a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3, and the plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, and a third light-emitting unit F3.

[0477] In an exemplary embodiment, in a unit row, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be periodically arranged in the first direction X, and the corresponding circuit units of the odd unit rows and the even unit rows are staggered. In one unit column, the first circuit unit Q1 and the third circuit unit Q3 are alternately arranged in the second direction Y, and in another unit column, the second circuit unit Q2 is sequentially arranged in the second direction Y.

[0478] In an exemplary embodiment, in a light-emitting row, the first light-emitting unit F1, the second light-emitting unit F2, and the third light-emitting unit F3 may be periodically arranged in the first direction X, and the corresponding light-emitting units of the odd-numbered light-emitting rows and the even-numbered light-emitting rows are staggered. In one light-emitting column, the first light-emitting unit F1 and the third light-emitting unit F3 are alternately arranged in the second direction Y, and in another light-emitting column, the second light-emitting unit F2 is sequentially arranged in the second direction Y.

[0479] In an exemplary embodiment, the first light-emitting device of the first light-emitting unit F1 is connected to the first pixel driving circuit of the first circuit unit Q1, and the position of the orthogonal projection of the first light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the first pixel driving circuit on the substrate. The second light-emitting device of the second light-emitting unit F2 is connected to the second pixel driving circuit of the second circuit unit Q2, and the position of the orthogonal projection of the second light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the second pixel driving circuit on the substrate. The third light-emitting device of the third light-emitting unit F3 is connected to the third pixel driving circuit of the third circuit unit Q3, and the position of the orthogonal projection of the third light-emitting device on the substrate substantially corresponds to the position of the orthogonal projection of the third pixel driving circuit on the substrate.

[0480] Fig.35 FIG. 1 is another wiring diagram of power lines and connection lines in a display substrate according to an exemplary embodiment of the present disclosure. Fig.35 As shown, in an exemplary embodiment of the present disclosure, the power line may include a first power line 81 , a second power line 82 , and a third power line 83 , and the connection line may include a first connection line 91 , a second connection line 92 , and a third connection line 93 .

[0481] In an exemplary embodiment, the shapes of the first power line 81, the second power line 82 and the third power line 83 can be straight lines or broken lines with the main body extending along the second direction Y, and the shapes of the first connection line 91, the second connection line 92 and the third connection line 93 can be straight lines or broken lines with the main body extending along the first direction X.

[0482] In an exemplary embodiment, any one or more of the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in at least one cell column.

[0483] In an exemplary embodiment, the first power line 81 and the third power line 83 can be disposed together in a cell column including the first circuit unit Q1 and the third circuit unit Q3 to form a cell column with a dual power line structure. The second power line 82 can be disposed alone in a cell column including the second circuit unit Q2 to form a cell column with a single power line structure.

[0484] In an exemplary embodiment, the first power line 81 is respectively connected to the first pixel driving circuits of multiple first circuit units Q1 in the unit column, the second power line 82 is respectively connected to the second pixel driving circuits of multiple second circuit units Q2 in the unit column, and the third power line 83 is respectively connected to the third pixel driving circuits of multiple third circuit units Q3 in the unit column.

[0485] In an exemplary embodiment, any one or more of the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in at least one cell row.

[0486] In an exemplary embodiment, the first connection line 91 can be arranged in one unit row and connected to the plurality of first power lines 81, respectively, so that the first connection line 91 extending along the first direction X of the main part and the first power line 81 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure. The second connection line 92 can be arranged in another unit row and connected to the plurality of second power lines 82, respectively, so that the second connection line 92 extending along the first direction X of the main part and the second power line 82 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure. The third connection line 93 can be arranged in another unit row and connected to the plurality of third power lines 83, respectively, so that the third connection line 93 extending along the first direction X of the main part and the third power line 83 extending along the second direction Y of the main part are connected to each other, forming a grid connection structure.

[0487] In an exemplary embodiment, the potentials of the first power line 81 , the second power line 82 , and the third power line 83 may be different.

[0488] In an exemplary embodiment, the first power line 81 , the second power line 82 , and the third power line 83 may be disposed in the same conductive layer, or in different conductive layers.

[0489] In an exemplary embodiment, the first connection line 91 , the second connection line 92 , and the third connection line 93 may be disposed in the same conductive layer, or in different conductive layers.

[0490] Fig.36 FIG. 1 is a schematic diagram of a power supply routing in a binding area of ​​an exemplary embodiment of the present disclosure, illustrating Figure 2 The power supply routing structure in area A. Fig.36As shown, the display substrate may include a display area 100 and a binding area 200 located on one side of the display area 100, the display area 100 includes at least a plurality of circuit units and a plurality of power lines, the plurality of circuit units may include at least a first circuit unit for setting a first pixel driving circuit, a second circuit unit for setting a second pixel driving circuit, and a third circuit unit for setting a third pixel driving circuit, the plurality of power lines may include at least a first power line 81, a second power line 82, and a third power line 83, the first power line 81 is connected to the first pixel driving circuit, the second power line 82 is connected to the second pixel driving circuit, and the third power line 83 is connected to the third pixel driving circuit. The binding area 200 may include at least a fan-out area connected to the display area 100, and the fan-out area may include at least multiple high-potential power leads, and the multiple high-potential power leads may include at least a first high-potential power lead 201, a second high-potential power lead 202, and a third high-potential power lead 203. After the multiple power lines of the display area 100 extend to the fan-out area of ​​the binding area 200, they are correspondingly connected to the multiple high-potential power leads, that is, the first power line 81 is connected to the first high-potential power lead 201, the second power line 82 is connected to the second high-potential power lead 202, and the third power line 83 is connected to the third high-potential power lead 203.

[0491] In an exemplary embodiment, the first power line 81, the second power line 82, and the third power line 83 may be in the shape of a line extending in the direction of the binding area 200, and may be arranged in sequence along the direction of the edge of the display area. The first high-potential power lead 201, the second high-potential power lead 202, and the third high-potential power lead 203 may be in the shape of a line extending in the direction of the edge of the display area, and may be arranged in sequence along the direction away from the display area 100. In an exemplary embodiment, the edge of the display area refers to the edge of the display area 100 on the side close to the binding area 200.

[0492] In an exemplary embodiment, a plurality of power lines and a plurality of high potential power leads may be provided in different conductive layers. After the first power line 81 extends from the display area 100 to the position of the first high potential power lead 201 in the binding area 200, it is connected to the first high potential power lead 201 through the first power via V51. After the second power line 82 extends from the display area 100 to the position of the second high potential power lead 202 in the binding area 200, it is connected to the second high potential power lead 202 through the first power via V51. After the third power line 83 extends from the display area 100 to the position of the third high potential power lead 203 in the binding area 200, it is connected to the third high potential power lead 203 through the first power via V51.

[0493] In an exemplary embodiment, in a direction perpendicular to the display substrate, the fan-out area in the binding area 200 may include multiple insulating layers and multiple conductive layers formed synchronously with the display area 100, and the first high potential power lead 201, the second high potential power lead 202 and the third high potential power lead 203 may be set in the same conductive layer, or may be set in different conductive layers.

[0494] In an exemplary embodiment, the first power line 81, the second power line 82 and the third power line 83 are arranged in the fifth conductive layer, and the first high potential power lead 201, the second high potential power lead 202 and the third high potential power lead 203 can be arranged together in one conductive layer among the first conductive layer to the fourth conductive layer.

[0495] In another exemplary embodiment, the first power line 81, the second power line 82 and the third power line 83 are arranged in the fifth conductive layer, and the first high potential power lead 201, the second high potential power lead 202 and the third high potential power lead 203 can be respectively arranged in three conductive layers from the first conductive layer to the fourth conductive layer.

[0496] In another exemplary embodiment, for the first power line 81, the second power line 82, and the third power line 83 being arranged in the fifth conductive layer, the first high potential power lead 201 and the third high potential power lead 203 may be arranged together in one of the first conductive layer to the fourth conductive layer, and the second high potential power lead 202 may be arranged alone in another of the first conductive layer to the fourth conductive layer. Alternatively, the first high potential power lead 201 and the second high potential power lead 202 may be arranged together in one of the first conductive layer to the fourth conductive layer, and the third high potential power lead 203 may be arranged alone in another of the first conductive layer to the fourth conductive layer. Alternatively, the first high potential power lead 201 may be arranged alone in one of the first conductive layer to the fourth conductive layer, and the second high potential power lead 202 and the third high potential power lead 203 may be arranged together in another of the first conductive layer to the fourth conductive layer.

[0497] Fig.37 The figure is a schematic diagram of a power supply line in a flexible circuit board of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the binding area 200 also includes a binding pin area located on the side of the fan-out area away from the display area 100. The binding pin area may include at least a plurality of binding pads, and the binding pads are configured to be bound and connected to an external flexible circuit board (FPC). The flexible circuit board can provide a plurality of power supply signals to a plurality of high-potential power supply leads of the binding area 200. Fig.37As shown, the flexible circuit board may include at least a control circuit 210, a plurality of circuit board pads and a plurality of power transmission lines, and the control circuit 210 is connected to the plurality of circuit board pads via the plurality of power transmission lines.

[0498] In an exemplary embodiment, the control circuit 210 may include at least a first control circuit 211, a second control circuit 212, and a third control circuit 213, the plurality of circuit board pads may include at least a first pad 221, a second pad 222, and a third pad 223, and the plurality of power transmission lines may include at least a first transmission line 231, a second transmission line 232, and a third transmission line 232. A first end of the first transmission line 231 is connected to the first control circuit 211, and a second end of the first transmission line 231 is connected to the first pad 221 after extending to the circuit board pad area. A first end of the second transmission line 232 is connected to the second control circuit 212, and a second end of the second transmission line 232 is connected to the second pad 222 after extending to the circuit board pad area. A first end of the third transmission line 232 is connected to the third control circuit 213, and a second end of the third transmission line 232 is connected to the third pad 223 after extending to the circuit board pad area.

[0499] In an exemplary embodiment, the control circuit may be a management integrated circuit (PMIC). The first control circuit 211 may provide a first power signal, the second control circuit 212 may provide a second power signal, and the third control circuit 213 may provide a third power signal.

[0500] In an exemplary embodiment, after the flexible circuit board is bound and connected to the binding pin area of ​​the display substrate, the first control circuit 211, the second control circuit 212 and the third control circuit 213 can respectively provide the first power signal, the second power signal and the third power signal to the corresponding power lines in the display area through the corresponding transmission lines and pads in the flexible circuit board, the corresponding binding pads in the binding area and the power lines.

[0501] In an exemplary embodiment, a plurality of first pads 221 , second pads 222 , and third pads 223 may be used in the flexible circuit board, and a plurality of first transmission lines 231 , second transmission lines 232 , and third transmission lines 232 may be used to improve reliability of signal transmission.

[0502] Fig.38 FIG. 1 is a schematic diagram of another power supply line in a flexible circuit board according to an exemplary embodiment of the present disclosure. Fig.38 As shown, the main structure of the flexible circuit board of this embodiment is Fig.37 The structures shown are basically the same, except that the control circuit 210 may use a management integrated circuit 214 .

[0503] In an exemplary embodiment, the management integrated circuit 214 may include at least three signal channels: a first signal channel 214A may provide a first power signal, a second signal channel 214B may provide a second power signal, and a third signal channel 214C may provide a third power signal.

[0504] In an exemplary embodiment, a first end of the first transmission line 231 is connected to the first signal channel 214A of the management integrated circuit 214, and a second end of the first transmission line 231 is connected to the first pad 221 after extending to the circuit board pad area. A first end of the second transmission line 232 is connected to the second signal channel 214B of the management integrated circuit 214, and a second end of the second transmission line 232 is connected to the second pad 222 after extending to the circuit board pad area. A first end of the third transmission line 232 is connected to the third signal channel 214C of the management integrated circuit 214, and a second end of the third transmission line 232 is connected to the third pad 223 after extending to the circuit board pad area.

[0505] In an exemplary embodiment, after the flexible circuit board is bound and connected to the binding pin area of ​​the display substrate, the first signal channel 214A, the second signal channel 214B and the third signal channel 214C of the management integrated circuit 214 can respectively provide the first power signal, the second power signal and the third power signal to the corresponding power lines in the display area through the corresponding transmission lines and pads in the flexible circuit board, the corresponding binding pads in the binding area and the power lines.

[0506] In an exemplary embodiment, a plurality of first pads 221 , second pads 222 , and third pads 223 may be used in the flexible circuit board, and a plurality of first transmission lines 231 , second transmission lines 232 , and third transmission lines 232 may be used to improve reliability of signal transmission.

[0507] Fig.39 FIG. 1 is a schematic diagram showing the connection between a low potential power supply line and a low potential connection line in a display substrate according to an exemplary embodiment of the present disclosure. Fig.39 As shown, the driving structure layer may also include multiple low-potential power lines and multiple low-potential connecting lines. The multiple low-potential power lines may include at least a fifth power line 85, a sixth power line 86 and a seventh power line 87. The multiple low-potential connecting lines may include at least a fifth connecting line 95, a sixth connecting line 96 and a seventh connecting line 97.

[0508] In an exemplary embodiment, the shapes of the fifth power line 85, the sixth power line 86 and the seventh power line 87 can be straight lines or broken lines with the main part extending along the second direction Y, and the shapes of the fifth connection line 95, the sixth connection line 96 and the seventh connection line 97 can be straight lines or broken lines with the main part extending along the first direction X.

[0509] In an exemplary embodiment, any one or more of the fifth power line 85 , the sixth power line 86 , and the seventh power line 87 may be provided in at least one cell column.

[0510] In an exemplary embodiment, the fifth power line 85 , the sixth power line 86 , and the seventh power line 87 may be individually disposed in one unit column to form a unit column of a single power line structure.

[0511] In an exemplary embodiment, the fifth power line 85, the sixth power line 86, and the seventh power line 87 have different potentials. The fifth power line 85 is respectively connected to the cathodes of the plurality of first light emitting devices in the unit column, the sixth power line 86 is respectively connected to the cathodes of the plurality of second light emitting devices and the fourth light emitting device in the unit column, and the seventh power line 87 is respectively connected to the cathodes of the plurality of third light emitting devices in the unit column.

[0512] In an exemplary embodiment, any one or more of the fifth connection line 95 , the sixth connection line 96 , and the seventh connection line 97 may be disposed in at least one cell row.

[0513] In an exemplary embodiment, the fifth connecting line 95 can be arranged in a unit row and connected to multiple fifth power lines 85 respectively, thereby realizing the interconnection between the fifth connecting line 95 extending along the first direction X of the main body and the fifth power line 85 extending along the second direction Y of the main body, forming a grid connection structure for transmitting the first low-potential power signal.

[0514] In an exemplary embodiment, the sixth connecting line 96 can be arranged in another unit row and connected to multiple sixth power lines 86 respectively, thereby realizing the interconnection between the sixth connecting line 96 extending along the first direction X of the main body and the sixth power line 86 extending along the second direction Y of the main body, forming a grid connection structure for transmitting the second low-potential power signal.

[0515] In an exemplary embodiment, the seventh connecting line 97 can be arranged in another unit row and connected to multiple seventh power lines 87 respectively, thereby realizing the interconnection between the seventh connecting line 97 extending along the first direction X of the main body and the seventh power line 87 extending along the second direction Y of the main body, forming a grid connection structure for transmitting the third low-potential power signal.

[0516] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer may include a plurality of conductive layers, and the fifth power line 85, the sixth power line 86, and the seventh power line 87 may be arranged in the same conductive layer, or may be arranged in different conductive layers. The fifth connection line 95, the sixth connection line 96, and the seventh connection line 97 may be arranged in the same conductive layer, or may be arranged in different conductive layers.

[0517] Fig.40 This is a schematic diagram of a power supply line in a border area of ​​an exemplary embodiment of the present disclosure, illustrating Figure 2 The power supply routing structure in area B. Fig.40 As shown, the display substrate may include a display area 100 and a frame area 300 located on at least one side of the display area 100, the display area 100 includes at least a plurality of light-emitting units and a plurality of cathode lines, the plurality of light-emitting units may include at least a first light-emitting unit for setting a first light-emitting device, a second light-emitting unit for setting a second light-emitting device, and a third light-emitting unit for setting a third light-emitting device, the plurality of cathode lines may include at least a first cathode line 310, a second cathode line 320, and a third cathode line 330, the first cathode line 310 may serve as a cathode of the first light-emitting device, the second cathode line 320 may serve as a cathode of the second light-emitting device, and the third cathode line 330 may serve as a cathode of the third light-emitting device. The frame area 300 may include at least a plurality of low-potential power leads, which may include at least a first low-potential power lead 301, a second low-potential power lead 302 and a third low-potential power lead 303. After the plurality of cathode lines of the display area 100 extend to the frame area 300, they are correspondingly connected to the plurality of low-potential power leads, that is, the first cathode line 310 is connected to the first low-potential power lead 301, the second cathode line 320 is connected to the second low-potential power lead 302, and the third cathode line 330 is connected to the third low-potential power lead 303.

[0518] In an exemplary embodiment, in the preparation of the cathode in the light-emitting structure layer, a patterned evaporation process can be used to separate the cathodes of the first light-emitting device, the second light-emitting device, and the third light-emitting device to form three strip cathode lines extending along the first direction, or to form three strip cathode lines extending along the second direction, that is, to form a first cathode line 310 serving as the cathode of the first light-emitting device, a second cathode line 320 serving as the cathode of the second light-emitting device, and a third cathode line 330 serving as the cathode of the third light-emitting device.

[0519] In an exemplary embodiment, the first low potential power lead 301, the second low potential power lead 302, and the third low potential power lead 303 may be in the shape of a line extending in the direction of the edge of the display area, and may be arranged in sequence in a direction away from the display area 100. In an exemplary embodiment, the edge of the display area refers to the edge of the display area 100 on the side close to the frame area 300.

[0520] In an exemplary embodiment, a plurality of cathode lines and a plurality of low potential power leads may be provided in different conductive layers. After the first cathode line 310 extends from the display area 100 to the position of the first low potential power lead 301 in the frame area 300, it is connected to the first low potential power lead 301 through the second power via V52. After the second cathode line 320 extends from the display area 100 to the position of the second low potential power lead 302 in the frame area 300, it is connected to the second low potential power lead 302 through the second power via V52. After the third cathode line 330 extends from the display area 100 to the position of the third low potential power lead 303 in the frame area 300, it is connected to the third low potential power lead 303 through the second power via V52.

[0521] In an exemplary embodiment, in a direction perpendicular to the display substrate, the border area 300 may include multiple insulating layers and multiple conductive layers formed synchronously with the display area 100, and the first low potential power lead 301, the second low potential power lead 302 and the third low potential power lead 303 may be arranged in the same conductive layer, or may be arranged in different conductive layers.

[0522] In an exemplary embodiment, the first low potential power lead 301, the second low potential power lead 302 and the third low potential power lead 303 can be arranged together in the anode conductive layer of the light-emitting structure layer. When the pixel definition layer is formed, the pixel definition layer in the frame area is provided with a second power via. When the cathode layer is formed, the first cathode line 310, the second cathode line 320 and the third cathode line 330 are respectively connected to the first low potential power lead 301, the second low potential power lead 302 and the third low potential power lead 303 through the second power via.

[0523] The inventor of the present application has found that the light extraction efficiency of red light emitting devices, blue light emitting devices and green light emitting devices is quite different. When the red light emitting devices, blue light emitting devices and green light emitting devices reach the same brightness under the same cross voltage △U between the high potential power line VDD and the low potential power line VSS, the saturation region margin voltages of the red light emitting devices, blue light emitting devices and green light emitting devices are different, and the saturation region margin voltage of the red / green light emitting devices is greater than the saturation region margin voltage of the blue light emitting device. The saturation region margin voltage refers to the voltage difference between the saturation region boundary of the pixel and the normal working region. For example, the saturation region margin voltage of the blue light emitting device is about 10%△U to 15%△U, the saturation region margin voltage of the red light emitting device is about 17%△U to 23%△U, and the saturation region margin voltage of the green light emitting device is about 25%△U to 30%△U. Therefore, the use of the same cross voltage △U by the red light emitting device, the blue light emitting device and the green light emitting device will increase power consumption.

[0524] The display substrate provided by the exemplary embodiment of the present disclosure adopts an independent design of the high potential power line VDD of the red light emitting device, the blue light emitting device and the green light emitting device, and uses the first power line to provide a first power signal for the first pixel driving circuit connected to the red light emitting device, the second power line to provide a second power signal for the second pixel driving circuit connected to the green light emitting device, and the third power line to provide a third power signal for the third pixel driving circuit connected to the blue light emitting device. Under the condition of ensuring the normal driving of the pixel driving circuit, the saturation region margin voltages of the red light emitting device, the blue light emitting device and the green light emitting device can be substantially the same when the same brightness is achieved, thereby effectively reducing power consumption. For example, by adjusting the voltages of the first power line, the second power line and the third power line, the saturation region margin voltages of the red light emitting device, the blue light emitting device and the green light emitting device are 10% △U to 15% △U, so that the saturation region margin voltage of the red light emitting device can be reduced by about 7%, and the saturation region margin voltage of the green light emitting device can be reduced by about 15%, and the corresponding power consumption will be reduced by about 5% to 7%.

[0525] The exemplary embodiment of the present disclosure sets a first connecting line, a second connecting line and a third connecting line, wherein the first connecting line is connected to the first power line, the second connecting line is connected to the second power line, and the third connecting line is connected to the third power line, thereby forming a grid connection structure on the display substrate for transmitting a first high-potential power signal, a second high-potential power signal and a third high-potential power signal, respectively. This can not only effectively reduce the resistance of the high-potential power line and reduce the voltage drop of the high-potential power signal, but also effectively improve the uniformity of the high-potential power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0526] The present invention adopts an independent design of the low-potential power line VSS of the red light-emitting device, the blue light-emitting device and the green light-emitting device. The first cathode line serves as the cathode of the first light-emitting device, the second cathode line serves as the cathode of the second light-emitting device, and the third cathode line serves as the cathode of the third light-emitting device. When the red light-emitting device, the blue light-emitting device and the green light-emitting device reach the same brightness, the saturation region margin voltages of the three light-emitting devices are basically the same, thereby effectively reducing power consumption.

[0527] The exemplary embodiment of the present disclosure forms a grid connection structure on the display substrate for transmitting a first low-potential power signal, a second low-potential power signal and a third low-potential power signal by setting a plurality of low-potential power lines and a plurality of low-potential connecting lines. This can not only effectively reduce the resistance of the low-potential power lines and reduce the voltage drop of the low-potential power signals, but also effectively improve the uniformity of the low-potential power signals in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0528] The present disclosure sets the power line in the second source-drain metal layer and the connecting line in the third source-drain metal layer, so that the power line and the connecting line only need one flat layer via to achieve connection, which minimizes the occupied space, is conducive to achieving high-resolution display, and can effectively improve the resolution (PPI) of the LTPO display substrate. The present disclosure sets the data signal line in the second source-drain metal layer, increases the distance between the data signal line and the corresponding signal line, reduces the parasitic capacitance between the data signal line and the corresponding signal line, and thus effectively reduces the capacitive load of the data signal line. On the one hand, the power line of the present disclosure can block the light emission of the light-emitting device and the reflected light of the film layer from irradiating the oxide transistor, which can prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor. On the other hand, it can effectively shield the influence of data voltage jump and other signals on the first node in the pixel driving circuit, avoid the influence of data voltage jump and other signals on the potential of the first node, and effectively avoid the deterioration of crosstalk. The preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.

[0529] The structure and preparation process shown above in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0530] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0531] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a display area and a binding area disposed on at least one side of the display area, and the preparation method may include:

[0532] A driving structure layer is formed on the substrate of the display area, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of circuit units at least include a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along a first direction, and a first power line, a second power line, and a third power line extending at least partially along a second direction, the first direction intersects with the second direction, and the first power line, the second power line, and the third power line have different potentials; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line, or the third power line, to form a grid connection structure for transmitting a power signal on the display substrate;

[0533] A light-emitting structure layer is formed on the driving structure layer, the light-emitting structure layer includes a plurality of light-emitting units, the plurality of light-emitting units include at least a first light-emitting unit provided with a first light-emitting device, a second light-emitting unit provided with a second light-emitting device, and a third light-emitting unit provided with a third light-emitting device, the first light-emitting device, the second light-emitting device, and the third light-emitting device emit light of different colors; the first light-emitting device is connected to the first pixel driving circuit, the second light-emitting device is connected to the second pixel driving circuit, and the third light-emitting device is connected to the third pixel driving circuit.

[0534] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a displa...

Claims

1. A display substrate, characterized in that: The invention comprises a display area and a binding area arranged on at least one side of the display area, wherein the display area comprises a driving structure layer arranged on a substrate and a light emitting structure layer arranged on a side of the driving structure layer away from the substrate, wherein the driving structure layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein the circuit unit comprises at least a pixel driving circuit, and the light emitting structure layer comprises a plurality of light emitting units, wherein the light emitting units comprise at least a light emitting device; wherein the plurality of circuit units comprises at least a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit, wherein the plurality of light emitting units comprises at least a first light emitting unit provided with a first light emitting device, a second light emitting unit provided with a second light emitting device, and a third light emitting unit provided with a third light emitting device, wherein the first light emitting device, the second light emitting device, and the third light emitting device The first light-emitting device emits light of different colors; the first light-emitting device is connected to the first pixel driving circuit, the second light-emitting device is connected to the second pixel driving circuit, and the third light-emitting device is connected to the third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along the first direction, and a first power line, a second power line and a third power line extending at least partially along the second direction, the first direction and the second direction intersect, and the first power line, the second power line and the third power line have different potentials; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line or the third power line, forming a grid connection structure for transmitting power signals on the display substrate.

2. The display substrate according to claim 1, characterized in that: The first power line and the third power line are arranged in the same unit column, or the first power line and the third power line are arranged in different unit columns.

3. The display substrate according to claim 1, characterized in that: In a direction perpendicular to the substrate, the driving structure layer includes a plurality of conductive layers, and any one or more of the first power line, the second power line and the third power line are arranged in at least one conductive layer.

4. The display substrate according to claim 1, characterized in that: At least one connecting line includes any one or more of a first connecting line, a second connecting line and a third connecting line; the first connecting line is connected to the first power line to form a grid connection structure for transmitting a first power signal on the display substrate; the second connecting line is connected to the second power line to form a grid connection structure for transmitting a second power signal on the display substrate; the third connecting line is connected to the third power line to form a grid connection structure for transmitting a third power signal on the display substrate.

5. The display substrate according to claim 4, characterized in that: Any one or more of the first connection line, the second connection line and the third connection line are arranged in at least one unit row.

6. The display substrate according to claim 4, characterized in that: In a direction perpendicular to the substrate, the driving structure layer includes a plurality of conductive layers, and any one or more of the first connecting line, the second connecting line and the third electrical connection are arranged in at least one conductive layer.

7. The display substrate according to claim 4, characterized in that: In a direction perpendicular to the substrate, the driving structure layer includes multiple conductive layers, and the first power line and the first connecting line are arranged in different conductive layers; or, the second power line and the second connecting line are arranged in different conductive layers; or, the third power line and the third connecting line are arranged in different conductive layers.

8. The display substrate according to claim 4, characterized in that: The multiple circuit units also include a fourth circuit unit provided with a fourth pixel driving circuit, the multiple light-emitting units also include a fourth light-emitting unit provided with a fourth light-emitting device, the fourth light-emitting unit and the second light-emitting device emit light of the same color, the driving structure layer also includes a fourth power line and a fourth connecting line, the fourth power line is connected to the fourth pixel driving circuit, the fourth connecting line is connected to the fourth power line, and a grid connection structure for transmitting a fourth power signal is formed on the display substrate.

9. The display substrate according to claim 8, characterized in that: The second connection line is also connected to the fourth power line, and the fourth connection line is also connected to the second power line.

10. The display substrate according to claim 1, characterized in that: The driving structure layer also includes a first data signal line, a second data signal line and a third data signal line, the first data signal line is connected to the first pixel driving circuit, the second data signal line is connected to the second pixel driving circuit, and the third data signal line is connected to the third pixel driving circuit; any one or more of the first data signal line, the second data signal line and the third data signal line are arranged in at least one unit column.

11. The display substrate according to claim 1, characterized in that: The driving structure layer also includes a fifth power line, a sixth power line and a seventh power line, the fifth power line is connected to the cathode of the first light-emitting device, the sixth power line is connected to the cathode of the second light-emitting device, and the seventh power line is connected to the cathode of the third light-emitting device.

12. The display substrate according to any one of claims 1 to 11, characterized in that: In a direction perpendicular to the substrate, the display substrate includes multiple conductive layers, an anode transfer line is provided in any one of the conductive layers or multiple conductive layers, the first power line and the third power line are arranged in different unit columns, the first pixel driving circuit is connected to the first light-emitting device through the anode transfer line, and / or the third pixel driving circuit is connected to the third light-emitting device through the anode transfer line.

13. The display substrate according to claim 12, characterized in that: The first light-emitting device at least includes a first anode, the first anode at least includes a main body and a connecting portion, an orthographic projection of at least part of the main body of the first anode on the substrate plane does not overlap with an orthographic projection of the first pixel driving circuit on the substrate plane, a first end of the anode adapter is connected to the main body of the first anode, a second end of the anode adapter is connected to the connecting portion of the first anode, and the connecting portion of the first anode is connected to the first pixel driving circuit; And / or, the third light-emitting device includes at least a third anode, the third anode includes at least a main body and a connecting portion, the orthographic projection of at least part of the main body of the third anode on the substrate plane does not overlap with the orthographic projection of the third pixel driving circuit on the substrate plane, the first end of the anode adapter wire is connected to the main body of the third anode, the second end of the anode adapter wire is connected to the connecting portion of the third anode, and the connecting portion of the third anode is connected to the third pixel driving circuit.

14. The display substrate according to claim 13, characterized in that: An orthographic projection of at least part of the main body of the first anode on the substrate plane at least partially overlaps with an orthographic projection of the third pixel driving circuit on the substrate plane; And / or, an orthographic projection of at least part of a main portion of the third anode on the substrate plane at least partially overlaps with an orthographic projection of the first pixel driving circuit on the substrate plane.

15. The display substrate according to claim 13, characterized in that: The orthographic projection of the anode switching line on the substrate plane at least partially overlaps with the orthographic projection of the second pixel driving circuit on the substrate plane; And / or, an orthographic projection of the anode switching line on the substrate plane at least partially overlaps with an orthographic projection of the fourth pixel driving circuit on the substrate plane.

16. The display substrate according to any one of claims 1 to 11, characterized in that: The first power line and the third power line are arranged in the same unit column; the first light-emitting device comprises at least a first anode, the first anode comprises at least a main body and a connecting part, a first end of the connecting part of the first anode is connected to the main body of the first anode, a second end of the connecting part of the first anode is connected to the first pixel driving circuit, and an orthographic projection of at least part of the main body of the first anode on the substrate plane at least partially overlaps with an orthographic projection of the first pixel driving circuit on the substrate plane; And / or, the third light-emitting device includes at least a third anode, and the third anode includes at least a main body and a connecting part, a first end of the connecting part of the third anode is connected to the main body of the third anode, a second end of the connecting part of the third anode is connected to the third pixel driving circuit, and an orthographic projection of at least part of the main body of the third anode on the substrate plane at least partially overlaps with an orthographic projection of the third pixel driving circuit on the substrate plane.

17. The display substrate according to any one of claims 1 to 11, characterized in that: The binding area includes at least a first high potential power lead, a second high potential power lead and a third high potential power lead, the first power lead is connected to the first high potential power lead, the second power lead is connected to the second high potential power lead, and the third power lead is connected to the third high potential power lead.

18. The display substrate according to claim 17, characterized in that: The display substrate also includes a flexible circuit board bound and connected to the binding area, the flexible circuit board at least includes a control circuit, a plurality of circuit board pads and a plurality of power transmission lines, the control circuit at least includes a first control circuit providing a first power signal, a second control circuit providing a second power signal and a third control circuit providing a third power signal, the plurality of circuit board pads include at least a first pad, a second pad and a third pad, and the plurality of power transmission lines include at least a first transmission line, a second transmission line and a third transmission line; the first control circuit is connected to the first high-potential power lead of the binding area through the first transmission line and the first pad, the second control circuit is connected to the second high-potential power lead of the binding area through the second transmission line and the second pad, and the third control circuit is connected to the third high-potential power lead of the binding area through the third transmission line and the third pad.

19. The display substrate according to claim 17, characterized in that: The display substrate also includes a flexible circuit board bound and connected to the binding area, the flexible circuit board at least includes a control circuit, a plurality of circuit board pads and a plurality of power transmission lines, the control circuit at least includes a management integrated circuit, the management integrated circuit at least includes a first signal channel providing a first power signal, a second signal channel providing a second power signal and a third signal channel providing a third power signal, the plurality of circuit board pads at least include a first pad, a second pad and a third pad, and the plurality of power transmission lines at least include a first transmission line, a second transmission line and a third transmission line; the first signal channel is connected to the first high potential power lead of the binding area through the first transmission line and the first pad, the second signal channel is connected to the second high potential power lead of the binding area through the second transmission line and the second pad, and the third signal channel is connected to the third high potential power lead of the binding area through the third transmission line and the third pad.

20. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 19.

21. A method for preparing a display substrate, characterized in that: The display substrate includes a display area and a binding area arranged on at least one side of the display area, and the preparation method includes: A driving structure layer is formed on the substrate of the display area, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of circuit units at least include a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit; the driving structure layer also includes at least one connecting line extending at least partially along a first direction, and a first power line, a second power line, and a third power line extending at least partially along a second direction, the first direction intersects with the second direction, and the first power line, the second power line, and the third power line have different potentials; the first power line is connected to the first pixel driving circuit, the second power line is connected to the second pixel driving circuit, and the third power line is connected to the third pixel driving circuit; at least one connecting line is connected to the first power line, the second power line, or the third power line, to form a grid connection structure for transmitting a power signal on the display substrate; A light-emitting structure layer is formed on the driving structure layer, the light-emitting structure layer includes a plurality of light-emitting units, the plurality of light-emitting units include at least a first light-emitting unit provided with a first light-emitting device, a second light-emitting unit provided with a second light-emitting device, and a third light-emitting unit provided with a third light-emitting device, the first light-emitting device, the second light-emitting device, and the third light-emitting device emit light of different colors; the first light-emitting device is connected to the first pixel driving circuit, the second light-emitting device is connected to the second pixel driving circuit, and the third light-emitting device is connected to the third pixel driving circuit.

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