Processors store operation data transfers improved performance and reliability

Abstract

A processor includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. When the cache memory determines that an available entry exists in the store queue within the cache memory, the cache memory requests a packet of information from the LSU. The LSU acknowledges the request and transfers the packet of information to the cache memory. Before receiving an additional request from the cache memory, the LSU expects an additional available entry in the cache memory, sends an additional acknowledgement to the cache memory, and transfers an additional packet of information. If an additional available entry exists in the cache store queue, the cache memory stores the additional packet of information. If an additional available entry does not exist in the cache store queue, the cache memory rejects the additional packet of information. When the cache memory subsequently requests an additional packet of information, the LSU must then retry the transfer of the additional packet of information. The cache memory can set or reset a time delay for requesting a subsequent packet of information based on several factors within the cache memory and the processor, including the number of available entries within the cache store queue. A corresponding method and computer program product are also disclosed.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to computer processor systems, and more particularly to systems and methods for improving the performance and reliability of memory operation data transfers between a processor and a processor cache memory. BACKGROUND

[0002] In computer processing systems, processors serve as central processing units and perform many important functions such as arithmetic and logic operations, program instruction execution, data transfers, and other processing system control and logic functions. Processors include caches to assist in transferring data between the processor core and the processing system memory. Caches typically include multiple levels or tiers, with a smaller, faster level one (LI) cache and a larger, relatively slower level two (L2) cache. Processors include a relatively small memory queue to temporarily store data, and each tier of the cache includes a queue to hold data before storing the data to the larger cache memory.

[0003] A communication protocol exists between the processor cache (L2) memory queue and the processor core memory queue to control the transfer of data between the processor core and the cache. The processor cache indicates that space is available in its memory by sending a request signal to the processor core for each available entry in the cache queue. The processor core responds to the cache with an acknowledgement signal and transfers a data packet from the processor queue to the cache. The cache accepts the data packet with the acknowledgement and stores the data packet in the cache memory queue. The LSU waits until the cache sends an additional request before sending an additional data packet to the cache.

[0004] In view of the foregoing, there is a need for systems and methods that improve the performance and reliability of data transfers between a processor core and a processor cache. Processor systems attempt to improve processor performance by anticipating empty entries in the processor cache memory queue. Additionally, multiple threads in the processor core share the processor cache and compete for entries in the cache memory queue, and cause the communication protocol between the processor core memory queue and the processor cache memory queue to become out of sync. The present invention prevents the processor cache from rejecting data transfers and minimizes the out of sync communication protocol between the processor core and the processor cache memory queue. SUMMARY

[0005] The present invention has been developed in response to the present state of the art, and in particular, in response to the problems and needs in the art that have not yet been fully solved by currently available systems and methods. The features and advantages of the present invention will become more fully apparent from the following description and appended claims, or can be learned by the practice of the present invention as described hereinafter.

[0006] According to embodiments of the application described herein, a processor is provided for improving performance of storage operation data transfers in a computer processing system. In embodiments, the computer processing system includes a processor, a memory, and a plurality of components for performing computer processing system functions. In embodiments, the processor includes a load and store unit (LSU) and a cache memory for storing data information to be transferred to the memory and / or other components in the computer processing system. In embodiments, the LSU includes a store queue having a plurality of entries for storing a plurality of packets. In embodiments, the cache memory includes a store queue having a plurality of entries for storing a plurality of packets. In embodiments, the cache memory determines that the cache store queue contains available entries. The cache memory transmits a request to the LSU to transfer a packet to the cache memory. In embodiments, the LSU transmits an acknowledgement in response to the cache request and transfers the packet from an entry in the LSU store queue to the cache memory. In embodiments, the cache memory receives the packet from the LSU and stores the packet in an available entry within the cache store queue.

[0007] In embodiments, the LSU anticipates that additional available entries exist in the cache memory, transmits an additional acknowledgement signal to the cache memory, and transfers an additional packet from an additional entry in the LSU store queue to the cache memory. The cache memory determines that additional available entries exist in the cache store queue, receives the packet from the LSU, and stores the packet in the additional available entry within the cache store queue. In embodiments, the cache memory delays a subsequent request for a subsequent packet, where the subsequent request also serves as an acknowledgement to the LSU that the cache successfully stored the additional packet within the cache store queue. In embodiments, the cache memory determines that additional available entries do not exist in the cache store queue and rejects the additional packet transferred from the LSU. The LSU must wait for the cache memory to transmit a new request before retrying the transfer of the additional information from the LSU store queue to the cache memory.

[0008] In embodiments, the cache storage calculates a time delay for sending a subsequent request for a subsequent packet to the LSU (subsequent request delay) based on a number of available entries within the cache storage queue. In embodiments, the cache storage calculates the subsequent request delay based on a recent average time for transferring a packet from the LSU storage queue to the cache storage queue. In embodiments, the cache storage sets and resets the subsequent request delay based on a threshold value, wherein the threshold value is based on the number of available entries in the cache storage queue. When the number of available entries in the cache storage queue is less than the threshold value, the cache storage sets the subsequent request delay to a determined time interval. When the number of available entries in the cache storage queue is greater than or equal to the threshold value, the cache storage resets the subsequent request delay to no time delay.

[0009] According to another embodiment of the application described herein, there is provided a method for improving performance of storage operation data transfers in a computer processing system, wherein the computer processing system includes a processor and a cache storage, the processor includes a load and store unit (LSU) having a storage queue, and the cache storage includes a storage queue. In embodiments, the method includes storing a packet in an entry in the LSU storage queue. In embodiments, the method includes the cache storage determining that there is an available entry within the cache storage queue and requesting the packet from the LSU. In embodiments, the method includes the LSU acknowledging the request from the cache storage and transferring the packet from the entry in the LSU storage queue to the cache storage. In embodiments, the method includes the cache storage receiving the packet from the LSU and storing the packet in the available entry within the cache storage queue.

[0010] In embodiments, the method includes the LSU expecting that the cache memory has an additional available entry in the cache storage queue. In embodiments, the method includes the LSU transmitting an additional acknowledgement to the cache memory prior to the cache memory requesting an additional information packet, and transmitting the additional information packet to the cache memory. In embodiments, the method includes the cache memory determining that there is an additional available entry within the cache storage queue, receiving the additional information packet from the LSU, and storing the additional information packet in the additional available entry within the cache storage queue. In embodiments, the method includes the cache memory delaying a subsequent request for a subsequent information packet from the LSU, where the subsequent request serves as an acknowledgement that the additional information packet is stored within the cache memory. In embodiments, the method alternatively includes the cache memory determining that there is not an additional available entry in the cache storage queue, and rejecting the transmission of the additional information packet from the LSU, thereby requiring the LSU to retry the transmission of the additional information packet when it receives another request from the cache memory.

[0011] In embodiments, the method includes the cache memory calculating a time delay for sending a subsequent request for a subsequent information packet to the LSU based on a number of available entries within the cache storage queue (subsequent request delay). In embodiments, the method includes the cache memory calculating the subsequent request delay based on a recent average time for transmitting information packets from the LSU storage queue to the cache storage queue. In embodiments, the method includes the cache memory setting and resetting the subsequent request delay based on a threshold value, where the threshold value is based on the number of available entries in the cache storage queue. The method includes the cache memory setting the subsequent request delay to a determined time interval when the number of available entries in the cache storage queue is less than the threshold value. The method includes the cache memory resetting the subsequent request delay to no time delay when the number of available entries in the cache storage queue is greater than or equal to the threshold value.

[0012] According to another embodiment of the application described herein, there is provided a computer program product for improving performance of storage operation data transfers in a computer processing system, wherein the computer processing system includes a processor and a cache memory, the processor includes a load and store unit (LSU) having a store queue, and the cache includes a store queue. In embodiments, the computer program product includes a non-transitory computer-readable storage medium having computer usable program code embodied therein. In embodiments, the computer usable program code is configured such that, when executed by a processor, performs operations. In embodiments, the computer program product operations include storing a packet of information in an entry in the LSU store queue. In embodiments, the computer program product operations include the cache memory determining that there is an available entry within the cache store queue and requesting a packet of information from the LSU. In embodiments, the computer program product operations include the LSU acknowledging the request from the cache memory and transferring a packet of information from an entry in the LSU store queue to the cache memory. In embodiments, the computer program product operations include the cache memory receiving the packet of information from the LSU and storing the packet of information in an available entry within the cache store queue.

[0013] In embodiments, the computer program product operations include the LSU anticipating that the cache memory has an additional available entry in the cache store queue. In embodiments, the computer program product operations include the LSU transmitting an additional acknowledgement to the cache memory prior to the cache memory requesting an additional packet of information and transferring the additional packet of information to the cache memory. In embodiments, the computer program product operations include the cache memory determining that there is an additional available entry within the cache store queue, receiving the additional packet of information from the LSU, and storing the additional packet of information in the additional available entry within the cache store queue. In embodiments, the computer program product operations include the cache memory delaying a subsequent request for a subsequent packet of information to the LSU, wherein the subsequent request serves as an acknowledgement of the additional packet of information being stored within the cache memory. In embodiments, the computer program product operations can alternatively include the cache memory determining that there is not an additional available entry in the cache store queue and denying the transfer of an additional packet of information from the LSU, thereby requiring the LSU to retry the transfer of the additional packet of information when it receives another request from the cache memory.

[0014] In embodiments, the computer program product operations include the cache memory computing a time delay for sending a subsequent request for a subsequent information packet to the LSU (subsequent request delay) based on a number of available entries in the cache storage queue. In embodiments, the computer program product operations include the cache memory computing the subsequent request delay based on a recent average time for transmitting information packets from the LSU storage queue to the cache storage queue. In embodiments, the computer program product operations include the cache memory setting and resetting the subsequent request delay based on a threshold value, wherein the threshold value is based on the number of available entries in the cache storage queue. The computer program product operations include the cache memory setting the subsequent request delay to a determined time interval when the number of available entries in the cache storage queue is less than the threshold value. The computer program product operations include the cache memory resetting the subsequent request delay to no time delay when the number of available entries in the cache storage queue is greater than or equal to the threshold value. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order that the advantages of the application will be readily understood, a more particular description of the application briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the application and are not therefore to be considered to be limiting of its scope, the application will be described and explained with additional specificity and detail by the use of the accompanying drawings, in which:

[0016] Figure 1 is a high level block diagram representing an example of a computer processing system in which systems and methods according to embodiments of the application can be implemented;

[0017] Figure 2 is a high level block diagram representing a processor or central processing unit within a computer processing system according to embodiments of the application;

[0018] Figure 3 is a high level block diagram representing a processor and cache memory components within a processor according to embodiments of the application; and

[0019] Figure 4 is a high level block diagram representing an improved system and computer implemented method for transmitting information within a computer processing system using cache memory within a processor core according to embodiments of the application. DETAILED DESCRIPTION

[0020] It will be readily understood that the components of the present application, as generally described and illustrated in the Figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the application, as represented in the Figures, is not intended to limit the scope of the application, as claimed, but is merely representative of certain examples of presently preferred embodiments of the application. The illustrated embodiments of the application will be best understood by reference to the drawings, wherein like parts are designated with like numerals throughout.

[0021] Exemplary embodiments are described herein that improve the performance and reliability of data transfers for storage operations within a computer processing system. A computer processing system includes one or more processors, memory, and a plurality of components that perform computer processing functions and controls. The processor includes a load and store unit (LSU) and a cache memory. The LSU and cache memory include storage queues having entries for storing packets of information. The LSU transfers packets of information to the cache memory where they are stored until the information needs to be transferred from the cache memory to main memory and / or other components within the computer processing system. The cache memory requests packets of information from the LSU when the cache determines that an available entry exists in the cache storage queue. The LSU acknowledges the request and transfers the packets of information from the LSU storage queue to the cache memory. The LSU expedites the data transfer by sending additional acknowledgements and additional packets of information to the cache memory in anticipation that the cache memory has an available entry in the cache storage queue. If the cache memory has an available entry in the cache storage queue, the cache memory accepts the additional packets of information. Alternatively, if the cache memory does not have an additional entry in the cache storage queue, the cache memory rejects the transfer of the additional packets of information. The LSU must then retry the transfer of the additional packets of information. The cache memory delays sending a subsequent request for a subsequent packet of information to the LSU to avoid requiring the cache to reject additional packets of information transferred from the LSU and requiring the LSU to retry the transfer of the additional packets of information.

[0022] Reference Figure 1This document generally illustrates a computer processing system 100 according to an embodiment. The computer processing system 100 may be an electronic computer framework comprising and / or employing any number of computing devices and networks utilizing various communication technologies and combinations thereof, as described herein. In some embodiments, the computer processing system 100 may be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of others. In some embodiments, the computer processing system 100 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. Additionally, the computer processing system 100 may be a cloud computing node. In some embodiments, the computer processing system 100 may be described in the general context of computer system executable instructions, such as program modules executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform a specific task or implement a specific abstract data type. In some embodiments, the computer processing system 100 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside in both local and remote computer system storage media, including memory storage devices.

[0023] like Figure 1 As shown, the computer processing system 100 has one or more central processing units (CPUs) 101 (commonly referred to or generally as processor 101). In some embodiments, processor 101 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 101 (also referred to as processing circuitry) may also include one or more accelerators (e.g., a graphics processing unit or GPU). In one embodiment, the processor includes cache 109 and controller 108 to assist in performing processor-related functions such as arithmetic and logical operations, program instruction execution, data transfer, and other processing system control and logic functions. In some embodiments, processor 101 is coupled to system memory 103 and various other components via system bus 102. System memory 103 may include read-only memory (ROM) 104 and random access memory (RAM) 105. ROM 104 is coupled to system bus 102 and may include a basic input / output system (BIOS) that controls certain basic functions of computer system 100. RAM is a read-write memory coupled to system bus 102 for use by processor 101. In some embodiments, system memory 103 provides temporary memory space for the operation of the instructions during operation. System memory 103 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0024] In certain embodiments, computer processing system 100 includes input / output (I / O) adapter 106 and communications adapter 107 coupled to the system bus 102. I / O adapter 106 can be a small computer system interface (SCSI) adapter that communicates with a hard drive 108 and / or any other similar component. I / O adapter 106 and a flash (DRAM) 118 and / or a hard drive 118 are collectively referred to herein as bulk storage 110. In certain embodiments, software 111 for execution on computer processing system 100 can be stored in bulk storage 110. Bulk storage 110 is an example of a tangible storage medium readable by processor 101, wherein the software 111 is stored as instructions for execution by processor 101 to cause computer system 100 to operate as described herein, such as described below with respect to the various figures. Examples of computer program products and execution of such instructions are discussed in greater detail herein.

[0025] In certain embodiments, communications adapter 107 interconnects system bus 102 with network 112, which can be an external network, enabling computer processing system 100 to communicate with other systems. In one embodiment, portions of system memory 103 and bulk storage 110 collectively store an operating system, which can be any appropriate operating system, such as the z / OS or AIX operating systems from IBM Corporation, to coordinate the functions of various components shown in FIG. 1. Figure 1

[0026] In certain embodiments, additional input / output devices are connected to system bus 102 via display adapter 115 and interface adapter 116. In embodiments, adapters 106, 107, 115, and 116 can be connected to one or more I / O buses, which are connected to system bus 102 via bus bridges (not shown). In embodiments, display 119 (e.g., a display screen or monitor) is connected to system bus 102 by display adapter 115, which can include a graphics controller to improve the performance of graphics intensive applications and a video controller. In embodiments, keyboard 121, mouse 122, speaker 123, and / or other devices can be interconnected to system bus 102 via interface adapter 116, which can include, for example, a Super I / O chip integrating multiple device adapters into a single integrated circuit. In certain embodiments, suitable I / O buses typically include a Figure 1 ​The computer processing system 100 configured therein includes processing capabilities in the form of a processor 101, storage capabilities including system memory 103 and mass storage 110, input devices such as a keyboard 121 and a mouse 122, and output capabilities including a speaker 123 and a display 119.

[0027] In some embodiments, the communication adapter 107 may use any suitable interface or protocol to transmit data, such as an Internet Small Computer System Interface (IPS). The network 112 may be a cellular network, radio network, wide area network (WAN), local area network (LAN), or the Internet. External computing devices may be connected to the computing system 100 via the network 112. In some embodiments, the external computing device may be an external network server or a cloud computing node.

[0028] It should be understood that Figure 1 The block diagram is not intended to indicate that the computer processing system 100 will include Figure 1 All components shown. Conversely, the computer processing system 100 may include... Figure 1 Any suitable fewer or additional components not shown herein (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, the embodiments described herein with respect to the computer processing system 100 can be implemented with any suitable logic, wherein the logic mentioned herein may include any suitable hardware (e.g., processor, embedded controller, or application-specific integrated circuit, etc.), software (e.g., applications, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0029] Figure 2A block diagram representing a processor or central processing unit 101 according to an embodiment of the application. In an embodiment, the processor includes one or more processor cores 200, 201. In an embodiment, the processor cores 200, 201 include a load-store unit (LSU) 210, 211 and a multi-level cache memory 109. In an embodiment, the cache memory 109 of each processor core includes a level one (LI) cache 220, 221 and a level two (L2) cache 230, 231. The level one (LI) cache 220, 221 typically includes memory with the fastest access time and is small in size. The level two (L2) cache 230, 231 typically includes memory with a faster access time than the LI cache 220, 221 and is much larger in size. As previously mentioned, the processor cores 200, 201 perform processor related functions such as arithmetic and logic operations, program instruction execution, data transfer, and other processing system control and logic functions. To perform these functions, the processor cores 200, 201 need to access information, instructions, and / or data from the processor memory 103 through the system bus 102. In an embodiment, the processor cores 200, 201 utilize the load-store unit 210, 211 and the multi-level cache memory 220, 221, 230, 231 to more efficiently and quickly transfer information. Information, including instructions and data, can be prefetched from the system memory 103 and stored in the LI cache 220 or the L2 cache 230 based on an algorithm within the processor core 200 that predicts which information is likely to be accessed from the system memory 103.

[0030] It should be appreciated that Figure 2 The block diagram of FIG. 1 is not intended to show all components included in the processor core 200, 201. Figure 2 includes two processor cores 200, 201, however this is merely intended to show an exemplary embodiment. The central processing unit 101 can include a single processor core 200 or multiple (more than two) processor cores 200, 201. As previously mentioned, the processor cores 200, 201 perform many processing related functions and can include Figure 2additional components and control logic not shown to assist in performing these functions. Moreover, specific embodiments of the processor cores 200, 201 include more than two levels of cache memory 108. In embodiments, the processor cores 200, 201 include a level three (L3) cache and a level four (L4) cache to improve performance and efficiency of accessing information from the system memory 103. Moreover, embodiments described herein with respect to the processor cores 200, 201 can be implemented with any suitable logic, where logic as referred to herein can include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any suitable combination of hardware, software, and firmware in various embodiments.

[0031] Figure 3 A block diagram representing a processor core according to embodiments of the present application. In embodiments, the processor core 200 includes a load-store unit (LSU) 210, an LI cache memory 220, and an L2 cache memory 230. In embodiments, the LSU 210 includes a store queue 250 and a load queue 255 that send and receive information to and from the LI 220 and L2 230 cache memories. This information includes data to be transferred, instructions to be executed, addresses to be accessed, or other information necessary for the processor 200 to perform its operations. In embodiments, the L2 cache 230 includes a corresponding store queue 260 and a load queue 265. In embodiments, the LSU 210 is coupled to the LI cache 220 and the L2 cache 230 to transfer and receive information. Likewise, the L2 cache 260 is coupled to the LSU 210 and the LI cache 220 to transfer and receive information. In embodiments, the L2 cache 230 is coupled to the system bus 102 to transfer and receive information from components within the processor system 100. In embodiments, the LSU 210, the LI cache 220, and the L2 cache 230 include logic to communicate and control the transfer of information between components.

[0032] It should be appreciated that Figure 3 The block diagram of FIG. 2 is not intended to show all components included in the processor core 200, but rather is intended to show only an exemplary embodiment of components in the processor core 200 that facilitate the transfer of information within the processor core 200 and within the processor system 100. Figure 3 includes a single processor core 200 having a single LSU 210, a single LI cache 220, and a single L2 cache 230. In alternative embodiments, the LI cache 220 and the L2 cache 230 can be partitioned into multiple cache segments. In this case, a separate LSU 210 can be implemented to communicate with and control the transfer of information to and from the partitioned LI cache 220 and L2 cache 230 segments. Additionally, Figure 3The embodiments described in the middle include control signals for communicating and transferring data between the LSU 210, the LI cache 220, and the L2 cache 230. In various embodiments, such control signals can be implemented with any suitable logic, where logic as referred to herein can include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0033] Figure 4 A block diagram representing an improved system and computer implemented method for transferring data information within a computer processing system 100 using a LSU 210 and a L2 cache memory 230 within a processor core 200. In an embodiment, the processor core includes a LSU 210 coupled to a L2 cache 230. In an embodiment, the LSU includes a storage queue 250 storing data information and a control module 270 transferring control and communication signals. In an embodiment, the L2 cache 230 includes a storage queue storing data information and a control module 280 transferring control and communication signals. In an embodiment, the LSU control module 270 is coupled to the L2 cache control module 280 through a control bus 275 and a data bus 285. In an embodiment, the LSU control module 270 and the L2 cache control module include logic, where the logic can include hardware, software, firmware, or a combination of hardware, software, and firmware.

[0034] In an embodiment, the L2 cache control module 280 transfers a POP signal along the control bus 275 to the LSU control module 270 when an entry in the L2 storage queue 260 is available. In an embodiment, the LSU control module 270 transfers a PUSH signal along the control bus 275 when data information is ready to be transferred from the LSU storage queue 250 to the L2 cache storage queue 260. The LSU 210 then initiates a transfer of data information from the LSU storage queue 250 to the L2 cache storage queue 260 through the data bus 285 until the data transfer is complete. In an embodiment, the L2 cache control module 280 transfers successive POP signals along the control bus 275 to indicate that additional entries are available within the L2 cache storage queue 260. The process is then repeated when the LSU control module 275 transfers a PUSH signal along the control bus 275 to indicate that additional data information is ready to be transferred from the LSU storage queue 250 to the L2 cache storage queue 260 and initiates a transfer of data information from the LSU storage queue 250 to the L2 cache storage queue 260 through the data bus 285.

[0035] In further embodiments, the LSU 210 accelerates the transfer of data information to the L2 cache 230 by anticipating that the L2 cache store queue has additional available entries. In embodiments, the LSU control module 270 responds to a POP signal from the L2 cache control module 280 by transmitting a PUSH signal along the control bus 275 and initiating the transfer of data information from the LSU store queue 250 to the L2 cache store queue 260. In embodiments, when a previous transfer of data information is complete and before receiving an additional POP signal from the L2 cache control module 280, the LSU control module 270 transmits an additional PUSH signal to the L2 cache control module 280 along the control bus 275. As previously described, the LSU control module 270 initiates a subsequent transfer of data information from the LSU store queue to the L2 cache store queue 260 along the data bus 285. Thus, the LSU 210 anticipates that the L2 cache 230 contains additional available entries in the L2 cache store queue 260 and increases the speed and performance of the transfer between the LSU store queue 250 and the L2 cache store queue 260. In embodiments, the L2 cache control module 280 transmits a POP signal to the LSU control module 270 along the control bus 275 indicating that the L2 cache control store 260 contains available entries and receives a transfer of data information from the LSU store queue 250. In embodiments, the L2 cache control module 280 transmits a BOUNCE signal to the LSU control module 270 along the control bus 275 indicating that the L2 cache control store 260 does not contain available entries and rejects a transfer of data information from the LSU store queue 250. In this case, the LSU 210 must wait for an available entry in the L2 cache 230 to retry the transfer of data information and, thus, the LSU control module 270 must wait to receive a subsequent POP signal from the L2 cache control module 280 along the control bus 275. Thus, this LSU incorrectly anticipates that an available entry exists in the L2 cache store queue 260 and decreases the store queue transfer performance between the LSU 210 and the L2 cache 230 in the processor core 200. Furthermore, if the LSU 210 releases data information transferred in a subsequent PUSH signal from the LSU store queue 250 before the LSU control module 270 receives a BOUNCE signal from the L2 cache control module 280, the risk of losing data information increases.

[0036] In further embodiments, the L2 cache 230 can delay indicating to the LSU 210 that an entry is available in the L2 cache store queue 260. As previously described, the L2 cache control module 280 transmits a POP signal when an entry in the L2 cache store queue 260 becomes available. In embodiments, the L2 delays transmitting the POP signal when an entry in the L2 cache store queue 260 becomes available. In embodiments, the delay can be a fixed duration interval time delay. In embodiments, the delay can be a time delay that can vary in length based on certain factors and / or metrics measured within the processor core 200. In embodiments, the delay can be calculated based on the time interval to transfer data information from the LSU store queue 250 to the L2 cache store queue 260. In embodiments, the delay can be a time interval adjusted based on the number of available entries in the L2 cache store queue 260. In embodiments, the delay can be calculated using an algorithm based on a combination of factors and metrics within the processor core, including but not limited to the number of available entries in the L2 store queue 260, free space in the L2 cache 230 or the LI cache 220, the average time to transfer data information between the LSU 230 and the L2 cache 250, and the frequency of store operations within the processor core. By delaying the transmission of the POP signal from the L2 cache control module 280 to the LSU control module 270, the L2 cache control module 280 ensures that the L2 cache store queue 260 can successfully complete additional data information transfers in the event that the LSU 210 attempts to accelerate data information transfers to the L2 cache 230 based on the expectation that the L2 store queue 260 contains additional available entries.

[0037] In further embodiments, the delay can be a fixed time interval that is turned on and off or set and reset based on a threshold, or a variable time interval that is periodically calculated based on factors and metrics measured within the processor core 200. In an exemplary embodiment, the delay is set or reset based on the number of available entries in the L2 cache storage queue 260. If the number of available entries in the L2 cache storage queue is less than a threshold, the L2 cache control module 280 turns on or sets the delay, and if the number of available entries in the L2 cache storage queue exceeds the threshold, the delay is turned off or reset. As an example, if the number of available entries in the L2 storage queue 260 is less than four entries, the L2 cache 230 delays sending a POP signal to the LSU 210, and if the number of available entries in the L2 cache storage queue 260 is greater than or equal to four entries, the sending of the POP signal to initiate a transfer of data information from the LSU 210 is not delayed. In another exemplary embodiment, the time delay is calculated to be longer or shorter based on certain performance metrics in the processor core, including but not limited to the number of available entries in the L2 cache storage queue 260, a recent average of the transfer time or transfer rate of data information transferred from the LSU storage queue 250 to the L2 cache storage queue 260, and / or a recent frequency of memory or store operations occurring within the processor core 200. The ability to strategically set or reset, or variably adjust, the time interval of the delay enhances the performance of data information transfers between the LSU storage queue 250 and the L2 cache storage queue 260 by maximizing the opportunity for the L2 cache 230 to accept expedited data information transfers from the LSU 210. When the L2 storage queue 260 is nearing capacity and has few available entries, or when other factors indicate that the processor core 200 environment is stressed, the L2 cache control module 280 delays sending a POP signal to the LSU control module 270. Alternatively, when the L2 storage queue 260 has several available entries, or when other factors indicate that the processor core 200 environment is not stressed, the L2 cache control module 280 does not delay sending a POP signal to the LSU control module 270. By strategically implementing a time delay of the L2 cache 230 to initiate data information transfers from the LSU storage queue 250 to the L2 cache storage queue, the L2 cache 230 can successfully handle additional requests from the LSU 210 to receive additional data information transfers and avoid having to reject such requests because the L2 cache storage queue 260 has no available entries.

[0038] The present application can be embodied as a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0039] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0040] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage and / or execution.

[0041] Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages.

[0042] The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0043] Aspects of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0044] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including

[0045] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0046] The diagrams of the flowcharts and block diagrams illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending on the functionality involved. Other implementations can be implemented with all the disclosed steps not present in a given implementation. It will further be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A processor included in a central processing unit (CPU), the CPU included in a computer processor system, the CPU coupled to a memory, the processor comprising: a load and store unit (LSU), the LSU including a control module and a store queue, the store queue including a plurality of entries for storing a plurality of packets; a cache memory, the cache memory an L2 cache, the L2 cache coupled to the LSU, the L2 cache including a control module and a store queue, the store queue including a plurality of entries for storing a plurality of packets; wherein the L2 cache determines that an available entry exists in the L2 cache store queue and transmits a request to the LSU to transfer a packet; wherein the LSU transmits an acknowledgement from the L2 cache and transfers the packet from the entry in the LSU store queue over a data bus coupled to the L2 cache; wherein the L2 cache receives the packet from the LSU store queue and stores the packet in the available entry in the L2 cache store queue; and wherein the LSU anticipates that the L2 cache store queue has an additional available entry, transmits an additional acknowledgement to the L2 cache prior to the L2 cache requesting an additional packet, and transfers an additional packet from an additional entry in the LSU store queue.

2. The processor of claim 1, wherein the L2 cache determines that an additional available entry exists in the L2 cache store queue, receives the additional packet from the LSU store queue, and stores the additional packet in the additional available entry in the L2 cache store queue; and wherein the L2 cache delays transmitting a subsequent request to the LSU for a subsequent packet to be transferred from the LSU, the subsequent request also serving as an acknowledgement to the LSU for storing the additional packet in the L2 cache.

3. The processor of claim 1, wherein the L2 cache requests a packet by transmitting a POP signal from the L2 cache control module along a control bus coupled to the LSU control module, and wherein the LSU acknowledges the request from the L2 cache by transmitting a PUSH signal from the LSU control module along the control bus coupled to the L2 cache control module.

4. The processor of claim 2, wherein the L2 cache control module determines a delay to request a subsequent packet, the delay a subsequent request delay, and calculates the subsequent request delay based on a number of available entries in the L2 cache store queue.

5. The processor of claim 4, wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer a packet from the LSU store queue to the L2 cache store queue.

6. The processor of claim 4, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is a number of available entries in the L2 cache store queue; wherein when the number of available entries in the L2 cache store queue is less than the threshold, the L2 cache control module sets the subsequent request delay to a fixed time interval; and wherein when the number of available entries in the L2 cache store queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

7. The processor of claim 3, wherein the L2 cache determines that there are no additional available entries in the L2 cache store queue; wherein the L2 cache control module transmits a BOUNCE signal to the LSU control module along a control bus to indicate that the additional packet is rejected and not stored in the L2 cache store queue; and wherein the LSU must wait for a subsequent request from the L2 cache before retrying transmission of the additional packet.

8. A method for improving performance of data information transmission of store operations within a computer processing system, the computer processing system comprising a processor and a memory, the processor comprising a cache memory and a load and store unit, the computer processing system further comprising a computer readable storage medium having computer usable program code embodied therein, the computer usable program code configured such that, when executed by the processor, performs operations, the method comprising: storing a packet within a load and store unit (LSU), the packet to be transmitted to the cache memory, the cache memory being an L2 cache, the LSU comprising a store queue having a plurality of entries to store a plurality of packets, the L2 cache comprising a store queue having a plurality of entries to store a plurality of packets; transmitting a request from the L2 cache to the LSU to transmit the packet to the L2 cache when the L2 cache determines that there is an available entry in the L2 cache store queue; transmitting an acknowledgement from the LSU to the L2 cache and transmitting the packet from an entry in the LSU store queue to the L2 cache; receiving the packet in the L2 cache and storing the packet in the available entry in the L2 cache store queue; and transmitting an additional acknowledgement from the LSU to the L2 cache and transmitting an additional packet from an additional entry in the LSU store queue to the L2 cache prior to the L2 cache requesting an additional packet in anticipation that the L2 cache has an additional available entry in the L2 cache store queue.

9. The method of claim 8, further comprising: ​ determining, by the L2 cache, that there is an additional available entry in the L2 cache store queue; storing the additional packet of information from the LSU store queue in the additional available entry within the L2 cache store queue; and delaying transmission of a subsequent request to the LSU for a subsequent packet of information to be transmitted from the LSU, the subsequent request also serving as an acknowledgement to the LSU to store the additional packet of information in the L2 cache.

10. The method of claim 8, wherein the L2 cache includes a control module, and transmitting the request by the L2 cache further comprises the L2 cache control module transmitting a POP signal along a control bus coupled to the LSU; and wherein the LSU includes a control module, and transmitting the acknowledgement by the LSU further comprises the LSU control module transmitting a PUSH signal along the control bus coupled to the L2 cache.

11. The method of claim 10, wherein the delay of the request for a subsequent packet of information is determined by the L2 cache control module, the delay being a subsequent request delay, the L2 cache control module calculating the subsequent request delay based on a number of available entries within the L2 cache store queue.

12. The method of claim 11, wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer a packet of information from the LSU store queue to the L2 cache store queue.

13. The method of claim 11, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is a number of available entries in the L2 cache store queue; wherein when the number of available entries in the L2 cache store queue is less than the threshold, the L2 cache control module sets the subsequent request delay to a fixed time interval; and wherein when the number of available entries in the L2 cache store queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

14. The method of claim 10, further comprising: when the L2 cache determines that there is not an additional available entry in the L2 cache store queue, rejecting the additional packet of information, wherein the L2 cache control module transmits a BOUNCE signal along a control bus to the LSU control module to indicate that the additional packet of information is rejected and not stored in the L2 cache store queue; and when the L2 cache transmits a subsequent request to the LSU, retrying transmission of the additional packet of information by the LSU. ​ 15. A computer program product for improving performance of transmission of data information for a store operation within a computer processing system, the computer processing system including a processor and a memory, the processor including a cache memory and a load and store unit, the computer program product comprising a non-transitory computer readable storage medium having computer usable program code embodied therein, the computer usable program code configured such that, when executed by at least one processor, the computer usable program code performs operations comprising: storing a packet of information within a load and store unit, the packet of information to be transmitted to the cache memory, the cache memory being an L2 cache, the load and store unit including a store queue having a plurality of entries to store a plurality of packets of information, the L2 cache including a store queue having a plurality of entries to store a plurality of packets of information; transmitting a request from the L2 cache to the load and store unit to transmit the packet of information to the L2 cache when the L2 cache determines that an available entry exists in the L2 cache store queue; transmitting an acknowledgement from the load and store unit to the L2 cache and transmitting the packet of information from an entry in the load and store unit store queue to the L2 cache; receiving the packet of information in the L2 cache and storing the packet of information in the available entry in the L2 cache store queue; and transmitting an additional acknowledgement from the load and store unit to the L2 cache and transmitting an additional packet of information from an additional entry in the load and store unit store queue to the L2 cache in anticipation of the L2 cache having an additional available entry in the L2 cache store queue prior to the L2 cache requesting an additional packet of information.

16. The computer program product of claim 15, further comprising: determining by the L2 cache that an additional available entry exists in the L2 cache store queue; storing the additional packet of information from the load and store unit store queue in the additional available entry within the L2 cache store queue; and delaying transmission of a subsequent request from the L2 cache for a subsequent packet of information to be transmitted from the load and store unit, the subsequent request also serving as an acknowledgement to the load and store unit to store the additional packet of information in the L2 cache.

17. The computer program product of claim 15, wherein the L2 cache includes a control module and transmitting the request by the L2 cache further comprises the L2 cache control module transmitting a POP signal along a control bus coupled to the load and store unit; and wherein the load and store unit includes a control module and transmitting the acknowledgement by the load and store unit further comprises the load and store unit control module transmitting a PUSH signal along the control bus coupled to the L2 cache. ​ ​ 18. The computer program product of claim 17, wherein a delay of a request for a subsequent packet is determined by the L2 cache control module, the delay being a subsequent request delay, the L2 cache control module calculating the subsequent request delay based on a number of available entries within the L2 cache storage queue.

19. The computer program product of claim 18, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is the number of available entries in the L2 cache storage queue; wherein when the number of available entries in the L2 cache storage queue is less than the threshold, the L2 cache control module sets the subsequent request delay to a fixed time interval; and wherein when the number of available entries in the L2 cache storage queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

20. The computer program product of claim 17, further comprising: rejecting the additional packet when the L2 cache determines that no additional available entry exists in the L2 cache storage queue, wherein the L2 cache control module transmits a BOUNCE signal to the LSU control module along a control bus to indicate that the additional packet is rejected and not stored in the L2 cache storage queue; and retrying transmission of the additional packet by the LSU when the L2 cache transmits a subsequent request to the LSU.

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