Light detection device, electronic apparatus, and method for manufacturing light detection device

Abstract

Provided is a light detection device capable of improving the saturation charge amount Qs of a photoelectric conversion unit. Specifically, the light detection device includes: a semiconductor substrate on which a plurality of photoelectric conversion units are formed; and an element separation part including a trench part formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer disposed in the trench part and covering a side wall surface of the trench part, and a functional layer disposed in a space inside the trench part covered by the semiconductor layer. The photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer. The semiconductor layer has a P-type impurity concentration of 1 e16 / cm3 or less. The functional layer is a layer that induces a hole on the functional layer side of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a light detection device, an electronic device, and a method for manufacturing the light detection device. Background Art

[0002] Conventionally, a light detection device has been proposed in which a groove portion is provided between photoelectric conversion units and a P-type semiconductor layer grown by epitaxial growth is arranged in the groove portion (for example, see Patent Document 1). In the light detection device described in Patent Document 1, the P-type semiconductor layer serves as a hole pinning layer, and the generation of dark current on the side wall surface of the groove portion is suppressed. Citation List Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-38981 Summary of the invention Problem that the invention aims to solve

[0004] In such a light detection device, it is necessary to further increase the amount of charge that can be accumulated in the photoelectric conversion unit (hereinafter, also referred to as “saturation charge amount Qs”).

[0005] An object of the present disclosure is to provide a photodetection device, an electronic device, and a method for manufacturing a photodetection device capable of increasing a saturation charge amount Qs of a photoelectric conversion unit. Solution to the problem

[0006] The light detection device disclosed in the present invention comprises: (a) a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and (b) an element separation portion, which comprises a groove portion formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer arranged in the groove portion and covering the sidewall surface of the groove portion, and a functional layer arranged in a space inside the groove portion covered by the semiconductor layer, wherein (c) the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, and (d) the semiconductor layer has a 1e16 / cm 3 The following P-type impurity concentration, and (e) the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.

[0007] Another light detection device disclosed in the present invention includes: (a) a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and (b) an element separation portion including a groove portion formed in the semiconductor substrate between the photoelectric conversion units and a P-type solid diffusion layer disposed in the groove portion and covering the sidewall surface of the groove portion, wherein (c) the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid diffusion layer, and (d) the P-type solid diffusion layer has a 1e16 / cm3 The impurity concentration of N type is as follows.

[0008] Another light detection device disclosed in the present invention includes: (a) a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and (b) an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate, an N-type epitaxial growth layer arranged in the groove portion and covering the sidewall surface of the groove portion, and a P-type epitaxial growth layer arranged in the space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein (c) the N-type epitaxial growth layer has a 1e16 / cm 3 The P-type impurity concentration is below 1e16 / cm 3 The impurity concentration of N type is as follows.

[0009] The electronic device disclosed herein includes a light detection device, the light detection device including: (a) a semiconductor substrate formed with a plurality of photoelectric conversion units; and (b) an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer arranged in the groove portion and covering the side wall surface of the groove portion, and a functional layer arranged in the space inside the groove portion covered by the semiconductor layer, wherein (c) the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, and (d) the semiconductor layer has a 1e16 / cm 3 The following P-type impurity concentration, and (e) the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.

[0010] Another electronic device disclosed herein includes a light detecting device, the light detecting device including: (a) a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and (b) an element separation portion including a groove portion formed in the semiconductor substrate between the photoelectric conversion units and a P-type solid phase diffusion layer disposed in the groove portion and covering a sidewall surface of the groove portion, wherein (c) the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer, and (d) the P-type solid phase diffusion layer has a 1e16 / cm 3 The impurity concentration of N type is as follows.

[0011] Another electronic device disclosed herein includes a light detection device, the light detection device including: (a) a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and (b) an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate, an N-type epitaxial growth layer arranged in the groove portion and covering the sidewall surface of the groove portion, and a P-type epitaxial growth layer arranged in a space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein (c) the N-type epitaxial growth layer has a 1e16 / cm 3 The P-type impurity concentration is below 1e16 / cm 3 The impurity concentration of N type is as follows.

[0012] The manufacturing method of the light detection device disclosed in the present invention comprises: (a) forming a groove portion in a semiconductor substrate; (b) forming an impurity concentration of 1e16 / cm on the side wall surface of the groove portion by epitaxial growth; 3 and (c) a step of doping P-type impurities from within the trench portion into the epitaxial growth layer by solid phase diffusion.

[0013] Another method for manufacturing the light detection device disclosed in the present invention comprises: (a) forming a groove portion in a semiconductor substrate; (b) while adding N-type impurities, forming a P-type impurity concentration of 1e16 / cm on the side wall surface of the groove portion by epitaxial growth; 3 and (c) while adding P-type impurities, forming an N-type impurity concentration of 1e16 / cm on the surface of the N-type epitaxial growth layer on the center side of the width direction of the groove portion by epitaxial growth. 3 The following are the steps for growing the P-type epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing the overall configuration of a solid-state imaging device according to the first embodiment. Figure 2 It is shown along Figure 1 A diagram showing a cross-sectional structure of a solid-state imaging device taken along line AA in FIG. Figure 3 It is shown in Figure 2 A diagram showing a cross-sectional structure of a solid-state imaging device when a region B in FIG. 1 is enlarged. Figure 4 It is shown Figure 3 Graph of the N-type impurity concentration distribution at the position indicated by line CC in FIG. Figure 5 It is a diagram showing a cross-sectional structure of a solid-state imaging device in the case where the semiconductor layer is of P type. Fig. 6A It is a diagram showing a method of manufacturing a solid-state imaging device. Figure 6B The present invention shows a method of manufacturing a solid-state imaging device. Figure 6C The present invention shows a method of manufacturing a solid-state imaging device. Fig.6D The present invention shows a method of manufacturing a solid-state imaging device. Fig. 6E The present invention shows a method of manufacturing a solid-state imaging device. Fig. 6F The present invention shows a method of manufacturing a solid-state imaging device. Figure 6G The present invention shows a method of manufacturing a solid-state imaging device. Figure 6H The present invention shows a method of manufacturing a solid-state imaging device. Fig. 7A 2 is a diagram illustrating a method of manufacturing a solid-state imaging device according to a modification example. Figure 7B 2 is a diagram illustrating a method of manufacturing a solid-state imaging device according to a modification example. Figure 7C 2 is a diagram illustrating a method of manufacturing a solid-state imaging device according to a modification example. Fig.7D 2 is a diagram illustrating a method of manufacturing a solid-state imaging device according to a modification example. Figure 8 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a second embodiment. Fig. 9 It is shown in Figure 8 A diagram showing a cross-sectional structure of a solid-state imaging device when a region D in FIG. 1 is enlarged. Fig.10 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. Fig.11 It is shown in Fig.10 A diagram showing a cross-sectional structure of a solid-state imaging device when a region E in FIG. 1 is enlarged. Fig.12 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a third embodiment. Fig.13 It is shown in Fig.12 A diagram showing a cross-sectional structure of a solid-state imaging device when a region F in FIG. 1 is enlarged. Fig.14 is a diagram showing potential distribution. Fig.15 1 is a diagram showing a cross-sectional configuration of a solid-state imaging device in the case of including a P-type semiconductor region. Fig.16is a diagram showing potential distribution. Fig.17A It is a diagram showing a method of forming an element isolation portion. Fig. 17B It is a diagram showing a method of forming an element isolation portion. Fig. 17C It is a diagram showing a method of forming an element isolation portion. Fig.17D It is a diagram showing a method of forming an element isolation portion. Fig.17E It is a diagram showing a method of forming an element isolation portion. Fig.17F It is a diagram showing a method of forming an element isolation portion. Figure 17G It is a diagram showing a method of forming an element isolation portion. Fig.18A It is a diagram showing a method of forming an element isolation portion. Fig.18B It is a diagram showing a method of forming an element isolation portion. Fig. 18C It is a diagram showing a method of forming an element isolation portion. Fig.18D It is a diagram showing a method of forming an element isolation portion. Fig.18E It is a diagram showing a method of forming an element isolation portion. Fig.18F It is a diagram showing a method of forming an element isolation portion. Figure 18G It is a diagram showing a method of forming an element isolation portion. Fig.18H It is a diagram showing a method of forming an element isolation portion. Fig.18I It is a diagram showing a method of forming an element isolation portion. Fig.19 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. Fig. 20 It is shown in Fig.19 A diagram showing a cross-sectional structure of a solid-state imaging device when a region G in FIG. 1 is enlarged. Fig.21 It is a diagram showing a method of forming an element isolation portion. Fig.22A It is a diagram showing a method of forming an element isolation portion. Fig. 22B It is a diagram showing a method of forming an element isolation portion. Fig.23 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. Fig.24It is shown in Fig.23 A diagram showing a cross-sectional structure of a solid-state imaging device when a region H in FIG. 1 is enlarged. Fig.25 It is a diagram showing a method of forming an element isolation portion. Fig.26A It is a diagram showing a method of forming an element isolation portion. Fig.26B It is a diagram showing a method of forming an element isolation portion. Fig. 27 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. Fig.28 It is shown in Fig. 27 A diagram showing a cross-sectional structure of a solid-state imaging device when region I in FIG. 1 is enlarged. Fig.29 It is a diagram showing a method of forming an element isolation portion. Fig. 30A It is a diagram showing a method of forming an element isolation portion. Fig. 30B It is a diagram showing a method of forming an element isolation portion. Fig.31 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a fourth embodiment. Fig.32 It is shown in Fig.31 A diagram showing a cross-sectional structure of a solid-state imaging device when a region J in FIG. 1 is enlarged. Fig.33A It is a diagram showing a method of forming an element isolation portion. Fig.33B It is a diagram showing a method of forming an element isolation portion. Fig.34A It is a diagram showing a method of forming an element isolation portion. Fig.34B It is a diagram showing a method of forming an element isolation portion. Fig.34C It is a diagram showing a method of forming an element isolation portion. Fig.35 is a diagram showing the overall configuration of an electronic device according to a fifth embodiment. DETAILED DESCRIPTION

[0015] In the following, reference will be made to Figures 1 to 35 Examples of a light detection device, an electronic device, and a method for manufacturing a light detection device according to an embodiment of the present disclosure are described. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. In addition, the effects described herein are illustrative and not restrictive, and other effects may exist.

[0016] 1. First embodiment: solid-state imaging device 1-1 Overall Structure of Solid-State Imaging Device 1-2 Main components 1-3 Method for manufacturing solid-state imaging device 1-4 Variation 2. Second Embodiment: Solid-State Imaging Device 2-1 Composition of the main parts 2-2 Modification 3. Third Embodiment: Solid-State Imaging Device 3-1 Composition of the main parts 3-2 Method for manufacturing solid-state imaging device 3-3 Variations 4. Fourth Embodiment: Solid-State Imaging Device 4-1 Composition of the main parts 4-2 Method for manufacturing solid-state imaging device 4-3 Variation 5. Fifth embodiment: Application example of electronic equipment

[0017] <1. First Embodiment: Solid-State Imaging Device> [1-1 Overall Configuration of Solid-State Imaging Device] A solid-state imaging device 1 (in a broad sense, “light detecting device”) according to a first embodiment of the present disclosure will be described. Figure 1 is a diagram showing the overall configuration of a solid-state imaging device 1 according to the first embodiment. Figure 1 The solid-state imaging device 1 in the embodiment is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor. Fig.35 As shown, the solid-state imaging device 1 (1002) captures image light (incident light) from a subject via a lens group 1001, converts the amount of incident light that forms an image on an imaging surface into an electrical signal in units of pixels, and outputs it as a pixel signal. like Figure 1 As shown, the solid-state imaging device 1 includes a pixel region 2 , a vertical drive circuit 3 , a column signal processing circuit 4 , a horizontal drive circuit 5 , an output circuit 6 , and a control circuit 7 .

[0018] The pixel region 2 includes a plurality of pixels 8 arranged in a two-dimensional array. The pixels 8 include Figure 2 The photoelectric conversion unit 21 and a plurality of pixel transistors are shown. Examples of the plurality of pixel transistors include four MOS transistors including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor. For example, the vertical drive circuit 3 includes a shift register, selects a desired pixel drive line 9, supplies a pulse for driving the pixel 8 to the selected pixel drive line 9, and drives each pixel 8 row by row. That is, the vertical drive circuit 3 selectively scans each pixel 8 in the pixel area 2 in sequence in the vertical direction in units of rows, and supplies a pixel signal based on a signal charge generated according to the amount of received light in the photoelectric conversion unit 21 of each pixel 8 to the column signal processing circuit 4 through the vertical signal line 10.

[0019] For example, the column signal processing circuit 4 is configured for each column of the pixels 8, and performs signal processing such as noise removal for each pixel column on the signals output from the pixels 8 of one row. For example, the column signal processing circuit 4 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing fixed pattern noise inherent to the pixels. For example, the horizontal driving circuit 5 includes a shift register, sequentially outputs horizontal scanning pulses to the column signal processing circuits 4 , sequentially selects each column signal processing circuit 4 , and causes each column signal processing circuit 4 to output a pixel signal after signal processing to the horizontal signal line 11 .

[0020] The output circuit 6 performs signal processing on pixel signals sequentially supplied from the respective column signal processing circuits 4 through the horizontal signal line 11 and outputs the pixel signals. As the signal processing, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc. can be used. The control circuit 7 generates a clock signal and a control signal as an operation reference for the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal. Then, the control circuit 7 outputs the generated clock signal and control signal to the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc.

[0021] [1-2 Structure of the main parts] Next, the detailed structure of the solid-state imaging device 1 will be described. Figure 2 It is shown along Figure 1 A cross-sectional view of the solid-state imaging device 1 taken along the line AA in FIG. Figure 3 It is shown in Figure 2 A diagram showing a cross-sectional configuration of the solid-state imaging device 1 when a region B in FIG. 1 is enlarged. like Figure 2 and Figure 3As shown, in the solid-state imaging device 1, a light receiving layer 17 formed by sequentially stacking a semiconductor substrate 12, a fixed charge film 13 (broadly, a "functional layer"), an insulating film 14, a light shielding film 15, and a planarizing film 16 is provided. In addition, a color filter layer 18 and a microlens array 19 are sequentially provided on the surface of the planarizing film 16 side of the light receiving layer 17 (hereinafter, also referred to as the "back side S1"). In addition, a wiring layer 20 is provided on the surface of the semiconductor substrate 12 side of the light receiving layer 17 (hereinafter, also referred to as the "front side S2").

[0022] For example, the semiconductor substrate 12 includes silicon (Si). In the semiconductor substrate 12, a photoelectric conversion unit 21 is formed in each region of each pixel 8. That is, a plurality of photoelectric conversion units 21 are arranged in a two-dimensional array on the semiconductor substrate 12. In the photoelectric conversion unit 21, a P-type semiconductor region 22 containing a P-type impurity and a P-type semiconductor region 24 containing a P-type impurity are formed on each of the light incident surface (hereinafter, also referred to as "back surface S3") side and the front surface S2 side of the semiconductor substrate 12. In addition, an N-type semiconductor region 23 continuous in the thickness direction of the semiconductor substrate 12 is formed between the P-type semiconductor region 22 and the P-type semiconductor region 24 to contact the semiconductor layer 27 surrounding the photoelectric conversion unit 21. That is, the photoelectric conversion unit 21 has an N-type semiconductor region 23 in a region in contact with the semiconductor layer 27. The semiconductor layer 27 is a layer covering the side wall surface S4 of the groove portion 25 formed between the photoelectric conversion units 21. As the P-type impurity, for example, boron (B) can be used. In addition, as N-type impurities, for example, phosphorus (P) and arsenic (As) can be used. The photoelectric conversion unit 21 forms a photodiode through a PN structure of a junction surface between the P-type semiconductor region 22 and the N-type semiconductor region 23 and a junction surface between the P-type semiconductor region 24 and the N-type semiconductor region 23. Then, photoelectric conversion is performed to generate a charge corresponding to the amount of light received. In addition, the photoelectric conversion unit 21 accumulates the charge generated by the photoelectric conversion in the N-type semiconductor region 23.

[0023] In addition, if Figure 3 and Figure 4 As shown, the N-type impurity concentration of the N-type semiconductor region 23 is higher on the groove portion 25 side than on the central portion side of the photoelectric conversion unit 21, and has a peak value of the N-type impurity concentration at the interface between the groove portion 25 (semiconductor layer 27) and the N-type semiconductor region 23. As a result, in the N-type semiconductor region 23, the N-type impurity concentration near the interface can be increased, and the amount of charge that can be accumulated in the photoelectric conversion unit 21 (i.e., the saturation charge amount Qs) can be increased. Figure 3 In the embodiment, the higher the N-type impurity concentration is, the darker the color of the N-type semiconductor region 23 is. Figure 3, a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 . Figure 4 It is shown Figure 3 Graph of the N-type impurity concentration distribution at the position indicated by the line CC in . In addition, the N-type impurity concentration of the N-type semiconductor region 23 is constant in the thickness direction of the semiconductor substrate 12. Therefore, the peak value of the N-type impurity concentration at the interface between the groove portion 25 (semiconductor layer 27) and the N-type semiconductor region 23 is continuous in the thickness direction of the semiconductor substrate 12. As a result, each of the amount of charge that can be accumulated on the back side S3 of the semiconductor substrate 12 and the amount of charge that can be accumulated on the front side S2 can be increased, and the saturation charge amount Qs can be further increased. Note that, for example, Figure 4 The impurity concentration distributions of the N-type semiconductor region 23 and the semiconductor layer 27 shown can be obtained by analysis using nanosecondary ion mass spectrometry (SIMS).

[0024] Furthermore, in the semiconductor substrate 12, a groove portion 25 is formed between adjacent photoelectric conversion units 21. The groove portion 25 is formed from the front surface S2 to the back surface S3 of the semiconductor substrate 12 along the side surface of the photoelectric conversion unit 21. That is, the groove portion 25 is formed in a lattice shape in the semiconductor substrate 12 so as to surround each photoelectric conversion unit 21. In addition, the groove portion 25 forms an element separation portion 26 together with the semiconductor layer 27, the fixed charge film 13, and the insulating film 14. The semiconductor layer 27 covering the side wall surface S4 of the groove portion 25 is arranged inside the groove portion 25. The semiconductor layer 27 is formed to surround each photoelectric conversion unit 21 when viewed from the thickness direction of the semiconductor substrate 12. As the semiconductor layer 27, for example, a non-doped semiconductor layer such as a non-doped epitaxial growth layer formed at a different time from the semiconductor substrate 12 can be used. The epitaxial growth layer is a semiconductor layer formed by epitaxially growing a semiconductor crystal. By using such an epitaxial growth layer, the P-type impurity concentration of the semiconductor layer 27 is 1e16 / cm 3 (1×10 16 / cm 3 ) or less (low value). By reducing the P-type impurity concentration, such as Figure 3 As shown, the semiconductor layer 27 can suppress the diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion unit 21, and can suppress the erosion of the N-type semiconductor region 23 in the photoelectric conversion unit 21. Therefore, it is possible to suppress the reduction of the saturation charge amount Qs of the photoelectric conversion unit 21. That is, the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased.

[0025] In addition, if Figure 4As shown, the N-type impurity concentration of the semiconductor layer 27 is set to 1e16 / cm on the surface of the semiconductor layer 27 that is farther from the side wall surface S4 of the groove portion 25 (hereinafter also referred to as "inner side surface S5"). 3 As described later, when manufacturing the solid-state imaging device 1, the impurity concentration is 1e16 / cm 3 The following semiconductor layer (e.g., epitaxial growth layer) is formed as semiconductor layer 27. Therefore, almost all N-type impurities in semiconductor layer 27 diffuse from N-type semiconductor region 23. Therefore, the N-type impurity concentration (1e16 / cm 3 hereinafter). For example, the layer thickness (film thickness) of the semiconductor layer 27 may be 10 nm or more. By reducing the N-type impurity concentration, as described later, a hole induction layer 27a may be formed on the inner side S5 side of the semiconductor layer 27 through the fixed charge film 13. As a material of the semiconductor layer 27, for example, the same material as the semiconductor substrate 12 (e.g., silicon (Si)) may be used.

[0026] In addition, the inner side surface S5 of the semiconductor layer 27 is covered by the fixed charge film 13. That is, the fixed charge film 13 is arranged in the space inside the groove portion 25 covered by the semiconductor layer 27 along the inner side surface S5 of the semiconductor layer 27. As the material of the fixed charge film 13, for example, a material that can generate negative fixed charges and achieve pinning by being deposited on the semiconductor layer 27 can be used. For example, a high refractive index material film or a high dielectric film having a negative fixed charge can be used. Specific examples thereof include oxides or nitrides (Al2O3, HfO2, Ta2O5, etc.) containing at least one element of aluminum (Al), hafnium (Hf), tantalum (Ta), zirconium (Zr) and titanium (Ti). As a result, as Figure 3 As shown, holes (positive holes) are induced by the fixed charge film 13 on the fixed charge film 13 side (the inner side S5 side) of the semiconductor layer 27 to form a portion in a high hole concentration state (hereinafter, also referred to as "hole inducing layer 27a"), and pinning of the side wall of the groove portion 25 is achieved. This pinning can suppress the dark current generated on the side wall of the groove portion 25. That is, it can be said that the fixed charge film 13 is a layer that induces holes on the fixed charge film 13 side (the inner side S5 side) of the semiconductor layer 27. In addition, the insulating film 14 is buried in the groove-shaped space inside the groove portion 25 covered with the semiconductor layer 27 and the fixed charge film 13. As a material of the insulating film 14, for example, silicon oxide (SiO2) or silicon nitride (SiN) can be used. As a result, the occurrence of electrical color mixing due to crosstalk in which charges photoelectrically converted by one photoelectric conversion unit 21 move to another photoelectric conversion unit 21 between adjacent photoelectric conversion units 21 is suppressed by the insulating film 14.

[0027] The fixed charge film 13 covers the bottom surface of the groove 25 and the back surface S3 of the semiconductor substrate 12 together with the semiconductor layer 27. In addition, the insulating film 14 covers the light incident surface of the fixed charge film 13 (hereinafter also referred to as "back surface S7") while being buried in the groove 25. The light shielding film 15 is arranged on the light incident surface (hereinafter, also referred to as "back surface S8") side of the insulating film 14, and is formed to open the light incident surface of each photoelectric conversion unit 21. As a material of the light shielding film 15, for example, aluminum (Al), tungsten (W) or copper (Cu) can be used. The planarization film 16 is arranged on the back surface S8 side of the insulating film 14 and continuously covers the back surface S8 and the light shielding film 15 so that the back surface S1 side of the light receiving layer 17 is a flat surface. As a material of the insulating film 14, for example, silicon oxide (SiO2) or silicon nitride (SiN) can be used.

[0028] The color filter layer 18 includes a plurality of color filters 28 formed on the back surface S1 side of the planarization film 16 and arranged corresponding to the photoelectric conversion unit 21. That is, one color filter 28 is formed for one photoelectric conversion unit 21. The plurality of color filters 28 include a plurality of types of color filters that transmit light of a predetermined wavelength included in the light collected by the microlens 29. As a result, each color filter 28 transmits light having a predetermined wavelength corresponding to the color filter 28 and allows the transmitted light to enter the photoelectric conversion unit 21. The microlens array 19 includes a plurality of microlenses 29 formed on the back surface S9 side (light receiving surface side) of the color filter layer 18 and arranged corresponding to the photoelectric conversion units 21. That is, one microlens 29 is formed for one photoelectric conversion unit 21. Therefore, each microlens 29 converges image light (incident light) from the subject and allows the converged incident light to enter the corresponding photoelectric conversion unit 21 via the color filter 28. The wiring layer 20 is arranged on the front surface S2 side of the semiconductor substrate 12. The wiring layer 20 includes an interlayer insulating film and wiring (not shown) stacked in multiple layers via the interlayer insulating film. Then, the wiring layer 20 drives the pixel transistor of each pixel 8 via the multilayer wiring.

[0029] In the solid-state imaging device 1 having the above-described configuration, light is irradiated from the back surface S3 side of the semiconductor substrate 12, the irradiated light is transmitted through the microlens 29 and the color filter 28, and the transmitted light is photoelectrically converted by the photoelectric conversion unit 21 to generate signal charges. Then, the generated signal charges are transmitted as pixel signals from the wiring formed by the wiring layer 20. Figure 1 The vertical signal line 10 in the output. Furthermore, in the solid-state imaging device 1, the fixed charge film 13 forms the hole inducing layer 27a on the fixed charge film 13 side of the semiconductor layer 27 and achieves pinning of the side wall of the groove portion 25. Then, the pinning suppresses dark current generated on the side wall of the groove portion 25.

[0030] Here, for example, Figure 5 As shown, in the case where the semiconductor layer 27 is a P+ type semiconductor layer 27 having a relatively high P-type impurity concentration, there is a possibility that the P-type impurities diffuse from the P+ type semiconductor layer 27 into the photoelectric conversion unit 21 and the N-type semiconductor region 23 in the photoelectric conversion unit 21 is corroded. Figure 5 The N-type semiconductor region 23 is eroded by the P-type impurities and the width is reduced from W1 to W2. Therefore, there is a possibility that the saturation charge amount Qs of the photoelectric conversion unit 21 is reduced. Figure 5 In the figure, the portion with a higher P-type impurity concentration is represented by a darker color. Figure 5 , a curve indicating the impurity concentration of the P type is represented by a dotted line overlapping with the P + type semiconductor layer 27 . Furthermore, in the case where the solid-state imaging device 1 has a plurality of pixels, the pixel 8 is miniaturized. Figure 5 In the solid-state imaging device 1 shown, when the pixel 8 is miniaturized, in addition to the reduction of the N-type semiconductor area 23 caused by the diffusion of the above-mentioned P-type impurities, a reduction of the N-type semiconductor area 23 due to the miniaturization of the pixel 8 also occurs, and therefore, it may be difficult to ensure the necessary saturation charge amount Qs.

[0031] On the other hand, in the solid-state imaging device 1 according to the first embodiment, as Figure 3 As shown, the semiconductor layer 27 is structured so that the P-type impurity concentration is 1e16 / cm 3 Therefore, diffusion of the P-type impurity from the semiconductor layer 27 into the photoelectric conversion unit 21 can be suppressed, and erosion of the N-type semiconductor region 23 within the photoelectric conversion unit 21 can be suppressed. Figure 3The case where the N-type semiconductor region 23 is not eroded by the P-type impurities and its width is maintained at W1 is shown. Therefore, it is possible to suppress the reduction in the amount of charge (saturation charge amount Qs) that can be accumulated in the photoelectric conversion unit 21. That is, the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. In addition, even in the case where the pixel 8 is miniaturized, the N-type semiconductor region 23 will not be reduced due to the diffusion of the P-type impurities. Therefore, the necessary saturation charge amount Qs can be ensured, and the solid-state imaging device 1 can be relatively easily provided with a plurality of pixels.

[0032] [1-3 Method for manufacturing solid-state imaging device] Next, a method of manufacturing the solid-state imaging device 1 according to the first embodiment will be described. First, if Fig. 6A As shown, a mask 30 having an opening at a position where the groove portion 25 is to be formed is formed on the front surface S2 of the semiconductor substrate 12. Subsequently, anisotropic dry etching is performed through the mask 30 to form the groove portion 25. As described above, by forming the groove portion 25 in the front-end-of-line process (FEOL), processing damage when forming the groove portion 25 can be restored using heat treatment performed in a subsequent process, and white spots and dark current can be suppressed. Subsequently, as Figure 6B As shown, the N-type semiconductor region 23 of the photoelectric conversion unit 21 is formed on the side wall surface S4 of the groove portion 25 using a conformal doping technique. As described above, since the groove portion 25 is formed by the FEOL process, the process of introducing N-type impurities from the inner side of the groove portion 25 can be applied to the formation of the N-type semiconductor region 23. As a method of doping N-type impurities, for example, a solid phase diffusion method, a plasma doping method, and an ion implantation method can be used. Note that in Figure 6B In the N-type semiconductor region 23, only Figure 3 The dark-colored portion (the portion having only a large N-type impurity concentration) is represented by spots. FIG. 6C to FIG. 6H A similar representation is used in .

[0033] Then, if Figure 6C As shown, a semiconductor crystal (e.g., silicon (Si)) is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 27 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. As the semiconductor layer 27, an impurity concentration of 1e16 / cm 3 The following epitaxial growth layer. Fig.6D As shown, silicon oxide (SiO2) 31 and doped polysilicon 32 are sequentially buried in the space inside the groove portion 25 covered with the semiconductor layer 27. Fig. 6EAs shown in FIG. 1 , a wiring layer 20 is formed on the front surface S2 side of the semiconductor substrate 12. Subsequently, after the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 is bonded to a logic substrate (not shown), as shown in FIG. Fig. 6F As shown, the semiconductor substrate 12 is polished from the back surface S3 side using the CMP technique to be thinned. Then, if Figure 6G As shown in FIG. 1 , the silicon oxide 31 and the doped polysilicon 32 are removed from the interior of the groove portion 25. Figure 6H As shown in FIG. 1 , the fixed charge film 13 and the insulating film 14 are sequentially formed in the groove portion 25. Then, as shown in FIG. Figure 2 As shown, the light shielding film 15, the planarizing film 16, the color filter layer 18, and the microlens array 19 are sequentially formed on the back surface S8 of the insulating film 14. As a result, the solid-state imaging device 1 according to the first embodiment is manufactured.

[0034] [1-4 Modification Example] (1) Note that in the first embodiment, the following example has been described: the semiconductor layer 37 is formed in a step (FEOL step) before the sensor substrate and the logic substrate are bonded or the semiconductor substrate 12 is thinned, but other configurations may be adopted. For example, it may be formed after the FEOL process. For example, first, after performing the above Fig. 6A and Figure 6B After the steps shown, Fig. 7A As shown in FIG. 1 , silicon oxide (SiO 2 ) 31 and doped polysilicon 32 are sequentially buried in the space inside the groove portion 25. Then, as shown in FIG. Figure 7B As shown in FIG. 1 , a wiring layer 20 is formed on the front surface S2 side of the semiconductor substrate 12. Subsequently, after the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 is bonded to a logic substrate (not shown), as shown in FIG. Figure 7C As shown, the semiconductor substrate 12 is polished from the back surface S3 side using a chemical mechanical polishing (CMP) technique to be thinned.

[0035] Then, if Fig.7D As shown, silicon oxide (SiO2) 31 and doped polysilicon 32 are removed from the interior of the groove portion 25. Figure 6G As shown, semiconductor crystal (for example, silicon (Si)) is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 27 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. Figure 6H As shown in FIG. 1 , the fixed charge film 13 and the insulating film 14 are sequentially formed in the groove portion 25. Then, as shown in FIG. Figure 2 As shown, a light shielding film 15 , a planarizing film 16 , a color filter layer 18 , and a microlens array 19 are sequentially formed on the back surface S8 of the insulating film 14 .

[0036] <2. Second Embodiment: Solid-State Imaging Device> [2-1 Structure of the main parts] Next, a solid-state imaging device 1 according to a second embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the second embodiment is similar to that of Figure 1 The structure in the figure will therefore be omitted. Figure 8 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to a second embodiment. Fig. 9 It is shown in Figure 8 A diagram showing a cross-sectional configuration of the solid-state imaging device 1 when a region D in FIG. Figure 8 and Fig. 9 In, with Figure 2 and Figure 3 Corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0037] like Figure 8 and Fig. 9 As shown, the second embodiment is different from the first embodiment in that an insulating film 33 and a conductor portion 34 to which a negative bias voltage is applied are sequentially buried in the space inside the groove portion 25, instead of Figure 2 The fixed charge film 13 and the insulating film 14 are shown. The inner side surface S5 of the semiconductor layer 27 is covered with the insulating film 33. As a result, the conductor portion 34 and the photoelectric conversion unit 21 (N-type semiconductor region 23) are insulated by the insulating film 33. As a material of the insulating film 33, for example, silicon oxide (SiO2) or a high dielectric constant insulating film can be used. In addition, the conductor part 34 is buried in the groove-shaped space inside the groove part 25 covered with the semiconductor layer 27 and the insulating film 33. That is, the conductor part 34 is arranged along the inner side surface S5 of the semiconductor layer 27 via the insulating film 33. As a material of the conductor part 34, for example, polysilicon or a metal material to which boron (B) is added can be used. In addition, a negative bias voltage is applied to the conductor part 34. As a result, as Fig. 9 As shown, holes (positive holes) are induced on the conductor portion 34 side (inner side S5 side) of the semiconductor layer 27 by the conductor portion 34 to form a portion (hole inducing layer 27a) in a high hole concentration state, and pinning of the side wall of the groove portion 25 is achieved. This pinning can suppress dark current generated on the side wall of the groove portion 25. Examples of a method of applying a negative bias voltage to the conductor portion 34 include a method of supplying power from the logic substrate (not shown) side and a method of applying a negative bias voltage from the back side S3 side of the semiconductor substrate 12.

[0038] [2-2 Modification Example] (1) Note that in the second embodiment, an example has been described in which the conductor portion 34 is buried in the space inside the groove portion 25, but other configurations may be employed. Fig.10 and Fig.11 As shown, the conductor portion 34 may cover the side wall surface S4 of the groove portion 25, so that the side wall portion has a groove-shaped space formed by the conductor portion 34 inside the groove portion 25. Here, polysilicon has the property of absorbing light. Therefore, for example, in Figure 8 and Fig. 9 In the case where the conductor portion 34 shown is formed using polysilicon, that is, in the case where the polysilicon is buried (filled) in the space inside the groove portion 25, the quantum efficiency QE may be reduced. In contrast, in this modification, the conductor portion 35 is formed in a manner having a groove-shaped space inside the groove portion 25. Therefore, for example, in the case where the conductor portion 34 is formed using polysilicon, the amount of polysilicon can be reduced to the amount of the space inside the groove portion 25, and the absorption of light by the polysilicon can be suppressed. As a result, the reduction in the quantum efficiency QE can be suppressed.

[0039] <3. Third Embodiment: Solid-State Imaging Device> [3-1 Structure of the main parts] Next, a solid-state imaging device 1 according to a third embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the third embodiment is similar to that of Figure 1 The structure in the figure will therefore be omitted. Fig.12 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to a third embodiment. Fig.13 It is shown in Fig.12 FIG. 1 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when the region F in FIG. 1 is enlarged. Fig.12 and Fig.13 In, with Figure 8 and Fig. 9 Corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0040] like Fig.12 and Fig.13 As shown, the third embodiment is different from the second embodiment in that a P-type solid phase diffusion layer 38 is used instead of Figure 8 The semiconductor layer 27 is shown. The P-type solid phase diffusion layer 38 is a layer disposed in the groove portion 25 and covering the side wall surface S4 of the groove portion 25. As the P-type solid phase diffusion layer 38, for example, a semiconductor layer obtained by introducing a P-type impurity (for example, boron (B)) into a non-doped epitaxial growth layer by solid phase diffusion can be used. By using such a semiconductor layer, such as Fig.13 As shown, the N-type impurity concentration of the P-type solid phase diffusion layer 38 is 1e16 / cm3 By reducing the N-type impurity concentration, such as Fig.14 As shown, the P-type solid phase diffusion layer 38 can make the potential gradient caused by the PN junction between the P-type solid phase diffusion layer 38 and the N-type semiconductor region 23 steeper. Therefore, the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. Fig.13 In FIG. 1 , a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 and the P type solid phase diffusion layer 38 , and a curve indicating the impurity concentration of the P type is represented by a single-dot chain line. Fig.14 is a diagram showing the potential distribution. Fig.14 , a curve indicating the potential distribution is represented by a dotted line overlapping the N-type semiconductor region 23 and the P-type solid-phase diffusion layer 38. Note that, for example, Fig.13 The distribution of N-type and P-type impurity concentrations shown can be obtained by analysis using Nano-SIMS.

[0041] In addition, the photoelectric conversion unit 21 has an N-type semiconductor region 23 in a region in contact with the P-type solid-phase diffusion layer 38. As the N-type semiconductor region 23, for example, a semiconductor region obtained by ion implantation of N-type impurities from the front surface S2 side of the semiconductor substrate 12 is used. Fig.13 As shown, the N-type impurity concentration of the N-type semiconductor region 23 is constant at each depth S2 from the front. Note that Fig.12 Shown omitted Figure 8 The situation of the fixed charge film 13 is shown. In addition, the solid-state imaging device 1 includes a portion on the back side S3 of the element separation portion 26 (hereinafter, also referred to as the "first element separation portion 26a") and a portion on the front side S2 (hereinafter, also referred to as the "second element separation portion 26b"). The width of the second element separation portion 26b is formed to be wider than the width of the first element separation portion 26a. In addition, the insulating material 39 is buried inside the second element separation portion 26b.

[0042] Here, for example, Fig.15 As shown in FIG. 1 , in the case where a P-type semiconductor region 55 obtained by ion-implanting P-type impurities into the N-type semiconductor region 23 from the side wall surface S4 of the groove portion 25 is used instead of the P-type solid phase diffusion layer 38, the N-type impurities are mixed in the P-type semiconductor region 55, and as shown in FIG. Fig.16 As shown in FIG. 1 , the potential gradient caused by the PN junction between the P-type semiconductor region 55 and the N-type semiconductor region 23 becomes gentle. Therefore, there is a possibility that the saturation charge amount Qs of the photoelectric conversion unit 21 decreases. Fig.15, a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 and the P type semiconductor region 55 , and a curve indicating the impurity concentration of the P type is represented by a one-dot chain line. Fig.16 is a diagram showing the potential distribution. Fig.16 , a curve indicating the potential distribution is represented by a dotted line overlapping the N-type semiconductor region 23 and the P-type semiconductor region 55 .

[0043] In contrast, in the solid-state imaging device 1 according to the first embodiment, as Fig.13 As shown, the P-type solid phase diffusion layer 38 has a 3 Therefore, it is possible to prevent N-type impurities from being mixed in the P-type solid phase diffusion layer 38, to make the potential gradient due to the PN junction between the P-type solid phase diffusion layer 38 and the N-type semiconductor region 23 steeper, and to increase the saturation charge amount Qs of the photoelectric conversion unit 21. In addition, even in the case where the pixel 8 is miniaturized, the necessary saturation charge amount Qs can be ensured, and the solid-state imaging device 1 can be made to have a plurality of pixels relatively easily.

[0044] [3-2 Method for manufacturing solid-state imaging device] Next, a method of manufacturing the solid-state imaging device 1 according to the third embodiment will be described. First, if Fig.17A As shown, a P-type semiconductor substrate 12 is prepared, and N-type impurities (e.g., phosphorus (P) and arsenic (As)) are ion-implanted from the front S2 side of the prepared semiconductor substrate 12 to form an N-type semiconductor region 23. The N-type semiconductor region 23 has a constant N-type impurity concentration at each depth from the front S2. Subsequently, a mask 40 having an opening at a position where the groove portion 25 is to be formed is formed on the front S2 of the semiconductor substrate 12. The mask 40 is formed by stacking a silicon nitride (SiN) film 41 and a silicon oxide (SiO2) film 42. Subsequently, anisotropic dry etching is performed via the mask 40 to form the groove portion 25.

[0045] Then, if Fig. 17B As shown, a semiconductor crystal (silicon (Si)) is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 43 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. The semiconductor layer 43 is formed only on the front surface S2 side of the groove portion 25, which is covered by the silicon nitride film 41 and forms the first element separation portion 26a (see Fig.12 ) is formed as the semiconductor layer 43 with an impurity concentration of 1e16 / cm 3 The following non-doped epitaxial growth layer. Fig. 17CAs shown, the semiconductor layer 43 is doped with a P-type impurity (e.g., boron (B)) from the inside of the groove portion 25 by a solid phase diffusion method to form a P-type solid phase diffusion layer 38. That is, the semiconductor layer 43 becomes the P-type solid phase diffusion layer 38. As a result, it is possible to prevent N-type impurities from being mixed in the P-type solid phase diffusion layer 38, and the concentration of the N-type impurities in the P-type solid phase diffusion layer 38 can be set to 1e16 / cm 3 the following.

[0046] Then, if Fig.17D As shown, silicon oxide (SiO2) 44 and doped polysilicon 45 are sequentially buried in the space inside the groove portion 25 covered with the P-type solid phase diffusion layer 38. The silicon oxide 44 is buried to cover the side of the P-type solid phase diffusion layer 38. The doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S10 of the mask 40. Subsequently, as shown in FIG. Fig.17E As shown, etching back is performed to bury the insulating material 39 from the surface S10 of the mask 40 and the groove portion 25 (see Fig.12 ) is removed from the position of the doped polysilicon 45. Then, as Fig.17F As shown in FIG. 1 , the insulating material 46 is buried on the front face S2 side of the groove portion 25. The burying of the insulating material 46 is performed until the insulating material 46 covers the entire surface S10 of the mask 40. Then, as shown in FIG. Figure 17G As shown, the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39. By such a process, the insulating material 46 is formed. Fig.12 The component separation section 26 is shown. Then, as Fig.12 As shown in FIG. 1 , an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, a Fig.12 The solid-state imaging device 1 is shown.

[0047] Next, another method of manufacturing the solid-state imaging device 1 will be described. Fig.18I As shown, the configuration of the second element separation portion 26b formed by this manufacturing method is slightly different from the configuration of the second element separation portion 26b formed by the above-mentioned forming method. First, if Fig.18A As shown, similar to the above-described formation method, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front S2 side of the semiconductor substrate 12 via a mask (not shown) to form the groove portion 25. Subsequently, as Fig.18BAs shown, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 43 is formed in the groove portion 25 and on the front surface S2 of the semiconductor substrate 12 to continuously cover the entire side wall surface S4 and bottom surface of the groove portion 25 and the front surface S2 of the semiconductor substrate 12. As the semiconductor layer 43, a layer with an impurity concentration of 1e16 / cm 3 The following non-doped epitaxial growth layer. Fig. 18C As shown, the semiconductor layer 43 is doped with a P-type impurity (e.g., boron (B)) from the inside of the groove portion 25 by a solid phase diffusion method to form a P-type solid phase diffusion layer 38. That is, the semiconductor layer 43 becomes the P-type solid phase diffusion layer 38. As a result, it is possible to prevent N-type impurities from being mixed in the P-type solid phase diffusion layer 38, and the concentration of the N-type impurities in the P-type solid phase diffusion layer 38 can be set to 1e16 / cm 3 the following.

[0048] Then, if Fig.18D As shown, silicon oxide (SiO2) 44 and doped polysilicon 45 are sequentially buried in the space inside the groove portion 25 covered with the P-type solid phase diffusion layer 38. The silicon oxide 44 is buried to cover the side of the P-type solid phase diffusion layer 38. In addition, the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S12 of the silicon oxide 44. Subsequently, as shown in FIG. Fig.18E As shown, the front surface S2 of the semiconductor substrate 12 is polished or the like using CMP technology or etch-back to expose the front surface S2 of the semiconductor substrate 12. Fig.18F As shown, a second element separation portion 26b (see Fig.12 ) is formed by stacking a silicon nitride (SiN) film 48 and a silicon oxide (SiO2) film 49. Figure 18G As shown, etching is performed via the mask 47 to form the groove portion 25 where the second element separation portion 26b is to be formed (see Fig.12 ) (hereinafter, also referred to as "groove portion 50"). Fig.18H As shown in FIG. 4 , the insulating material 46 is buried in the groove portion 50. The burying of the insulating material 46 is performed until the insulating material 46 covers the entire surface of the mask 47 S10. Then, as shown in FIG. Fig.18I As shown, the insulating material 46 is polished from the surface S11 side using CMP technology to form Fig.12 The insulating material 39 shown in FIG. Fig.12 The component separation section 26 is shown. Then, as Fig.12 As shown in FIG. 1 , an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, a Fig.12The solid-state imaging device 1 is shown.

[0049] [3-3 Modification Example] (1) Note that in the third embodiment, an example has been described in which the N-type semiconductor region 23 is provided as the N-type region of the photoelectric conversion unit 21, but other configurations may be employed. Fig.19 and Fig. 20 As shown, in the region of the photoelectric conversion unit 21 in contact with the groove portion 25, an N-type semiconductor region (hereinafter, also referred to as "N+ type semiconductor region 51") having a relatively high N-type impurity concentration can be provided as a part of the N-type semiconductor region 23. As a result, since a PN junction is formed between the P-type solid phase diffusion layer 38 and the N+ type semiconductor region 51 (region having a relatively high N-type impurity concentration), the potential gradient can be made steeper, and the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. Fig. 20 In FIG. 1 , a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 and the P type solid phase diffusion layer 38 , and a curve indicating the impurity concentration of the P type is represented by a single-dot chain line.

[0050] A method of forming the element separation portion 26 when such a configuration is adopted will be described. FIG. 17A to FIG. 17G In the case of the manufacturing method shown in the figure, similar to the forming method, first, similar to Fig.17A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front surface S2 side of the semiconductor substrate 12 via the mask 40 to form the groove portion 25. Subsequently, as shown in FIG. Fig.21 As shown, N-type impurities are ion-implanted from the inside of the groove portion 25 to form an N+ type semiconductor region 51 on the side wall surface S4 and the bottom surface of the groove portion 25. Fig. 17B In the step shown, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 43 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. Thereafter, by FIG. 17C to FIG. 17G The steps shown form Fig.19 The component separation portion 26 is shown.

[0051] In addition, when using FIG. 18A to FIG. 18I In the case of a formation method similar to the formation method of the element separation portion 26 shown in FIG. Fig.18A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front S2 side of the semiconductor substrate 12 via a mask (not shown) to form the groove portion 25. Subsequently, as shown in FIG. Fig.22AAs shown, N-type impurities are ion-implanted from the inside of the groove portion 25 to form an N+ type semiconductor region 51 on the entire side wall surface S4 and the bottom surface of the groove portion 25. Subsequently, similar to Fig.18B In the step shown, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and a semiconductor layer 43 is formed in the groove portion 25 and on the front surface S2 of the semiconductor substrate 12 to continuously cover the entire side wall surface S4 and bottom surface of the groove portion 25 and the front surface S2 of the semiconductor substrate 12. Thereafter, by FIG. 18C to FIG. 18I The steps shown form Fig. 22B The component separation portion 26 is shown. Note that Fig. 22B As shown, the configuration of the second element separation portion 26b formed by this forming method is different from the configuration of the second element separation portion 26b formed by the above-mentioned forming method ( Fig.19 The structure of the second element separation portion 26b in is slightly different.

[0052] (2) In addition, in the third embodiment, the example has been described in which the P-type solid-phase diffusion layer 38 is provided as the P-type layer of the element separation portion 26, but other configurations may be adopted. Fig.23 and Fig.24 As shown, a P-type epitaxial growth layer 52 formed by epitaxial growth while adding a P-type impurity may be provided instead of the P-type solid phase diffusion layer 38. Here, for example, when a layer formed by ion implantation of a P-type impurity from the inside of the groove portion 25 is used instead of the P-type epitaxial growth layer 52, the P-type impurity ions may be implanted into the N-type semiconductor region 23 when the layer is formed. In contrast, when the P-type epitaxial growth layer 52 is used, as shown in FIG. Fig.24 As shown, it is not necessary to mix P-type impurities into the N-type semiconductor region 23 when forming the P-type epitaxial growth layer 52. Therefore, since the PN junction is formed by the N-type semiconductor region 23 with a low P-type impurity concentration and the P-type epitaxial growth layer 52, the potential gradient can be made steeper and the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. Fig.24 In FIG. 1 , a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 and the P type solid phase diffusion layer 38 , and a curve indicating the impurity concentration of the P type is represented by a single-dot chain line.

[0053] A method of forming the element separation portion 26 in the case of adopting such a configuration will be described. FIG. 17A to FIG. 17G In the case of the manufacturing method shown in the figure, similar to the forming method, first, similar to Fig.17A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front surface S2 side of the semiconductor substrate 12 via the mask 40 to form the groove portion 25. Subsequently, as shown in FIG. Fig.25As shown, while adding P-type impurities, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and a P-type epitaxial growth layer 52 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. Fig. 17C The steps shown in FIG. 17D to FIG. 17G The steps shown form Fig.23 The component separation portion 26 is shown.

[0054] In addition, when using FIG. 18A to FIG. 18I In the case of a formation method similar to the formation method of the element separation portion 26 shown in FIG. Fig.18A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front S2 side of the semiconductor substrate 12 via a mask (not shown) to form the groove portion 25. Subsequently, as shown in FIG. Fig.26A As shown, a semiconductor crystal is epitaxially grown while adding a P-type impurity to the side wall surface S4 of the groove portion 25, and a P-type epitaxial growth layer 52 is formed in the groove portion 25 and on the front surface S2 of the semiconductor substrate 12 to continuously cover the entire side wall surface S4 and bottom surface of the groove portion 25 and the front surface S2 of the semiconductor substrate 12. Fig. 18C Follow the steps shown and execute FIG. 18D to FIG. 18I The steps shown are to form Fig.26B The component separation portion 26 is shown. Note that Fig.26B As shown, the configuration of the second element separation portion 26b formed by this forming method is different from the configuration of the second element separation portion 26b formed by the above-mentioned forming method ( Fig.23 The structure of the second element separation portion 26b in is slightly different.

[0055] (3) In addition, for example, Fig. 27 and Fig.28 As shown, it is possible to provide by combining the above-mentioned modifications (1) and (2) Fig.19 The N+ type semiconductor region 51 and Fig.23 As a result, the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. Fig.28 In FIG. 1 , a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23 and the P type solid phase diffusion layer 38 , and a curve indicating the impurity concentration of the P type is represented by a single-dot chain line. A method of forming the element separation portion 26 in the case of adopting such a configuration will be described. FIG. 17A to FIG. 17G In the case of the manufacturing method shown in the figure, similar to the forming method, first, similar to Fig.17AIn the step shown in FIG. 1 , N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front surface S2 side of the semiconductor substrate 12 via the mask 40 to form the groove portion 25. Subsequently, similar to Fig.21 In the step shown in FIG. 1 , N-type impurities are ion-implanted from the inside of the groove portion 25 to form an N+-type semiconductor region 51 on the side wall surface S4 and the bottom surface of the groove portion 25. Fig.29 As shown, while adding P-type impurities, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and a P-type epitaxial growth layer 52 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. Fig. 17C The steps shown are FIG. 17D to FIG. 17G The steps shown form Fig. 27 The component separation portion 26 is shown.

[0056] In addition, when using FIG. 18A to FIG. 18I In the case of a formation method similar to the formation method of the element separation portion 26 shown in FIG. Fig.18A In the step shown in FIG. 1 , N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front surface S2 side of the semiconductor substrate 12 via a mask (not shown) to form the groove portion 25. Subsequently, similar to FIG. Fig.22A In the step shown in FIG. 1 , N-type impurities are ion-implanted from the inside of the groove portion 25 to form an N+-type semiconductor region 51 on the entire side wall surface S4 and the bottom surface of the groove portion 25. Fig. 30A As shown, a semiconductor crystal is epitaxially grown while adding a P-type impurity to the side wall surface S4 of the groove portion 25, and a P-type epitaxial growth layer 52 is formed in the groove portion 25 and on the front surface S2 of the semiconductor substrate 12 to continuously cover the entire side wall surface S4 and bottom surface of the groove portion 25 and the front surface S2 of the semiconductor substrate 12. Fig. 18C Follow the steps shown and execute FIG. 18D to FIG. 18I The steps shown are to form Fig. 30B The component separation portion 26 is shown. Note that Fig. 30B As shown, the configuration of the second element separation portion 26b formed by this forming method is different from the configuration of the second element separation portion 26b formed by the above-mentioned forming method ( Fig. 27 The structure of the second element separation portion 26b in is slightly different.

[0057] <4. Fourth Embodiment: Solid-State Imaging Device> [4-1 Composition of the main parts] Next, a solid-state imaging device 1 according to a fourth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the fourth embodiment is similar to that of Figure 1The structure in the figure will therefore be omitted. Fig.31 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to a fourth embodiment. Fig.32 It is shown in Fig.31 A diagram showing a cross-sectional configuration of the solid-state imaging device 1 when the region J in FIG. Fig.31 and Fig.32 In, with Fig.12 and Fig.13 The corresponding parts are denoted by the same figure marks and repeated descriptions are omitted.

[0058] like Fig.31 and Fig.32 As shown, the fourth embodiment is different from the third embodiment in that an N-type epitaxial growth layer 53 and a P-type epitaxial growth layer 54 are used instead of Fig.12 The P-type solid phase diffusion layer 38 shown in FIG. An N-type epitaxial growth layer 53 and a P-type epitaxial growth layer 54 are sequentially stacked on the side wall surface S4 of the trench portion 25 . The N-type epitaxial growth layer 53 is a layer disposed in the groove portion 25 and covering the side wall surface S4 of the groove portion 25. As the N-type epitaxial growth layer 53, for example, an epitaxial growth layer formed by epitaxial growth while adding N-type impurities can be used. By using such an epitaxial growth layer, as Fig.31 As shown, the P-type impurity concentration of the N-type epitaxial growth layer 53 is 1e16 / cm 3 By reducing the impurity concentration of the P type, the N type epitaxial growth layer 53 can make the potential gradient caused by the PN junction between the N type epitaxial growth layer 53 and the P type epitaxial growth layer 54 steeper. Therefore, the saturation charge amount Qs of the photoelectric conversion unit 21 can be increased. Fig.31 , a curve indicating the impurity concentration of the N type is represented by a dotted line overlapping the N type semiconductor region 23, the N type epitaxial growth layer 53 and the P type epitaxial growth layer 54, and a curve indicating the impurity concentration of the P type is represented by a single-dot chain line.

[0059] The P-type epitaxial growth layer 54 is a layer arranged in the space inside the groove portion 25 covered by the N-type epitaxial growth layer 53 and in contact with the N-type epitaxial growth layer 53. As a result, the P-type epitaxial growth layer 54 is stacked on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the groove portion 25, and forms a PN junction with the N-type epitaxial growth layer 53. As the P-type epitaxial growth layer 54, for example, an epitaxial growth layer formed by epitaxial growth while adding a P-type impurity can be used. By using such an epitaxial growth layer, as Fig.31 As shown, the N-type impurity concentration of the P-type epitaxial growth layer 54 is 1e16 / cm 3By reducing the N-type impurity concentration, the P-type epitaxial growth layer 54 can make the potential gradient caused by the PN junction steeper. Therefore, it is possible to further suppress the decrease in the saturation charge amount Qs of the photoelectric conversion unit 21. Note that Fig.12 Shown omitted Figure 8 The situation of the fixed charge film 13 is shown.

[0060] [4-2 Method for manufacturing solid-state imaging device] Next, a method of manufacturing the solid-state imaging device 1 according to the fourth embodiment will be described. In adopting FIG. 17A to FIG. 17G The manufacturing method shown is similar to the manufacturing method of the case, similar to Fig.17A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front surface S2 side of the semiconductor substrate 12 via the mask 40 to form the groove portion 25. Subsequently, as shown in FIG. Fig.33A As shown, while adding N-type impurities, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the groove portion 25, and an N-type epitaxial growth layer 53 is formed in the groove portion 25 to cover the side wall surface S4 and the bottom surface of the groove portion 25. Fig.33B As shown, a semiconductor crystal is epitaxially grown while adding a P-type impurity to a surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the groove portion 25 (hereinafter, also referred to as a "center side surface S13"), and a P-type epitaxial growth layer 54 is formed in the groove portion 25 to cover the center side surface S13 of the N-type epitaxial growth layer 53. Fig. 17C The steps shown in FIG. 17D to FIG. 17G The steps shown form Fig.31 The component separation section 26 is shown. Then, as Fig.31 As shown in FIG. 1 , an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, a Fig.31 The solid-state imaging device 1 is shown.

[0061] In addition, in adopting FIG. 18A to FIG. 18I In the case of a manufacturing method similar to the manufacturing method of the solid-state imaging device 1 shown in FIG. 1 , first, similar to Fig.18A In the step shown, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the front S2 side of the semiconductor substrate 12 via a mask (not shown) to form the groove portion 25. Subsequently, as shown in FIG. Fig.34AAs shown, while adding N-type impurities to the side wall surface S4 of the groove portion 25, etc., a semiconductor crystal is epitaxially grown, and an N-type epitaxial growth layer 53 is formed in the groove portion 25 and on the front surface S2 of the semiconductor substrate 12 to continuously cover the entire side wall surface S4 and bottom surface of the groove portion 25 and the front surface S2 of the semiconductor substrate 12. Subsequently, as Fig.34B As shown, while adding P-type impurities, a semiconductor crystal is epitaxially grown on the surface of the N-type epitaxial growth layer 53 on the center side of the width direction of the groove portion 25 (center side surface S13), and a P-type epitaxial growth layer 54 is formed in the groove portion 25 to continuously cover the entire center side surface S13 of the N-type epitaxial growth layer 53. Fig. 18C Follow the steps shown and execute FIG. 18D to FIG. 18I The steps shown to form Fig.34C The component separation portion 26 is shown. Note that Fig.34C As shown, the structure of the second element separation portion 26b formed by this manufacturing method is different from the structure of the second element separation portion 26b formed by the above-mentioned manufacturing method ( Fig.31 The second element separation portion 26b in the embodiment is slightly different. Fig.31 As shown in FIG. 1 , an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, a Fig.31 The solid-state imaging device 1 is shown.

[0062] [4-3 Modification Example] (1) Note that the present technology can be applied to all light detection devices, including a distance measuring sensor which is also called a time-of-flight (ToF) sensor and measures distance, in addition to the solid-state imaging device 1 as an image sensor described above. A distance measuring sensor is a sensor that emits irradiation light toward an object, detects reflected light (i.e., irradiation light reflected from the surface of the object), and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. As a light receiving pixel structure of the distance measuring sensor, the structure of the above-mentioned pixel 8 can be adopted.

[0063] <5. Fifth Implementation Example: Application Example of Electronic Equipment> The technology according to the present disclosure (the present technology) can be applied to various electronic devices. Fig.35 This is a diagram showing a schematic configuration example of an imaging device (video camera, digital camera, etc.) as an electronic device to which the present technology is applied. like Fig.35As shown, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (the solid-state imaging device 1 according to the first embodiment), a digital signal processor (DSP) circuit 1003, a frame memory 1004, a monitor 1005, and a memory 1006. The DSP circuit 1003, the frame memory 1004, the monitor 1005, and the memory 1006 are connected to each other via a bus 1007.

[0064] The lens group 1001 guides incident light (image light) from a subject to the solid-state imaging device 1002 , and forms an image on a light incident surface (pixel region) of the solid-state imaging device 1002 . The solid-state imaging device 1002 includes the CMOS image sensor of the first embodiment described above and converts the light quantity of incident light imaged on the light incident surface by the lens group 1001 into an electrical signal in units of pixels and supplies the electrical signal to the DSP circuit 1003 as a pixel signal. The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state imaging device 1002. Then, the DSP circuit 1003 supplies the image signal of each frame subjected to the image processing to the frame memory 1004 to temporarily store the image signal in the frame memory 1004. The monitor 1005 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays an image (moving image) of a subject based on a pixel signal of each frame temporarily stored in the frame memory 1004 . The memory 1006 includes a DVD, a flash memory, etc. The memory 1006 reads and records the pixel signal of each frame temporarily stored in the frame memory 1004 .

[0065] Note that the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, and can also be applied to other electronic devices. In addition, the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002, but other configurations can also be adopted. For example, other light detection devices to which the present technology is applicable, such as the solid-state imaging device 1 according to each of the second to fourth embodiments and the solid-state imaging device 1 according to each modified example of the second to fourth embodiments, etc. can be used.

[0066] Note that the present disclosure may also have the following configurations. (1) A light detection device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion, comprising a groove portion formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer arranged in the groove portion and covering the side wall surface of the groove portion, and a functional layer arranged in the space inside the groove portion covered by the semiconductor layer, wherein The photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, The semiconductor layer has a 1e16 / cm 3 The following P-type impurity concentrations, and The functional layer is a layer that induces holes on the functional layer side of the semiconductor layer. (2) The light detection device according to (1), wherein: The N-type semiconductor region has a peak of N-type impurity concentration at an interface between the semiconductor layer and the N-type semiconductor region. (3) The light detection device according to (1) or (2), wherein: The functional layer is a fixed charge film that is disposed along a surface of the semiconductor layer that is farther from the sidewall surface of the groove portion and has negative fixed charges. (4) The light detection device according to (1) or (2), wherein: The functional layer is a conductor portion, the conductor portion is arranged along a surface of the semiconductor layer that is farther from a side wall surface of the trench portion, and a negative bias voltage is applied to the conductor portion. (5) The light detection device according to (4), wherein: The conductor portion covers the side wall surface of the groove portion so that the side wall has a groove-shaped space formed by the conductor portion inside the groove portion. (6) The light detection device according to (4), wherein: The semiconductor layer is a semiconductor layer formed at a different timing from that of the semiconductor substrate. (7) The light detection device according to (4), wherein: The semiconductor layer is an epitaxial growth layer. (8) A light detection device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate and a P-type solid phase diffusion layer arranged in the groove portion and covering the side wall surface of the groove portion, wherein: The photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer, and The P-type solid phase diffusion layer has a 1e16 / cm3 The impurity concentration of N type is as follows. (9) A light detection device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion, comprising a groove portion formed between the photoelectric conversion units in the semiconductor substrate, an N-type epitaxial growth layer arranged in the groove portion and covering the side wall surface of the groove portion, and a P-type epitaxial growth layer arranged in the space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein: The N-type epitaxial growth layer has a thickness of 1e16 / cm 3 The following P-type impurity concentrations, and The P-type epitaxial growth layer has a thickness of 1e16 / cm 3 The impurity concentration of N type is as follows. (10) An electronic device comprising a light detecting device, the light detecting device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, which comprises a groove portion formed in the semiconductor substrate between the photoelectric conversion units, a semiconductor layer arranged in the groove portion and covering the sidewall surface of the groove portion, and a functional layer arranged in a space inside the groove portion covered by the semiconductor layer, wherein the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, and the semiconductor layer has a 1e16 / cm 3 The impurity concentration of the P type is below, and the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer. (11) An electronic device, comprising a light detecting device, the light detecting device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, comprising a groove portion formed in the semiconductor substrate between the photoelectric conversion units and a P-type solid phase diffusion layer disposed in the groove portion and covering a side wall surface of the groove portion, wherein the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer, and the P-type solid phase diffusion layer has a 1e16 / cm 3 The impurity concentration of N type is as follows. (12) An electronic device, comprising a light detecting device, the light detecting device comprising: a semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, comprising a groove portion formed in the semiconductor substrate between the photoelectric conversion units, an N-type epitaxial growth layer arranged in the groove portion and covering the sidewall surface of the groove portion, and a P-type epitaxial growth layer arranged in a space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein the N-type epitaxial growth layer has a P-type epitaxial growth layer having ...3 The P-type impurity concentration is below 1e16 / cm 3 The impurity concentration of N type is as follows. (13) A method for manufacturing a light detection device, the method comprising: a step of forming a groove portion in a semiconductor substrate; The impurity concentration of 1e16 / cm is formed on the side wall surface of the groove by epitaxial growth. 3 following the step of epitaxially growing the layer; and A step of doping P-type impurities from within the trench portion into the epitaxial growth layer by solid phase diffusion. (14) A method for manufacturing a light detection device, the method comprising: a step of forming a groove portion in a semiconductor substrate; While adding N-type impurities, a P-type impurity concentration of 1e16 / cm is formed on the sidewall surface of the groove portion by epitaxial growth. 3 The following steps of growing an N-type epitaxial layer; and While adding the P-type impurities, an N-type impurity concentration of 1e16 / cm is formed on the surface of the N-type epitaxial growth layer on the center side of the width direction of the groove portion by epitaxial growth. 3 The following are the steps for growing the P-type epitaxial layer. Reference numerals list

[0067] 1Solid-state imaging device 2 pixel area 3 Vertical drive circuit 4 columns of signal processing circuit 5Horizontal drive circuit 6 Output Circuit 7. Control Circuit 8 pixels 9 pixel drive lines 10 vertical signal lines 11 horizontal signal lines 12Semiconductor substrate 13 Fixed Charge Membrane 14 Insulation film 15 shading film 16 Flattening film 17 Light receiving layer 18 Color filter layers 19Microlens array 20 wiring layers 21 Photoelectric conversion unit 22P type semiconductor region 23N-type semiconductor region 24P type semiconductor region 25 Groove 26 Component separation unit 27Semiconductor layer 27a Hole inducing layer 28 color filters 29 Microlenses 30 masks 32 doped polysilicon 33 Insulation film 34 Conductor 35 Conductor 37Semiconductor layer 38P solid phase diffusion layer 39 Insulation Materials 40 Mask 41 Silicon nitride film 42 Silicon oxide film 43Semiconductor layer 44 Silicon oxide 45 doped polysilicon 46 Insulation Materials 47 Mask 48 Silicon nitride film 49 Silicon oxide film 50 Groove 51N+ type semiconductor area 52P epitaxial growth layer 53N epitaxial growth layer 54P epitaxial growth layer 55P type semiconductor region 1000 Imaging Device 1001 Lens Group 1002 Solid-state imaging device 1003 DSP Circuit 1004 Frame Memory 1005 Monitor 1006 Memory 1007 Bus

Claims

1. A light detection device, comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion, comprising a groove portion formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer arranged in the groove portion and covering the side wall surface of the groove portion, and a functional layer arranged in the space inside the groove portion covered by the semiconductor layer, wherein The photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, The semiconductor layer has a 1e16 / cm 3 The following P-type impurity concentrations, and The functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.

2. The light detection device according to claim 1, wherein: The N-type semiconductor region has a peak of N-type impurity concentration at an interface between the semiconductor layer and the N-type semiconductor region.

3. The light detection device according to claim 1, wherein: The functional layer is a fixed charge film that is disposed along a surface of the semiconductor layer that is farther from the sidewall surface of the groove portion and has negative fixed charges.

4. The light detection device according to claim 1, wherein: The functional layer is a conductor portion, the conductor portion is arranged along a surface of the semiconductor layer that is farther from a side wall surface of the trench portion, and a negative bias voltage is applied to the conductor portion.

5. The light detection device according to claim 4, wherein: The conductor portion covers the side wall surface of the groove portion so that the side wall has a groove-shaped space formed by the conductor portion inside the groove portion.

6. The light detection device according to claim 1, wherein: The semiconductor layer is a semiconductor layer formed at a different timing from that of the semiconductor substrate.

7. The light detection device according to claim 6, wherein: The semiconductor layer is an epitaxial growth layer.

8. A light detection device, comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate and a P-type solid phase diffusion layer arranged in the groove portion and covering the side wall surface of the groove portion, wherein: The photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer, and The P-type solid phase diffusion layer has a 1e16 / cm 3 The impurity concentration of N type is as follows.

9. A light detection device, comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and An element separation portion, comprising a groove portion formed between the photoelectric conversion units in the semiconductor substrate, an N-type epitaxial growth layer arranged in the groove portion and covering the side wall surface of the groove portion, and a P-type epitaxial growth layer arranged in the space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein: The N-type epitaxial growth layer has a thickness of 1e16 / cm 3 The following P-type impurity concentrations, and The P-type epitaxial growth layer has a thickness of 1e16 / cm 3 The impurity concentration of N type is as follows.

10. An electronic device, comprising a light detection device, the light detection device comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate, a semiconductor layer arranged in the groove portion and covering the side wall surface of the groove portion, and a functional layer arranged in the space inside the groove portion covered by the semiconductor layer, wherein the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the semiconductor layer, and the semiconductor layer has a 1e16 / cm 3 The impurity concentration of the P type is below, and the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.

11. An electronic device, comprising a light detection device, the light detection device comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate and a P-type solid diffusion layer arranged in the groove portion and covering the side wall surface of the groove portion, wherein the photoelectric conversion unit has an N-type semiconductor region in a region in contact with the P-type solid diffusion layer, and the P-type solid diffusion layer has a 1e16 / cm 3 The impurity concentration of N type is as follows.

12. An electronic device, comprising a light detection device, the light detection device comprising: A semiconductor substrate having a plurality of photoelectric conversion units formed thereon; and an element separation portion, which includes a groove portion formed between the photoelectric conversion units in the semiconductor substrate, an N-type epitaxial growth layer arranged in the groove portion and covering the side wall surface of the groove portion, and a P-type epitaxial growth layer arranged in the space inside the groove portion covered by the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, wherein the N-type epitaxial growth layer has a 1e16 / cm 3 The P-type impurity concentration is below 1e16 / cm 3 The impurity concentration of N type is as follows.

13. A method for manufacturing a light detection device, the method comprising: a step of forming a groove portion in a semiconductor substrate; The impurity concentration of 1e16 / cm is formed on the side wall surface of the groove by epitaxial growth. 3 The following steps of epitaxial growth layer; and A step of doping P-type impurities from within the trench portion into the epitaxial growth layer by solid phase diffusion.

14. A method for manufacturing a light detection device, the method comprising: a step of forming a groove portion in a semiconductor substrate; While adding N-type impurities, a P-type impurity concentration of 1e16 / cm is formed on the sidewall surface of the groove portion by epitaxial growth. 3 The following steps of growing an N-type epitaxial layer; and While adding the P-type impurities, an N-type impurity concentration of 1e16 / cm is formed on the surface of the N-type epitaxial growth layer on the center side of the width direction of the groove portion by epitaxial growth. 3 The following are the steps for growing the P-type epitaxial layer.

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