A method for determining the frequency of a clock signal and a chip

Abstract

The present application discloses a method and a chip for determining the frequency of a clock signal. The method includes: in response to a frequency detection instruction for a signal of a clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulative counter to start counting the signal of a reference clock; if it is determined that a counting end condition is satisfied, controlling the linear feedback shift register and the accumulative counter to stop counting, and determining the frequency of the signal of the clock to be measured based on a first count value of the linear feedback shift register and a second count value of the accumulative counter. In this way, since the feedback logic circuit structure of the linear feedback shift register is simple and the feedback logic circuit has a simple processing logic, and the processing speed of the counting signal is much faster than that of an ordinary accumulative counter for the counting signal, the counting of the linear feedback shift register is faster, and its counting frequency can be higher than the frequency of the signal of the clock to be measured, thereby realizing the effective detection of a high-frequency clock signal.

Description

Technical Field

[0001] This application relates to the technical field of frequency determination, and in particular, to a method for determining the frequency of a clock signal and a chip. Background Art

[0002] Frequency detection is of great significance in the field of chip security. Physical chips are often affected by unstable environments, resulting in errors in the chip system. In cryptographic chips, these unstable factors are often intentional actions of attackers to attack the chip entity in order to obtain the key information in the chip. One of the common attack methods includes frequency attacks. Using an abnormal frequency can cause the original program to skip specific operations, and the attacker can further obtain the key information. To protect against frequency attacks, a frequency meter is usually used. A frequency meter is an instrument for measuring the frequency of a signal, which can accurately determine the frequencies of various periodic signals such as electrical signals and optical signals, and it has an important position in the field of electronic measurement. Currently, frequency meters based on digital circuits have achieved high-precision and high-stability frequency measurements. Signal spectrum analysis based on frequency meters has also extended to more application scenarios, including communication, radar, etc. According to the results of the frequency meter, abnormal frequencies can be blocked, so that the system does not work at abnormal frequencies, achieving the purpose of information protection.

[0003] Frequency measurement requires a wide measurement range and high test accuracy, and the frequencies used in frequency attacks often have the characteristics of extremely high frequencies. Therefore, frequency measurement needs to be adapted to high-frequency environments. Currently, there are detection methods based on analog circuits and frequency detection methods based on digital circuits. The analog frequency meter used in the detection method based on analog circuits measures the frequency by charging and discharging a capacitor. The frequency of the clock signal is calculated by detecting the relationship between the number of capacitor charge and discharge times and time. This method has low accuracy.

[0004] The frequency measurement accuracy of digital circuits is higher than that of analog circuit measurements, but the existing digital circuit measurement methods are also affected by circuit process conditions and are difficult to measure high-frequency clocks. Traditional counters (such as progressive addition counters) trigger the counter value to increase by 1 every clock cycle. As the bit width increases, the circuit complexity will increase, which will in turn affect the counting frequency of the progressive addition counter. When the clock frequency is higher than the counting frequency of its counter, the counter cannot capture some pulse signals of the clock signal and can no longer count effectively. Therefore, the frequency of high-frequency clocks cannot be detected. Summary of the Invention

[0005] Embodiments of this application provide a method for determining the frequency of a clock signal and a chip, and this method can effectively detect the frequency of a high-frequency clock signal.

[0006] The technical solution of this application is implemented as follows:

[0007] In a first aspect, the present application provides a method for determining the frequency of a clock signal, including:

[0008] In response to a frequency detection instruction for the signal of the clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulative counter to start counting the signal of a reference clock; wherein, the bit width of the linear feedback shift register is greater than a counter bit width threshold, and the circuit complexity of the linear feedback shift register is less than a circuit complexity threshold;

[0009] If it is determined that the counting end condition is satisfied, controlling the linear feedback shift register and the accumulative counter to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulative counter;

[0010] Based on the first count value and the second count value, determining the frequency of the signal of the clock to be measured.

[0011] In a second aspect, the present application provides a chip, including: a control unit and a processing unit, wherein,

[0012] The control unit is configured to, in response to a frequency detection instruction for the signal of the clock to be measured corresponding to the chip, control a linear feedback shift register to start counting the signal of the clock to be measured, and control an accumulative counter to start counting the signal of a reference clock; wherein, the bit width of the linear feedback shift register is greater than a counter bit width threshold, and the circuit complexity of the linear feedback shift register is less than a circuit complexity threshold;

[0013] The control unit is further configured to, if it is determined that the counting end condition is satisfied, control the linear feedback shift register and the accumulative counter to stop counting, and obtain a first count value of the linear feedback shift register and a second count value of the accumulative counter;

[0014] The processing unit is configured to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

[0015] In an embodiment of the present application, a method for determining the frequency of a clock signal is provided, including: in response to a frequency detection instruction for a signal of a clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulation counter to start counting the signal of a reference clock; if it is determined that a counting end condition is satisfied, controlling the linear feedback shift register and the accumulation counter to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulation counter; based on the first count value and the second count value, determining the frequency of the signal of the clock to be measured. In this way, since the feedback logic circuit structure of the linear feedback shift register is simple, the feedback logic circuit has a simple processing logic, and the processing speed of the counting signal is much faster than that of an ordinary accumulation counter for the counting signal. Therefore, the linear feedback shift register counts faster, and its counting frequency can be higher than the frequency of the signal of the clock to be measured, thereby realizing effective detection of a high-frequency clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic flowchart of a method for determining the frequency of a clock signal provided by an embodiment of the present application;

[0017] Figure 2 is a schematic flowchart of a frequency detection method based on counting of a linear feedback shift register provided by an embodiment of the present application;

[0018] Figure 3 is a schematic structural diagram of a composition of a frequency detection system based on counting of a linear feedback shift register provided by an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of a frequency detection process of a frequency detection system based on counting of a linear feedback shift register provided by an embodiment of the present application;

[0020] Figure 5 is a schematic structural diagram of a composition of a chip provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to be able to understand the features and technical content of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are only for reference and illustration purposes and are not used to limit the embodiments of the present application.

[0022] In the related art, a frequency detection method based on a digital circuit usually uses a clock with stable frequency and high precision, such as a quartz crystal oscillator clock as a reference clock. For frequency measurement, at the same moment, the reference clock and the clock to be measured start counting simultaneously. After the same period of clock, the counts of the two are respectively (the count value of the reference clock within the same period of time) and (During the same period of time, the counting value of the clock to be measured), the frequency relationship can be obtained based on the counting value relationship: Based on this frequency relationship, the frequency of the clock to be measured can be obtained As shown in formula (1):

[0023] (1);

[0024] Compare the frequency of the clock to be measured with the frequency threshold to determine whether the current frequency is abnormal. As shown in the above formula, the accuracy of the measured frequency is related to the counting size during this period related. The larger it is, the higher the accuracy of the measured clock frequency (based on formula (1), the larger the denominator, the higher the accuracy of the clock frequency to be measured (fine). For example, a frequency accuracy represented by one hundredth is higher than that represented by one third). This means that high-precision measurement requires a large-bit-width counter to achieve, but a large-bit-width counter will be limited by high-frequency effects. The traditional progressive addition counter will increase the circuit complexity while increasing the bit width. The increase in circuit complexity will lead to a decrease in the counting frequency. When the clock frequency is higher than the counting frequency of its counter, the counter can no longer count effectively. Therefore, ordinary measuring meters have limited applications in high-frequency detection.

[0025] Based on the problems in the related art, the present application provides a method for determining the frequency of a clock signal. This method can be applied to the frequency detection scenario of the clock signal of a cryptographic chip, such as Figure 1 shown, the method includes:

[0026] S101. In response to a frequency detection instruction for the signal of the clock to be measured, control the linear feedback shift register to start counting the signal of the clock to be measured, and control the accumulative counter to start counting the signal of the reference clock.

[0027] It should be noted that the bit width of the linear feedback shift register can be greater than the counter bit width threshold, that is, the bit width of the linear feedback shift register is relatively large. Among them, the bit width of the linear feedback shift register can be the number of binary digits used to store the counting value in the linear feedback shift register, and the counter bit width threshold can be a preset large bit width value, such as 15, 18, 20, etc.

[0028] In some embodiments, the circuit structure of the linear feedback shift register is different from that of the accumulative counter. The bit width of the accumulative counter can be less than the counter bit width threshold, the bit width of the linear feedback shift register can be greater than the bit width of the accumulative counter, and the circuit complexity of the linear feedback shift register is less than that of the accumulative counter.

[0029] In some embodiments, since the bit width of the linear feedback shift register is greater than the counter bit width threshold, the bit width of the linear feedback shift register is relatively large, and it has a wide measurement range. It can count high-frequency clock signals to achieve high-precision detection of clock signals.

[0030] In some embodiments, the clock to be measured can be the internal clock of the cryptographic chip or the external clock of the cryptographic chip; the reference clock can be a clock with stable frequency and high precision. For example, the reference clock can be a quartz crystal oscillator clock. The signals of the clock to be measured and the reference clock can both be periodic signals, such as square wave signals. The linear feedback shift register can be used to count the period of the signal of the clock to be measured, and the accumulative counter can be used to count the period of the signal of the reference clock.

[0031] In some embodiments, the frequency detection instruction for the signal of the clock to be measured can be an instruction for detecting the frequency of the signal of the clock to be measured. This frequency detection instruction can be triggered by the user through the human-machine interface to detect whether the frequency of the signal of the clock to be measured is abnormal. When it is determined that the frequency detection instruction for the signal of the clock to be measured is received, the linear feedback shift register and the accumulative counter can be controlled to start counting simultaneously.

[0032] S102: If it is determined that the counting end condition is satisfied, control the linear feedback shift register and the accumulative counter to stop counting, and obtain the first count value of the linear feedback shift register and the second count value of the accumulative counter.

[0033] It should be noted that the counting end condition can be a condition for indicating that the linear feedback shift register and the accumulative counter need to stop counting. The counting end condition can be triggered by the counting situation of the linear feedback shift register. For example, the counting end condition can be that the count value of the linear feedback shift register reaches a preset count value, and this preset count value can be less than or equal to the maximum count value of the linear feedback shift register.

[0034] In some embodiments, when it is determined that the counting end condition is satisfied, the linear feedback shift register and the accumulative counter can be controlled to stop counting simultaneously. The count value when the linear feedback shift register stops counting is determined as the first count value, and the count value when the accumulative counter stops counting is determined as the second count value.

[0035] In some embodiments, since the signal of the clock under test and the signal of the reference clock may be different, the circuit structures of the linear feedback shift register and the accumulative counter are different, the bit widths of the linear feedback shift register and the accumulative counter are different, and the circuit complexities of the linear feedback shift register and the accumulative counter are different. Therefore, the first count value obtained by counting the clock under test with the linear feedback shift register and the second count value obtained by counting the reference clock with the accumulative counter may also be different.

[0036] S103. Determine the frequency of the signal of the clock under test based on the first count value and the second count value.

[0037] In some embodiments, when the linear feedback shift register is a linear feedback shift register, the linear feedback shift register may not be the true count value of the signal of the clock under test; when the accumulative counter is an accumulative counter, the second count value may be the true count value of the signal of the reference clock. After obtaining the first count value and the second count value, the second count value can be converted based on the first count value and the maximum count value of the linear feedback shift register, so as to obtain the true count value of the signal of the clock under test, and the frequency of the signal of the clock under test can be determined based on the true count value and the counting duration.

[0038] In the embodiments of the present application, in response to a frequency detection instruction for a clock signal, control the linear feedback shift register to start counting the signal of the clock under test, and control the accumulative counter to start counting the signal of the reference clock; if it is determined that the counting end condition is satisfied, control the linear feedback shift register and the accumulative counter to stop counting, and obtain the first count value of the linear feedback shift register and the second count value of the accumulative counter; determine the frequency of the signal of the clock under test based on the first count value and the second count value. In this way, since the feedback logic circuit structure of the linear feedback shift register is simple, the feedback logic circuit has a simple processing logic, and the processing speed of the counting signal is much faster than that of an ordinary accumulative counter for the counting signal, the counting of the linear feedback shift register is faster, and its counting frequency can be higher than the frequency of the signal of the clock under test, so as to effectively detect a high-frequency clock signal.

[0039] In some embodiments of the present application, during the process of determining whether the counting end condition is satisfied, the first sequence state of the linear feedback shift register can be obtained; based on the preset correspondence relationship between the sequence state and the count value of the linear feedback shift register, determine the count value corresponding to the first sequence state; if the count value corresponding to the first sequence state is a candidate count value, determine that the counting end condition is satisfied.

[0040] In some embodiments, the first sequence state may be a combined state presented by the numerical values of each binary bit in a linear feedback shift register. Exemplarily, when the bit width of the linear feedback shift register is 16, the first sequence state may be a sequence composed of 16 binary numerical values (0 or 1) corresponding to 16 binary bits, such as 0000010010000001. The first sequence state may reflect the counting situation of the signal of the linear feedback shift register for the clock under test, and one sequence state corresponds to one count value.

[0041] In some embodiments, since the number of signal cycles of the clock under test is continuously increasing and the corresponding count values are also continuously changing, the first sequence state of the linear feedback shift register is also continuously changing. The first sequence state of the linear feedback shift register can be continuously obtained, or the sequence state of the linear feedback shift register can be obtained once every preset time interval.

[0042] In some embodiments, the preset correspondence between the sequence state of the linear feedback shift register and the count value can be established in advance. One sequence state corresponds to one count value. After the binary sequence corresponding to one sequence state is converted into a decimal number, the decimal number may be different from the corresponding count value. The linear feedback shift register can be tested in advance to determine the true count values corresponding to different sequence states, so as to obtain the correspondence between the sequence state of the linear feedback shift register and the count value.

[0043] In some embodiments, after obtaining the first sequence state of the linear feedback shift register, the first sequence state can be matched with each sequence state in the preset correspondence to obtain the count value corresponding to the first sequence state.

[0044] In some embodiments, the candidate count value may be 2 N , where N is an integer greater than or equal to 0, and the candidate count value is less than the total number of sequence states of the linear feedback shift register. For example, the candidate count value may be 1, 2, 4, etc. Exemplarily, if the bit width of the linear feedback shift register is 22 and the total number of sequence states of the linear feedback shift register is 4194303, the candidate count value may be 1, 2, 1024, 16384, etc.

[0045] In some embodiments, the candidate count value may include one or more, and the candidate count value can be determined by the bit width of the linear feedback shift register. For example, if the bit width of the linear feedback shift register is 22, the candidate count value can be in accordance with 2 nIncrement in a manner of (n <= 22) times. When n = 2, the candidate count value can increment in a manner of 4 times, so the candidate count value can be 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, 262144, 1048576.

[0046] In some embodiments, one or more candidate count values can be determined according to the bit width of the linear feedback shift register. After that, when it is determined that the count value corresponding to the first sequence state is the same as any one of the candidate count values, it can be determined that the counting end condition is satisfied, and the counting of the linear feedback shift register and the accumulative counter is stopped.

[0047] It can be understood that since the candidate count value is 2 N , N is a non - negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register. Therefore, when the count value corresponding to the first sequence state of the obtained linear feedback shift register is the candidate count value, it can be determined that the counting end condition is satisfied, thereby improving the efficiency of clock signal frequency detection.

[0048] In some embodiments of the present application, the process of creating the preset correspondence relationship between the sequence state and the count value of the linear feedback shift register may include: testing the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and the reference count value corresponding to the reference sequence state; creating the preset correspondence relationship between the sequence state and the count value of the linear feedback shift register based on each reference sequence state and the corresponding reference count value.

[0049] It should be noted that the number of reference sequence states can be determined by the bit width of the linear feedback shift register. For example, if the bit width of the linear feedback shift register is M, the corresponding number of reference sequence states can be 2 M - 1.

[0050] In some embodiments, one kind of sequence state corresponds to one kind of reference count value. The reference count values corresponding to different reference sequence states can be the actual count values corresponding to the sequence states. During the process of testing the linear feedback shift register, record the reference count value corresponding to each reference sequence state, and create the preset correspondence relationship between the sequence state and the count value of the linear feedback shift register according to the one - to - one correspondence relationship between each reference sequence state and the corresponding reference count value.

[0051] In some embodiments, the preset correspondence between the sequence state and the count value of the linear feedback shift register can be reflected in the form of a preset correspondence table, in which a reference sequence state corresponds to a reference count value. In addition, after creating the preset correspondence between the sequence state and the count value of the linear feedback shift register, the preset correspondence table can be stored. During the storage of the preset correspondence table, the reference sequence state and the corresponding reference count value can be stored as an entry.

[0052] It can be understood that by testing the linear feedback shift register, obtaining each reference sequence state and the corresponding reference count value of the linear feedback shift register, and creating a preset correspondence between the sequence state and the count value of the linear feedback shift register based on the reference sequence state and the corresponding reference count value, it is convenient to quickly determine the true count value of the linear feedback shift register based on this preset correspondence during the subsequent process of counting the signal of the clock to be measured.

[0053] In some embodiments of the present application, the candidate count values corresponding to the linear feedback shift register may include multiple, and each candidate count value and the number of candidate count values can be determined in advance. During the process of determining each candidate count value, the maximum count value and the bit width of the linear feedback shift register can be obtained; based on the maximum count value and the bit width, each candidate count value of the linear feedback shift register can be determined.

[0054] In some embodiments, the maximum count value of the linear feedback shift register can be determined by the bit width of the linear feedback shift register. The bit width of the linear feedback shift register can be determined before it leaves the factory, and the bit widths of different linear feedback shift registers are different.

[0055] In some embodiments, multiple candidate count values can be determined according to the maximum count value and the bit width of the linear feedback shift register. Exemplarily, if the bit width of the linear feedback shift register is 20, then the corresponding maximum count value is 2 20 -1 = 1048575, since 2 20 = 4 10 Therefore, 10 candidate count values can be set in increments of 4 times, and each candidate count value is 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, 262144. Here, the bit width of the linear feedback shift register, the increment method of the candidate count values, and the candidate count values are only exemplary descriptions, and the present application does not limit this.

[0056] It can be understood that according to the maximum count value and bit width of the linear feedback shift register, each candidate count value of the linear shift register is determined. When it is determined that the count value of the linear feedback shift register reaches the candidate count value, the counting can be stopped, and the frequency of the clock signal to be measured can be detected, avoiding determining each count value corresponding to the clock signal to be measured, thereby improving the efficiency of frequency detection.

[0057] In some embodiments of the present application, in response to a frequency detection instruction for the signal of the clock to be measured, the linear feedback shift register is controlled to start counting the signal of the clock to be measured, and the accumulative counter is controlled to start counting the signal of the reference clock, that is, after step S101, if the count value of the linear feedback shift register reaches the first value, the detection of each candidate count value is started to determine whether the count value corresponding to the linear feedback shift register is the same as any one of the candidate count values.

[0058] It should be noted that the first value is 1 / Q of the maximum count value of the accumulative counter of the linear feedback shift register. Q can be preset, and Q is an integer greater than 1. For example, Q can be 1 / 5, 1 / 8, etc. Q can also be determined according to the increasing multiple of the candidate count value. Q can be greater than or equal to the increasing multiple. For example, if the increasing multiple of each candidate count value is 4, then Q can be 5, 6, 7, etc.

[0059] In some embodiments, starting the detection of each candidate count value can be to determine whether the current count value of the linear feedback shift register is the same as the candidate count value, that is, starting from the time when the count value of the accumulative counter reaches the first value, the real-time count value of the linear feedback shift register is compared with each candidate count value.

[0060] In some embodiments, during the process of starting the accumulative counter to count the signal of the reference clock, the actual count value of the accumulative counter can be compared with the size of the first value to determine whether the actual count value of the accumulative counter reaches the first value. When it is determined that it reaches the first value, the detection of the candidate count value of the linear feedback shift register can be started, and when it is determined that the real-time count value of the linear feedback shift register is the same as any one of the candidate count values, the counting is stopped.

[0061] It can be understood that since the first value is 1 / Q of the maximum count value of the accumulative counter of the linear feedback shift register, therefore, when the count value of the accumulative counter reaches the first value, starting the detection of each candidate count value can ensure that the detection of the candidate count value is completed without exceeding the maximum count value of the accumulative counter, and make the counting as long as possible.

[0062] In some embodiments of the present application, based on the first count value and the second count value, the frequency of the signal of the clock to be measured is determined. That is, step S103 can be implemented through the following steps S1031 to S1033, and each step is described separately below.

[0063] S1031. Based on the first count value and the maximum count value of the linear feedback shift register, determine the first conversion coefficient.

[0064] In some embodiments, the first count value can be the actual count value determined according to the sequence state of the linear feedback shift register. The first count value is less than the maximum count value of the linear feedback shift register. The maximum value of the linear feedback shift register and the first count value can be divided to obtain the first conversion coefficient, that is, the first count value can be divisible by the maximum value of the linear feedback shift register.

[0065] Exemplarily, if the bit width of the linear feedback shift register is 22, the maximum count value of the linear feedback shift register is 2 22 -1 = 4194303. If the first count value is 4, the first conversion coefficient is 1048575; if the first count value is 16, the first conversion coefficient is 262144. The maximum value of the linear feedback shift register and the first count value here are only exemplary descriptions, and the present application does not limit this.

[0066] S1032. Use the first conversion coefficient to perform conversion processing on the second count value to obtain the third count value.

[0067] In some embodiments, the second count value and the first conversion coefficient can be multiplied to obtain the third count value. The obtaining of the third count value can be considered as converting the second count value into a count value equivalent to the maximum count value of the linear feedback shift register.

[0068] S1033. Based on the third count value and the clock signal frequency threshold, determine the frequency of the signal of the clock to be measured.

[0069] It should be noted that the clock signal frequency threshold can be a preset clock signal frequency value. This clock signal frequency value can be a relatively large frequency value. The clock signal frequency threshold can be used to determine whether the signal of the clock to be measured is abnormal. If it is determined that the signal of the clock to be measured is abnormal, it indicates that the cryptographic chip where the clock to be measured is located, or the cryptographic chip connected to the clock to be measured may be at risk of being attacked; if it is determined that the signal of the clock to be measured is abnormal, it indicates that the cryptographic chip where the clock to be measured is located is safe.

[0070] In some embodiments, there is an association relationship among the clock signal frequency threshold, the clock signal count threshold, the third count value, and the frequency of the signal of the clock to be measured. Therefore, when the third count value, the clock signal frequency threshold, and the clock signal count threshold are determined, the frequency of the signal of the clock to be measured can be calculated.

[0071] It can be understood that based on the first count value and the maximum count value of the linear feedback shift register, the first conversion coefficient is determined, and the second count value is processed by using the first conversion coefficient. Based on the third count value and the clock signal frequency threshold obtained after conversion, the actual frequency of the signal of the clock to be measured is avoided from being measured, and the convenience of frequency detection is improved.

[0072] In some embodiments of the present application, after obtaining the frequency of the signal of the clock to be measured, if it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, the operation currently being executed by the password chip corresponding to the clock to be measured is interrupted. Herein, the password chip corresponding to the clock to be measured may be the password chip where the clock to be measured is located, that is, the clock to be measured is the internal clock of the password chip; the password chip corresponding to the clock to be measured may also be an external clock connected to the clock to be measured, and this external clock can be used to control the input of external signals into the password chip.

[0073] In some embodiments, the operation currently being executed by the password chip may include encrypting plaintext data, decrypting encrypted data, etc. The fact that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold indicates that the current password chip may be at risk of being attacked. In this case, interrupting the operation currently being executed by the password chip corresponding to the clock to be measured can protect the operations related to the password chip from abnormal occurrences.

[0074] In other embodiments, when it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, the secret information in the password chip can also be directly cleared. Herein, the secret information may include encryption keys, decryption keys, plaintext to be encrypted, encrypted ciphertext, etc. By clearing the secret information in the password chip, it can be prevented that the secret information in the secret chip is not stolen, and the security of the secret information is ensured.

[0075] It can be understood that when it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, by interrupting the operation currently being executed by the password chip corresponding to the clock to be measured, or clearing the secret information in the password chip, the information in the password chip can be prevented from being leaked or tampered with, thereby achieving the purpose of protecting the information in the password chip.

[0076] In some embodiments of the present application, after obtaining the third count value through step S1032, a first ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured may also be determined based on the third count value and the clock signal count threshold; if the first ratio is less than or equal to a preset threshold, the operation currently being executed by the password chip corresponding to the clock signal to be measured is interrupted, or the secret information in the password chip is cleared.

[0077] In some embodiments, the preset threshold may be any positive integer set in advance. For example, the preset threshold may be 1, 2, etc. If it is determined that the first ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured is less than or equal to the preset threshold, it indicates that the frequency of the clock signal to be measured is relatively close to the clock signal frequency threshold, or the frequency of the clock signal to be measured exceeds the clock signal frequency threshold, that is, it indicates that the frequency of the clock signal to be measured is abnormal, and there may be a risk that the password chip corresponding to the clock signal to be measured is being attacked. Therefore, protective measures need to be taken for the password chip.

[0078] In some embodiments, the clock signal count threshold may be any count value determined in advance. The ratio of the third count value to the clock signal count threshold is equal to the ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured. Therefore, without determining the actual frequency of the clock signal to be measured, the ratio of the third count value to the clock signal count threshold can be directly determined as the first ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured.

[0079] It can be understood that determining the first ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured through the third count value and the clock signal count threshold avoids the step of calculating the actual frequency of the clock signal to be measured and improves the abnormal detection efficiency of the password chip; comparing the first ratio of the clock signal frequency threshold to the frequency of the clock signal to be measured with the preset threshold, and interrupting the operation currently being executed by the password chip corresponding to the clock signal to be measured or clearing the secret information in the password chip when it is determined that the first ratio is less than or equal to the preset threshold can protect the information in the password chip.

[0080] Next, the implementation process of the application embodiment in the actual application scenario will be introduced.

[0081] The present application provides a frequency detection method based on linear feedback shift register counting, as Figure 2 shown, the method includes:

[0082] S201. Start counting the reference clock and the clock signal to be measured.

[0083] In some embodiments, an accumulative counter may be used to count the periods of the signals of a reference clock, and a linear feedback shift register may be used to count the periods of the signals of a clock under test. The signals generated by the reference clock and the clock under test may both be periodic signals, and it is possible to control the counting of the reference clock and the clock under test simultaneously.

[0084] S202. Determine whether the count value for the reference clock reaches a preset ratio (equivalent to "1 / Q" in other embodiments) of the maximum count value of the accumulative counter.

[0085] If so, perform the following steps S203 to S206; otherwise, return to step S201 to continue execution. Among them, the preset ratio may be 1 / 4, 1 / 5, etc.

[0086] S203. Start looking for the micro-scale value (equivalent to the "candidate count value" in other embodiments).

[0087] In some embodiments, the micro-scale value may be the actual count value corresponding to the sequence state of the linear feedback shift register counter. Taking N = 22 as an example, the frequency detection process of the linear feedback shift register is introduced. The linear feedback shift register with N = 22 (N may also be other values, such as 23, 222, etc.) can represent 2 N -1 sequence states and repeat the sequence states after a period of 2 N -1, so its counting period is 2 N -1 = 4194303. In this way, a clock frequency 4 million times that of the reference clock can be measured. That is, a 1 GHz clock can be measured using a 1 kHz frequency. Similarly, a linear feedback shift register counter for detecting other high-speed frequencies can be constructed. The linear feedback shift register is a random sequence, but the designer can know the sequence states of specific periods and set a period division with a 4-fold increase (essentially a 2 n -fold increase is sufficient), and divide the linear feedback shift register counting. Here, record the sequence states with counts of 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, 262144, 1048576, and divide the timing period into 11 micro-scales from 1 to 11. The micro-scale 11 is obtained as 2 22 = 4 11 , where N = 22 and n = 2; the micro-scale 22 is obtained as 2 22 = 2 22 , where N = 22 and n = 1.

[0088] Exemplarily, in order to improve the detection accuracy, it is necessary to ensure a sufficiently long detection time and also to ensure that the micro-scale can definitely be detected. Therefore, first select a value within 1 / 4 of the maximum count value of the cumulative counter, such as 1 / 5. When the count value of the cumulative counter reaches 1 / 5 of the maximum count value, start detecting the micro-scale. At this time, the time to detect the micro-scale must be less than or equal to 4 / 5 of the maximum count value. In this way, it is certain that the detection can be completed before the count value of the cumulative counter overflows.

[0089] S204. If the count value of the linear feedback shift register reaches the micro-scale value, stop counting and record the micro-scale value and the count value of the cumulative counter.

[0090] In some embodiments, there is a mapping relationship between the sequence state and the actual count value of the linear feedback shift register, that is . Therefore, by obtaining the sequence state of the linear feedback shift register, the count value of the linear feedback shift register can be determined according to this mapping relationship. After that, if it is determined that the count value of the linear feedback shift register reaches any micro-scale value, the counting of the clock under test and the reference clock can be stopped, and the micro-scale value and the count value of the cumulative counter obtained when the counting stops can be recorded.

[0091] S205. According to the micro-scale value, shift the count value of the cumulative counter (equivalent to "performing conversion processing on the second count value" in other embodiments) to obtain the shifted count value (equivalent to "the third count value" in other embodiments).

[0092] In some embodiments, the number of bits to shift the count value of the cumulative counter can be determined by the micro-scale value and the bit width of the linear feedback shift register. If the bit width of the linear feedback shift register is 22 and the micro-scale value is 1,048,576, the binary number corresponding to the count value of the cumulative counter can be shifted left by 2 bits (i.e., multiplied by 4) to obtain the shifted count value.

[0093] S206. Determine the frequency of the clock under test according to the shifted count value, the frequency threshold, and the count threshold.

[0094] In some embodiments, using the count value (micro-scale value) corresponding to the current sequence state of the linear feedback shift register count value and the count value of the reference clock during this period, the frequency of the clock under test can be calculated ( ).

[0095] However, in security protection, it is often not necessary to calculate the actual frequency of the clock. Once a specific frequency threshold is reached, the frequency can be considered abnormal. At this time, the linear feedback shift register high-speed frequency meter can be further simplified. It can be simply calculated that when the linear feedback shift register count reaches the 1048576 sequence, the corresponding time of the count multiplied by 4 is the count period of 4194304; when the count reaches the 65536 sequence, the corresponding time of the count multiplied by 4 * 4 * 4 is the count period of 4194304. Therefore, the mapping relationship can be directly superimposed on . At this time, the only variable to be tested is , which can be directly compared with a specific threshold to determine whether the frequency is abnormal. When the linear feedback shift register is at the 1048576 sequence, the count value of is shifted left by 2 bits, that is, multiplied by 4, to align with the count period of 4194304 of the linear feedback shift register. When the linear feedback shift register is at the 262144 sequence, the count value of is shifted left by 4 bits, that is, multiplied by 16, to align with the count period of 4194304 of the linear feedback shift register. And so on, the sequence mapping of the linear feedback shift register can be converted to `, normalized to the reference frequency count state when the linear feedback shift register executes 4194304 cycles, and the frequency comparison is completed.

[0096] In some embodiments, the specified frequency and the mapping threshold satisfy the relationship shown in the following formula (2):

[0097] (2);

[0098] Among them, , respectively represent the frequency threshold and the frequency of the reference clock, , respectively represent the maximum count value and the count threshold of the linear feedback shift register.

[0099] Furthermore, since the threshold and the value to be measured are the same, therefore, the above formula (2) is expressed by formula (3):

[0100] (3);

[0101] Among them, , is a positive integer. Combining formula (3) and formula (1) can obtain formula (4):

[0102] (4);

[0103] Therefore, through ( `) and The ratio can determine the ratio of the frequency threshold to the frequency of the clock under test, and then the frequency of the clock under test can be determined based on this ratio and the frequency threshold. . Among them, can be understood as the count value obtained after shifting the count value of the accumulative counter.

[0104] S207. Compare the frequency of the clock under test with the frequency threshold to determine whether the frequency of the clock under test is abnormal.

[0105] After calculating the frequency of the clock under test, it can be determined whether the frequency of the clock under test is greater than or equal to the frequency threshold. If the frequency of the clock under test is greater than or equal to the frequency threshold, it can be determined that the frequency of the clock under test is abnormal, and there may be a risk that the cryptographic chip corresponding to the frequency of the clock under test is attacked; otherwise, it can be determined that the frequency of the clock under test is normal, and the cryptographic chip corresponding to the frequency of the clock under test is safe.

[0106] It can be understood that when using a linear feedback shift register for counting, compared with a traditional counter, in the counting of the clock under test, the linear feedback shift register method used not only has better area resources, but also has better timing, and can detect higher-frequency frequencies; by setting linear feedback shift register counters with different bit widths, wide-range and high-precision measurements can be achieved. At the same time, as part of the frequency detection, the result can be simply compared through shift normalization to determine whether the frequency is abnormal; compared with a detector that needs to completely calculate the actual frequency, it saves the operation area, and only uses shift logic to complete the unification and comparison of the frequency of the signal of the clock under test and the frequency threshold.

[0107] The frequency detection method based on linear feedback shift register counting provided by this application uses linear feedback shift register counting to replace the traditional counting method, can test the clock frequency of higher frequencies, and at the same time adopts multi-period measurement and threshold selection methods to pursue the accuracy and controllability of clock frequency detection, and can achieve high-precision, wide-range and controllable frequency measurement.

[0108] This application provides a frequency detection system based on linear feedback shift register counting, as Figure 3As shown in the figure, the frequency detection system 300 based on linear feedback shift register counting includes an accumulative counter 301, a linear feedback shift register counter 302, a synchronization and enabling module 303, a micro-scale detection module 304, a shift module 305, a frequency comparison module 306, and an alarm module 307. Among them, the accumulative counter 301 includes an addition logic sub-module 3011 and a first register 3012, and the linear feedback shift register counter 302 includes an exclusive OR logic sub-module 3021 and a second register 3022.

[0109] The accumulative counter 301 and the linear feedback shift register counter 302 control the timing range through the synchronization and enabling module 303 to ensure that the timers start, collect, and end simultaneously. The micro-scale detection module 304 is started under a set rule (such as when the count value of the accumulative counter 301 reaches 1 / 4 of the maximum count value) to detect the linear feedback shift register counter 302. After detecting the micro-scale, the counting is stopped; the shift module 305 shifts the count value of the ended accumulative counter 301 based on the micro-scale, maps it to the value when the maximum linear feedback shift register is reached, and determines the frequency of the clock under test based on the shifted count value; the frequency comparison module 306 compares the frequency of the clock under test with the frequency threshold to determine whether it is abnormal; the alarm module 307 can send a warning message when it is determined that the frequency of the clock under test is abnormal to prompt the user that there may be a risk of the password chip corresponding to the clock under test being attacked currently.

[0110] In some embodiments, the frequency detection system 300 based on linear feedback shift register counting provided by the present application can detect the frequency of the signal of the clock under test inside the password chip. In addition, in the password chip entity, there is a risk of obtaining password information through physical intrusion methods, including using a high-frequency clock for physical attacks, such as Figure 4 As shown in the figure, the frequency detection system 300 based on linear feedback shift register counting can detect the frequency of the signal of the clock under test 402 outside the password chip 401. When it is determined that the signal of the clock under test 402 is abnormal through the frequency detection system 300 based on linear feedback shift register counting, the frequency detection system 300 based on linear feedback shift register counting can also reset the password chip 401.

[0111] The frequency detection system based on linear feedback shift register counting provided by the present application can detect the frequency of the signal of the current clock under test. When a high-frequency clock is detected, the secret information in the password chip can be cleared to achieve the effect of information protection.

[0112] The present application also provides a chip, Figure 5 which is a schematic diagram of the composition structure of a chip provided by an embodiment of the present application, as Figure 5As shown, the chip 500 includes a control unit 501 and a processing unit 502, where:

[0113] The control unit 501 is configured to, in response to a frequency detection instruction for a signal of a clock to be measured, control a linear feedback shift register to start counting the signal of the clock to be measured, and control an accumulation counter to start counting the signal of a reference clock; wherein, the bit width of the linear feedback shift register is greater than a counter bit width threshold, and the circuit complexity of the linear feedback shift register is less than a circuit complexity threshold;

[0114] The control unit 501 is further configured to, if it is determined that a counting end condition is satisfied, control the linear feedback shift register and the accumulation counter to stop counting, and obtain a first count value of the linear feedback shift register and a second count value of the accumulation counter;

[0115] The processing unit 502 is configured to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

[0116] In some embodiments, the processing unit 502 is further configured to determine a first conversion coefficient based on the first count value and the maximum count value of the linear feedback shift register; use the first conversion coefficient to perform a conversion process on the second count value to obtain a third count value; and determine the frequency of the signal of the clock to be measured based on the third count value and a clock signal frequency threshold.

[0117] In some embodiments, the control unit 501 is further configured to, if it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, interrupt the operation currently executed by the cryptographic chip corresponding to the clock to be measured, or clear the secret information in the cryptographic chip.

[0118] In some embodiments, the processing unit 502 is further configured to determine a first ratio of the clock signal frequency threshold to the frequency of the signal of the clock to be measured based on the third count value and a clock signal count threshold; the control unit 501 is further configured to, if the first ratio is less than or equal to a preset threshold, interrupt the operation currently executed by the cryptographic chip corresponding to the clock to be measured, or clear the secret information in the cryptographic chip.

[0119] In some embodiments, the linear feedback shift register includes a linear feedback shift register; the processing unit 502 is further configured to obtain a first sequence state of the linear feedback shift register; determine a count value corresponding to the first sequence state based on a preset correspondence between the sequence state of the linear feedback shift register and the count value; if the count value corresponding to the first sequence state is a candidate count value, determine that the count end condition is satisfied; the candidate count value is 2N, where N is a non-negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register.

[0120] In some embodiments, the processing unit 502 is further configured to test the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and a reference count value corresponding to the reference sequence state; the number of the reference sequence states is determined by the bit width of the linear feedback shift register; create a preset correspondence between the sequence state and the count value of the linear feedback shift register based on each reference sequence state and the corresponding reference count value.

[0121] In some embodiments, there are multiple candidate count values; the processing unit 502 is further configured to obtain the maximum count value and the bit width of the linear feedback shift register; determine each candidate count value of the linear feedback shift register based on the maximum count value and the bit width.

[0122] In some embodiments, the control unit 501 is further configured to, if the count value of the accumulative counter reaches a first value, start detecting each candidate count value to determine whether the count value corresponding to the linear feedback shift register is the same as any one of the candidate count values; wherein, the first value is 1 / Q of the maximum count value of the accumulative counter, and Q is an integer greater than 1.

[0123] It should be noted that the description of the chip in the embodiments of the present application is similar to the description of the embodiments of the method for determining the frequency of the above clock signal, and has similar beneficial effects as the method embodiments, so details are not described herein. For the technical details not disclosed in the embodiments of the present device, please refer to the description of the method embodiments of the present application for understanding.

[0124] It should be noted that in this article, the term "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including at least one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0125] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0126] In addition, each functional unit in each embodiment of the present application can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above integrated units can be implemented in the form of hardware.

[0127] As mentioned above, only the implementation manners of the present application are described, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all of them should be covered by the protection scope of the present application.

Claims

1. A method for determining the frequency of a clock signal, characterized in that: include: In response to a frequency detection instruction for a signal of a clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulative counter to start counting the signal of a reference clock; If it is determined that the counting end condition is met, controlling the linear feedback shift register and the accumulative counter to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulative counter; Determine the frequency of the signal of the clock to be measured based on the first count value and the second count value; The determining the frequency of the signal of the clock to be measured based on the first count value and the second count value includes: determining a first conversion coefficient based on the first count value and a maximum count value of the linear feedback shift register; The second count value is converted using the first conversion coefficient to obtain a third count value; and the frequency of the signal of the clock to be measured is determined based on the third count value and a clock signal frequency threshold.

2. The method according to claim 1, characterized in that The method further comprises: If it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, the operation currently being performed by the cryptographic chip corresponding to the clock to be measured is interrupted, or the secret information in the cryptographic chip is cleared.

3. The method according to claim 1, characterized in that The method further comprises: Determine a first ratio of the clock signal frequency threshold to the frequency of the signal of the clock to be measured based on the third count value and the clock signal count threshold; If the first ratio is less than or equal to a preset threshold, the operation currently being performed by the cryptographic chip corresponding to the clock to be tested is interrupted, or the secret information in the cryptographic chip is cleared.

4. The method according to any one of claims 1 to 3, characterized in that: The determining that the counting end condition is satisfied includes: Acquiring a first sequence state of the linear feedback shift register; Determining the count value corresponding to the first sequence state based on a preset correspondence relationship between the sequence state and the count value of the linear feedback shift register; If the count value corresponding to the first sequence state is a candidate count value, it is determined that the counting end condition is met; the candidate count value is 2 N , N is a non-negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register.

5. The method according to claim 4, characterized in that The method further comprises: Testing the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and a reference count value corresponding to the reference sequence state; the number of the reference sequence states is determined by the bit width of the linear feedback shift register; Based on the respective reference sequence states and the corresponding reference count values, a preset corresponding relationship between the sequence state and the count value of the linear feedback shift register is created.

6. The method according to claim 4, characterized in that The candidate count value includes a plurality of candidate count values; and the method further includes: Obtaining a maximum count value and a bit width of the linear feedback shift register; Based on the maximum count value and the bit width, candidate count values ​​of the linear feedback shift register are determined.

7. The method according to claim 6, characterized in that The method further comprises: If the count value of the accumulator counter reaches a first value, the detection of each candidate count value is started to determine whether the count value corresponding to the linear feedback shift register is the same as any candidate count value; wherein the first value is 1 / Q of the maximum count value of the accumulator counter, and Q is an integer greater than 1.

8. A chip, characterized in that: include: A control unit and a processing unit, wherein The control unit is used to control the linear feedback shift register to start counting the signal of the clock to be measured, and control the accumulative counter to start counting the signal of the reference clock in response to a frequency detection instruction for the signal of the clock to be measured corresponding to the chip; The control unit is further configured to control the linear feedback shift register and the accumulative counter to stop counting if it is determined that the counting end condition is met, and obtain a first count value of the linear feedback shift register and a second count value of the accumulative counter; The processing unit is used to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value; The processing unit is also used to determine a first conversion coefficient based on the first count value and the maximum count value of the linear feedback shift register; use the first conversion coefficient to convert the second count value to obtain a third count value; and determine the frequency of the signal of the clock to be measured based on the third count value and the clock signal frequency threshold.

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