Processor and method implemented by host instruction set architecture platform

Abstract

The invention relates to a processor and a method implemented by a host instruction set architecture platform. The processor is configured as a host instruction set architecture platform operable to execute a second operation instruction under the host instruction set architecture while simulating a first operation instruction under the customer instruction set architecture related to generation or update of the plurality of condition flags, the first operation instruction is an operation instruction for executing operation on a first operand from a first source address and a second operand from a second source address; the second operation instruction is an operation instruction for executing an operation on a first operand from the first source address and a second operand from the second source address and storing a plurality of condition marks to the first destination address according to an operation result.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers, and more particularly to a processor and a method implemented by a host instruction set architecture platform. Background Art

[0002] A reduced instruction set computer (RISC) processor is a processor that executes fewer types of computer instructions. The basic starting point of a RISC processor is to reduce the complexity of hardware design by streamlining the machine instruction system while increasing the speed of instruction execution. In a RISC processor, both simple and complex operations are completed by blocks of simple instructions. Summary of the invention

[0003] According to an embodiment of the present disclosure, the processor is configured as a host instruction set architecture platform, which can be operated to: execute a second operation instruction under the host instruction set architecture when simulating a first operation instruction under the client instruction set architecture and related to the generation or update of multiple condition flags, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on a first operand from the first source address and a second operand from the second source address and stores the multiple condition flags to a first destination address according to the operation result.

[0004] According to an embodiment of the present disclosure, a method implemented by a host instruction set architecture platform includes: when simulating a first operation instruction under a client instruction set architecture and related to the generation or update of multiple condition flags, executing a second operation instruction under the host instruction set architecture, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on a first operand from the first source address and a second operand from the second source address and stores the multiple condition flags to a first destination address according to the operation result.

[0005] According to the computer-readable storage medium of the embodiment of the present disclosure, computer-executable instructions are stored thereon, wherein when the computer-executable instructions are executed by one or more processors, the one or more processors execute the above-mentioned method implemented by the host instruction set architecture platform.

[0006] According to an embodiment of the present disclosure, the computer program product includes computer executable instructions, wherein when the computer executable instructions are executed by one or more processors, the one or more processors execute the above-mentioned method implemented by the host instruction set architecture platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying figures in which like reference numerals refer to similar elements.

[0008] Figure 1 Detailed description is a flowchart illustrating an operation instruction simulation method implemented by a processor configured as a host instruction set architecture platform according to an embodiment of the present disclosure.

[0009] Figure 2 is a block diagram illustrating an example computing device in which a processor according to various embodiments of the present disclosure may be used. DETAILED DESCRIPTION

[0010] The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments may be implemented using the parts of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are provided to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be implemented without these specific details. In other examples, known features may be omitted or simplified in order to avoid blurring the illustrative embodiments.

[0011] In addition, various operations are described as multiple discrete operations in sequence in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations do not need to be performed in the order presented.

[0012] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. These phrases generally do not refer to the same embodiment; however, they may refer to the same embodiment. Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0013] With the help of binary conversion technology, applications under the client instruction set architecture can be run on the host instruction set architecture platform, for example, applications under the advanced RISC machine (ARM) instruction set architecture or the X86 instruction set architecture can be run on the fifth-generation RISC (RISC-five, RISC-V) platform. In order to simulate the operation instructions under other instruction set architectures on the RISC-V platform, it is necessary to simulate the conditional flags under the instruction set architecture on the RISC-V platform, save these conditional flags in memory or registers, and update these conditional flags with reference to source operands and result operands. Since the RISC-V platform does not support conditional flags, complex pure software operations are required to update and use these conditional flags on the RISC-V platform.

[0014] In view of the above situation, a processor according to an embodiment of the present disclosure is proposed, which, when configured as a host instruction set architecture platform that does not support conditional flags, can simulate operating instructions under a client instruction set architecture that supports conditional flags through fewer operating instructions.

[0015] Figure 1 1 is a flow chart showing a method for simulating an operation instruction executed by a processor configured as a host instruction set architecture platform according to an embodiment of the present disclosure. Figure 1 As shown, the operation instruction simulation method 100 includes: S102, when simulating a first operation instruction under a client instruction set architecture and related to the generation or update of multiple condition flags, executing a second operation instruction under a host instruction set architecture, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on a first operand from the first source address and a second operand from the second source address and stores multiple condition flags to a first destination address according to the operation result.

[0016] In some embodiments, when the first operation instruction is associated with a logical AND operation on a first operand and a second operand, the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores multiple condition flags to a first destination address based on the operation result.

[0017] In some embodiments, when the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are integer operands, the second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores multiple condition flags to a first destination address based on the operation result.

[0018] In some embodiments, when the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are floating-point operands, the second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores a plurality of condition flags to a first destination address based on the operation result.

[0019] In some embodiments, Figure 1 As shown, the operation instruction simulation method 100 may further include: S104, when simulating a first conditional operation instruction under a client instruction set architecture based on one or more condition flags among multiple condition flags, executing a branch operation instruction under a host instruction set architecture, wherein the first conditional operation instruction is an operation instruction that performs a specified operation when one or more condition flags satisfy a first predetermined condition, and the branch operation instruction is an operation instruction that refers to multiple condition flags stored in a first destination address and jumps to a specified address when one or more condition flags satisfy a first predetermined condition.

[0020] In some embodiments, Figure 1 As shown, the operation instruction simulation method 100 may further include: S106, when simulating a second conditional operation instruction under the client instruction set architecture based on one or more conditional flags among multiple conditional flags, executing a transfer operation instruction under the host instruction set architecture, wherein the second conditional operation instruction is an operation instruction for copying the content in the third source address to the second destination address when one or more conditional flags satisfy a second predetermined condition, and the transfer operation instruction is an operation instruction for copying the content in the third source address to the second destination address with reference to multiple conditional flags stored in the first destination address and when one or more conditional flags satisfy a second predetermined condition.

[0021] In some embodiments, the host instruction set architecture platform can be implemented as a reduced instruction set architecture platform (e.g., a RISC-V platform). In other words, the host instruction set architecture can be a reduced instruction set architecture (e.g., a RISC-V instruction set architecture).

[0022] In some embodiments, the client instruction set architecture may be an X86 instruction set architecture (e.g., an X86_64 instruction set architecture). In this case, the plurality of conditional flags include a Carry (CF) flag, an Overflow (OF) flag, a Signed (SF) flag, a Zero (ZF) flag, and a Parity (PF) flag.

[0023] In some embodiments, the client instruction set architecture may be an advanced reduced instruction set architecture (e.g., an ARM64 instruction set architecture). In this case, the plurality of conditional flags include a carry (CF) flag, an overflow (VF) flag, a negative (NF) flag, and a zero (ZF) flag.

[0024] In one example, the host instruction set architecture is the RISC-V instruction set architecture, and the client instruction set architecture is the X86 instruction set architecture. In this case: I. In the case where the first operation instruction is associated with a logical AND operation on a first operand and a second operand, the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores a CF flag, an OF flag, an SF flag, a ZF flag, and a PF flag to a specified address in a general register based on the operation result. At this time, the CF flag = 0; the OF flag = 0; if the sign bit of the operation result is 1, the SF flag = 1, otherwise the SF flag = 0; if all bits of the operation result are 0, the ZF flag = 1, otherwise the ZF flag = 0; if there are an even number of set bits in the operation result, the PF flag = 1, and if there are an odd number of set bits in the operation result, the PF flag = 0.

[0025] II. In the case where the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are integer operands, the second operation instruction is an operation instruction for performing an integer comparison operation on the first operand and the second operand and storing at least a CF flag, an OF flag, an SF flag, and a PF flag to a designated address in a general register based on the operation result. At this time, if the operation result indicates that the second operand is greater than the first operand as an unsigned number, the CF flag = 1, otherwise the CF flag = 0; if there is an overflow in the operation result, the OF flag = 1, otherwise the OF flag = 0; if the sign bit of the operation result is 1, the SF flag = 1, otherwise the SF flag = 0; if there are an even number of set bits in the operation result, the PF flag = 1, and if there are an odd number of set bits in the operation result, the PF flag = 0.

[0026] III. In the case where the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are floating-point operands, the second operation instruction is an operation instruction for performing a floating-point comparison operation on the first operand and the second operand and storing the CF flag, the OF flag, the SF flag, the ZF flag, and the PF flag to a specified address in a general register based on the operation result. At this time, if the operation result indicates that the first operand is less than the second operand or the first operand and / or the second operand are illegal floating-point numbers, the CF flag=1, otherwise the CF flag=0; the OF flag=0; the SF flag=0; if the operation result indicates that the first operand is equal to the second operand or the first operand and / or the second operand are illegal floating-point numbers, the ZF flag=1, otherwise the ZF flag=0; if the first operand and / or the second operand are illegal floating-point numbers, the PF flag=1, otherwise the PF flag=0.

[0027] IV. A branch operation instruction is an operation instruction that refers to the CF flag, OF flag, SF flag, ZF flag, and PF flag stored at a designated address in a general register and jumps to the corresponding designated address when one or more of the flags satisfies one of the following conditions (note that different conditions may correspond to the same or different designated addresses): (1) CF flag = 1; (2) CF flag = 0; (3) ZF flag = 1; (4) ZF flag = 0; (5) SF flag = OF flag; (6) SF flag != OF flag; (7) CF flag = 0 and ZF flag = 0; (8) CF flag = 1 or ZF flag = 1; (9) ZF flag = 0 and SF flag = OF flag; (10) ZF flag = 1 or SF flag != OF flag; (11) SF flag = 1; (12) SF flag = 0; (13) PF flag = 1; (14) PF flag = 0; (15) OF flag = 1; (16) OF flag = 0.

[0028] V. The transfer operation instruction is an operation instruction that refers to the CF flag, the OF flag, the SF flag, the ZF flag, and the PF flag stored at the specified address in the general register and copies the content in the third source address to the second destination address when one or more of the flags satisfies one of the following conditions: (1) CF flag = 1; (2) CF flag = 0; (3) ZF flag = 1; (4) ZF flag = 0; (5) SF flag = OF flag; (6) SF flag != OF flag; (7) CF flag = 0 and ZF flag = 0; (8) CF flag = 1 or ZF flag = 1; (9) ZF flag = 0 and SF flag = OF flag; (10) ZF flag = 1 or SF flag != OF flag; (11) SF flag = 1; (12) SF flag = 0; (13) PF flag = 1; (14) PF flag = 0; (15) OF flag = 1; (16) OF flag = 0.

[0029] In another example, the host instruction set architecture is the RISC-V instruction set architecture and the guest instruction set architecture is the ARM instruction set architecture. In this case: I. In the case where the first operation instruction is associated with a logical AND operation on a first operand and a second operand, the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores a CF flag, a VF flag, a NF flag, and a ZF flag to a designated address in a general register based on the operation result. At this time, the CF flag = 0; the VF flag = 0; if the sign bit of the operation result is 1, the NF flag = 1, otherwise the NF flag = 0; if all bits of the operation result are 0, the ZF flag = 1, otherwise the ZF flag = 0.

[0030] II. In the case where the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are integer operands, the second operation instruction is an operation instruction for performing an integer comparison operation on the first operand and the second operand and storing a CF flag, a VF flag, a NF flag, and a ZF flag to a designated address in a general register based on the operation result. At this time, if the operation result indicates that the first operand is greater than the second operand as an unsigned number, the CF flag = 1, otherwise the CF flag = 0; if the operation result has an overflow, the VF flag = 1, otherwise the VF flag = 0; if the sign bit of the operation result is 1, the NF flag = 1, otherwise the NF flag = 0; if the operation result indicates that the first operand is equal to the second operand, the ZF flag = 1, otherwise the ZF flag = 0.

[0031] III. In the case where the first operation instruction is associated with a comparison operation on a first operand and a second operand and both the first operand and the second operand are floating-point operands, the second operation instruction is an operation instruction for performing a floating-point comparison operation on the first operand and the second operand and storing the CF flag, the VF flag, the NF flag, and the ZF flag to a specified address in a general register based on the operation result. At this time, if the operation result indicates that the first operand is less than the second operand or the first operand and / or the second operand are illegal floating-point numbers, the CF flag=1, otherwise the CF flag=0; the VF flag=0; the NF flag=0; if the operation result indicates that the first operand is equal to the second operand or the first operand and / or the second operand are illegal floating-point numbers, the ZF flag=1, otherwise the ZF flag=0.

[0032] IV. A branch operation instruction is an operation instruction that refers to the CF flag, VF flag, NF flag, and ZF flag stored at a designated address in a general register and jumps to the corresponding designated address when one or more of the flags satisfies one of the following conditions (note that different conditions may correspond to the same or different designated addresses): (1) ZF flag = 1; (2) ZF flag = 0; (3) CF flag = 1; (4) CF flag = 0; (5) NF flag = 1; (6) NF flag = 0; (7) VF flag = 1; (8) VF flag = 0; (9) CF flag = 1 and ZF flag = 0; (10) CF flag = 0 or ZF flag = 1; (11) NF flag = VF flag; (12) NF flag != VF flag; (13) ZF flag = 0 and NF flag = VF flag; (14) ZF flag = 1 or NF flag != VF flag; (15) other conditions.

[0033] V. The transfer operation instruction refers to an operation instruction that refers to the CF flag, VF flag, NF flag, and ZF flag stored at a specified address in a general register and copies the content in the third source address to the second destination address when one or more of the flags satisfies one of the following conditions: (1) ZF flag = 1; (2) ZF flag = 0; (3) CF flag = 1; (4) CF flag = 0; (5) NF flag = 1; (6) NF flag = 0; (7) VF flag = 1; (8) VF flag = 0; (9) CF flag = 1 and ZF flag = 0; (10) CF flag = 0 or ZF flag = 1; (11) NF flag = VF flag; (12) NF flag != VF flag; (13) ZF flag = 0 and NF flag = VF flag; (14) ZF flag = 1 or NF flag != VF flag; (15) other conditions.

[0034] In some embodiments, the host instruction set architecture platform can support multiple client instruction set architectures at the same time. For example, the RISC-V platform as the host instruction set architecture platform can simultaneously support the X86 instruction set architecture and the ARM instruction set architecture as client instruction set architectures, and the CF flag, OF flag, SF flag, ZF flag, and PF flag under the X86 instruction set architecture and the CF flag, VF flag, NF flag, and ZF flag under the ARM instruction set architecture can be stored in different addresses of the same general register.

[0035] In some embodiments, the host instruction set architecture platform may support multiple client instruction set architectures, and may store a type flag of the currently supported client instruction set architecture in a control and status register (CSR). For example, a RISC-V platform as a host instruction set architecture platform may support the X86 instruction set architecture and the ARM instruction set architecture as client instruction set architectures, and may store a type flag of the currently supported client instruction set architecture in the CSR (for example, if the type flag is 1, the currently supported client instruction set architecture is the X86 instruction set architecture, otherwise the currently supported client instruction set architecture is the ARM instruction set architecture).

[0036] Figure 2 is a block diagram illustrating an example computing device in which a processor according to various embodiments of the present disclosure may be used. Figure 2 As shown, the computing device 200 includes one or more processors (or processor cores) 210, one or more memory / storage devices 220, and one or more communication resources 230, wherein these processors, memory / storage devices, and communication resources can be communicatively coupled to each other via a bus 240 or other interface circuits. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 202 can be executed to provide an execution environment for one or more network slices / sub-slices to utilize the hardware resources of the computing device 200.

[0037] Processor 210 may include, for example, processor 212 and processor 214. Processor 210 may be, for example, a central processing unit (CPU), a RISC processor, a complex instruction set computer (CISC) processor, a graphic processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0038] The memory / storage device 220 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 220 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a flash memory, a solid-state memory, etc.

[0039] The communication resources 230 may include interconnect or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices 204 or one or more databases 206 or other network elements via the network 208. For example, the communication resources 230 may include wired communication components (e.g., for coupling via a universal serial bus (USB), Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® low energy) components, Wi-Fi® components, and other communication components.

[0040] The instructions 250 may include software, programs, applications, applets, applications, or other executable code for causing at least any one of the processors 210 to perform various processing procedures. The instructions 250 may reside in whole or in part in at least one of the processors 210 (e.g., in a cache of the processor), the memory / storage device 220, or any suitable combination thereof. In addition, any portion of the instructions 250 may be transmitted to the hardware resources 200 from any combination of the peripheral device 204 or the database 206. Therefore, the memory of the processor 210, the memory / storage device 220, the peripheral device 204, and the database 206 are examples of computer-readable and machine-readable media.

[0041] Although certain embodiments have been illustrated and described herein for purposes of description, the embodiments illustrated and described may be replaced with a variety of alternative and / or equivalent embodiments or implementations that achieve the same purpose without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, the embodiments described herein are expressly limited only by the appended claims and their equivalents.

Claims

1. A processor configured as a host instruction set architecture platform, the host instruction set architecture platform being operable to: When simulating a first operation instruction under a guest instruction set architecture related to the generation or update of a plurality of conditional flags, a second operation instruction under a host instruction set architecture is executed, wherein: The first operation instruction is an operation instruction to perform an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction to perform an operation on the first operand from the first source address and the second operand from the second source address and store the multiple condition flags to a first destination address according to the operation result.

2. The processor according to claim 1, wherein: The first operation instruction is associated with a logical AND operation on the first operand and the second operand, and the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

3. The processor according to claim 1, wherein: The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are integer operands. The second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

4. The processor according to claim 1, wherein: The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are floating-point operands. The second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

5. The processor according to any one of claims 1 to 4, wherein: The host instruction set architecture platform is further operable to: When simulating a first conditional operation instruction based on one or more condition flags among the multiple condition flags under the client instruction set architecture, a branch operation instruction under the host instruction set architecture is executed, wherein the first conditional operation instruction is an operation instruction that performs a specified operation when the one or more condition flags satisfy a first predetermined condition, and the branch operation instruction is an operation instruction that refers to the multiple condition flags stored in the first destination address and jumps to a specified address when the one or more condition flags satisfy the first predetermined condition.

6. The processor according to any one of claims 1 to 4, wherein: The host instruction set architecture platform is further operable to: When simulating a second conditional operation instruction under the client instruction set architecture based on one or more condition flags among the multiple condition flags, a transfer operation instruction under the host instruction set architecture is executed, wherein the second conditional operation instruction is an operation instruction for copying the content in the third source address to the second destination address when the one or more condition flags satisfy a second predetermined condition, and the transfer operation instruction is an operation instruction for copying the content in the third source address to the second destination address with reference to the multiple condition flags stored in the first destination address and when the one or more condition flags satisfy the second predetermined condition.

7. The processor according to any one of claims 1 to 4, wherein: The host instruction set architecture is a reduced instruction set architecture.

8. The processor according to any one of claims 1 to 4, wherein: The client instruction set architecture is an X86 instruction set architecture, and the multiple condition flags include a carry flag, an overflow flag, a sign flag, a zero flag, and a parity flag.

9. The processor according to any one of claims 1 to 4, wherein: The client instruction set architecture is an advanced reduced instruction set architecture, and the plurality of condition flags include a carry flag, an overflow flag, a negative flag, and a zero flag.

10. The processor according to any one of claims 1 to 4, wherein: The host instruction set architecture platform is further operable to: The type flag of the guest instruction set architecture is stored in a control status register.

11. The processor according to any one of claims 1 to 4, wherein: The first destination address is an address in a general register.

12. A method implemented by a host instruction set architecture platform, comprising: When simulating a first operation instruction under a client instruction set architecture and related to generation or update of multiple condition flags, a second operation instruction under a host instruction set architecture is executed, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores the multiple condition flags to a first destination address according to the operation result.

13. The method according to claim 12, wherein: The first operation instruction is associated with a logical AND operation on the first operand and the second operand, and the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

14. The method according to claim 12, wherein: The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are integer operands. The second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

15. The method according to claim 12, wherein: The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are floating-point operands. The second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores the multiple condition flags to the first destination address based on the operation result.

16. The method according to any one of claims 12 to 15, further comprising: When simulating a first conditional operation instruction based on one or more condition flags among the multiple condition flags under the client instruction set architecture, a branch operation instruction under the host instruction set architecture is executed, wherein the first conditional operation instruction is an operation instruction that performs a specified operation when the one or more condition flags satisfy a first predetermined condition, and the branch operation instruction is an operation instruction that refers to the multiple condition flags stored in the first destination address and jumps to a specified address when the one or more condition flags satisfy the first predetermined condition.

17. The method according to any one of claims 12 to 15, further comprising: When simulating a second conditional operation instruction under the client instruction set architecture based on one or more condition flags among the multiple condition flags, a transfer operation instruction under the host instruction set architecture is executed, wherein the second conditional operation instruction is an operation instruction for copying the content in the third source address to the second destination address when the one or more condition flags satisfy a second predetermined condition, and the transfer operation instruction is an operation instruction for copying the content in the third source address to the second destination address with reference to the multiple condition flags stored in the first destination address and when the one or more condition flags satisfy the second predetermined condition.

18. A computer-readable storage medium having computer-executable instructions stored thereon, wherein: The computer executable instructions, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 12 to 17.

19. A computer program product comprising computer executable instructions, wherein: The computer executable instructions, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 12 to 17.

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