A SIMD instruction conversion optimization method based on implicit instruction parallelism

Abstract

The present invention discloses a SIMD instruction conversion optimization method based on implicit instruction parallelism. When executing an executable file in a dynamic instruction conversion mode, the operands of the computing instruction are divided into multiple segments of data, and the x86 architecture instruction is converted into multiple instruction sequences for loading, computing and storing each segment of data. For an ARM core with affinity, the computing process is parallelized by having different computing cores execute the instruction sequences respectively. For an ARM core without affinity, the computing process is parallelized in a multi-threading mode. The original instruction is replaced by the ARM instruction sequences corresponding to different parallel modes to complete the dynamic conversion of the instruction, thereby effectively improving the execution efficiency of the instruction conversion.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to a SIMD instruction conversion optimization method based on implicit instruction parallelism. Background Art

[0002] The SIMD extended instruction set under the existing x86 architecture supports a variety of word lengths. For example, in 256-bit mode, vector registers can store 256-bit data, and common operations include arithmetic operations and logical operations on 256-bit vectors. NEON is a SIMD extended instruction set in the ARM architecture, and its data vector length is usually 128 bits. Therefore, when using NEON instructions to process longer data related to the SIMD instructions of the x86 architecture, it is necessary to first split the data of the x86 architecture into multiple shorter data that can be processed by the NEON instructions and then process them separately. However, since additional splitting and merging operations need to be performed, the execution performance of executable files may be reduced when simulating the execution of SIMD instructions of the x86 architecture in the ARM architecture based on data splitting. Summary of the invention

[0003] In view of this, the present invention provides a SIMD instruction conversion optimization method based on implicit instruction parallelism, which completes the parallelization of the instruction calculation process through multi-core or multi-threading to achieve efficient dynamic conversion of instructions.

[0004] The present invention provides a SIMD instruction conversion optimization method based on implicit instruction parallelism, which specifically includes the following steps:

[0005] Step 1: Load and execute the executable file through dynamic instruction conversion to obtain the current instruction to be converted;

[0006] Step 2: If the current instruction to be converted is a computing instruction in the x86 architecture, then obtain the operand of the current instruction to be converted, record the size of the elements in the operand as the first element size, record the maximum value of the length of each operand as the first length, and record the word length of the ARM instruction as the first word length. When the product of the first element size and the first length is greater than the first word length, execute step 3; when the product of the first element size and the first length is not greater than the first word length, convert the current instruction to be converted into an ARM instruction and then execute step 8; if the current instruction to be converted is not a computing instruction in the x86 architecture, convert the current instruction to be converted into an ARM instruction and then execute step 8;

[0007] Step 3, dividing the operand of the current instruction to be converted that satisfies the condition that the product of the length and the first element size is greater than the first word length into a set number of segments, and recording the maximum value of the set number of segments as N; selecting an ARM instruction with the same function as the first ARM instruction, constructing N first ARM instruction sequences including an ARM load instruction, a first ARM instruction and an ARM store instruction, and the N first ARM instruction sequences respectively complete the loading, calculation and result storage of the nth segment data of each operand, wherein n is an integer in the value range [1, N];

[0008] Step 4: Get whether the ARM processor supports setting the affinity of the CPU core. If it supports setting the affinity, execute step 5; otherwise, execute step 7.

[0009] Step 5: Form a second ARM instruction sequence by using the ARM computing core affinity related instructions, and add the second ARM instruction sequence to each first ARM instruction sequence to form N ARM multi-core instruction sequences;

[0010] Step 6: transfer the N ARM multi-core instruction sequences to the N ARM computing cores, and each ARM computing core completes the execution of the corresponding ARM multi-core instruction sequence according to the affinity setting in the N ARM multi-core instruction sequences, and executes step 8 after all ARM computing cores have completed the execution;

[0011] Step 7: Create a third ARM instruction sequence from thread creation related instructions, add the third ARM instruction sequence to each first ARM instruction sequence to form N ARM multi-threaded instruction sequences; start the execution of the N ARM multi-threaded instruction sequences in parallel, and execute step 8 after all the N ARM multi-threaded instruction sequences have completed execution;

[0012] Step 8: If the executable file has not been executed, execute step 2; otherwise, complete the execution of the executable file and end this process.

[0013] Furthermore, the value of setting the number of segments in step 3 is the result of rounding up the ratio of the product of the first element size and the length of the operand to the first word length.

[0014] Furthermore, the method of obtaining whether the ARM processor supports setting the affinity of the CPU core in step 4 is: obtaining data of the affinity-related status register, and determining the value of a specific bit.

[0015] Furthermore, a data synchronization mechanism is added to the ARM multi-core instruction sequence, specifically in the following manner: in the first ARM instruction sequence, a shared memory area synchronization instruction is added before each ARM instruction.

[0016] Furthermore, the shared memory area synchronization instruction is a DMB instruction.

[0017] Further, a data synchronization mechanism is added to the ARM multi-core instruction sequence, specifically in the following manner: the ARM multi-core instruction sequence is split into an ARM multi-core loading instruction sequence, an ARM multi-core computing instruction sequence and an ARM multi-core storage instruction sequence, wherein the ARM multi-core loading instruction sequence is formed by adding the second ARM instruction sequence to the front of each fourth ARM instruction sequence, and the fourth ARM instruction sequence only includes ARM loading instructions; the ARM multi-core computing instruction sequence is formed by adding the second ARM instruction sequence to the front of each fifth ARM instruction sequence, and the fifth ARM instruction sequence only includes ARM computing instructions; the ARM multi-core storage instruction sequence is formed by adding the second ARM instruction sequence to the front of each sixth ARM instruction sequence, and the sixth ARM instruction sequence only includes ARM storage instructions;

[0018] N ARM computing cores simultaneously execute the ARM multi-core loading instruction sequence, the ARM multi-core computing instruction sequence and the ARM multi-core storage instruction sequence in sequence.

[0019] Furthermore, a data synchronization mechanism is added to the ARM multi-threaded instruction sequence, specifically in the following manner: the ARM multi-threaded instruction sequence is formed by adding a third ARM instruction sequence before each seventh ARM instruction sequence, the seventh ARM instruction sequence comprising an ARM load instruction and a first ARM instruction; the execution of N ARM multi-threaded instruction sequences is started in parallel, and after the N ARM multi-threaded instruction sequences are all executed, the execution results of the N ARM multi-threaded instruction sequences are stored serially using an ARM storage instruction. Beneficial Effects

[0020] When executing an executable file in a dynamic instruction conversion manner, the present invention divides the operands of the calculation instruction into multiple segments of data, converts the x86 architecture instruction into multiple instruction sequences for loading, calculating and storing each segment of data, and for ARM cores with affinity, the calculation process is parallelized by having different computing cores execute the instruction sequences respectively, and for ARM cores without affinity, the calculation process is parallelized in a multi-threaded manner, and the original instruction is replaced by the ARM instruction sequence corresponding to different parallel modes to complete the dynamic conversion of the instruction, thereby effectively improving the execution efficiency of the instruction conversion. DETAILED DESCRIPTION

[0021] The present invention is described in detail with reference to the following embodiments.

[0022] The present invention provides a SIMD instruction conversion optimization method based on implicit instruction parallelism, the core idea of ​​which is: when executing an executable file in a dynamic instruction conversion mode, the operands of the calculation instruction are divided into multiple segments of data, and the x86 architecture instruction is converted into multiple instruction sequences for loading, calculating and storing each segment of data. For ARM cores with affinity, the calculation process is parallelized by having different calculation cores execute the instruction sequences respectively. For ARM cores without affinity, the calculation process is parallelized in a multi-threaded manner, and the original instruction is replaced by the ARM instruction sequence corresponding to different parallel modes to complete the dynamic conversion of the instruction.

[0023] The present invention provides a SIMD instruction conversion optimization method based on implicit instruction parallelism, which specifically includes the following steps:

[0024] Step 1: Load and execute the executable file through dynamic instruction conversion to obtain the current instruction to be converted.

[0025] Step 2. If the current instruction to be converted is a computing instruction in the x86 architecture, obtain the operand of the current instruction to be converted, record the size of the elements in the operand as the first element size, record the maximum value of the length of each operand as the first length, and record the word length of the ARM instruction as the first word length. When the product of the first element size and the first length is greater than the first word length, execute step 3; when the product of the first element size and the first length is not greater than the first word length, convert the current instruction to be converted into an ARM instruction and then execute step 8; if the current instruction to be converted is not a computing instruction in the x86 architecture, convert the current instruction to be converted into an ARM instruction and then execute step 8.

[0026] The computing instructions of the existing x86 architecture or ARM architecture usually have multiple operands. If the product of the length of the operand with the largest length among the multiple operands and the size of the first element is not greater than the first word length, then the lengths of all operands are not greater than the first word length. Therefore, the present invention only needs to calculate the maximum length among the operands.

[0027] Step 3, for the operands of the current instruction to be converted, the operands that meet the condition that the product of the length and the first element size is greater than the first word length are divided into a set number of segments, the value of the set number of segments is the result of rounding up the ratio of the product of the first element size and the length of the operand to the first word length, and the maximum value of the set number of segments is recorded as N; select multiple ARM registers, select an ARM instruction with the same function as the current instruction to be converted as the first ARM instruction, construct N first ARM instruction sequences including an ARM load instruction, a first ARM instruction and an ARM storage instruction, and the N first ARM instruction sequences respectively complete the loading, calculation and result storage of the nth segment data of each operand, where n is an integer in the value range [1,N].

[0028] Step 4: Get whether the ARM processor supports setting the affinity of the CPU core. If it supports setting the affinity, execute step 5; otherwise, execute step 7.

[0029] The method of obtaining whether the ARM processor supports setting the affinity of the CPU core is: obtaining data of the affinity-related status register, and determining the value of a specific bit.

[0030] Step 5: construct a second ARM instruction sequence including ARM instructions for obtaining and setting the affinity of the current ARM computing core, and add the second ARM instruction sequence before each first ARM instruction sequence to form N ARM multi-core instruction sequences.

[0031] Step 6: transfer the N ARM multi-core instruction sequences to the N ARM computing cores. Each ARM computing core determines the ARM multi-core instruction sequence it should execute according to the affinity settings in the N ARM multi-core instruction sequences, and completes the execution of the ARM multi-core instruction sequence. After all ARM computing cores have completed the execution of the ARM multi-core instruction sequence, execute step 8.

[0032] Step 7: construct a third ARM instruction sequence including ARM instructions for creating a thread and calling a thread, and add the third ARM instruction sequence before each first ARM instruction sequence to form N ARM multi-threaded instruction sequences; start the execution of the N ARM multi-threaded instruction sequences in parallel, and execute step 8 after all the N ARM multi-threaded instruction sequences have completed execution.

[0033] Step 8: If the executable file has not been executed, execute step 2; otherwise, complete the execution of the executable file and end this process.

[0034] In order to avoid the data synchronization problem during the instruction conversion process, the present invention realizes synchronization by adding a data synchronization mechanism in the ARM multi-core instruction sequence. The first synchronization method is: adding a shared memory area synchronization instruction before each ARM instruction in the first ARM instruction sequence, for example, the synchronization instruction is a DMB instruction. The second synchronization method is: constructing N fourth ARM instruction sequences containing ARM loading instructions, adding the second ARM instruction sequence before each fourth ARM instruction sequence to form N ARM multi-core loading instruction sequences; constructing N fifth ARM instruction sequences containing ARM computing instructions, adding the second ARM instruction sequence before each fifth ARM instruction sequence to form N ARM multi-core computing instruction sequences; constructing N sixth ARM instruction sequences containing ARM storage instructions, adding the second ARM instruction sequence before each sixth ARM instruction sequence to form N ARM multi-core storage instruction sequences; N ARM computing cores simultaneously and sequentially execute the ARM multi-core loading instruction sequence, the ARM multi-core computing instruction sequence and the ARM multi-core storage instruction sequence.

[0035] In order to further improve the operating efficiency of the synchronization mechanism during multi-core mode execution, the present invention respectively adopts the first synchronization method and the second synchronization method to complete the execution of multiple executable files, records the execution time to calculate the average execution time, and uses the synchronization method with the smaller average execution time as the final synchronization method.

[0036] In addition, for the method of completing the conversion in multiple threads, the present invention adopts the following method to achieve synchronization, specifically:

[0037] Construct N seventh ARM instruction sequences including an ARM load instruction and a first ARM instruction, and add the third ARM instruction sequence before each seventh ARM instruction sequence to form N ARM multi-threaded instruction sequences; start the execution of the N ARM multi-threaded instruction sequences in parallel, and after the N ARM multi-threaded instruction sequences are all executed, use ARM storage instructions to serially complete the storage of the execution results of the N ARM multi-threaded instruction sequences. Example

[0038] In this embodiment, a SIMD instruction conversion optimization method based on implicit instruction parallelism provided by the present invention is used to realize the conversion of computing instructions of the x86 architecture to instructions of the ARM architecture, including the following steps:

[0039] S1. Determine whether the ARM processor supports setting the affinity of the CPU core. If it does, execute S2; otherwise, execute S3.

[0040] ARM processors can set and manage affinity through specific instructions. For example, in some advanced ARM architectures, instructions similar to SET_AFFINITY are provided. In this embodiment, the MRS (Move from Special-register) instruction is used to read the contents of the program status register (CPSR) or other special registers to check whether there is a flag bit related to affinity. The specific code is as follows:

[0041] MRS r0, CPSR

[0042] TST r0, #0x1000 / / Assume bit 12 may be related to affinity

[0043] BEQ no_affinity / / If this bit is 0, affinity may not be supported

[0044] MOV r0, #1

[0045] B end

[0046] no_affinity:

[0047] MOV r0, #0

[0048] end:

[0049] BxF

[0050] In the above code, whether the CPU core supports affinity is determined by checking a specific bit (known) in the program status register (CPSR). Specifically, if the bit is detected to be set, it means that the processor supports affinity-related functions.

[0051] S2. When converting the computing instructions of AVX512, convert them into four NEON instructions, and generate machine instructions to schedule these four NEON instructions to four ARM computing cores for parallel execution.

[0052] For AVX512's arithmetic and logic calculation instructions, such as addition VADDPD, subtraction VPSUBPD, multiplication VMULPD, division VDIVPD, bitwise AND VANDPD, bitwise OR VORPD, bitwise XOR VXORPD, etc., the operands of these instructions are 512-bit data, which are divided into four 128-bit data blocks, and the results are calculated and saved separately. Taking the instruction with two operands as an example, the instruction sequence assigned to each computing core includes:

[0053] S2.1, remember the memory layout is:

[0054] input1_data: A continuous memory area that stores the first input operand (corresponding to zmm1 in AVX512), aligned to 128 bits, with each 128-bit data block containing two double-precision floating-point numbers.

[0055] input2_data: A continuous memory area that stores the second input operand (corresponding to zmm2 in AVX512), also aligned to 128 bits.

[0056] output_data: A continuous memory area used to store the results (corresponding to zmm0 in AVX512), also 128-bit aligned.

[0057] S2.2, take the instruction sequence generated for a certain computing core as an example, where r0, r1, r2, and d0 are all registers, and the registers allocated to different computing cores are different. VADD.F64 is double-precision addition, and convertible NEON instructions such as addition VADD, subtraction VSUB, multiplication VMUL, division VDIV, bitwise AND VAND, bitwise OR VOR, bitwise XOR VXOR, etc. Assume that r0 points to the starting address of the first 128-bit data block of input1_data, r1 points to the starting address of the first 128-bit data block of input2_data, and r2 points to the starting address of the first 128-bit data block of output_data. Load the first 128-bit data block (two double-precision floating-point numbers) from input1_data to the q0 register, specifically:

[0058] VLD1.64 {d0, d1}, [r0] / / Load the first 128-bit data block (two double-precision floating point numbers) from input2_data into the q1 register

[0059] VLD1.64 {d2, d3}, [r1]

[0060] VADD.F64 q0, q0, q1 / / Perform double-precision floating-point addition

[0061] VST1.64 {d0, d1}, [r2] / / Store the result to the location corresponding to output_data.

[0062] S2.3. Schedule the four NEON code segments obtained to the four ARM computing cores, construct a scheduling instruction sequence, and insert the scheduling instruction sequence into the NEON code segment. The following code takes the 0th ARM computing core as an example, and executes the scheduling settings of the first NEON computing instruction on core 0:

[0063] MRS X0, MPIDR_EL1 / / Read the value of the MPIDR_EL1 register into the general register X0 to obtain core-related identification information

[0064] AND X1, X0, #0x3 / / Obtain the value of the lower two digits through AND calculation (assuming the core number is in the lower two digits, the specific adjustment depends on the architecture), as the core number, store in X1

[0065] CMP X1, #0 / / Compare whether it is core 0

[0066] B.NE skip_core_0 / / If it is not core 0, jump to the address of skip_core_0.

[0067] The following is the first NEON addition instruction after setting affinity and executing it after determining core 0:

[0068] MOV X2, #0 / / Move the immediate value 0 (representing the core 0 number) to register X2 to set affinity

[0069] STR X2, CORE_AFFINITY_REG / / Assuming there is such a register for setting core affinity, write the core number to this register

[0070] DSB SY / / Data synchronization barrier to ensure that affinity settings take effect

[0071] ISB / / instruction synchronization barrier, refresh pipeline

[0072] ### Here is the NEON code segment generated in the previous step

[0073] #######

[0074] ######

[0075] skip_core_0

[0076] The above code is an example of scheduling settings.

[0077] S3. Build the machine code that calls the pthread function to schedule the four NEON code segments to four ARM threads for execution. The specific code is as follows:

[0078] LDR r12, =pthread_create / / Load pthread_create function address

[0079] MOV r4, #0 / / Allocate space for thread identifier and clear it to zero

[0080] STR r4, [SP, #-4]! / / Thread attributes are set to NULL (using default attributes)

[0081] MOV r5, #0 / / Set the function pointer to be executed by the thread

[0082] STR r6, address of the first NEON code segment

[0083] BLX r12 / / Call pthread_create function

[0084] First, the address of the pthread_create function is obtained, then space is allocated for the identifier of the new thread, the thread attribute is set to NULL, the address of the first NEON code segment is assigned to the register, and finally the pthread_create function is called to create the thread.

[0085] S4. To avoid data synchronization problems, the following two methods are evaluated for performance, and the synchronization mechanism with the lowest performance overhead is selected. The specific steps are as follows:

[0086] S4.1. Evaluate memory barriers:

[0087] Add a memory barrier, that is, add a DMB instruction before each NEON instruction. The specific instruction is: DMB SY, where SY represents the shared memory area to ensure the order of memory access; perform multiple calculations to evaluate the execution time of the executable file after adding the memory barrier.

[0088] S4.2. Evaluate the performance of statistics after loading data and then calculating:

[0089] The data loading instructions VST in the four NEON code segments are uniformly executed; the calculation instructions are then uniformly executed, and finally the storage instructions are uniformly executed; multiple calculations are performed to evaluate the execution time of the executable file.

[0090] S4.3. Compare the execution time of the above two methods and select the data synchronization method with the shorter execution time.

[0091] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A SIMD instruction conversion optimization method based on implicit instruction parallelism, characterized in that: The specific steps include: Step 1: Load and execute the executable file through dynamic instruction conversion to obtain the current instruction to be converted; Step 2: If the current instruction to be converted is a computing instruction in the x86 architecture, then obtain the operand of the current instruction to be converted, record the size of the elements in the operand as the first element size, record the maximum value of the length of each operand as the first length, and record the word length of the ARM instruction as the first word length. When the product of the first element size and the first length is greater than the first word length, execute step 3; when the product of the first element size and the first length is not greater than the first word length, convert the current instruction to be converted into an ARM instruction and then execute step 8; if the current instruction to be converted is not a computing instruction in the x86 architecture, convert the current instruction to be converted into an ARM instruction and then execute step 8; Step 3, dividing the operand of the current instruction to be converted that satisfies the condition that the product of the length and the first element size is greater than the first word length into a set number of segments, and recording the maximum value of the set number of segments as N; Select an ARM instruction with the same function as the first ARM instruction, construct N first ARM instruction sequences including an ARM load instruction, a first ARM instruction and an ARM store instruction, and use the N first ARM instruction sequences to complete the loading, calculation and result storage of the nth segment of data of each operand respectively, where n is an integer in the range of [1, N]; Step 4: Get whether the ARM processor supports setting the affinity of the CPU core. If it supports setting the affinity, execute step 5; otherwise, execute step 7. Step 5: Form a second ARM instruction sequence by using the ARM computing core affinity related instructions, and add the second ARM instruction sequence to each first ARM instruction sequence to form N ARM multi-core instruction sequences; Step 6: transfer the N ARM multi-core instruction sequences to the N ARM computing cores, and each ARM computing core completes the execution of the corresponding ARM multi-core instruction sequence according to the affinity setting in the N ARM multi-core instruction sequences, and executes step 8 after all ARM computing cores have completed the execution; Step 7: Create a third ARM instruction sequence from thread creation related instructions, add the third ARM instruction sequence to each first ARM instruction sequence to form N ARM multi-threaded instruction sequences; start the execution of the N ARM multi-threaded instruction sequences in parallel, and execute step 8 after all the N ARM multi-threaded instruction sequences have completed execution; Step 8: If the executable file has not been executed, execute step 2; otherwise, complete the execution of the executable file and end this process.

2. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The value of setting the number of segments in step 3 is the result of rounding up the ratio of the product of the first element size and the length of the operand to the first word length.

3. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The method of obtaining whether the ARM processor supports setting the affinity of the CPU core in step 4 is: obtaining data of the affinity-related status register, and determining the value of a specific bit.

4. The SIMD instruction conversion optimization method according to claim 1, characterized in that: A data synchronization mechanism is added to the ARM multi-core instruction sequence, specifically in the following manner: in the first ARM instruction sequence, a shared memory area synchronization instruction is added before each ARM instruction.

5. The SIMD instruction conversion optimization method according to claim 4, characterized in that: The shared memory area synchronization instruction is a DMB instruction.

6. The SIMD instruction conversion optimization method according to claim 1, characterized in that: A data synchronization mechanism is added to the ARM multi-core instruction sequence, specifically in the following manner: the ARM multi-core instruction sequence is split into an ARM multi-core loading instruction sequence, an ARM multi-core computing instruction sequence, and an ARM multi-core storage instruction sequence, wherein the ARM multi-core loading instruction sequence is formed by adding the second ARM instruction sequence to the front of each fourth ARM instruction sequence, and the fourth ARM instruction sequence only includes ARM loading instructions; the ARM multi-core computing instruction sequence is formed by adding the second ARM instruction sequence to the front of each fifth ARM instruction sequence, and the fifth ARM instruction sequence only includes ARM computing instructions; the ARM multi-core storage instruction sequence is formed by adding the second ARM instruction sequence to the front of each sixth ARM instruction sequence, and the sixth ARM instruction sequence only includes ARM storage instructions; N ARM computing cores simultaneously execute the ARM multi-core loading instruction sequence, the ARM multi-core computing instruction sequence and the ARM multi-core storage instruction sequence in sequence.

7. The SIMD instruction conversion optimization method according to claim 1, characterized in that: A data synchronization mechanism is added to the ARM multi-threaded instruction sequence, specifically in the following manner: the ARM multi-threaded instruction sequence is formed by adding a third ARM instruction sequence before each seventh ARM instruction sequence, the seventh ARM instruction sequence comprising an ARM load instruction and a first ARM instruction; the execution of N ARM multi-threaded instruction sequences is started in parallel, and after the N ARM multi-threaded instruction sequences are all executed, the execution results of the N ARM multi-threaded instruction sequences are stored serially using an ARM storage instruction.