Pulse stream processing method and device based on multi-core processor
By splitting and combining operator units in the pulse processing flow on a multi-core processor, forming functional blocks, and automatically deploying these functional blocks, the problems of long delay, poor flexibility and low throughput in the prior art are solved, and more efficient pulse data processing is achieved.
Patent Information
- Application Number
- CN202411692675.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-03-04
AI Technical Summary
Existing pulse data processing methods lack a general-purpose, automatic deployment framework in terms of delay, poor flexibility and low throughput, especially in multi-core processor environments.
By splitting the pulse processing process into several operator units, combining the number of cores of the processor and the average running time of the operator units, the operator units are evenly combined and divided into functional blocks, and finally, each functional block is automatically deployed in a hierarchical manner on the multi-core processor, and the parallel capabilities of the multi-core processor are used to realize the flow processing of pulse data.
It improves the real-time, flexibility, versatility and throughput of pulsed data processing, and solves the problems of long delay, poor flexibility and low throughput in traditional methods.
Smart Images
Figure CN119557095A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital signal processing, and more specifically, to a pulse stream processing method and device based on a multi-core processor. Background Art
[0002] With the development of processor technology, multi-core processors are increasingly used in signal processing. Traditional sequential execution programming and batch processing design cannot give full play to the performance advantages of multi-core processors, and it is difficult to adapt to the requirements of low latency and high throughput in data signal processing. Data flow programming emphasizes data-driven. After clearly defining the connection relationship between input data and output data, it does not use command-driven. When the data is ready, that is, the input is valid, the data calculation and processing will be executed immediately.
[0003] Dataflow programming is parallel in nature. It can give full play to the performance advantages of multi-core processors and is a high-performance parallel programming model that solves the problem of efficient utilization of multi-core processors. Dataflow programming splits and deploys data processing algorithms to each core in a data-driven way, and uses the pipeline parallel characteristics of the software to fully explore the potential parallelism of data processing algorithms and achieve load balancing between each core.
[0004] In the conventional design of data flow, a static instance of a data flow program is described as a directed graph according to its structure. Each node in the graph represents a computing unit, and the edge represents the data transmission path. Each node at each level transmits and calculates data step by step, and finally outputs the data processing results.
[0005] However, in the existing pulse data processing process, the batch processing method of sequential execution is still commonly used, that is, after accumulating a certain number of pulses, data processing is performed and the processing results are output. Although this processing method can ensure the integrity of the data, the processing delay is large and it cannot meet the requirements of some real-time systems for processing delay and throughput. After the emergence of multi-core processors, although pulse processing operators can be manually deployed on different cores with the help of their parallel characteristics, there is still a lack of a universal, configurable, and automatically deployable processing framework. Manual or customized deployment methods have weak versatility and poor flexibility. Once the pulse data processing process undergoes major changes, the deployment of operators will need to be manually re-planned and redeveloped, which also increases the difficulty and repetitive workload of multi-core deployment of pulse processing. Summary of the invention
[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a pulse stream processing method and device based on a multi-core processor, which can improve the real-time performance, flexibility, versatility and throughput of pulse data processing.
[0007] The object of the present invention is achieved through the following solutions:
[0008] A pulse stream processing method based on a multi-core processor comprises the following steps:
[0009] The pulse processing process is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of processor cores and the average running time of the operator units.
[0010] The functional blocks are hierarchically deployed on the multi-core processor, and the parallel capability of the multi-core processor is utilized to realize pipeline processing of pulse data and output the processing results in real time.
[0011] Furthermore, the pulse processing process is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of processor cores and the average running time of the operator units, which specifically includes the following sub-steps:
[0012] S1, split the processing flow after obtaining the pulse description word into N operator units, and the definition of each operator unit includes: input data, output data, operator execution function pointer, operator name and operator identification information, and obtain an operator unit linked list;
[0013] S2, in core 0, through the test process, the average execution time of each operator is statistically obtained; considering the load balancing of each core, combined with the execution time of each operator and the number of processor cores, the adjacent operators are combined and divided on the operator unit linked list to obtain M function blocks; the definition of each function block includes the operator linked list, the number of operators, the function block input data, the function block output data, the function block execution function pointer and the core number to be deployed; the function blocks are connected and combined to obtain a function block linked list; in the function block execution function, the execution function of each operator is called in turn and the input and output data are passed to realize the function of the function block, and finally the processing result of the function block is output.
[0014] Furthermore, the specific process of the function block executing the function includes:
[0015] Based on the function block list, apply for inter-core communication resources and configure the inter-core communication virtual bus controller. Inter-core communication is achieved through shared memory and virtual bus controller:
[0016] S21, allocate one inter-core read data communication handle and one inter-core write data communication handle to each functional block;
[0017] S22, after obtaining the inter-core communication handles of all functional blocks, the topology information of the entire inter-core communication can be obtained, and the inter-core communication routing table is generated according to the topology information;
[0018] S23, for each group of inter-core communications, create a data exchange pipeline in the inter-core shared memory for transmitting inter-core communication data;
[0019] S24, the inter-core communication routing table and all data exchange pipeline information are stored in the virtual bus controller, and finally the virtual bus controller provides a unified interface for inter-core communication.
[0020] Furthermore, each functional block reads input data from a processor core at a previous stage through a virtual bus controller, and after completing data processing of the functional block, sends the processing result to a processor core at a subsequent stage.
[0021] Furthermore, the hierarchical deployment of each functional block on the multi-core processor, utilizing the parallel capability of the multi-core processor, realizing pipeline processing of pulse data and outputting the processing results in real time, specifically includes the following sub-steps:
[0022] By creating a template function for pulse stream processing, different functional blocks are deployed step by step on different cores in a multi-core processor, and each level of processor core uses a data-driven approach to execute the function of the current functional block.
[0023] Furthermore, the method of creating a template function for pulse stream processing deploys different functional blocks on different cores in a multi-core processor step by step, and each level of processor core uses a data-driven method to execute the function of the current functional block, specifically including the following sub-steps:
[0024] In the template function, query the current core number and match it with the deployment core number field in the function block, and then retrieve the information of the function block that can be successfully matched;
[0025] After obtaining the execution function pointer of the function block, the output data of the previous level core is read through the virtual bus controller: if there is corresponding data in the bus controller, the data is read, and the function block execution function is executed, and the processing result is sent to the next level core; if not, continue to query the bus controller.
[0026] Furthermore, the method further comprises the steps of:
[0027] In core 0, the number of pulses that have been processed is counted according to a certain period, and by comparing the number of pulses that have been processed with the number of input pulses of core 0, a decision is made as to whether to dilute the pulses: if the number of input pulses is greater than the number of pulses that have been processed, the pulses of the next period are diluted to avoid increasing the processing delay of the system due to the backlog of pulse data; if the input pulses are equal to the number of pulses that have been processed, no pulse dilution is required.
[0028] Further, in step S21, the inter-core communication handle includes a source core number, a destination core number, a name, and data length information.
[0029] Furthermore, in step S23, each of the data exchange pipes contains the requested shared memory size, data readable flag, data writable flag, transmission data length, data transfer address, source core number, destination core number and data update flag information.
[0030] A pulse stream processing device based on a multi-core processor comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, any of the above methods is executed.
[0031] The beneficial effects of the present invention include:
[0032] (1) The present invention provides a pulse stream processing method for a universal and configurable multi-core processor. Compared with the traditional method, the present invention can realize automatic deployment on a multi-core processor based on splitting the pulse processing flow into several operators, and can adapt to different pulse density scenarios, solving the problems of long delay, poor flexibility and low throughput in pulse data processing.
[0033] (2) The present invention specifically addresses the defects of existing batch-based pulse data processing methods, such as long delay, poor flexibility and low throughput, and proposes a new universal and configurable pulse stream processing framework based on a multi-core processor: by splitting the pulse processing flow into a number of operator units, and on this basis, combining the number of processor cores and the average running time of the operator units, the operator units are evenly combined and divided into functional blocks, and finally the functional blocks are automatically hierarchically deployed on the multi-core processor. With the help of the parallel capability of the multi-core processor, the pipeline processing of pulse data is realized and the processing results are output in real time, thereby improving the real-time, flexibility, universality and throughput of pulse data processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0035] Figure 1 A mapping relationship diagram of operator units, function blocks, and processor core deployment in an embodiment of the present invention;
[0036] Figure 2 This is a diagram of the inter-core communication structure of an embodiment of the present invention;
[0037] Figure 3 It is a flow chart of the function block execution template function of an embodiment of the present invention;
[0038] Figure 4 It is a flow chart of the pulse stream processing template function according to an embodiment of the present invention;
[0039] Figure 5 This is a pulse stream processing timing diagram of an embodiment of the present invention;
[0040] Figure 6 This is a simulation test scene diagram of an embodiment of the present invention. DETAILED DESCRIPTION
[0041] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.
[0042] The specific implementation process of the present invention is as follows:
[0043] In view of the technical problems of weak versatility, poor flexibility, long delay and low throughput of the existing pulse data processing methods, the solutions of the present invention are as follows:
[0044] Signal processing of non-cooperative signals usually involves extracting the time, space, and frequency domain characteristics of the pulse through signal detection and parameter measurement, generating a pulse descriptive word (PDW), and then processing the pulse descriptive word with algorithms such as sorting, positioning, identification, and tracking to ultimately obtain the various parameters of the radiation source target.
[0045] In a non-cooperative signal processing system, the extraction of pulse description words is usually implemented by hardware. Here, the present invention only discusses the processing flow after the pulse description words are obtained.
[0046] First, the processing flow after obtaining the pulse description word is divided into N operator units. The definition of each operator unit includes: input data, output data, operator execution function pointer, operator name, operator identification and other information, as shown in formula (1):
[0047] Fun i ={(DataIn i ,DataOut i ,OperPt i ,Name i ,FunID i )} (1)
[0048] Fun i Indicates the operator unit, DataIn i Indicates operator input data, DataOut i Indicates operator output data, OperPt i Indicates the operator execution function pointer, Namei Indicates the operator name, FunID i Indicates the operator identifier.
[0049] Get an operator unit linked list TotalFunList.
[0050] TotalFunList = {Fun 1 ,Fun 2 ,……,Fun N} (2)
[0051] Then, the average execution time of each operator is statistically obtained through the test process in core 0. Considering the load balancing of each core, combined with the execution time of each operator and the number of processor cores, the adjacent operators of the operators are combined and divided on the operator linked list TotalFunList to obtain M function blocks. The definition of each function block includes the operator linked list, the number of operators, the function block input data, the function block output data, the function block execution function pointer, and the core number to be deployed, as shown in formula (3):
[0052] Pro i ={(SubFunList i ,FunNum i ,DataIn i ,DataOut i ,OperPt i ,CoreNum i )} (3)
[0053] Pro i Indicates a function block, SubFunList i Indicates the operator list, FunNum i Indicates the number of operators, DataIn i Indicates the function block input data, DataOut i Indicates the function block output data, CoreNum i Indicates the number of the core to be deployed, OperPt i Indicates the function block execution function pointer.
[0054] The function blocks are connected and combined to obtain a function block list ProList. The process is as follows: Figure 1 shown.
[0055] ProList = {Pro 1 ,Pro 2 ,……,Pro N} (4)
[0056] In the function block execution function, each operator execution function is called in turn and the input and output data are passed to realize the function of the function block, and finally the processing result of the function block is output. The specific process of the function block execution function is as follows: Figure 3 shown.
[0057] On the basis of obtaining the function block list ProList, apply for inter-core communication resources and configure the inter-core communication virtual bus controller. Figure 2 As shown, inter-core communication is achieved through shared memory and a virtual bus controller:
[0058] 1) Each functional block is allocated an inter-core read data communication handle and a write data communication handle. The inter-core communication handle includes information such as the source core number, the destination core number, the name, and the data length.
[0059] 2) After obtaining the inter-core communication handles of all functional blocks, the topology information of the entire inter-core communication can be obtained, and the inter-core communication routing table is generated according to the topology information.
[0060] 3) For each group of inter-core communication, a data exchange pipeline is created in the inter-core shared memory to transmit inter-core communication data. Each data exchange pipeline contains information such as the requested shared memory size, data readable flag, data writable flag, transmission data length, data transfer address, source core number, destination core number, data update flag, etc.
[0061] 4) The inter-core communication routing table and all data exchange pipeline information are stored in the virtual bus controller, and the virtual bus controller ultimately provides a unified interface for inter-core communication.
[0062] For each functional block, it needs to read input data from the processor core of the previous level through the virtual bus controller, and after completing the data processing of the functional block, send the processing result to the processor core of the next level.
[0063] After completing the resource configuration for inter-core communication, different functional blocks are deployed on different cores in the multi-core processor step by step by creating a template function for pulse stream processing. Each level of processor core uses a data-driven approach to execute the function of the current functional block. The deployment process of each functional block is as follows: Figure 1 As shown, the template function flow of pulse stream processing is as follows Figure 4 shown.
[0064] Specifically, in the template function, the current core number is queried and matched with the deployed core number field in the function block, and the information of the function block that can be successfully matched is taken out. After obtaining the execution function pointer of the function block, the output data of the previous level core is read through the virtual bus controller: if there is corresponding data in the bus controller, the data is read, and the function block execution function is executed, and the processing result is sent to the next level core; if not, the bus controller is queried again.
[0065] In addition, in core 0, the number of pulses that have been processed is counted according to a certain period, and by comparing the number of pulses that have been processed with the number of input pulses of core 0, a decision is made as to whether to dilute the pulses: if the number of input pulses is greater than the number of pulses that have been processed, the pulses of the next period are diluted to avoid increasing the processing delay of the system due to the backlog of pulse data; if the input pulses are equal to the number of pulses that have been processed, there is no need to dilute the pulses.
[0066] By counting, comparing and diluting the number of processed pulses, adaptive control of the number of pulses is achieved, so that the pulse stream processing on the multi-core processor can both maximize the processing capability and avoid untimely pulse processing, which leads to a backlog of pulse data and increased system delay, so as to achieve the purpose of being able to dynamically adapt to different pulse density scenarios of non-cooperative signals.
[0067] In other embodiments of the present invention, experimental verification is performed by setting up and installing sensor equipment, antenna arrays, and signal simulators in a microwave darkroom, such as Figure 6 The sensor is equipped with a domestic FT-M6678 processor, which performs preprocessing, angle measurement, clustering, and sorting of pulse data, and outputs the data to the test simulation equipment for recording and analysis after processing. The specific implementation steps are as follows:
[0068] Step 1: Decompose the pulse processing flow into six operators: preprocessing (PreSort), angle measurement (AngleMeasure), clustering (Cluster), repetition frequency sorting (PriSort), modulation mode recognition (ModRec), and automatic gain control (AGC).
[0069] Step 2: According to the definition of formula (1), configure the members of each operator structure to obtain the operator linked list TotalFunList, which contains 6 operators in total.
[0070] Step 3: Set up a signal simulator to transmit electromagnetic wave signals through the antenna array.
[0071] Step 4: Start the sensor test process, receive electromagnetic wave signals, generate pulse data, call the operators in the operator list in sequence in FT-M6678, complete the entire pulse processing process, and complete the operator time performance statistics to obtain the average running time of each operator. The statistical results are shown in Table 1.
[0072] Step 5, according to the average running time of each operator, adjacent operators are combined and divided to obtain the function block list ProList, which contains 4 function blocks in total: function block 1 contains a preprocessing operator, function block 2 contains an angle measurement operator, function block 3 contains a clustering operator, and function block 4 contains a repetition frequency sorting operator, a modulation mode recognition operator, and an automatic gain control operator.
[0073] Step 6, according to the member definition in the function block linked list ProList, apply for the inter-core communication dedicated data exchange channel between adjacent function blocks, generate the inter-core communication routing table, and complete the configuration of the inter-core communication virtual bus controller.
[0074] Step 7, execute the pulse stream processing module function, deploy the four functional blocks to cores 0 to 3 respectively, and output the processing results to the simulation test device, such as Figure 5 shown.
[0075] By setting different signal simulator parameters and antenna positions, the pulse processing flow under the multi-core stream processing framework is tested, and the test results are shown in Table 2. As can be seen from Table 2, when setting different pulse densities, carrier frequencies, debugging methods, and antenna positions, correct processing results can be obtained, and the number of processed pulses can be adaptively adjusted as the pulse density changes, and the total processing delay is about 3ms, which meets the real-time requirements.
[0076] Table 1 Operator time performance
[0077]
[0078] Table 2 Test results
[0079]
[0080]
[0081] From the above verification, it can be seen that the present invention, based on the operator splitting and combination of the pulse signal processing flow, uses the parallel characteristics of multi-core processors to construct a universal and configurable pulse stream processing framework. This method can improve the versatility, flexibility, and real-time performance of pulse stream data processing, and can achieve adaptation to signals with different pulse densities.
[0082] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.
[0083] Example 1
[0084] A pulse stream processing method based on a multi-core processor comprises the following steps:
[0085] The pulse processing process is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of processor cores and the average running time of the operator units.
[0086] The functional blocks are hierarchically deployed on the multi-core processor, and the parallel capability of the multi-core processor is utilized to realize pipeline processing of pulse data and output the processing results in real time.
[0087] Example 2
[0088] On the basis of Example 1, the pulse processing flow is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of cores of the processor and the average running time of the operator units, specifically including the sub-steps:
[0089] S1, split the processing flow after obtaining the pulse description word into N operator units, and the definition of each operator unit includes: input data, output data, operator execution function pointer, operator name and operator identification information, and obtain an operator unit linked list;
[0090] S2, in core 0, through the test process, the average execution time of each operator is statistically obtained; considering the load balancing of each core, combined with the execution time of each operator and the number of processor cores, the adjacent operators are combined and divided on the operator unit linked list to obtain M function blocks; the definition of each function block includes the operator linked list, the number of operators, the function block input data, the function block output data, the function block execution function pointer and the core number to be deployed; the function blocks are connected and combined to obtain a function block linked list; in the function block execution function, the execution function of each operator is called in turn and the input and output data are passed to realize the function of the function block, and finally the processing result of the function block is output.
[0091] Example 3
[0092] Based on Example 2, the specific process of the function block executing the function includes:
[0093] Based on the function block list, apply for inter-core communication resources and configure the inter-core communication virtual bus controller. Inter-core communication is achieved through shared memory and virtual bus controller:
[0094] S21, allocate one inter-core read data communication handle and one inter-core write data communication handle to each functional block;
[0095] S22, after obtaining the inter-core communication handles of all functional blocks, the topology information of the entire inter-core communication can be obtained, and the inter-core communication routing table is generated according to the topology information;
[0096] S23, for each group of inter-core communications, create a data exchange pipeline in the inter-core shared memory for transmitting inter-core communication data;
[0097] S24, the inter-core communication routing table and all data exchange pipeline information are stored in the virtual bus controller, and finally the virtual bus controller provides a unified interface for inter-core communication.
[0098] Example 4
[0099] On the basis of Embodiment 3, each functional block reads input data from the processor core of the previous stage through the virtual bus controller, and after completing the data processing of the functional block, sends the processing result to the processor core of the next stage.
[0100] Example 5
[0101] On the basis of Example 1, the hierarchical deployment of each functional block on the multi-core processor, using the parallel capability of the multi-core processor, realizes the pipeline processing of pulse data and outputs the processing results in real time, specifically including the following sub-steps:
[0102] By creating a template function for pulse stream processing, different functional blocks are deployed step by step on different cores in a multi-core processor, and each level of processor core uses a data-driven approach to execute the function of the current functional block.
[0103] Example 6
[0104] On the basis of Example 5, the template function for pulse stream processing is created to deploy different functional blocks on different cores in the multi-core processor step by step, and each level of processor core uses a data-driven method to execute the function of the current functional block, which specifically includes sub-steps:
[0105] In the template function, query the current core number and match it with the deployment core number field in the function block, and then retrieve the information of the function block that can be successfully matched;
[0106] After obtaining the execution function pointer of the function block, the output data of the previous level core is read through the virtual bus controller: if there is corresponding data in the bus controller, the data is read, and the function block execution function is executed, and the processing result is sent to the next level core; if not, continue to query the bus controller.
[0107] Example 7
[0108] On the basis of Example 1, the method further comprises the following steps:
[0109] In core 0, the number of pulses that have been processed is counted according to a certain period, and by comparing the number of pulses that have been processed with the number of input pulses of core 0, a decision is made as to whether to dilute the pulses: if the number of input pulses is greater than the number of pulses that have been processed, the pulses of the next period are diluted to avoid increasing the processing delay of the system due to the backlog of pulse data; if the input pulses are equal to the number of pulses that have been processed, no pulse dilution is required.
[0110] Example 8
[0111] Based on Example 1, in step S21, the inter-core communication handle includes the source core number, the destination core number, the name, and the data length information.
[0112] Example 9
[0113] Based on Example 1, in step S23, each of the data exchange pipes contains the requested shared memory size, data readable flag, data writable flag, transmission data length, data transfer address, source core number, destination core number and data update flag information.
[0114] Example 10
[0115] A pulse stream processing device based on a multi-core processor includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method described in any one of Embodiments 1 to 8 is executed.
[0116] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.
[0117] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.
[0118] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.
Claims
1. A pulse stream processing method based on a multi-core processor, characterized in that: The following steps are involved: The pulse processing process is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of processor cores and the average running time of the operator units. The functional blocks are hierarchically deployed on the multi-core processor, and the parallel capability of the multi-core processor is utilized to realize pipeline processing of pulse data and output the processing results in real time.
2. The pulse stream processing method based on a multi-core processor according to claim 1, characterized in that: The pulse processing process is split into several operator units, and on this basis, the operator units are evenly combined and divided into functional blocks in combination with the number of processor cores and the average running time of the operator units, which specifically includes the following sub-steps: S1, split the processing flow after obtaining the pulse description word into N operator units, and the definition of each operator unit includes: input data, output data, operator execution function pointer, operator name and operator identification information, and obtain an operator unit linked list; S2, in core 0, through the test process, the average execution time of each operator is statistically obtained; considering the load balancing of each core, combined with the execution time of each operator and the number of processor cores, the adjacent operators are combined and divided on the operator unit linked list to obtain M function blocks; the definition of each function block includes the operator linked list, the number of operators, the function block input data, the function block output data, the function block execution function pointer and the core number to be deployed; the function blocks are connected and combined to obtain a function block linked list; in the function block execution function, the execution function of each operator is called in turn and the input and output data are passed to realize the function of the function block, and finally the processing result of the function block is output.
3. The pulse stream processing method based on a multi-core processor according to claim 2, characterized in that: The specific process of the function block executing the function includes: Based on the function block list, apply for inter-core communication resources and configure the inter-core communication virtual bus controller. Inter-core communication is achieved through shared memory and virtual bus controller: S21, allocate one inter-core read data communication handle and one inter-core write data communication handle to each functional block; S22, after obtaining the inter-core communication handles of all functional blocks, the topology information of the entire inter-core communication can be obtained, and the inter-core communication routing table is generated according to the topology information; S23, for each group of inter-core communications, create a data exchange pipeline in the inter-core shared memory for transmitting inter-core communication data; S24, the inter-core communication routing table and all data exchange pipeline information are stored in the virtual bus controller, and finally the virtual bus controller provides a unified interface for inter-core communication.
4. The pulse stream processing method based on a multi-core processor according to claim 3, characterized in that: Each functional block reads input data from the processor core of the previous level through the virtual bus controller, and after completing the data processing of the functional block, sends the processing result to the processor core of the next level.
5. The pulse stream processing method based on a multi-core processor according to claim 1, characterized in that: The step of hierarchically deploying each functional block on a multi-core processor and utilizing the parallel capability of the multi-core processor to realize pipeline processing of pulse data and output the processing result in real time specifically includes the following sub-steps: By creating a template function for pulse stream processing, different functional blocks are deployed step by step on different cores in a multi-core processor, and each level of processor core uses a data-driven approach to execute the function of the current functional block.
6. The pulse stream processing method based on a multi-core processor according to claim 5, characterized in that: The method of creating a template function for pulse stream processing deploys different functional blocks on different cores in a multi-core processor step by step, and each level of processor core uses a data-driven method to execute the function of the current functional block, specifically including the following sub-steps: In the template function, query the current core number and match it with the deployment core number field in the function block, and then retrieve the information of the function block that can be successfully matched; After obtaining the execution function pointer of the function block, the output data of the previous level core is read through the virtual bus controller: if there is corresponding data in the bus controller, the data is read, and the function block execution function is executed, and the processing result is sent to the next level core; if not, continue to query the bus controller.
7. The pulse stream processing method based on a multi-core processor according to claim 1, characterized in that: Also includes the steps: In core 0, the number of pulses that have been processed is counted according to a certain period, and by comparing the number of pulses that have been processed with the number of input pulses of core 0, a decision is made as to whether to dilute the pulses: if the number of input pulses is greater than the number of pulses that have been processed, the pulses of the next period are diluted to avoid increasing the processing delay of the system due to the backlog of pulse data; if the input pulses are equal to the number of pulses that have been processed, no pulse dilution is required.
8. The pulse stream processing method based on a multi-core processor according to claim 1, characterized in that: In step S21, the inter-core communication handle includes the source core number, the destination core number, the name, and the data length information.
9. The pulse stream processing method based on a multi-core processor according to claim 1, characterized in that: In step S23, each of the data exchange pipes contains the requested shared memory size, data readable flag, data writable flag, transmission data length, data transfer address, source core number, destination core number and data update flag information.
10. A pulse stream processing device based on a multi-core processor, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 8 is executed.