A method and system for designing a DMA engine module based on FPGA

Abstract

The application belongs to the technical field of PCIE high-speed serial interface, and discloses a design method and system of a DMA engine module based on FPGA.The system comprises a DMA sending engine module, a DMA receiving engine module and a DMA interrupt module.The application is provided with preset double channels for frequency selection or different mode selection, the channels are in full-duplex mode, the outgoing and incoming are not interfered with each other and are completely controllable.The back transmission comparison self-checking function is added, so that whether the current channel is running normally or not can be judged quickly and conveniently.The DMA sending and receiving state machine transfer method provided by the application can realize more efficient transmission on the premise of using fewer resources.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of PCIE high-speed serial interface, and particularly relates to a design method and system of a DMA engine module based on FPGA. BACKGROUND

[0002] With the increasing requirement of bandwidth of modern communication system, the bus performance is gradually upgraded, and the traditional bus has been eliminated because it cannot adapt to the requirement of high-speed data transmission. The application field of PCI technology has been greatly limited after continuous revision and development. The PCIE bus has a good application prospect because it greatly improves the transmission rate. The PCIE can effectively solve the defects of the PCI bus, can provide greater bus bandwidth, and the bus frequency of PCIE V3.0 can reach 4Ghz at most.

[0003] Through the above analysis, the problems and defects of the prior art are that the DMA receiving function and the sending function of PCIE cannot be realized by using fewer FPGA logic resources in the prior art communication, and the transmission efficiency is low. SUMMARY

[0004] In order to overcome the problems in the related art, the application discloses a design method and system of a DMA engine module based on FPGA, and particularly relates to a design method of a DMA engine module based on FPGA k7 series PCIE interface.

[0005] The technical solution is as follows: a design system of a DMA engine module based on FPGA, which comprises:

[0006] A DMA sending engine module is used to execute corresponding enable control mode by judging invalid state of DMA write arbitration request and read arbitration request, and judging valid indication signal of internal cache space of IP core, and to determine binary count size of flow control counter.

[0007] A DMA receiving engine module is used to execute receiving packet TLP packet header data and receiving packet TLP data load by judging length signal marker and receiving error indication signal marker, and to store in a memory.

[0008] A DMA interrupt module is used to execute corresponding read and write interrupt request signals and corresponding interrupt response by judging MSI interrupt enable and legacy interrupt enable.

[0009] The signal sending of the DMA sending engine module and the signal receiving of the DMA receiving engine module (2) are independent and do not interfere with each other.

[0010] The bus master DMA uses a device on the bus as a DMA controller, and the DMA controller controls the whole transmission process of the DMA by configuring the DMA register configured by the user to directly carry data to a storage unit in the computer memory.

[0011] Another object of the present application is to provide a FPGA-based DMA engine module design method, comprising:

[0012] The designed DMA sending engine module judges the invalid state of the DMA write arbitration request and the read arbitration request, judges the valid indication signal of the internal cache space of the IP core, executes the corresponding enable control mode, and determines the binary count size of the flow control counter;

[0013] The signal sent by the DMA sending engine module is received, and the designed DMA receiving engine module executes the receiving of the TLP packet header data and the receiving of the TLP data payload by judging the length signal marker and the receiving error indication signal marker, and stores them in the memory;

[0014] The designed DMA interrupt module executes the corresponding read / write interrupt request signal and the corresponding interrupt response by judging the MSI interrupt enable and the legacy interrupt enable.

[0015] Further, the DMA sending engine module design comprises:

[0016] (1) Wait for the PCIE link indication signal to be pulled high;

[0017] (2) The DMA write arbitration request and the read arbitration request are invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the internal cache space valid indication signal of the IP core is 1, and the bus master mode is enabled;

[0018] (3) The DMA write arbitration request and the read arbitration request are invalid, the DMA read start signal is pulled high, the internal cache space valid indication signal of the IP core is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16;

[0019] (4) The DMA write arbitration request and the read arbitration request are invalid, the internal cache space valid indication signal of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0020] (5) The DMA write arbitration request and the read arbitration request are invalid, the internal cache space valid indication signal of the IP core is 1, and the bar1 read operation request signal is pulled high;

[0021] (6) The packet header information of the TIP message is sent, and one clock cycle is maintained;

[0022] (7) Send the header information and data information of the TIP packet, and maintain one clock cycle;

[0023] (8) Send the data information of the TIP packet, and maintain 254 clock cycles;

[0024] (9) Send the last 32 bits of data of the TIP packet, and calculate the number of TIP packets, and maintain one clock cycle;

[0025] (10) The TIP packet sending is completed, and the next state is entered.

[0026] Further, after step (10), the following is performed:

[0027] (11) The IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high;

[0028] (12) The IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high;

[0029] (13) The DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16;

[0030] (14) The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0031] Further, after step (14), the following is performed:

[0032] (a) Send the memory read request packet header 1, and maintain one clock cycle;

[0033] (b) Send the memory read request packet header 2, and maintain one clock cycle;

[0034] (c) Send the memory read request packet number completion, and maintain one clock cycle;

[0035] (d) The IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high;

[0036] The IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high;

[0037] The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled;

[0038] DMA read arbitration request invalid, DMA read start signal pulled high, IP core internal cache space valid indication signal is 1, bus master mode enabled, non-forwarding mode enabled, flow control counter not equal to 16.

[0039] (e) maintain a clock cycle;

[0040] Send read bar0 CPLD completion message packet header 1, maintain a clock cycle;

[0041] Send read bar0 CPLD completion message packet header 2, maintain a clock cycle;

[0042] IP core internal cache space valid indication signal is 1, bar1 read operation request signal pulled high;

[0043] DMA write arbitration request invalid, DMA write start signal pulled high, cache data FIFO data is non-empty state, IP core internal cache space valid indication signal is 1, bus master mode enabled;

[0044] DMA read arbitration request invalid, DMA read start signal pulled high, IP core internal cache space valid indication signal is 1, bus master mode enabled, non-forwarding mode enabled, flow control counter not equal to 16.

[0045] (f) send read bar1 CPLD completion message packet header 1, maintain a clock cycle;

[0046] Send read bar1 CPLD completion message packet header 2, maintain a clock cycle;

[0047] IP core internal cache space valid indication signal is 1, bar0 read operation request signal pulled high;

[0048] DMA write arbitration request invalid, DMA write start signal pulled high, cache data FIFO data is non-empty state, IP core internal cache space valid indication signal is 1, bus master mode enabled;

[0049] DMA read arbitration request invalid, DMA read start signal pulled high, IP core internal cache space valid indication signal is 1, bus master mode enabled, non-forwarding mode enabled, flow control counter not equal to 16.

[0050] Further, the DMA receive engine module design includes:

[0051] (i) wait for PCIE link indication signal pulled high;

[0052] (ii) TYPE is a completion packet format type, CS is 0, receive error indication signal is 0, read start signal pulled high;

[0053] length signal is 1, the receive error indication signal is 0, and the TYPE is a memory write request packet format, the bar0 write operation indication signal is pulled high;

[0054] length signal is 1, the receive error indication signal is 0, and the TYPE is a memory write request packet format, the bar1 write operation indication signal is pulled high;

[0055] length signal is 1, the receive error indication signal is 0, and the TYPE is a memory read request packet format, the bar0 read operation indication signal is pulled high;

[0056] length signal is 1, the receive error indication signal is 0, and the TYPE is a memory read request packet format, the bar1 read operation indication signal is pulled high;

[0057] (iii) bar0 write operation completion;

[0058] bar1 write operation completion;

[0059] bar0 read arbitration;

[0060] bar0 read completion;

[0061] bar1 read arbitration;

[0062] bar1 read completion;

[0063] (iv) receive completion packet TLP packet header data completion;

[0064] receive completion packet TLP data payload completion.

[0065] Further, the DMA interrupt module design includes:

[0066] Step 1, wait for the PCIE link indication signal to be pulled high;

[0067] Step 2, MSI interrupt enable, DMA write completion MSI interrupt request signal is pulled high;

[0068] MSI interrupt enable, DMA read completion MSI interrupt request signal is pulled high;

[0069] MSI interrupt enable, DMA external request interrupt request signal is pulled high;

[0070] Step 3, legacy interrupt enable, DMA write completion legacy interrupt request signal is pulled high;

[0071] legacy interrupt enable, DMA read completion legacy interrupt request signal is pulled high;

[0072] Legacy interrupt enable, DMA external legacy interrupt request signal is pulled high;

[0073] Legacy interrupt enable, DMA write completion legacy interrupt release request signal is pulled high;

[0074] Legacy interrupt enable, DMA read completion legacy interrupt release request signal is pulled high;

[0075] Legacy interrupt enable, DMA external legacy interrupt release request signal is pulled high;

[0076] Step 3, maintaining a clock cycle;

[0077] Step 4, receiving an MSI interrupt response signal;

[0078] Maintaining a clock cycle;

[0079] Step 5, receiving a legacy interrupt response signal;

[0080] Maintaining a clock cycle, releasing interrupt information configuration;

[0081] Receiving a legacy interrupt response signal.

[0082] Further, the FPGA-based DMA engine module design method runs in a functional logic state machine and performs communication transmission.

[0083] In combination with all the above technical solutions, the present application has the beneficial effects that: PCIE has two working modes, one is PIO working mode, and the other is DMA working mode, PIO is mainly applied to small data or double-word transmission, DMA is mainly applied to data block transmission, and is suitable for large data transmission, the larger the data volume, the more obvious the advantages of the DMA working mode. In order to realize high-speed PCIE transmission, the present application provides an FPGA-based Endpoint state machine transfer and design method based on FPGA. The DMA receiving function and sending function of PCIE are realized by using less FPGA logic resources. A double channel is preset for frequency selection or different mode selection, the channel is full-duplex mode, the transmission and the incoming do not interfere with each other, and are completely controllable. The back transmission comparison self-checking function is added, so that the running normality of the current channel can be judged quickly and conveniently. The DMA sending and receiving state machine transfer method provided by the present application can realize more efficient transmission under the premise of using less resources. BRIEF DESCRIPTION OF DRAWINGS

[0084] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure;

[0085] Figure 1 is a schematic diagram of a FPGA-based DMA engine module design system provided by an embodiment of the present application;

[0086] In the figure: 1, DMA sending engine module; 2, DMA receiving engine module; 3, DMA interrupt module. DETAILED DESCRIPTION

[0087] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of ways other than those specifically described herein, and the present application is not limited to the embodiments described herein as long as they do not depart from the spirit of the present application. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the scope of the present application.

[0088] In Embodiment 1, if a common PIO (Programming I / O) sending mechanism is used, only one double word can be sent at a time, and the CPU in the computer needs to participate in the sending. When a large amount of data is sent, the CPU cannot perform other work, which seriously affects the performance of the computer.

[0089] Therefore, the FPGA-based DMA engine module design system provided by an embodiment of the present application uses a DMA (Direct Memory Access) mechanism to perform large-capacity data transmission, and bypasses the CPU through DMA transmission. The essence of DMA transmission is to directly copy data from one address space to another address space, and the CPU is only used for initialization and related control, and the transmission process is completed by the DMA controller. DMA can be divided into system DMA and bus master DMA (Bus Master DMA), which are described as follows: One is system DMA, which uses a separate DMA controller on the bus to control DMA transmission between two devices on the bus. The other is bus master DMA, which uses a device on the bus to act as a DMA controller to control the DMA transmission of the master device and the slave device.

[0090] The FPGA-based DMA engine module design system provided by the present application uses bus master DMA, and the user configures the DMA register. The DMA controller controls the entire transmission process of the DMA by configuring the register, that is, directly moves the data to a certain storage unit in the computer memory.

[0091] Theoretically, a large amount of data can be transported at a time, but in actual transmission, the CPU cannot allocate a large continuous memory space at a time. Therefore, it is necessary to perform multiple DMA transmissions, interrupt the CPU processor after each transmission is completed, and then the CPU reconfigures the DMA. The following are the core steps to realize the DMA receiving and sending function, which is responsible for the control of the DMA transmission process. The function logic state machine of the FPGA-based DMA engine module is analyzed as follows.

[0092] As shown in Figure 1 The FPGA-based DMA engine module design system includes: a DMA sending engine module 1, which executes corresponding enable control mode by judging the invalid state of DMA write arbitration request and read arbitration request, and judging the valid indication signal of the internal cache space of the IP core, and determines the binary count size of the flow control counter;

[0093] A DMA receiving engine module 2 is used to execute receiving packet TLP packet header data and receiving packet TLP data load by judging the length signal marker and the receiving error indication signal marker, and storing in the memory;

[0094] A DMA interrupt module 3 is used to execute corresponding read and write interrupt request signals and corresponding interrupt responses by judging the MSI interrupt enable and the legacy interrupt enable.

[0095] The application also provides a FPGA-based DMA engine module design method, comprising:

[0096] The designed DMA sending engine module is used to judge the invalid state of DMA write arbitration request and read arbitration request, and judge the valid indication signal of the internal cache space of the IP core, execute corresponding enable control mode, and determine the binary count size of the flow control counter;

[0097] The signal sent by the DMA sending engine module is received, and the designed DMA receiving engine module is used to execute receiving packet TLP packet header data and receiving packet TLP data load by judging the length signal marker and the receiving error indication signal marker, and storing in the memory;

[0098] The designed DMA interrupt module is used to execute corresponding read and write interrupt request signals and corresponding interrupt responses by judging the MSI interrupt enable and the legacy interrupt enable.

[0099] The DMA sending engine module 1 is designed as follows:

[0100] First, wait for the PCIE link indication signal to be pulled high;

[0101] Further, the DMA write arbitration request and the read arbitration request are invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0102] Further, the DMA write arbitration request and the read arbitration request are invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0103] Further, the DMA write arbitration request and the read arbitration request are invalid, the IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high.

[0104] Further, the DMA write arbitration request and the read arbitration request are invalid, the IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high.

[0105] Further, the header information of the TIP packet is sent, and one clock cycle is maintained.

[0106] Further, the header information and the data information of the TIP packet are sent, and one clock cycle is maintained.

[0107] Further, the data information of the TIP packet is sent, and 254 clock cycles are maintained.

[0108] Further, the last 32 bits of data of the TLP packet are sent, and the number of TLP packets is calculated, and one clock cycle is maintained.

[0109] Further, the TLP packet is sent, and the next state is entered.

[0110] Further, the IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high.

[0111] Further, the IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high.

[0112] Further, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0113] Further, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0114] Further, the memory read request packet header 1 is sent, and a clock cycle is maintained;

[0115] Further, the memory read request packet header 2 is sent, and a clock cycle is maintained;

[0116] Further, the memory read request packet number completion is sent, and a clock cycle is maintained;

[0117] Further, the IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high;

[0118] Further, the IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high;

[0119] Further, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0120] Further, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0121] Further, a clock cycle is maintained;

[0122] Further, the read bar0 CPLD completion packet header 1 is sent, and a clock cycle is maintained;

[0123] Further, the read bar0 CPLD completion packet header 2 is sent, and a clock cycle is maintained;

[0124] Further, the IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high;

[0125] Further, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0126] Further, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0127] Further, the read bar1 CPLD completion packet header 1 is sent, and a clock cycle is maintained;

[0128] Further, the read bar1 CPLD completion packet header 2 is sent, and a clock cycle is maintained;

[0129] Further, the IP core internal cache space effective indication signal is 1, and the bar0 read operation request signal is pulled high;

[0130] Further, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space effective indication signal is 1, and the bus master mode is enabled.

[0131] Further, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space effective indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0132] The DMA receiving engine module is designed as follows:

[0133] First, the PCIE link indication signal is pulled high;

[0134] Further, the TYPE is a complete packet format type, the CS is 0, the receiving error indication signal is 0, and the read start signal is pulled high.

[0135] Further, the length signal flag is 1, the receiving error indication signal is 0, the TYPE is a memory write request packet format, and the bar0 write operation indication signal is pulled high.

[0136] Further, the length signal flag is 1, the receiving error indication signal is 0, the TYPE is a memory write request packet format, and the bar1 write operation indication signal is pulled high.

[0137] Further, the length signal flag is 1, the receiving error indication signal is 0, the TYPE is a memory read request packet format, and the bar0 read operation indication signal is pulled high.

[0138] Further, the length signal flag is 1, the receiving error indication signal is 0, the TYPE is a memory read request packet format, and the bar1 read operation indication signal is pulled high.

[0139] Further, the bar0 write operation is completed.

[0140] Further, the bar1 write operation is completed.

[0141] Further, the bar0 read arbitration is performed.

[0142] Further, the bar0 read operation is completed.

[0143] Further, the bar1 read arbitration is performed.

[0144] Further, the bar1 read operation is completed.

[0145] Further, the receive completion packet TLP packet header data is completed.

[0146] Further, the receive completion packet TLP data payload is completed.

[0147] DMA interrupt module design:

[0148] First, wait for the PCIE link indication signal to pull high;

[0149] Further, the MSI interrupt is enabled, and the DMA write completion MSI interrupt request signal is pulled high;

[0150] Further, the MSI interrupt is enabled, and the DMA read completion MSI interrupt request signal is pulled high;

[0151] Further, the MSI interrupt is enabled, and the DMA external request interrupt request signal is pulled high;

[0152] Further, the legacy interrupt is enabled, and the DMA write completion legacy interrupt request signal is pulled high;

[0153] Further, the legacy interrupt is enabled, and the DMA read completion legacy interrupt request signal is pulled high;

[0154] Further, the legacy interrupt is enabled, and the DMA external legacy interrupt request signal is pulled high;

[0155] Further, the legacy interrupt is enabled, and the DMA write completion legacy interrupt release request signal is pulled high;

[0156] Further, the legacy interrupt is enabled, and the DMA read completion legacy interrupt release request signal is pulled high;

[0157] Further, the legacy interrupt is enabled, and the DMA external legacy interrupt release request signal is pulled high;

[0158] Further, maintain a clock cycle;

[0159] Further, the MSI interrupt response signal is received;

[0160] Further, maintain a clock cycle;

[0161] Further, the legacy interrupt response signal is received;

[0162] Further, maintain a clock cycle, and release the interrupt information configuration;

[0163] Further, the legacy interrupt response signal is received.

[0164] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0165] The information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the embodiment of the method of the present invention. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0166] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0167] An embodiment of the present invention also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps of any of the above-mentioned method embodiments when executing the computer program.

[0168] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0169] An embodiment of the present invention also provides an information data processing terminal, which is used to provide a user input interface to implement the steps in the above-mentioned method embodiments when executed on an electronic device. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0170] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0171] The embodiment of the present application provides a computer program product, when the computer program product runs on an electronic device, causes the electronic device to execute the steps in each method embodiment.

[0172] The integrated unit, if in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods, which can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer readable storage medium, and the computer program can implement the steps of each method embodiment when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunications signal and a software distribution medium. For example, a U disk, a mobile hard disk, a magnetic disk or an optical disk.

[0173] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any modification, equivalent replacement and improvement within the technical range disclosed by the present application, which is made by any person skilled in the art and is within the spirit and principle of the present application, should be covered within the protection scope of the present application.

Claims

1. A DMA engine module design system based on FPGA, characterized in that: The system includes: The DMA sending engine module (1) executes the corresponding enable control mode and determines the binary count size of the flow control counter by judging the invalid state of the DMA write arbitration request and the read arbitration request, and judging the valid indication signal of the internal cache space of the IP core; The DMA receiving engine module (2) is used to execute receiving packet TLP header data and receiving packet TLP data load by judging the length signal identifier and the receiving error indication signal identifier, and store them in the memory; The DMA interrupt module (3) is used to execute the corresponding read and write interrupt request signals and execute the corresponding interrupt response by judging whether the MSI interrupt is enabled and the legacy interrupt is enabled; The DMA send engine module (1) design includes: (1) Wait for the PCIE link indication signal to go high; (2) DMA write arbitration request and read arbitration request are invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled; (3) DMA write arbitration request and read arbitration request are invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16; (4) DMA write arbitration request and read arbitration request are invalid, the IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high; (5) DMA write arbitration request and read arbitration request are invalid, the IP core internal cache space valid indication signal is 1, and the bar1 read operation request signal is pulled high; (6) Send the header information of the TIP message, maintaining one clock cycle; (7) Send the header information and data information of the TIP message, maintaining one clock cycle; (8) Send the data information of the TIP message, maintaining 254 clock cycles; (9) Send the last 32 bits of data of the TLP message and calculate the number of TLP messages, maintaining one clock cycle; (10) The TLP message is sent and enters the next state.

2. The FPGA-based DMA engine module design system according to claim 1, characterized in that: The signal transmission of the DMA transmission engine module (1) and the signal reception of the DMA reception engine module (2) do not interfere with each other and operate independently.

3. The FPGA-based DMA engine module design system according to claim 1, wherein: The system uses bus-master DMA, which uses the device on the bus as a DMA controller. The DMA controller controls the entire DMA transfer process by configuring user-configured DMA registers and directly moves data to a storage unit in the computer memory.

4. A DMA engine module design method based on FPGA, characterized in that: The method is applied to the FPGA-based DMA engine module design system according to any one of claims 1 to 3, and the method includes: The designed DMA sending engine module (1) is used to judge the invalid state of DMA write arbitration request and read arbitration request, as well as the valid indication signal of the internal cache space of the IP core, to execute the corresponding enable control mode, and to determine the binary count size of the flow control counter; Receive the signal sent by the DMA sending engine module (1), and use the designed DMA receiving engine module (2) to judge the length signal identifier and the reception error indication signal identifier, execute the reception packet TLP header data and the reception packet TLP data load, and store them in the memory; The designed DMA interrupt module (3) is used to judge whether the MSI interrupt is enabled and the legacy interrupt is enabled, and then the corresponding read and write interrupt request signals and the corresponding interrupt response are executed respectively.

5. The FPGA-based DMA engine module design method according to claim 4, wherein: After step (10), proceed with: (11) The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; (12) The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; (13) The DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16; (14) The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

6. The FPGA-based DMA engine module design method according to claim 5, wherein: After step (14), you need to do the following: (a) Send the memory read request packet header 1, which lasts for one clock cycle; (b) Send the memory read request packet header 2, which lasts for one clock cycle; (c) Sending the memory read request message is completed, and it lasts for one clock cycle; (d) The IP core internal cache space valid indication signal is 1, and the bar0 read operation request signal is pulled high; The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled; The DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16; (e) maintain one clock cycle; Send the read bar0 CPLD completion message packet header 1, maintaining one clock cycle; Send the read bar0 CPLD completion message packet header 2, maintaining one clock cycle; The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled; The DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16; (f) Send the read bar1 CPLD to complete the message packet header 1, which lasts for one clock cycle; Send the read bar1 CPLD to complete the message packet header 2, which lasts for one clock cycle; The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled; The DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

7. The FPGA-based DMA engine module design method according to claim 4, wherein: The DMA receive engine module design includes: (i) Wait for the PCIE link indication signal to go high; (ii) TYPE is the completion packet format type, CS is 0, the receive error indication signal is 0, and the read start signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and the TYPE is the memory write request packet format, and the bar0 write operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and the TYPE is the memory write request packet format, and the bar1 write operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and the TYPE is the memory read request packet format, and the bar0 read operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and the TYPE is the memory read request packet format, and the bar1 read operation indication signal is pulled high; (iii) The write operation of bar0 is completed; bar1 write operation completed; bar0 read arbitration; bar0 read completed; bar1 read arbitration; bar1 read completed; (iv) Receiving the TLP header data of the completion packet; The receiving completion packet TLP data payload is completed.

8. The FPGA-based DMA engine module design method according to claim 4, wherein: The DMA interrupt module design includes: Step 1: Wait for the PCIE link indication signal to go high. Step 2: MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA writing is completed; MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA read is completed; MSI interrupt is enabled, and the DMA external request interrupt request signal is pulled high; Step 3: Enable the legacy interrupt and pull the legacy interrupt request signal high when DMA write is completed. The legacy interrupt is enabled, and the DMA read completion legacy interrupt request signal is pulled high; Legacy interrupt is enabled, and the DMA external legacy interrupt request signal is pulled high; The legacy interrupt is enabled, and the DMA write completion legacy interrupt release request signal is pulled high; The legacy interrupt is enabled, and the DMA read completion legacy interrupt release request signal is pulled high; Legacy interrupt is enabled, please release the DMA external legacy interrupt request signal and pull it high; Step 3, maintain one clock cycle; Step 4, receiving the MSI interrupt response signal; Maintain one clock cycle; Step 5: Receive the legacy interrupt response signal; Maintain one clock cycle to release the interrupt information configuration; Receive legacy interrupt response signal.

9. The FPGA-based DMA engine module design method according to claim 4, wherein: This method runs on the functional logic state machine to perform communication transmission.

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