Heterogeneous core particle modeling method, system, device and readable storage medium based on SST framework and SystemC simulator

Abstract

The present invention relates to the technical field of computer structure simulation, and in particular to a heterogeneous core particle modeling method, system, device and readable storage medium based on an SST framework and a SystemC simulator, wherein a simulator is configured for each core particle so that each core particle is implemented in a corresponding simulator respectively, and the simulator uses SystemC to construct a corresponding simulation code; each core particle simulator uses an external interface to instantiate and integrate SST components under a structure simulation toolkit to obtain a target model, so as to interconnect and simulate multiple core particle simulators through the target model, and the structure simulation toolkit uses an SST framework and the clocks of the SST components of each core particle simulator in the SST framework are synchronized; and each core particle simulator is provided with an identifier for indicating the state of the simulator itself sending data to the outside and a reserved memory address space for writing user or structure simulation toolkit data into the simulator. The present invention integrates multiple SystemC simulators under the SST framework, and can realize simulation modeling of a multi-core heterogeneous system.

Description

Technical Field

[0001] The present invention relates to the technical field of computer structure simulation, and in particular to a heterogeneous core particle modeling method, system, device and readable storage medium based on an SST framework and a SystemC simulator. Background Art

[0002] Over the years, the complexity of chip design has increased day by day. Most chip-based products need to run software to function. When a chip product needs to be released, both the hardware and the software need to pass testing to complete the pre-shipment preparation. SystemC is a system-level modeling language based on C++ that can be used for modeling, simulation and testing in the chip industry. SystemC is a library written in C++ that provides a language for modeling and simulation at the system and hardware levels. It is widely used by chip manufacturers to simulate and model their own chips. It is used as a simulator to enable system designers and architects to design digital systems at a high level, allowing them to model and analyze system behavior earlier than traditional hardware description languages ​​​​(such as VHDL and Verilog) without sacrificing accuracy.

[0003] In the current chip industry, with the development of chiplets and systems on wafers, more and more technical solutions are being used to integrate multiple chiplets in a single system. However, simulators written in SystemC can only simulate the behavior of a single chiplet and cannot simulate and model a system containing multiple or multiple chiplets. Summary of the invention

[0004] To this end, the present invention provides a heterogeneous core particle modeling method, system, device and readable storage medium based on the SST framework and the SystemC simulator, and integrates multiple SystemC simulators under the SST framework to realize simulation modeling of multi-core heterogeneous systems using the SST framework.

[0005] According to the design scheme provided by the present invention, on the one hand, a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator is provided, comprising:

[0006] A simulator is configured for each core particle, so that each core particle is implemented in a corresponding simulator, and the simulator uses SystemC to construct a corresponding simulation code;

[0007] Each chip simulator uses an external interface to instantiate and integrate SST components under a structural simulation toolkit to obtain a target model, so as to perform interconnection simulation on multiple chip simulators through the target model. The structural simulation toolkit adopts an SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized;

[0008] Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

[0009] As a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator of the present invention, further, each core particle simulator is instantiated and integrated under the structural simulation toolkit using an external interface, including:

[0010] An external function library is set in each core particle simulator, and the external function library is used to provide a calling function interface to the structural simulation toolkit;

[0011] Each core particle simulator is configured in the structural simulation toolkit so that each core particle simulator is abstracted as an SST component in the structural simulation toolkit. The SST components are connected through SST Link and process data transmission events based on event processors.

[0012] As a heterogeneous core grain modeling method based on the SST framework and the SystemC simulator of the present invention, further, the calling function interface at least includes: a first function interface for configuring the core grain simulator, a second function interface for starting the core grain simulator, a third function interface for stopping the core grain simulator, a fourth function interface for checking the status identifier of the core grain simulator sending data to the outside, a fifth function interface for reading data from the core grain simulator, and a sixth function interface for writing data to the core grain simulator.

[0013] As a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator of the present invention, further, interconnection simulation of multiple core particle simulators is performed through a target model, including:

[0014] Set the SST clock frequency and obtain the cycle duration based on the SST clock frequency;

[0015] The cycle duration is used as the core simulator clock control parameter. The SST component controls the core simulator clock based on the clock control parameter. The SST components synchronize their clocks through the SST clock handler.

[0016] As a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator of the present invention, further, interconnection simulation of multiple core particle simulators is performed through a target model, including:

[0017] In response to the request to send data externally, the chip simulator adjusts the external data status flag to the external state. When the SST component checks the external data status flag in each clock cycle, when the external data status flag is the external state, the SST component reads the data to be sent externally by the chip simulator based on the external interface, and transmits the data to the peer SST component through the SST Link.

[0018] After receiving the data, the SST component at the opposite end writes the data into the corresponding chip simulator through the external interface to realize data transmission between multiple chip simulators.

[0019] As a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator of the present invention, further, the SST component reads the data to be sent externally by the core particle simulator based on the external interface, including:

[0020] Obtaining input parameters from an external interface according to the data sent externally, wherein the input parameters include a blank array, a length, and a memory address;

[0021] The SST component calls the external interface based on the read input parameters, so that the chip simulator uses the memory address as the starting address, adds the externally sent data to the blank array, and sets the data length so that the SST component can obtain the externally sent data.

[0022] As a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator of the present invention, further, the opposite end SST component writes data into the corresponding core particle simulator through an external interface, including:

[0023] Setting external interface write parameters according to received data, the write parameters including data array, length and memory address;

[0024] The peer SST component calls the external interface based on the write parameters, so that the corresponding chip simulator uses the memory address as the starting address and writes the data array into the specified memory address of the corresponding chip simulator according to the length.

[0025] In another aspect, the present invention further provides a heterogeneous core-grain modeling system based on the SST framework and the SystemC simulator, comprising: a core-grain simulation configuration module and a component instantiation integration module, wherein:

[0026] A core particle simulation configuration module is used to configure a simulator for each core particle so that each core particle is implemented in a corresponding simulator, wherein the simulator uses SystemC to construct a corresponding simulation code;

[0027] A component instantiation integration module is used for each chip simulator to perform SST component instantiation integration under a structural simulation toolkit using an external interface to obtain a target model so as to perform interconnection simulation on multiple chip simulators through the target model. The structural simulation toolkit adopts an SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized;

[0028] Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

[0029] In another aspect, the present invention further provides an electronic device, comprising:

[0030] at least one processor, and a memory coupled to the at least one processor;

[0031] The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0032] In yet another aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the method described above can be implemented.

[0033] Beneficial effects of the present invention:

[0034] The present invention uses the chip simulator developed by SystemC as a black box, and integrates heterogeneous chiplets under the SST framework by providing a function library to the outside, so as to simulate and model a multi-chip heterogeneous system, and can realize clock synchronization and data transmission among multiple SystemC simulators. In the chip design stage, it can simulate and model a system with multiple and various chiplets to test and verify the performance of the chip system, speed up the design time of the chip system, reduce the system verification cost, and has good application prospects in the field of system chip front-end design and verification test. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the heterogeneous core particle modeling process based on the SST framework and the SystemC simulator in the embodiment;

[0036] Figure 2 The internal structure of the SystemC simulator in the embodiment is shown;

[0037] Figure 3 This is a schematic diagram of the SystemC simulator accessing the SST framework in the embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions.

[0039] In order to solve the problem that the SystemC simulator cannot simulate a multi-chip system, the embodiment of the present invention refers to Figure 1 As shown, a heterogeneous core particle modeling method based on the SST framework and the SystemC simulator is provided, including:

[0040] S101, configuring a simulator for each core particle, so that each core particle is implemented in a corresponding simulator, wherein the simulator uses SystemC to construct a corresponding simulation code;

[0041] S102, each chip simulator uses an external interface to instantiate and integrate SST components under a structural simulation toolkit to obtain a target model, so as to perform interconnection simulation on multiple chip simulators through the target model, wherein the structural simulation toolkit adopts an SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized;

[0042] Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

[0043] like Figure 2 As shown in the figure, the SystemC simulator is integrated using a black box approach. There is no need to change the core code of the simulator. Only the top module of the upper layer needs to provide some external interfaces. Conventional interfaces may include: config, which configures the SystemC simulator function; start, which starts the SystemC simulator function; end, which stops the SystemC simulator function; read, which reads data from the SystemC simulator function; write, which writes data to the SystemC simulator function.

[0044] For easy integration, only the SystemC simulator provides call functions to the SST framework, and SST does not provide callback functions to the SystemC simulator. When the SystemC simulator needs the SST framework to operate, such as sending data to the outside, the SystemC simulator will change a flag of its top module, and the SST framework will periodically check this flag according to the set clock frequency, and determine the operation to be performed through the flag. A fixed memory address space is reserved inside the SystemC simulator for users and the SST framework to write data. When the user needs to read the data sent through the SST framework, just read it from this memory address. When the user needs to send data to the outside through the SST framework, just write the data into a specific data segment, and the SST framework will take the data to be sent from the memory address.

[0045] Specifically, each core particle simulator is instantiated and integrated under the structural simulation toolkit using an external interface, and can be designed to include:

[0046] An external function library is set in each core particle simulator, and the external function library is used to provide a calling function interface to the structural simulation toolkit;

[0047] Each core particle simulator is configured in the structural simulation toolkit so that each core particle simulator is abstracted as an SST component in the structural simulation toolkit. The SST components are connected through SST Link and process data transmission events based on event processors.

[0048] like Figure 3 As shown in the figure, in the SST framework, each individual simulator is abstracted as an SST component, and the SST components are connected through SST Link. The SST component has an event processor inside, which can process the SST events received through the SST Link. The SST component also has a clock processor inside, which is used to manage the clocks of all simulator components under the SST framework.

[0049] Specifically, the interconnection simulation of the multi-chip simulator can be designed to include:

[0050] Set the SST clock frequency and obtain the cycle duration based on the SST clock frequency;

[0051] The cycle duration is used as the core simulator clock control parameter. The SST component controls the core simulator clock based on the clock control parameter. The SST components synchronize their clocks through the SST clock handler.

[0052] Among them, in response to the request for sending data externally, the chip simulator adjusts the external data status flag to the external state. When the SST component checks the external data status flag within the clock cycle, when the external data status flag is the external state, the SST component reads the data to be sent externally by the chip simulator based on the external interface, and transmits the data to the opposite SST component through the SST Link; after the opposite SST component receives the data, it writes the data to the corresponding chip simulator through the external interface to realize data transmission between multiple chip simulators.

[0053] In the clock processor function of the SST component, the clock control of the SystemC simulator can be achieved by calling the sc_start function. The sc_start function is the clock library of SystemC, which controls all SystemC components to execute forward for a period of time. By setting the SST clock frequency, the duration of a cycle is calculated, and this duration is used as the input parameter of the sc_start function to control the SystemC simulator to run a cycle. In this way, the SST framework can achieve precise control of the SystemC simulator clock. The clocks between each SST component are synchronized. After the SST components are synchronized with the clocks of their respective SystemC simulators, the clock synchronization of multiple SystemC simulators can be achieved.

[0054] By setting up an SST Link for the SST component, the SST component can send and receive SST events through the SST Link, and set an event trigger function for each SST Link. When the SST Link receives an event, it triggers this function and passes the SST event as an input parameter to this trigger function. After parsing the SST event in this function, the data is passed to other SystemC simulators. The SST component can fetch the data to be sent into the SST component through the read interface provided by SystemC in the previous section, and then send the data to another SST component through the SST Link. After the SST component on the other end receives the data, it writes the data to the SystemC simulator through the write interface provided by SystemC. Through this process, data transmission between multiple SystemC simulators can be achieved.

[0055] Furthermore, based on the above method, an embodiment of the present invention also provides a heterogeneous core grain modeling system based on the SST framework and the SystemC simulator, comprising: a core grain simulation configuration module and a component instantiation integration module, wherein:

[0056] A core particle simulation configuration module is used to configure a simulator for each core particle so that each core particle is implemented in a corresponding simulator, wherein the simulator uses SystemC to construct a corresponding simulation code;

[0057] A component instantiation integration module is used for each chip simulator to perform SST component instantiation integration under a structural simulation toolkit using an external interface to obtain a target model so as to perform interconnection simulation on multiple chip simulators through the target model. The structural simulation toolkit adopts an SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized;

[0058] Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

[0059] like Figure 3 As shown in the figure, during the interconnection of multiple SystemC simulators, the content of the interface provided to the outside can be summarized as follows:

[0060] The SystemC simulator provides a config interface, through which SST inputs configuration parameters to the simulator. The SystemC simulator also needs to instantiate itself within this function.

[0061] The SystemC simulator provides a start interface, through which SST notifies the simulator to start running. The SST framework sends a start instruction to all components in the simulation system to ensure that all simulators start running simulations at the same time.

[0062] The SystemC simulator provides an end interface, through which SST notifies the simulator of the end of simulation, destroys the instantiation of the simulator, and releases system resources.

[0063] The SystemC simulator provides a send_notify interface. When the SystemC simulator needs to transmit data to the outside, it will change the flag of the top module. SST will call this function to check this flag every time the clock is triggered. If the function return value is true, the SST framework will know that it needs to send an event to the outside.

[0064] The SystemC simulator provides a read function, which takes a blank array, length, and memory address as input parameters. When SST calls this function, the SystemC simulator uses this memory address as the starting address and copies the data of this length into the blank array. The SST interface can copy the data inside the SystemC simulator through this interface.

[0065] The SystemC simulator provides a write function, which takes as input the data array, length, and memory address. When SST calls this function, the SystemC simulator will use this memory address as the starting address and copy the data of this length from the data array to this address. The SST interface can write data to the specified address location inside the SystemC simulator through this interface.

[0066] In the interconnection of multiple SystemC simulators, the content of using the SST framework to instantiate and integrate SST components in SystemC simulators can be summarized as follows:

[0067] Step 1: Add the SST component code of the SystemC simulator in the sst-element\src\sst\elements directory.

[0068] Step 2: Create a new SystemC simulator type that inherits SST:Compenet.

[0069] Step 3: Register the clock in the creation function, register the event trigger function of the SST Link, call the config function of the SystemC simulator, and instantiate the simulator.

[0070] Step 4: Create an event trigger function for SST Link. When the SST component receives an event through SST Link, the function will be triggered. The function will parse the SST event and call the write function of the SystemC simulator to write the parsed data into the SystemC simulator.

[0071] Step 5: Create a clock trigger function. The SST framework will call this function periodically according to the set clock frequency.

[0072] Step 6: In the clock trigger function, call the send_notify function of the SystemC simulator to check whether there is data to be sent out.

[0073] Step 7: If there is data to be sent out, call the read function of the SystemC simulator to read the data, encapsulate the data in the SST event, and send it to other SystemC simulators through the SST Link.

[0074] Step 8: In the clock trigger function, calculate the duration of a cycle by setting the processor frequency. For example, when the processor frequency is set to 100MHz, the duration of a cycle is 10 nanoseconds. Call the sc_start() function in the clock trigger function, and input the cycle duration and the time unit of the cycle.

[0075] Step 9: Create the destructor of the SST component and call the end function of the SystemC simulator in the function.

[0076] Furthermore, an embodiment of the present invention further provides an electronic device, including:

[0077] at least one processor, and a memory coupled to the at least one processor;

[0078] The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0079] Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, the method described above can be implemented.

[0080] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0081] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0082] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0083] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0084] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A heterogeneous core particle modeling method based on SST framework and SystemC simulator, characterized in that: Include: A simulator is configured for each core particle, so that each core particle is implemented in a corresponding simulator, and the simulator uses SystemC to construct a corresponding simulation code; Each chip simulator uses an external interface to instantiate and integrate the SST component under the structural simulation toolkit to obtain a target model, so as to interconnect and simulate multiple chip simulators through the target model. The structural simulation toolkit adopts the SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized; wherein each chip simulator uses an external interface to instantiate and integrate under the structural simulation toolkit, including: setting an external function library in each chip simulator, and using the external function library to provide a calling function interface to the structural simulation toolkit; configuring each chip simulator in the structural simulation toolkit to abstract each chip simulator into an SST component in the structural simulation toolkit, and the SST components are connected through SST Link and process data transmission events based on event processors; Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

2. The heterogeneous core grain modeling method based on the SST framework and the SystemC simulator according to claim 1 is characterized in that: The calling function interface includes at least: a first function interface for configuring the chip simulator, a second function interface for starting the chip simulator, a third function interface for stopping the chip simulator, a fourth function interface for checking the status identifier of the chip simulator sending data to the outside, a fifth function interface for reading data from the chip simulator, and a sixth function interface for writing data to the chip simulator.

3. The heterogeneous core grain modeling method based on the SST framework and the SystemC simulator according to claim 1 is characterized in that: Interconnect simulation of multi-chip simulators through target models, including: Set the SST clock frequency and obtain the cycle duration based on the SST clock frequency; The cycle duration is used as the core simulator clock control parameter. The SST component controls the core simulator clock based on the clock control parameter. The SST components synchronize their clocks through the SST clock handler.

4. The heterogeneous core grain modeling method based on the SST framework and the SystemC simulator according to claim 1, characterized in that: Interconnect simulation of multi-chip simulators through target models, including: In response to the request to send data externally, the chip simulator adjusts the external data status flag to the external state. When the SST component checks the external data status flag in each clock cycle, when the external data status flag is the external state, the SST component reads the data to be sent externally by the chip simulator based on the external interface, and transmits the data to the opposite SST component through the SST Link; After receiving the data, the SST component at the opposite end writes the data into the corresponding chip simulator through the external interface to realize data transmission between multiple chip simulators.

5. The heterogeneous core grain modeling method based on the SST framework and the SystemC simulator according to claim 4 is characterized in that: The SST component reads the data to be sent out by the chip simulator based on the external interface, including: Obtaining input parameters from an external interface according to the data sent externally, wherein the input parameters include a blank array, a length, and a memory address; The SST component calls the external interface based on the read input parameters, so that the chip simulator uses the memory address as the starting address, adds the externally sent data to the blank array, and sets the data length so that the SST component obtains the externally sent data.

6. The heterogeneous core grain modeling method based on the SST framework and the SystemC simulator according to claim 4 is characterized in that: The peer SST component writes data to the corresponding chip simulator through an external interface, including: Setting external interface write parameters according to received data, the write parameters including data array, length and memory address; The peer SST component calls the external interface based on the write parameters, so that the corresponding chip simulator uses the memory address as the starting address and writes the data array into the specified memory address of the corresponding chip simulator according to the length.

7. A heterogeneous core particle modeling system based on SST framework and SystemC simulator, characterized in that: Contains: core particle simulation configuration module and component instantiation integration module, among which, A core particle simulation configuration module is used to configure a simulator for each core particle so that each core particle is implemented in a corresponding simulator, wherein the simulator uses SystemC to construct a corresponding simulation code; A component instantiation integration module is used for each chip simulator to perform SST component instantiation integration under a structural simulation toolkit using an external interface to obtain a target model so as to perform interconnection simulation on multiple chip simulators through the target model. The structural simulation toolkit adopts an SST framework and the clocks of the SST components of each chip simulator in the SST framework are synchronized. Each chip simulator is instantiated and integrated under the structural simulation toolkit using an external interface, including: setting an external function library in each chip simulator, and providing a calling function interface to the structural simulation toolkit using the external function library; configuring each chip simulator in the structural simulation toolkit so as to abstract each chip simulator as an SST component in the structural simulation toolkit, wherein the SST components are connected through an SST Link and process data transmission events based on an event processor; Each core simulator is provided with an identification for indicating the state of the simulator itself sending data externally and a reserved memory address space for writing user or structural simulation toolkit data into the simulator.

8. An electronic device, characterized in that: include: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 6 can be implemented.

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