Method, device, medium, and program product for layout processing

Abstract

According to an embodiment of the present disclosure, there are provided a method, a device, a medium, and a program product for layout processing. In this method, based on splitting conditions related to the layout splitting of an initial layout, regional association information for a plurality of regions in the initial layout is determined, and the regional association information indicates whether two adjacent regions among the plurality of regions are relevant in the layout splitting; and in response to the regional association information indicating that a first region adjacent to a second region among the plurality of regions is relevant in the layout splitting, based on the relevance between the first region and the second region, a coloring result of the first region and a coloring result of the second region are determined, wherein the color of the graphic indicates the sub-layout to which the graphic will be split.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of integrated circuits, and particularly to methods, devices, computer-readable storage media, and computer program products for layout processing. Background Art

[0002] A circuit layout (which can also be simply referred to as a layout) is a series of graphics converted from a circuit that has been designed, simulated, and optimized, and it contains physical information data related to devices such as the size of the integrated circuit and the topological definition of each layer. Integrated circuit manufacturers manufacture masks based on this data. The layout pattern on the mask determines the size of the devices or the physical layer of the connections on the chip.

[0003] Double patterning technology defines higher-density patterns by splitting patterns that cannot be achieved by single exposure and using multiple exposures and etching. The introduction of double patterning technology enables chip manufacturing to break through the size limit of single exposure and achieve higher-density pattern definition. In chip manufacturing, it is desirable to effectively split the layout to use double patterning technology or multiple patterning technology. Summary of the Invention

[0004] In a first aspect of the present disclosure, a layout processing method is provided. The method includes: determining region association information for a plurality of regions in an initial layout based on splitting conditions related to the layout splitting of the initial layout, where the region association information indicates whether two adjacent regions among the plurality of regions are related in layout splitting; and in response to the region association information indicating that a first region and a second region adjacent among the plurality of regions are related in layout splitting, determining a coloring result for the first region and a coloring result for the second region based on the correlation between the first region and the second region, where the color of the graphic indicates the sub-layout to which the graphic will be split.

[0005] In a second aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory, where the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. The instructions, when executed by the at least one processing unit, cause the device to execute the method of the first aspect.

[0006] In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer program product includes computer-executable instructions that, when executed by a processor, implement the method according to the first aspect of the present disclosure.

[0007] In a fourth aspect of the present disclosure, a computer program product is provided. The computer program product includes computer-executable instructions that, when executed by a processor, implement the method according to the first aspect of the present disclosure.

[0008] It should be understood that the content described in this content section is not intended to define the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0010] Figure 1 FIG. 1 shows a schematic diagram of an exemplary environment in which embodiments of the present disclosure can be implemented;

[0011] Figure 2 FIG. 2 shows a flowchart of a process for layout processing according to some embodiments of the present disclosure;

[0012] Figure 3 FIG. 3 shows a schematic diagram of an example of two adjacent regions according to some embodiments of the present disclosure; and

[0013] Figure 4 FIG. 4 shows a block diagram of an electronic device in which one or more embodiments of the present disclosure can be implemented. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not used to limit the protection scope of the present disclosure.

[0015] In the description of the embodiments of the present disclosure, the term "comprising" and its like should be understood as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". There may also be other explicit and implicit definitions hereinafter.

[0016] In this document, unless otherwise specified, performing a step "in response to A" does not mean that the step is immediately performed after "A", but may include one or more intermediate steps.

[0017] It is understandable that the data involved in the present technical solution (including but not limited to the data itself, the acquisition or use of the data) should comply with the requirements of the corresponding laws, regulations and related provisions.

[0018] Figure 1 FIG. shows a schematic diagram of an exemplary environment 100 in which embodiments of the present disclosure can be implemented. The exemplary environment 100 may include an electronic device 110.

[0019] As Figure 1 shown, the electronic device 110 obtains an initial layout 120. The layout may include a graphical representation formed by arranging and wiring various electronic components and interconnect lines on a plane according to certain rules and requirements. Here, the initial layout 120 may be an un-split original layout.

[0020] In some embodiments, the electronic device 110 may split the initial layout 120 based on split conditions 130 through a tool or application, so that the multiple sub-layouts obtained after splitting (for example, may include sub-layout 125-1, sub-layout 125-2,...) can be used in double or multiple patterning techniques. For example, in double patterning techniques, the initial layout 120 needs to be split into two sub-layouts. Correspondingly, in multiple patterning techniques, the initial layout 120 needs to be split into multiple sub-layouts. It should be understood that the number of layout splits can be set according to the requirements of the corresponding lithography technique, and no limitation is intended here.

[0021] In some embodiments, the split conditions 130 may include split conditions defined according to design rule check (DRC) rules, or may include user-defined split conditions. It should be understood that the split conditions 130 may include any appropriate conditions required for layout splitting in the corresponding lithography technique.

[0022] The electronic device 110 may be any type of device with computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / video camera, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device may, for example, include a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0023] It should be understood that the structures and functions of the various elements in environment 100 are described only for exemplary purposes, without implying any limitation on the scope of the present disclosure.

[0024] As briefly mentioned above, in the chip design stage of semiconductor processes, as the size of semiconductor devices continues to shrink, single-exposure lithography technology becomes inapplicable after reaching a certain size limit. Therefore, double patterning technology is introduced. Double patterning technology divides the patterns that cannot be achieved by single exposure originally and uses multiple exposures and etching to define higher-density patterns. The introduction of double patterning technology enables chip manufacturing to break through the size limit of single exposure and achieve higher-density pattern definition, but at the same time brings new design challenges and complexities. For chip manufacturers and designers, how to effectively split the layout into two or more sub-layouts is an important challenge in current chip manufacturing.

[0025] Double exposure splitting is a two-color coloring problem based on DRC rules. Through DRC rules, the graphics that violate the rules in the same layer are assigned to different layers. Traditional splitting techniques need to establish a set of all the graphics marked by the DRC splitting rules and then transform them into a two-color coloring problem. However, with the progress of the manufacturing process, the number of graphics is increasing, and storing and computing these graphics requires a large amount of computing and storage resources, resulting in certain usage limitations of the tool in some manufacturing processes.

[0026] In view of this, according to an embodiment of the present disclosure, an improved solution for layout processing is proposed. According to the solution of the embodiment of the present disclosure, based on the splitting conditions related to the layout splitting of the initial layout, the region association information for multiple regions in the initial layout is determined, and the region association information indicates whether two adjacent regions in the multiple regions are relevant in the layout splitting. In response to the region association information indicating that the adjacent first region and the second region in the multiple regions are relevant in the layout splitting, based on the correlation between the first region and the second region, the coloring result of the first region and the coloring result of the second region are determined, where the color assigned to the graphics indicates the sub-layout to which the graphics will be split.

[0027] In this way, by combining the splitting conditions, the association information of multiple regions in the initial layout is determined, and the coloring result of the associated regions is determined, so that the splitting result for the initial layout can be determined. Such a layout splitting scheme can improve the efficiency and accuracy of layout splitting. In addition, according to the relevance or irrelevance of adjacent regions among multiple regions, the associated adjacent regions and the individual regions that have no association with other regions can be respectively corresponding to distributed nodes. In this way, the calculations for different regions can be executed in parallel through the corresponding distributed nodes. By synchronizing the calculation results of each distributed node, the effects of accelerating the calculation and reducing the memory can be achieved, effectively reducing the memory and running time of the initial layout on advanced nodes.

[0028] Some example embodiments of the present disclosure will be further described below with reference to the accompanying drawings.

[0029] Figure 2 A flowchart of a process 200 for layout processing according to some embodiments of the present disclosure is shown. For ease of discussion, these embodiments will be described with reference to Figure 1 an environment 100. These embodiments can be implemented in Figure 1 an electronic device 110. It should be understood that the method 200 may further include additional blocks not shown and / or some (or certain) of the shown blocks may be omitted, and the scope of the present disclosure is not limited in this regard.

[0030] In block 210, based on splitting conditions related to the layout splitting of the initial layout, the electronic device 110 determines the region association information for multiple regions in the initial layout. A layout may include a graphical representation formed by arranging and routing various electronic components and interconnects on a plane according to certain rules and requirements. Here, the initial layout 120 may be an un-split original layout. The initial layout 120 may include multiple divided regions.

[0031] In some embodiments, based on the configuration information of the initial layout 120, the electronic device 110 may divide the initial layout 120 into multiple regions. The configuration information of the initial layout 120 may include information such as electronic components, layout, routing, etc. of the initial layout 120 itself, and may also include information on some configurations of the initial layout 120 defined by the user.

[0032] In some embodiments, the configuration information may include the hierarchy information and cell information of the initial layout 120. The hierarchy information may include, for example, information about the top level, intermediate level, bottom level, etc. of the layout. The cell information is a type of attribute information of the layout itself. Cells may include, for example, basic components such as transistors and resistors, or may also include circuit modules composed of multiple basic components and having specific logic functions, such as AND gates and flip-flops. Accordingly, based on the hierarchy information and cell information of the initial layout 120, the initial layout 120 can be divided into multiple cells. For example, in such an embodiment, the multiple regions may refer to multiple cells.

[0033] Alternatively or additionally, in some embodiments, the configuration information may include the type information of the initial layout 120. The type information may include, for example, information about the metal layers of the initial layout 120 (such as the metal layer 0 M0, metal layer 1 M1, metal layer 2 M2, or other special types of metal layers), via layer information (such as the V0 layer for connecting the M0 and M1 layers, the V1 layer for connecting higher metal layers such as the M1 and M2 layers), etc., which are not limited herein. Accordingly, based on the type information of the initial layout 120, the initial layout 120 can be appropriately divided into multiple regions.

[0034] Alternatively or additionally, in some embodiments, the configuration information may include custom information about the layout division size. Such a division size may be, for example, the size of a tile. Accordingly, based on the custom information about the layout split size of the initial layout 120, the initial layout 120 can be divided into multiple tiles.

[0035] Alternatively or additionally, in some embodiments, the configuration information may include constraints based on split conditions and information related to dividing the initial layout 120 according to multiple functions in the initial layout 120. Such functions may include, for example, storage functions, computing functions, etc., and the modules where they are located may be storage modules, computing modules, etc. It should be noted that when dividing the initial layout 120 according to functional modules, it is necessary to be subject to split conditions such as DRC rules. For example, if two modules have different functions but are subject to the DRC rules, they need to be associated and not divided into two regions. Accordingly, based on the constraints of the split conditions and the information related to dividing the initial layout 120 according to multiple functions in the initial layout 120, the initial layout 120 can be divided into multiple regions.

[0036] Thus, the initial layout 120 can be divided into multiple regions in any one of the above-mentioned multiple ways or a combination thereof. It should be understood that for different layout division methods, the shape, size, etc. of each region in the divided multiple regions are not limited herein. This allows users to select different region division methods according to different layouts, thereby preparing for subsequent splitting of the layout to match the corresponding mask.

[0037] In some embodiments, the splitting conditions can at least include design rule check DRC rules. The splitting conditions can also include other rules for restricting layout splitting. The splitting conditions can, for example, include requirements for layout splitting restrictions regarding geometric rules, electrical rules, process-related rules, etc. in the layout. For example, requirements regarding the width of lines, the spacing between lines, the dimensions of various graphics (such as rectangles, polygons, etc.), short circuit and open circuit conditions, etc. in the layout. It should be understood that the splitting conditions can include any appropriate rules or requirements for restricting layout splitting, and are not limited herein.

[0038] Here, the region association information indicates whether two adjacent regions among the multiple regions are relevant in layout splitting. It should be noted that what the region association information indicates can be whether any two adjacent regions among the multiple regions are relevant in layout splitting. That is to say, for each region, whether it is associated with adjacent regions. For ease of discussion, the following will be combined with Figure 3 to discuss in detail how to determine whether two adjacent regions are relevant in layout splitting.

[0039] Figure 3 The schematic diagram of an example structure 300 of two adjacent regions according to some embodiments of the present disclosure is shown. The example structure 300 can be located within the initial layout 120 in the environment 100 of Figure 1 The example structure 300 can be an example structure of two adjacent regions involved in the process 200 of Figure 2

[0040] As Figure 3 shown, in some embodiments, two adjacent regions can include an adjacent first region 310 and a second region 320, and the first region 310 and the second region 320 can have a common division boundary 330. To determine the region association information for the multiple regions, the electronic device 110 can determine whether the first boundary pattern near the division boundary 330 in the first region 310 and the second boundary pattern near the division boundary 330 in the second region 320 are restricted by the splitting conditions.

[0041] Taking Figure 3 ​For example, the shapes near the division boundary 330 in the first region 310 include shape 317 and shape 318, which can be respectively referred to as the first boundary shapes. The shapes near the division boundary 330 in the second region 320 include shape 327 and shape 328, which can be respectively referred to as the second boundary shapes. It can be determined whether the shapes 317 and 318 are subject to splitting conditions such as DRC rules with respect to the shapes 327 and 328 respectively.

[0042] For example, according to the DRC rules, if shape 317 and shape 327 need to comply with the DRC rules, then shape 317 and shape 327 are subject to the DRC rules. If there is no need for shape 317 and shape 327 to comply with any DRC rules, that is, they are not related, then shape 317 and shape 327 are not subject to the DRC rules. A similar judgment method can also be used for other boundary shapes in the first region 310 and other boundary shapes in the second region 320, which will not be elaborated here.

[0043] In some embodiments, if the first boundary shape and the second boundary shape are subject to splitting conditions, the electronic device 110 can determine that the first region 310 and the second region 320 are related in layout splitting. It should be understood that if there is at least one pair of the first boundary shape and the second boundary shape that is subject to splitting conditions, it can be determined that the first region 310 and the second region 320 are related in layout splitting. Still taking Figure 3 as an example, for the boundary shapes in the first region 310 and the second region 320, if only shape 317 and shape 327 are subject to splitting conditions, it can be determined that the first region 310 and the second region 320 are related in layout splitting.

[0044] In some embodiments, if the first boundary shape and the second boundary shape are not subject to splitting conditions, the electronic device 110 can determine that the first region 310 and the second region 320 are not related in layout splitting. It should be understood that in the first region 310 and the second region 320, if there is no pair of the first boundary shape and the second boundary shape that is subject to splitting conditions, it can be determined that the first region 310 and the second region 320 are not related in layout splitting. For example, if shape 317 and shape 318 are not subject to splitting conditions with respect to shape 327 and shape 328 respectively, it can be determined that the first region 310 and the second region 320 are not related in layout splitting.

[0045] In addition to determining whether two adjacent regions among multiple regions are relevant in layout splitting through the above methods, there can also be the following exemplary determination methods. For example, it is possible to determine whether two adjacent regions among multiple regions are relevant in layout splitting from aspects such as the circuit function of the initial layout 120 and the annotations of the layout design, etc.

[0046] For example, in terms of circuit function, it is possible to determine whether two adjacent regions are relevant based on the circuit connection relationship of the initial layout 120. Also, it is possible to determine whether there is a logical function correlation between two adjacent regions. For example, if the input port and output port of an AND gate are respectively in two adjacent regions, etc., it can be determined that the two adjacent regions are relevant and cannot be split. In terms of the annotations of the layout design, there may be some annotation information such as symbols, texts, colors, etc., indicating that two adjacent regions cannot be split, and thus the relevance of the two adjacent regions can be determined. It should be understood that there can be multiple suitable ways to determine the relevance of regions.

[0047] In some embodiments, the first boundary pattern in the first region 310 near the division boundary 330 and the second boundary pattern in the second region 320 near the division boundary 330 can be determined in the following manner. Specifically, based on the splitting condition, the electronic device 110 can determine the outward expansion size for each of the multiple regions. Then, based on the expansion size and the division boundary 330, the electronic device 110 can respectively determine the first expanded region 325 in the second region 320 for the first region 310 and the second expanded region 315 in the first region 310 for the second region 320. Correspondingly, the electronic device 110 can determine the pattern in the first region 310 that is within the second expanded region 315 as the first boundary pattern, and determine the pattern in the second region 320 that is within the first expanded region 325 as the second boundary pattern.

[0048] In some embodiments, to determine the expansion size, the electronic device 110 can determine the maximum pattern spacing indicated by the splitting condition as the expansion size. For example, in Figure 3 it, the expansion size can be the horizontal size. It should be understood that the size and expansion direction of the expansion size can be determined according to two adjacent regions with different layouts, different sizes, etc., and are not limited here. By using the maximum pattern spacing as the expansion size, the boundary patterns of each region can be determined accurately, conveniently, and quickly.

[0049] Return to reference Figure 2, in block 220, if the region association information indicates that the adjacent first region and second region among multiple regions are relevant in the layout splitting, based on the relevance between the first region and the second region, determine the coloring result of the first region and the coloring result of the second region. Here, the color of the graphic indicates the sub-layout to which the graphic will be split.

[0050] In some embodiments, to determine the coloring result of the first region and the coloring result of the second region, based on the splitting condition, the electronic device 110 may perform graphic coloring based on at least two colors on the multiple regions respectively. Then, based on the graphic coloring of the first region and the second region and the relevance between the first region and the second region, the electronic device 110 may determine the coloring result of the first region and the coloring result of the second region.

[0051] In such an embodiment, the multiple regions of the initial layout may be uniformly colored first, and then the first region and the second region may be colored. Here, the at least two colors may respectively correspond to at least two sub-layouts. As an example, if the double patterning technique is to be used, graphic coloring based on two colors may be performed on the multiple regions respectively, so that the coloring colors of the two sub-layouts respectively correspond to two masks. If the multiple patterning technique is to be used, graphic coloring based on multiple colors may be performed on the multiple regions respectively, so that the coloring colors of the multiple sub-layouts respectively correspond to multiple masks.

[0052] Exemplarily, the electronic device 110 may detect the splitting condition for the result of the current graphic coloring to verify the relevance of adjacent regions. In some embodiments, if the region association information indicates that the third region among multiple regions and the adjacent region of the third region are not relevant in the layout splitting, based on the graphic coloring of the third region, the electronic device 110 may determine the coloring result for the third region. That is to say, for a certain region or some regions among the multiple regions, if it has no relevance with the adjacent region in the layout splitting, it can be regarded as a separate region. As an example, the coloring result of such a separate region may be saved separately.

[0053] In some embodiments, based at least on the coloring result of the first region and the coloring result of the second region, the electronic device 110 may determine the splitting result for the initial layout 120. The splitting result may indicate splitting each graphic in the initial layout 120 into at least two sub-layouts. As an example, if the splitting of the initial layout 120 is for using the double patterning technique, the splitting result may indicate splitting each graphic in the initial layout 120 into two sub-layouts. If the splitting of the initial layout 120 is for using the multiple patterning technique, the splitting result may indicate splitting each graphic in the initial layout 120 into multiple sub-layouts. It should be understood that the number of sub-layouts for splitting the initial layout 120 may be set according to the lithography technique to be used.

[0054] Here, the coloring results of the first region and the second region can be used as at least a part of the splitting result. The coloring result of the third region can be used as at least another part of the splitting result. Thus, for adjacent regions with relevance among multiple regions and individual regions not related to adjacent regions, respective coloring results are obtained. Correspondingly, by combining these coloring results of multiple regions, the splitting result of the initial layout 120 can be determined.

[0055] In some embodiments, in order to further determine the coloring results of the first region 310 and the second region 320, the electronic device 110 can align the colors of the first boundary pattern and the second boundary pattern in the first region 310 and the second region 320 that are subject to splitting conditions. Because for the graphic coloring based on at least two colors performed on multiple regions discussed above, it belongs to the initial coloring, and the initial coloring does not yet consider the patterns located in different regions that are subject to splitting conditions. Since the first boundary pattern and the second boundary pattern subject to splitting conditions will correspond to the same photomask, it is necessary to update the coloring to make the coloring colors of the two consistent. How to align the colors of the first boundary pattern and the second boundary pattern subject to splitting conditions will be discussed in detail below.

[0056] Then, the electronic device 110 can determine the target boundary pattern whose color has changed through color alignment from the first boundary pattern and the second boundary pattern. Furthermore, based on the color change of the target boundary pattern, the electronic device 110 can perform a coloring transformation on the target region where the target boundary pattern is located to determine the coloring result of the target region. The target region can be the first region 310 or the second region 320.

[0057] Take Figure 3 as an example. If during the initial coloring, the coloring color of the pattern 317 is the first color and the coloring color of the pattern 327 is the second color, and assuming that the coloring colors of the two are to be aligned to the first color during the updated coloring, then it can be determined that the target boundary pattern whose color has changed through this color alignment is the pattern 327. Furthermore, based on the coloring color of the pattern 327 changing from the second color to the first color, a coloring transformation (which can also be called color flipping) can be performed on the second region 320 where the pattern 327 is located, so as to determine the coloring result of the second region 320. Taking the non-boundary pattern 322 in the second region 320 as an example, assuming that the pattern 322 and the pattern 327 are subject to splitting conditions and the initial coloring color of the pattern 322 is the first color, then after the coloring transformation of the second region 320, the coloring color of the pattern 322 will be updated to the second color.

[0058] Thus, by sequentially performing initial coloring, updated coloring, and color flipping, the coloring effect of multiple regions can be ensured, avoiding coloring chaos or coloring errors. This further guarantees the accuracy of layout splitting.

[0059] In addition to determining the coloring results of the first region and the second region by initial coloring, updated coloring, and color flipping as discussed above, there may be other ways to determine the coloring results of the first region and the second region. In some other embodiments, to determine the coloring results of the first region and the second region, the electronic device 110 may determine the coloring results of the first region and the second region based on the correlation between the first region and the second region, and then perform graphic coloring on other regions in the multiple regions except for the first region and the second region having the correlation to determine the coloring results of these other regions. As an example, the electronic device 110 may first align the colors of the first boundary graphic and the second boundary graphic in the first region and the second region that are subject to the splitting conditions, and then, for each region in the multiple regions, perform a coloring transformation, i.e., color flipping, on other graphics in the region based on the coloring colors of their respective boundary graphics.

[0060] In some embodiments, to align the colors of the first boundary graphic and the second boundary graphic, based on the first boundary graphic and the second boundary graphic, the electronic device 110 may construct a structured representation corresponding at least to the first region and the second region. Then, the electronic device 110 may color the graphics in the structured representation to align the colors of the first boundary graphic and the second boundary graphic.

[0061] It should be understood that the structured representation does not apply to individual regions that are not related to adjacent regions. As an example, the structured representation may be an undirected weighted graph. In other examples, the structured representation may also be any other suitable type of representation for layout graphics. In such an embodiment, the structured representation may be equivalent to abstracting the initial layout 120 into a representation that includes at least the first boundary graphic and the second boundary graphic.

[0062] In some embodiments, the structured representation may include: nodes (Nodes) corresponding to the first boundary graphic and the second boundary graphic respectively; a first link (also referred to as an identical link) representing the association between the first boundary graphic and the second boundary graphic; a second link (also referred to as a combined link) representing the association between the first boundary graphic and other graphics in the first region where it is located; and a second link representing the association between the second boundary graphic and other graphics in the second region where it is located.

[0063] In such an embodiment, each pair of a first boundary graph and a second boundary graph subject to splitting conditions in multiple regions can be abstracted as a node respectively, the association relationship between the first boundary graph and the second boundary graph can be abstracted as a first link, and the association relationships between the first boundary graph and other graphs in the first region, and between the second boundary graph and other graphs in the second region can be abstracted as second links respectively. Thus, a structured representation of the initial layout 120 can be constructed. Then, by updating the coloring of the graphs in the structured representation, the colors of the first boundary graph and the second boundary graph can be aligned.

[0064] In some embodiments, a corresponding weight can be configured for the first link. For example, when the structured representation is an undirected weighted graph, a corresponding weight can be configured for each first link. To color the graphs in the structured representation, if there are multiple first links between the first region and the second region, and the weight of a target first link among the multiple first links is greater than the weights of other first links, the electronic device 110 can color the graphs in the structured representation based on the first boundary graph and the second boundary graph corresponding to the target first link.

[0065] Since there can be multiple first boundary graphs in the first region and multiple second boundary graphs in the second region, when updating the coloring, a pair of a first boundary graph and a second boundary graph needs to be selected to determine the color for updating the coloring. As an example, the first link with the largest weight can be selected from the multiple first links, and thus the coloring can be updated based on the first boundary graph and the second boundary graph corresponding to the first link with the largest weight. This can improve the efficiency and effectiveness of updating the coloring of adjacent regions with relevance.

[0066] Thus, by abstracting a structured representation from the initial layout, the graph coloring of associated adjacent regions can be conveniently updated. This further speeds up the efficiency of layout splitting.

[0067] In some embodiments, based on the splitting result of the initial layout, the electronic device 110 can perform a detection regarding the splitting conditions on the first boundary graph and the second boundary graph associated through the first link to verify the splitting result. To determine that the association between the first region and the second region is based on the splitting conditions rather than being associated erroneously for other reasons, a detection regarding the splitting conditions, or a conflict test, can be performed on the associated first boundary graph and second boundary graph.

[0068] As an example, if it is detected that two associated regions are not based on the splitting conditions, and the boundary figures of these two regions are not restricted by the splitting conditions, then these two regions can be regarded as separate regions respectively. Correspondingly, the coloring and flipping of these two regions can be updated again. If it is detected that each pair of associated regions among multiple regions are all based on the splitting conditions, it is determined that the splitting result is correct. Such further verification can ensure the accuracy of the splitting result.

[0069] Embodiments of the present disclosure determine the association information of multiple regions divided by an initial layout by combining splitting conditions, and determine the coloring result of the associated regions, so as to determine the splitting result for the initial layout. Such a layout splitting scheme can improve the efficiency and accuracy of layout splitting. In addition, according to the relevance or irrelevance of adjacent regions among multiple regions, the associated adjacent regions and the separate regions that have no association with other regions can be respectively corresponding to distributed. In this way, the calculations for different regions can be executed in parallel through corresponding distributed nodes. By synchronizing the calculation results of each distributed node, the effects of accelerating the calculation and reducing the memory can be achieved, effectively reducing the memory and running time of the initial layout on advanced nodes.

[0070] Figure 4 A block diagram of an electronic device 400 in which one or more embodiments of the present disclosure may be implemented is shown. It should be understood that Figure 4 The electronic device 400 shown is merely exemplary and should not constitute any limitation to the functions and scope of the embodiments described herein. Figure 4 The electronic device 400 shown can be used to implement Figure 1 the electronic device 110.

[0071] As Figure 4 shown, the electronic device 400 is in the form of a general-purpose electronic device. The components of the electronic device 400 may include but are not limited to one or more processors or processing units 410, a memory 420, a storage device 430, one or more communication units 440, one or more input devices 450, and one or more output devices 460. The processing unit 410 may be an actual or virtual processor and is capable of performing various processes according to the programs stored in the memory 420. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing ability of the electronic device 400.

[0072] The electronic device 400 generally includes multiple computer storage media. Such media can be any accessible media that the electronic device 400 can access, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 420 can be a volatile memory (such as registers, caches, random access memory (RAM)), a non-volatile memory (such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 430 can be a removable or non-removable medium and can include machine-readable media, such as flash drives, magnetic disks, or any other medium that can be capable of storing information and / or data (such as training data for training) and can be accessed within the electronic device 400.

[0073] The electronic device 400 can further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in Figure 4 , a disk drive for reading from or writing to a removable, non-volatile magnetic disk (such as a "floppy disk") and an optical disk drive for reading from or writing to a removable, non-volatile optical disk can be provided. In these cases, each drive can be connected to a bus (not shown) by one or more data media interfaces. The memory 420 can include a computer program product 425 having one or more program modules that are configured to execute the various methods or actions of the various embodiments of the present disclosure.

[0074] The communication unit 440 enables communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 400 can be implemented by a single computing cluster or multiple computer machines that can communicate through a communication connection. Thus, the electronic device 400 can operate in a networked environment using a logical connection with one or more other servers, network personal computers (PCs), or another network node.

[0075] The input device 450 can be one or more input devices, such as a mouse, keyboard, trackball, etc. The output device 460 can be one or more output devices, such as a display, speaker, printer, etc. The electronic device 400 can also communicate with one or more external devices (not shown) as needed through the communication unit 440, such as storage devices, display devices, etc., communicate with one or more devices that enable a user to interact with the electronic device 400, or communicate with any device that enables the electronic device 400 to communicate with one or more other electronic devices (such as a network card, modem, etc.). Such communication can be performed via an input / output (I / O) interface (not shown).

[0076] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, and the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is further provided, the computer program product being tangibly stored on a non-transitory computer-readable medium and including computer-executable instructions, and the computer-executable instructions being executed by a processor to implement the method described above.

[0077] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is produced that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other devices to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured article that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0079] The computer-readable program instructions can be loaded onto a computer, other programmable data processing device, or other device, such that a series of operational steps are executed on the computer, other programmable data processing device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing device, or other device implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0080] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0081] The various implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art in the field without departing from the scope and spirit of the described implementations. The choice of terms used herein is intended to best explain the principles of the implementations, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the field to understand the various implementation manners disclosed herein.

Claims

1. A layout processing method, characterized in that: The method comprises: Determining, based on a splitting condition related to the layout splitting of the initial layout, region association information for a plurality of regions in the initial layout, the region association information indicating whether two adjacent regions in the plurality of regions are related in the layout splitting; In response to the region association information indicating that a first region and a second region adjacent to each other in the plurality of regions are related in the layout splitting, determining, from a structured representation corresponding to at least the first region and the second region, a first link of an association between a first boundary graphic and a second boundary graphic constrained by the splitting condition in the first region and the second region; If there are a plurality of first links between the first region and the second region, and the weight of a target first link among the plurality of first links is greater than the weights of other first links, coloring the graph in the structured representation based on a first boundary graph and a second boundary graph corresponding to the target first link so that the colors of the first boundary graph and the second boundary graph constrained by the splitting condition in the first region and the second region are aligned; and In response to the color alignment, a coloring transformation is performed on the first region or the second region to determine a coloring result of the first region and a coloring result of the second region, wherein the color of the graphic indicates the sub-layout into which the graphic will be split.

2. The method according to claim 1, characterized in that The first area and the second area have a common division boundary, and determining the area association information for the plurality of areas includes: determining whether a first boundary graphic close to the division boundary in the first region and a second boundary graphic close to the division boundary in the second region are constrained by the splitting condition; and In response to the first boundary graphic and the second boundary graphic being constrained by the splitting condition, it is determined that the first region and the second region are related in layout splitting.

3. The method according to claim 2, characterized in that The method further includes determining a first boundary graphic close to the partition boundary in the first region and a second boundary graphic close to the partition boundary in the second region by: Based on the splitting condition, determining an outward expansion size for each of the multiple regions; Based on the expansion size and the division boundary, respectively determine a first expansion region located in the second region for the first region and a second expansion region located in the first region for the second region; as well as A graphic in the first region that is located within the second expanded region is determined as the first boundary graphic, and a graphic in the second region that is located within the first expanded region is determined as the second boundary graphic.

4. The method according to claim 3, characterized in that Determining the external expansion size includes: The maximum graphic spacing indicated by the splitting condition is determined as the external expansion size.

5. The method according to claim 1, characterized in that Aligning the colors of the first boundary graphic and the second boundary graphic constrained by the splitting condition in the first area and the second area comprises: Based on the splitting condition, respectively performing graphic coloring based on at least two colors on the multiple regions, wherein the at least two colors correspond to the at least two sub-layouts respectively; and Based on the graphic coloring of the first region and the second region and the correlation between the first region and the second region, the colors of the first boundary graphic and the second boundary graphic in the first region and the second region are aligned.

6. The method according to claim 5, characterized in that The method further comprises: In response to the region association information indicating that a third region among the multiple regions is not related to adjacent regions of the third region in layout splitting, a coloring result for the third region is determined based on coloring the graph of the third region.

7. The method according to claim 5, characterized in that Aligning the colors of the first boundary graphic and the second boundary graphic in the first area and the second area further comprises: determining a target boundary graphic whose color is changed by the color alignment from the first boundary graphic and the second boundary graphic; and Based on the color change of the target boundary graphic, a coloring transformation is performed on a target region where the target boundary graphic is located to determine a coloring result of the target region, where the target region is the first region or the second region.

8. The method according to claim 1, characterized in that Also includes: Based on the first boundary graphic and the second boundary graphic, the structured representation corresponding to at least the first area and the second area is constructed.

9. The method according to claim 8, characterized in that The structured representation also includes: nodes corresponding to the first boundary graph and the second boundary graph respectively; a second link representing an association between the first boundary graphic and other graphics in the first region where the first boundary graphic is located; and A second link representing an association between the second boundary graphic and other graphics in the second area where the second boundary graphic is located.

10. The method according to claim 1, characterized in that The method further comprises: Based at least on the coloring result of the first area and the coloring result of the second area, a splitting result for the initial layout is determined, and the splitting result indicates that each graphic in the initial layout is split into at least two sub-layouts.

11. The method according to claim 9, characterized in that The method further comprises: Based on the splitting result of the initial layout, the first boundary graphic and the second boundary graphic associated through the first link are checked for the splitting condition to verify the splitting result, wherein the splitting result indicates that each graphic in the initial layout is split into at least two sub-layouts.

12. The method according to claim 1, characterized in that The method further comprises: Based on the configuration information of the initial layout, the initial layout is divided into the multiple areas, The configuration information includes at least one of the following: The hierarchical structure information and unit information of the initial layout, The type information of the initial layout, Customized information about the size of the layout division, or related information about dividing the initial layout according to multiple functions in the initial layout based on the constraints of the splitting conditions.

13. The method according to claim 1, characterized in that The splitting condition at least includes a design rule check (DRC) rule.

14. An electronic device, characterized in that: include: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 13 when executed by the at least one processing unit.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executable by a processor to implement the method according to any one of claims 1 to 13.

16. A computer program product comprising computer executable instructions, characterized in that: The computer executable instructions implement the method according to any one of claims 1 to 13 when executed by a processor.

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