Electronic device

Abstract

The invention discloses an electronic device which comprises a substrate and a time sequence control module. The time sequence control module transmits a plurality of time sequence control signals to the substrate, and comprises an overcurrent protection circuit for detecting the time sequence control signals. The over-current protection circuit comprises a subtractor and a comparator electrically connected with the subtractor. Wherein the time sequence control signals comprise a first time sequence control signal and a second time sequence control signal, the subtracter calculates a first current difference value between the pumping current values of the first time sequence control signal and the second time sequence control signal, and the comparator compares the first current difference value with a first threshold value; when the first current difference value is larger than or equal to the first threshold value, the over-current protection circuit executes an over-current protection mechanism.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to an electronic device with an overcurrent protection circuit. Background Art

[0002] With the development of technology, the appearance design of electronic devices has become more sophisticated. For example, the borderless design of display devices is the current trend. In order to achieve a borderless design, the driving circuit of the display device is often directly integrated with the display array on the same substrate, such as the gate driver design on the panel (GOP). However, in the process of electronic devices, if foreign objects fall onto the wiring of the driving circuit (such as the GOP circuit) in the peripheral area, or if damage or electrostatic discharge (ESD) is caused by the process, the wiring of the driving circuit will be short-circuited, which will generate a huge current in the peripheral area and may cause part of the substrate to burn.

[0003] Therefore, an electronic device with an overcurrent protection mechanism is needed to improve the above problems. Summary of the invention

[0004] The present invention provides an electronic device, characterized in that it comprises: a substrate and a timing control module, wherein the timing control module comprises an overcurrent protection circuit, and the overcurrent protection circuit comprises a subtractor and a comparator electrically connected to the subtractor. The timing control module transmits a timing control signal to the substrate; the overcurrent protection circuit detects a draw current value of the timing control signal. Wherein, the timing control signal comprises a first timing control signal and a second timing control signal, the subtractor calculates a current difference between the draw current value of the second timing control signal and the draw current value of the first timing control signal, the comparator compares the current difference with a first threshold value, and when the current difference is greater than or equal to the first threshold value, the overcurrent protection circuit executes an overcurrent protection mechanism.

[0005] The present invention further provides an electronic device, characterized in that it comprises: a substrate and a timing control module, wherein the timing control module comprises an overcurrent protection circuit, and the overcurrent protection circuit comprises a subtractor and a comparator electrically connected to the subtractor. The timing control module transmits a timing control signal to the substrate; the overcurrent protection circuit detects the draw current value of at least one timing control signal. Wherein, at least one timing control signal comprises a plurality of cycles, wherein at least one timing control signal has a draw current value at a specific time point of each cycle, and these draw current values ​​have a maximum value and a minimum value, the subtractor calculates a second current difference between the maximum value and the minimum value, the comparator compares the second current difference with a second threshold value, and when the second current difference is greater than or equal to the second threshold value, the overcurrent protection circuit performs an overcurrent protection mechanism.

[0006] Other novel features of the present invention will become more apparent from the following detailed description when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention;

[0008] Figure 2 is a timing diagram of a timing control signal according to an embodiment of the present invention;

[0009] Figure 3 is a circuit structure diagram of an overcurrent protection circuit according to an embodiment of the present invention;

[0010] Figure 4 is a circuit structure diagram of an overcurrent protection circuit according to another embodiment of the present invention;

[0011] FIG5(A) is a first schematic diagram of the timing of a timing control signal according to another embodiment of the present invention;

[0012] FIG5(B) is a second schematic diagram of the timing of FIG5(A);

[0013] FIG. 5(C) is a circuit structure diagram of an overcurrent protection circuit according to another embodiment of the present invention.

[0014] Explanation of symbols:

[0015] 1 Electronic devices

[0016] 2 substrate

[0017] 3 Circuit Board

[0018] 4 Timing Control Module

[0019] 5. Driving Circuit

[0020] 6 Display Array

[0021] 7 Pulse Width Modulator

[0022] 8 Timing Controller

[0023] 9-bit level adjuster

[0024] 10 Overcurrent protection circuit

[0025] 11 Subtractor

[0026] 12 Comparator

[0027] 13 First Multiplexer

[0028] 14 Second multiplexer

[0029] 15. First sampling circuit

[0030] 151 First Sampler

[0031] 152 First register

[0032] 153 Second comparator

[0033] 16. Second sampling circuit

[0034] 161 Second Sampler

[0035] 162 Second register

[0036] 163 Third comparator

[0037] 17 Adder

[0038] T1 first threshold

[0039] T2 Second threshold

[0040] t Timeline

[0041] Time t1~t9

[0042] AA display area

[0043] B Non-display area

[0044] CLK1~CLK(N) timing control signal

[0045] CLK(N)max Maximum draw current value

[0046] CLK(N)min Minimum draw current value

[0047] P1, P2, P3 cycles

[0048] S1 Specific Node

[0049] CLKmax(S1) Maximum current draw value on a specific node

[0050] CLKmax_max(S1) Maximum value

[0051] CLKmax_min(S1) minimum value

[0052] base preset base value

[0053] temp1 first temporary value

[0054] temp2 Second temporary value

[0055] sync synchronization trigger signal

[0056] VGH High potential

[0057] VGL Low potential

[0058] RESET Reset signal

[0059] 13' Third Multiplexer

[0060] 14' Fourth Multiplexer

[0061] 15' Third sampling circuit

[0062] 16' Fourth sampling circuit DETAILED DESCRIPTION

[0063] When read in conjunction with the accompanying drawings, the following embodiments are used to clearly demonstrate the above and other technical contents, features and / or effects of the present invention. Through the description of the specific implementation methods, those skilled in the art will further understand the technical means and effects adopted by the present invention to achieve the above-mentioned purpose. In addition, since the content disclosed in the present invention should be easy to understand and can be implemented by those skilled in the art, all equivalent substitutions or modifications that do not depart from the concept of the present invention should be included in the claims.

[0064] It should be noted that, herein, unless specifically stated otherwise, “a” or “an” element is not limited to a single element but may refer to one or more elements.

[0065] In addition, ordinals such as "first" or "second" in the specification and claims are only used to describe the claimed elements, and do not represent or indicate that the claimed elements have any order, and are not the order between the claimed elements and another claimed element or between the steps of the manufacturing method. The use of these ordinals is only to distinguish one claimed element with a specific name from another claimed element with the same name.

[0066] Furthermore, the term "adjacent" in the specification and claims is used to describe being near each other, but does not necessarily mean being in contact with each other.

[0067] In addition, the descriptions of "when..." or "when..." in the present invention indicate "at the moment, before or after", etc., and are not limited to the situation of simultaneous occurrence, which are explained here together. The descriptions of "disposed on..." and the like in the present invention indicate the corresponding positional relationship between two elements, and are not limited to whether the two elements are in contact, unless otherwise specified, which are explained here together. Furthermore, when the present invention records multiple effects, if the word "or" is used between the effects, it means that the effects can exist independently, but it does not exclude that multiple effects can exist at the same time.

[0068] In addition, the term "connect" or "couple" in the specification and claims may refer to not only direct connection with another element but also indirect connection or electrical connection with another element.

[0069] In addition, in the specification and claims, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The number given here is an approximate number, that is, in the absence of specific instructions for "about", "approximately", "substantially", and "roughly", the meaning of "about", "approximately", "substantially", and "roughly" can still be implied. In addition, the terms "range from a first value to a second value" and "range between a first value and a second value" mean that the range includes the first value, the second value, and other values ​​therebetween.

[0070] In addition, the technical features of different embodiments disclosed in the present invention may be combined to form another embodiment.

[0071] In addition, the electronic device disclosed in the present invention may include a display device, an antenna device, a sensing device, a touch display, a curved display or a free shape display, but is not limited thereto. The electronic device 1 may be a bendable or flexible electronic device. The electronic device 1 may, for example, include a liquid crystal, a light emitting diode, fluorescence, phosphorescence, other suitable display media, or a combination thereof, but is not limited thereto. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum dot, QD, which may be, for example, QLED, QDLED) or other suitable materials or any combination of the above materials, but is not limited thereto. The display device may, for example, include a spliced ​​display device, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include a spliced ​​antenna device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In addition, the shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device can have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support the display device, the antenna device or the splicing device.

[0072] For the convenience of description, the electronic device will be described below in the form of a display device, but the present invention is not limited thereto.

[0073] Figure 1 FIG. 1 is a schematic diagram of the structure of an electronic device 1 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 1 includes: a substrate 2, a circuit board 3 and a timing control module 4, wherein the timing control module 4 is disposed on the circuit board 3, and the timing control module 4 includes an overcurrent protection circuit 10. The substrate 2 is electrically connected to the circuit board 3. When the electronic device 1 is in the form of a display device, the substrate 2 can be a display array substrate, and the circuit board 3 can be provided with a control circuit of the display array substrate, but is not limited thereto. The timing control module 4 can transmit a plurality of timing control signals CLK1~CLK(N) to the substrate 2, wherein N is a positive integer greater than or equal to 2. In one embodiment, the timing control signals CLK1~CLK(N) can be transmitted through different routings. The overcurrent protection circuit 10 is used to detect the current size of the timing control signals CLK1~CLK(N) transmitted by the timing control module 4, and includes a subtractor 11 and a comparator 12.

[0074] At least one feature of the present invention is that the overcurrent protection circuit 10 can perform a first detection mechanism or a second detection mechanism on the timing control signals CLK1-CLK(N) through the subtractor 11 and the comparator 12, and determine whether to perform an overcurrent protection mechanism. The form of the overcurrent protection mechanism includes but is not limited to: causing the timing control module 4 to stop transmitting the timing control signals CLK1-CLK(N) to the substrate 2.

[0075] To clearly explain the content of the present invention, the timing control signals CLK1 -CLK(N) will be described first, and the details of each element will be described in the subsequent paragraphs.

[0076] Figure 2 1 is a timing diagram of the timing control signals CLK1-CLK(N) according to an embodiment of the present invention. For the convenience of explanation, N is taken as an example of 5, that is, the timing control signals CLK1-CLK(N) include a first timing control signal CLK1, a second timing control signal CLK2, a third timing control signal CLK3, a fourth timing control signal CLK4 and a fifth timing control signal CLK5. In addition, Figure 2 The timing diagram corresponds to a timing within an operation period of the electronic device 1 (e.g., a screen display period), wherein the horizontal axis of the timing diagram is a time axis t, and the vertical axis is a potential or current, wherein the time axis t includes a plurality of time points, such as t1 to t9, and each adjacent two time points have the same interval. Furthermore, the numbers between the first timing control signal CLK1 to the Nth timing control signal CLK(N) are arranged according to the timing sequence, that is, for Figure 2In the embodiment, the first timing control signal CLK1 has the earliest high potential period (the duration of VGH, corresponding to time points t1 to t4), and the fifth timing control signal CLK5 has the latest high potential period (corresponding to time points t5 to t8). In addition, the timing of the high potential periods between every two adjacent timing control signals (such as CLK1 and CLK2, CLK2 and CLK3, CLK3 and CLK4, CLK4 and CLK5) has the same time interval, for example, all separated by 1 time point, but not limited thereto.

[0077] like Figure 2 As shown, the timing control signals CLK1-CLK5 can provide a basic current (e.g., a current value of 0) during the low potential period (the duration of VGL), and the timing control signals CLK1-CLK5 can provide a current (hereinafter referred to as a pump current) with a current value different from the basic current during the high potential period (the duration of VGH). The pump current value of the pump current can change with time, so it has a maximum pump current value and a minimum pump current value. In this embodiment, the maximum pump current value corresponds to the starting time point of the high potential period, and under normal circumstances, the pump current value will decrease to the minimum current value as time passes. For example, the first timing control signal CLK1 at the starting time point of the high potential period (VGH) (e.g. Figure 2 The maximum current draw value CLK1max is at t1 or t8 in the figure, and decreases to the minimum current value CLK1min (e.g., decreases to the base current) over time. In addition, the high potential period (VGH) of the timing control signals CLK1-CLK5 all provide the same potential waveform (e.g., a square wave signal of the same magnitude), so the current draw of the timing control signals CLK1-CLK5 also has the same waveform.

[0078] It should be noted that the present invention uses the example of the timing control signals CLK1 - CLK5 providing positive potentials during the high potential period as an example. Those skilled in the art can infer the situation where the timing control signals CLK1 - CLK5 provide negative potentials during the high potential period.

[0079] The first detection mechanism or the second detection mechanism of the present invention can detect the draw current value of the timing control signals CLK1 - CLK5 to reduce the probability of substrate burnout due to wiring short circuit.

[0080] The first detection mechanism of the present invention is: a current difference (hereinafter referred to as a first current difference) between the draw current values ​​of one of the timing control signals CLK1~CLK5 and another of the timing control signals is calculated by a subtractor 11, wherein the one of the timing control signals and the another of the timing control signals are two timing control signals (e.g., CLK1 and CLK2) that are adjacent in time sequence; for convenience of explanation, the first timing control signal CLK1 and the second timing control signal CLK2 are used as an example for explanation, wherein the first timing control signal CLK1 has a maximum draw current value (CLK1max) at a first time point (e.g., t1), and the second timing control signal CLK2 has a maximum draw current value (CLK2max) at a second time point (e.g., t2), so the first current difference may be a current difference between the maximum draw current value (CLK2max) of the second timing control signal CLK2 and the maximum draw current value (CLK1max) of the first timing control signal CLK1. Next, the comparator 12 compares the first current difference (eg, CLK2max-CLK1max) with a first threshold value T1 (indicated at Figure 3 ), when the first current difference (CLK2max-CLK1max) is greater than or equal to the first threshold value T1, the overcurrent protection circuit 10 performs the overcurrent protection mechanism.

[0081] It should be noted that, although in the present embodiment, the first current difference (e.g., CLK2max-CLK1max) is obtained by subtracting the maximum draw current value (e.g., CLK2max) of the timing control signal (e.g., CLK2) with a later timing from the maximum draw current value (e.g., CLK1max) of the timing control signal (e.g., CLK1) with an earlier timing, in other embodiments, the first current difference may also be in the opposite form (e.g., CLK1max-CLK2max), but is not limited thereto.

[0082] In one embodiment, the overcurrent protection circuit 10 may be configured to execute the current protection mechanism as long as any first current difference (eg, CLK2max-CLK1max, CLK3max-CLK2max, . . . , CLK5max-CLK4max) is detected to be greater than or equal to the first threshold value T1, but this is not limiting.

[0083] In addition, in one embodiment, the timing control signals (CLK1-CLK5) further include a last timing control signal, such as a fifth timing control signal CLK5, which has a maximum draw current value (CLK5max) at a fifth time point (such as t5) after the second time point (such as t2). In one embodiment, the subtractor 11 can calculate a current difference (such as CLK1max-CLK5max) between the draw current values ​​of the first timing control signal (such as CLK1) and the fifth timing control signal (such as CLK5), and the comparator 12 can compare the current difference (such as CLK1max-CLK5max) with a first threshold value (T1); when the current difference (such as CLK1max-CLK5max) is greater than or equal to the first threshold value T1, the overcurrent protection circuit 10 also performs an overcurrent protection mechanism.

[0084] In one embodiment, the first threshold value T1 may be between 5 and 250 mA (5mA≦T1≦250mA). In one embodiment, the first threshold value may be between 10 and 250 mA (10mA≦T1≦250mA). In one embodiment, the first threshold value may be between 10 and 200 mA (10mA≦T1≦200mA). In one embodiment, the first threshold value may be between 10 and 150 mA (10mA≦T1≦150mA). In one embodiment, the first threshold value may be between 10 and 100 mA (10mA≦T1≦100mA). In one embodiment, the first threshold value may be between 15 and 100 mA (15mA≦T1≦100mA). In one embodiment, the first threshold value may be between 20 and 50 mA (20 mA≦ T1≦50 mA). The present invention is not limited thereto.

[0085] Next, the details of the substrate 2, the circuit board 3 and the timing control module 4 will be described in detail. Please refer to Figure 1 and Figure 2 .

[0086] First, the details of the substrate 2 are described. In addition to being used in a display device, the substrate 2 can also be used in an antenna device, a sensing device or a splicing device, etc., and is not limited thereto. In one embodiment, an active component may be provided on the substrate 2, and the active component may include a transistor. The substrate 2 includes a flexible substrate or a non-flexible substrate, and its material may include, for example, glass, quartz, a wafer, a sapphire substrate, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable materials or a combination of the above materials, but the present invention is not limited thereto.

[0087] In addition, when the electronic device 1 is a display device, the substrate 2 may be a display array substrate. The substrate 2 may include a display area (AA) and a non-display area (B), wherein the non-display area (B) is disposed next to the display area (AA), and the non-display area (B) is electrically connected to the timing control module 4. In one embodiment, the peripheral area (B) may include at least one driving circuit 5, such as a gate driving circuit, a source driving circuit, etc., and is not limited thereto. In one embodiment, the display area (AA) may include a display array 6, wherein the driving circuit 5 is electrically connected to the display array 6. In one embodiment, the driving circuit 5 includes a gate driver design circuit (GOP circuit), the GOP circuit receives the timing control signals CLK1~CLK(N) from the timing control module 4, and generates a plurality of gate signals according to the timing control signals CLK1~CLK(N). In one embodiment, the display array 6 may include a plurality of scan lines (not shown), and each of the timing control signals CLK1~CLK(N) may correspond to a single or multiple scan lines.

[0088] Next, the details of the circuit board 3 are described. The circuit board 3 is disposed outside the substrate 2. A variety of electronic components can be disposed on the circuit board 3, and these electronic components can form a variety of electronic circuits, such as the timing control module 4, but are not limited thereto. In one embodiment, the circuit board 3 can be a printed circuit board (PCB), a flexible printed circuit (FPC), etc., but are not limited thereto.

[0089] Next, the details of the timing control module 4 are described. In one embodiment, the timing control module 4 may include a pulse width modulator (PWM) 7, a time controller (TCON) 8 and a level shifter (LS) 9, wherein the pulse width modulator 7 is electrically connected to the timing controller 8, the timing controller is electrically connected to the level shifter 9, and the overcurrent protection circuit 10 may be disposed in the level shifter 9, but may also be separated. In one embodiment, the pulse width modulator 7, the timing controller 8 or the level shifter 9 may each be implemented in the form of an electronic circuit, but in another embodiment, if the circuit board 3 has a processor, the pulse width modulator 7, the timing controller 8 or the level shifter 9 may also be implemented in the form of software or firmware. In one embodiment, the pulse width modulator 7 may provide an initial voltage to the timing controller 8. The timing controller 8 may use the initial voltage to generate the timing control signals CLK1~CLK(N). The level adjuster 9 can adjust the voltage levels of the timing control signals CLK1-CLK(N) and transmit the adjusted timing control signals CLK1-CLK(N) to the substrate 2. In one embodiment, the level adjuster 9 can transmit the timing control signals CLK1-CLK(N) to the overcurrent protection circuit 10 at the same time.

[0090] In addition, in one embodiment, the overcurrent protection circuit 10 can be electrically connected to the pulse width adjuster 7 or the timing controller 8 (at least one), whereby, when the overcurrent protection circuit 10 performs the overcurrent protection mechanism, the overcurrent protection circuit 10 can transmit a control signal to the pulse width adjuster 7, the timing controller 8 or the level adjuster 9 to stop the operation of the pulse width adjuster 7, the timing controller 8 or the level adjuster 9, but is not limited thereto. When the pulse width adjuster 7, the timing controller 8 or the level adjuster 9 is an electronic circuit, the above mechanism can be implemented by at least setting a switch element (such as a transistor) in the pulse width adjuster 7, the timing controller 8 or the level adjuster 9, but is not limited thereto.

[0091] Next, the circuit structure and circuit operation of the overcurrent protection circuit 10 will be described with reference to an embodiment. Figures 1 to 3 , and for the convenience of description, N is taken as 5. It should be noted that the circuit structure and circuit operation method of the present invention are not limited to the following contents.

[0092] Figure 3 FIG. 1 is a circuit diagram of an overcurrent protection circuit 10 according to an embodiment of the present invention, which is applicable to (but not limited to) the first detection mechanism. Figure 3As shown, the overcurrent protection circuit 10 suitable for the first detection mechanism may include a subtractor 11, a comparator 12, a first multiplexer 13, a second multiplexer 14, a first sampling circuit 15 and a second sampling circuit 16, wherein the first multiplexer 13 is electrically connected to the first sampling circuit 15, the first sampling circuit 15 is electrically connected to the subtractor 11, the second multiplexer 14 is electrically connected to the second sampling circuit 16, the second sampling circuit 16 is electrically connected to the subtractor 11, and the subtractor 11 is electrically connected to the comparator 12.

[0093] First, the details of the first multiplexer 13 and the second multiplexer 14 are described. In one embodiment, the first multiplexer 13 may include a plurality of input terminals (e.g., at least 5) to receive the timing control signals CLK1~CLK5 transmitted by the level adjuster 9 (e.g., simultaneously or sequentially). The first multiplexer 13 may include an output terminal to output one of the timing control signals CLK1~CLK5. The second multiplexer 14 also includes a plurality of input terminals (e.g., at least 5) to receive the timing control signals CLK1~CLK5 transmitted by the level adjuster 9. The second multiplexer 14 also includes an output terminal to output one of the timing control signals CLK1~CLK(N). That is, the overcurrent protection circuit 10 can receive the timing control signal transmitted by the level adjuster 9 through the first multiplexer 13 and the second multiplexer 14.

[0094] In one embodiment, the first multiplexer 13 and the second multiplexer 14 may include switch elements (not shown) inside, so the first multiplexer 13 and the second multiplexer 14 may select the timing control signal output each time by switching the switch elements, but the invention is not limited thereto. In addition, when the first multiplexer 13 outputs a timing control signal (e.g., outputs the first timing control signal CLK1), the second multiplexer 14 is set to output another timing control signal (e.g., outputs the second timing control signal CLK2).

[0095] Next, the details of the first sampling circuit 15 and the second sampling circuit 16 are described. In one embodiment, the first sampling circuit (15) is disposed between the first multiplexer (13) and the subtractor (11), and the second sampling circuit (16) is disposed between the second multiplexer (14) and the subtractor (11), wherein. The first sampling circuit 15 may include a first sampler 151 and a first register 152, wherein the first sampler 151 is disposed between the first multiplexer 13 and the first register 152. The second sampling circuit 16 may include a second sampler 161 and a second register 162, wherein the second sampler 161 is disposed between the second multiplexer 14 and the second register 162. In one embodiment, the first sampling circuit 15 may sample the first timing control signal CLK1 starting from a first time point (e.g., t1) corresponding to the maximum draw current value CLK1max of the draw current of the first timing control signal CLK1 via the first sampler 151, and the second sampling circuit 16 may sample the second timing control signal CLK2 starting from a second time point (e.g., t2) corresponding to the maximum draw current value CLK2max of the draw current of the second timing control signal CLK2 via the second sampler 161, but the present invention is not limited thereto.

[0096] Depend on Figure 2 As can be seen from the timing diagram, the current extraction timing of each timing control signal CLK1~CLK5 is different. Therefore, if the first current difference is to be calculated (taking the first timing control signal CLK1 and the second timing control signal CLK2 as an example), the timings of the maximum current extraction values ​​(such as CLK1max and CLK2min) of the two timing control signals (CLK1 and CLK2) can be aligned to calculate the first current difference.

[0097] In this regard, in one embodiment, the first sampler 151 may be configured to start sampling the first timing control signal CLK1 from a first time point (e.g., t1) corresponding to a maximum current draw value CLK1max of the first timing control signal CLK1 to obtain one or more current draw values ​​of the first timing control signal CLK1. In one embodiment, the second sampler 161 may be configured to start sampling the second timing control signal CLK2 from a second time point (e.g., t2) corresponding to a maximum current draw value CLK2max of the second timing control signal CLK2 to obtain one or more current draw values ​​of the second timing control signal, wherein the first time point (e.g., t1) is smaller than the second time point (e.g., t2). In one embodiment, the first sampler 151 and the second sampler 161 may each set the sampling time point by inputting a synchronization trigger signal (sync). In this way, the sampled first timing control signal CLK1 and the second timing control signal CLK2 may be aligned.

[0098] Next, the first sampler 151 stores the sampled current value of the first timing control signal CLK1 into the first register 152, and the first register 152 transmits the current value of the first timing control signal CLK1 to the subtractor 11. Similarly, the second sampler 161 stores the sampled current value of the second timing control signal CLK2 into the second register 162, and the second register 162 transmits the current value of the second timing control signal CLK2 to the subtractor 11.

[0099] Next, the subtractor 11 is described. In one embodiment, the subtractor 11 can perform a difference calculation on the draw current value of the first timing control signal CLK1 and the draw current value of the second timing control signal CLK2 to obtain a first current difference value (e.g., CLK2max-CLK1max) between the second timing control signal CLK2 and the first timing control signal CLK1, and transmit the first current difference value (e.g., CLK2max-CLK1max) to the comparator 12. In one embodiment, the first current difference value can be, for example, the current value at the same time point after the two timing control signals (CLK1 and CLK2) are aligned and subtracted (e.g., CLK1max and CLK2max after alignment), but it can also be the draw current values ​​at multiple aligned time points that are subtracted to obtain multiple differences, and then the multiple differences are averaged. In addition, in one embodiment, the subtractor 11 can receive a reset signal (RESET) to reset after each subtraction, but is not limited thereto.

[0100] Next, the comparator 12 is described. In one embodiment, the comparator 12 may include two input terminals and an output terminal, wherein one input terminal may receive a first current difference (e.g., CLK2max-CLK1max), and the other input terminal may receive a first threshold value T1, and compare the first current difference (e.g., CLK2max-CLK1max) with the first threshold value T1. The comparator 12 may output a control signal (disable) to the pulse width adjuster 7, the timing controller 8, or the level adjuster 9 according to the comparison result, thereby controlling the operation of the pulse width adjuster 7, the timing controller 8, or the level adjuster 9. Thus, for example, when a short circuit occurs in the routing of the second timing control signal CLK2, the draw current value of the second timing control signal CLK2 will be higher than normal (e.g., Figure 2 ) of the draw current value, at this time, the overcurrent protection circuit 10 can execute the overcurrent protection mechanism according to the result that the first current difference (CLK2max-CLK1max) is greater than or equal to the first threshold value T1 (other timing control signals can be deduced in the same way), so that the electronic device 1 stops operating to prevent burning due to short circuit.

[0101] In addition, in one embodiment, the overcurrent protection circuit 10 may further include an adder 17, which is disposed between the subtractor 11 and the comparator 12. The adder 17 may add the first current difference (e.g., CLK2max-CLK1max) and a preset base value (base), so that the value input to the comparator 12 will be CLK2max-CLK1max+base. The advantage of this method is that the setting of the first threshold value T1 can be made more flexible. For example, through the present invention, the judgment of the protection current of the electronic device can be reduced due to process variations or user ambient temperature changes.

[0102] Thereby, the over-current protection circuit 10 of this embodiment can implement the first detection mechanism.

[0103] In addition, the over-current protection circuit 10 also has different implementations. Figure 4 is a circuit structure diagram of an overcurrent protection circuit 10 according to another embodiment of the present invention, which is also applicable to (but not limited to) the first detection mechanism, and please also refer to Figures 1 to 4 , and for the convenience of explanation, N is taken as 5 as an example.

[0104] because Figure 4 Examples and Figure 3 The embodiments are generally similar, so only the differences are described below: Figure 3 In the embodiment, the first multiplexer 13 and the second multiplexer 14 obtain the timing control signals CLK1 - CLK5 in advance, and output one of them to the first sampling circuit 15 and the second sampling circuit 16 for sampling; Figure 4 In the embodiment, a third sampling circuit 15' and a fourth sampling circuit 16' are used to sample a plurality of timing control signals CLK1-CLK5, and then the sampled timing control signals CLK1-CLK5 are transmitted to a third multiplexer 13' and a fourth multiplexer 14', so that the third multiplexer 13' and the fourth multiplexer 14' can directly transmit one of the timing control signals CLK1-CLK5 to the subtractor 11. In other words, Figure 4 The third sampling circuit 15 ′ and the fourth sampling circuit 16 ′ of the embodiment can be moved out of the overcurrent protection circuit 10 , thereby reducing the number of components of the overcurrent protection circuit 10 itself.

[0105] Next, the second detection mechanism of the present invention is described. Please also refer to Figure 5(A)~5(C)5(A) is a first schematic diagram of the timing of a timing control signal (taking the first timing control signal CLK1 as an example) of another embodiment of the present invention, which shows the timing continuity state of the first timing control signal CLK1, FIG5(B) is a second schematic diagram of the timing of FIG5(A), which presents the draw current value of the first timing control signal CLK1 in each cycle P1~P3 according to the corresponding relationship of each time point, and FIG5(C) is a circuit structure diagram of an overcurrent protection circuit 10 of another embodiment of the present invention, which can be applied to the second detection mechanism (but can also be applied to the first detection mechanism), and for the convenience of explanation, N is taken as an example of 5.

[0106] The second detection mechanism of the present invention is: the overcurrent detection circuit 10 detects the draw current value of one of the timing control signals at a specific time point S1 in each cycle, and compares the difference between a maximum value and a minimum value of the draw current values ​​at the specific time point S1 of each cycle with a second threshold value T2, and determines whether a short circuit occurs. The following takes the detection of the first timing control signal CLK1, and the specific time point S1 is the time point of the maximum draw current value in the cycle as an example.

[0107] As shown in FIG5(A), the first timing control signal CLK1 may include a plurality of periods, such as a first period P1, a second period P2, and a third period P3. At time point t1 during the high potential period (VGH) of the first period P1, the first timing control signal CLK1 has a maximum draw current value CLK1max(t1) in the first period P1; at time point t8 during the high potential period (VGH) of the second period P2, the first timing control signal CLK1 has a maximum draw current value CLK1max(t8) in the second period P2; at time point t9 during the high potential period (VGH) of the third period P3, the first timing control signal CLK1 has a maximum draw current value CLK1max(t8) in the second period P2. 15 When the maximum draw current value CLK1max (t 15 ). In other words, when the time points t1, t8 and t 15 When the specific time point S1 of each cycle P1-P3 is used, the draw current value CLK1max(S1) of the first timing control signal CLK1 at the specific time point S1 of each cycle P1-P3 is the maximum draw current value CLK1max(t1), CLK1max(t8) and CLK1max(t 15 In one embodiment, the maximum draw current values ​​CLK1max(t1), CLK1max(t8) and CLK1max(t 15 ) may be identical, not identical, or neither identical.

[0108] In one embodiment, the over-current detection circuit 10 can find out the first timing control signal CLK1 at a specific time point S1 (t1, t8 and t 15 ) on the load current value (for example, CLK1max(t1), CLK1max(t8) and CLK1max(t 15 )) and the minimum value (defined as CLK1max_max(S1), marked in FIG5(C)) and the maximum value (defined as CLK1max-min(S1), marked in FIG5(C)) among the maximum value and the minimum value, and a current difference between the maximum value and the minimum value is calculated (defined as CLK1max_max(S1)-CLK1max_min(S1), marked in FIG5(C), hereinafter referred to as the second current difference). Then, the overcurrent protection circuit 10 can compare the second current difference CLK1max_max(S1)-CLK1max_min(S1) with the second threshold value T2 (marked in FIG5(C)). When the second current difference CLK1max_max(S1)-CLK1max_min(S1) is greater than or equal to the second threshold value T2, the overcurrent protection circuit 10 can execute the overcurrent protection mechanism.

[0109] In one embodiment, the over-current protection circuit 10 may be configured to execute the current protection mechanism as long as it detects that the second current difference of any timing control signal (eg, CLK1 - CLK5 ) is greater than or equal to the second threshold value, but this is not a limitation.

[0110] In one embodiment, the second threshold value T2 may be between 5 and 250 mA (5mA≦T2≦250mA). In one embodiment, the second threshold value may be between 10 and 250 mA (10mA≦T2≦250mA). In one embodiment, the second threshold value may be between 10 and 200 mA (10mA≦T2≦200mA). In one embodiment, the second threshold value may be between 10 and 150 mA (10mA≦T2≦150mA). In one embodiment, the second threshold value may be between 10 and 100 mA (10mA≦T2≦100mA). In one embodiment, the second threshold value may be between 15 and 100 mA (15mA≦T2≦100mA). In one embodiment, the first threshold value may be between 20 and 50 mA (20 mA≦ T1≦50 mA). The present invention is not limited thereto.

[0111] In one embodiment, the first threshold value T1 and the second threshold value T2 may be different, but this is not a limitation. In one embodiment, the electronic device 1 may have both the first detection mechanism and the second detection mechanism, but may also have only one of them.

[0112] The second detection mechanism can at least be implemented by the circuit structure of FIG. 5(C) .

[0113] As shown in FIG5(C), the overcurrent protection circuit 10 may include a subtractor 11, a comparator 12, a first multiplexer 13, a second multiplexer 14, a first sampling circuit 15, and a second sampling circuit 16, wherein the first multiplexer 13 is electrically connected to the first sampling circuit 15, the first sampling circuit 15 is electrically connected to the subtractor 11, the second multiplexer 14 is electrically connected to the second sampling circuit 16, the second sampling circuit 16 is electrically connected to the subtractor 11, and the subtractor 11 is electrically connected to the comparator 12. The following takes the detection of the first timing control signal CLK1 as an example.

[0114] First, the details of the first multiplexer 13 and the second multiplexer 14 are described. In one embodiment, the first multiplexer 13 and the second multiplexer 14 each receive at least one of the timing control signals CLK1 -CLK5 and output the first timing control signal CLK1 to the first sampling circuit 15 and the second sampling circuit 16 .

[0115] Next, the details of the first sampling circuit 15 and the second sampling circuit 16 are described. In one embodiment, the first sampling circuit 15 comprises a first sampler 151, a first register 152 and a second comparator 153, wherein the second comparator 153 comprises two input terminals and an output terminal, and the first sampler 151 is connected to one input terminal of the second comparator 153, and the first register 152 is connected to the other input terminal and the output terminal of the second comparator 153.

[0116] When the first sampling circuit 15 operates, the first sampler 151 extracts the current of the first timing control signal CLK1 at a specific node S1 (e.g., t1, t8, or t 15 ) on the maximum draw current value CLK1max(S1) (for example, CLK1max(t1), CLK1max(t8) and CLK1max(t 15 )) is sampled, and the maximum draw current value CLK1max(S1) sampled each time is continuously transmitted to an input terminal of the second comparator 153. The first register 152 continuously transmits a first temporary value temp1 to another input terminal of the second comparator 153, so that the second comparator 153 continuously compares the maximum draw current value CLK1max(S1) with the first temporary value temp1. As long as the maximum draw current value CLK1max(S1) is greater than the first temporary value temp1, the output terminal of the second comparator 153 outputs the maximum draw current value CLK1max(S1) to the first register 152, and the first register 152 replaces the current value of the first temporary value temp1 with the maximum draw current value CLK1max(S1).

[0117] Thus, when all the sampled maximum draw current values ​​CLK1max(S1) (eg, CLK1max(t1), CLK1max(t8) or CLK1max(t 15 )) are compared with the first temporary value temp1, the first temporary value temp1 in the first register 152 can form the maximum value CLK1max_max(S1) of the maximum draw current value CLK1max(S1) at the specific time point S1 in the period P1~P3 of the first timing control signal CLK1. Afterwards, the first register 152 can transmit the first temporary value temp1 with the maximum value CLK1max_max(S1) to the subtractor 11. In one embodiment, the initial value of the first temporary value temp1 is set to a low current value, such as the lowest current value or the current value of 0, but is not limited thereto.

[0118] In addition, in one embodiment, the second sampling circuit 16 includes a second sampler 161, a second register 162 and a third comparator 163, wherein the third comparator 163 includes two input terminals and an output terminal, and the second sampler 161 is connected to one of the input terminals of the third comparator 163, and the second register 162 is connected to the other input terminal and the output terminal of the second comparator 163.

[0119] When the second sampling circuit 16 is in operation, the second sampler 161 extracts the current of the first timing control signal CLK1 at a specific time point S1 (eg, t1, t8 or t 15 ) on the maximum draw current value CLK1max(S1) (for example, CLK1max(t1), CLK1max(t8) and CLK1max(t 15)) is sampled, and the maximum draw current value CLK1max(S1) obtained by each sampling is continuously transmitted to an input terminal of the third comparator 163, the second register 162 continuously transmits a second temporary value temp2 to another input terminal of the third comparator 163, and the third comparator 163 continuously compares the maximum draw current value CLK1max(S1) with the second temporary value temp2. ​​As long as the maximum draw current value CLK1max(S1) is less than the second temporary value temp2, the third comparator 163 outputs the maximum draw current value CLK1max(S1) to the second register 162, and the second register 162 replaces the current value of the second temporary value temp2 with the maximum draw current value CLK1max(S1). Thus, after all the sampled current values ​​are compared with the second temporary value temp2, the second temporary value temp2 in the second register 162 may be the minimum value CLK1max_min(S1) among the maximum draw current values ​​CLK1max(S1) at a specific time point S1 in a plurality of cycles P1-P3 of the first signal (CLK1). Then, the second register 162 may transmit the second temporary value (i.e., CLK1max_min(S1)) to the subtractor 11. In one embodiment, the initial value of the second temporary value is set to a high current value, such as the maximum draw current value CLK1max(S1) when no short circuit occurs, but is not limited thereto.

[0120] Next, the subtractor 11 and the comparator are described. In one embodiment, the subtractor 11 can perform a difference calculation on the maximum value CLK1max_max (S1) and the minimum value CLK1max_min (S1) of the draw current value at a specific time point S1 of each cycle P1 to P3 of the first timing control signal CLK1 to obtain a second current difference CLK1max_max (S1)-CLK1max_min (S1), and the comparator 12 can compare the second current difference CLK1max_max (S1)-CLK1max_min (S1) with the second threshold value T2 to determine whether to execute the over-current protection mechanism.

[0121] For example, if the first period P1 is normal and a short circuit occurs in the second period P2, the maximum draw current value CLK1max(t8) in the second period P2 will be higher than the maximum draw current value CLK1max(t8) in the normal state (such as the maximum draw current value CLK1max(t8) in FIG. 5(B)). At this time, through the second detection mechanism, the overcurrent protection circuit 10 can know that the second current difference (e.g., CLK1max(t8)-CLK1max(t1)) is greater than or equal to the second threshold value T2, and execute the overcurrent protection mechanism.

[0122] In addition, as Figure 3Embodiment: In one embodiment, the over-current protection circuit 10 of the embodiment of FIG. 5 may also be added with an adder 17 .

[0123] In addition, as Figure 4 Embodiment. In one embodiment, the overcurrent protection circuit 10 of the embodiment of FIG. 5 may also replace the first sampling circuit 15 and the second sampling circuit 16 with a third sampling circuit 15' and a fourth sampling circuit 16', and move them to the outside of the overcurrent protection circuit 10, and input the sampled maximum value (e.g., CLK1max_max(S1)) to the third multiplexer 13', and input the sampled minimum value (e.g., CLK1max_min(S1)) to the fourth multiplexer 14'.

[0124] In addition, in one embodiment, the electronic device 1 of the present invention can also perform a third detection mechanism. The third detection mechanism can be used to detect the situation where all the routings of the timing control signals (such as CLK1 to CLK5) are short-circuited (hereinafter referred to as full short-circuit).

[0125] Please refer again Figure 2 The third detection mechanism is set as follows: calculating the difference (CLK1max-CLK5, defined as the third current difference) between the maximum draw current value of the first timing control signal CLK1 in a second cycle of the electronic device 1 and the draw current value of another timing control signal (e.g., the fifth timing control signal CLK5) at the same time point (e.g., t8) through the subtractor 11; then, comparing the third current difference CLK1max-CLK5 with the maximum draw current value CLK1max of the first timing control signal CLK1 through the comparator 12; and when the third current difference CLK1max-CLK5 is not equal to the maximum draw current value CLK1max of the first timing control signal CLK1, executing the overcurrent protection mechanism.

[0126] In other words, when the time point is t8, the first timing control signal CLK1 corresponds to the high potential VGH, and the current draw value of the first timing control signal CLK1 is the maximum current draw value CLK1max. When the time point is t8, the fifth timing control signal CLK5 corresponds to the low potential VGL. Normally, the current draw value of the fifth timing control signal CLK5 should be close to zero (or set to a minimum current value). Therefore, under normal circumstances, the third current difference between the current draw values ​​of the first timing control signal CLK1 and the fifth timing control signal CLK5 at the same time point t8 can be regarded as the maximum current draw value of the first timing control signal CLK1. On the contrary, when the circuit is fully short-circuited, the current draw value of the fifth timing control signal CLK5 at the time point t8 will not be zero or the minimum current value. Therefore, under the condition of full short-circuit, the third current difference will be smaller than the maximum current draw value of the first timing control signal CLK1.

[0127] It is known to those skilled in the art that the third detection mechanism can be used Figure 3 Example or Figure 4 The structure of the embodiment can be realized by simply changing the input of each component, for example, the two input terminals of the subtractor 11 are changed to input the maximum current value of the first timing control signal CLK1 during the second operation period of the electronic device 1 and the current value of the fifth timing control signal CLK5 at the same time point, and the two input terminals of the comparator 12 are changed to input the third current difference and the maximum current value CLK1max of the first timing control signal CLK1, etc. The present invention is not limited thereto.

[0128] In one embodiment, the electronic device 1 may include at least two overcurrent protection circuits 10, one of which executes the first detection mechanism and the other executes the third detection mechanism, but is not limited thereto. In one embodiment, the electronic device 1 may include at least three overcurrent protection circuits 10 to respectively execute the first detection mechanism, the second detection mechanism, and the third detection mechanism. In one embodiment, the first detection mechanism, the second detection mechanism, and the third detection mechanism may be executed by the same overcurrent protection circuit 10, as long as the detection time points of each detection mechanism do not overlap. In one embodiment, each detection mechanism is executed during the interval between the previous and next operation periods of the electronic device 1 (e.g., the interval between two display screens), but is not limited thereto.

[0129] In one embodiment, the present invention can at least compare the presence and connection methods of components in the electronic device 1 as evidence of whether the object falls within the scope of patent protection, but is not limited thereto.

[0130] In the present invention, the electronic device 1 manufactured in the above embodiment can be used in combination with a touch panel to serve as a touch device. Furthermore, if the electronic device manufactured in the above embodiment of the present invention is in the form of a display device or a touch display device, it can be applied to any product known in the art that requires a display screen, such as a display, a mobile phone, a notebook computer, a video camera, a camera, a music player, a mobile navigation device, a television, a car dashboard, a center console, an electronic rearview mirror, a head-up display, and other products that require displaying images.

[0131] Thus, the present invention provides an improved electronic device 10, which can provide an over-current detection mechanism with a low misjudgment probability, or enhance the effect of over-current protection.

[0132] The features of the various embodiments of the present invention may be mixed and matched as desired as long as they do not violate the spirit of the invention or conflict with each other.

[0133] The above embodiments are merely examples for the convenience of explanation. The scope of rights claimed by the present invention should be based on the scope of the claims, but not limited to the above embodiments.

Claims

1. An electronic device, characterized in that: Include: a substrate; and A timing control module transmits a plurality of timing control signals to the substrate and comprises an over-current protection circuit for detecting a draw current value of the at least one timing control signal, wherein the over-current protection circuit comprises a subtractor and a comparator, and the subtractor is electrically connected to the comparator; Among them, the at least one timing control signal includes multiple cycles, the at least one timing control signal includes multiple cycles, wherein the at least one timing control signal has a draw current value at a specific time point in each cycle, and these draw current values ​​have a maximum value and a minimum value. The subtractor calculates a second current difference between the maximum value and the minimum value, and the comparator compares the second current difference with a second threshold value. When the second current difference is greater than or equal to the second threshold value, the overcurrent protection circuit executes an overcurrent protection mechanism.

2. The electronic device according to claim 1, wherein: The second threshold value is between 10 and 200 mA.

3. The electronic device according to claim 2, wherein: The overcurrent protection circuit further includes a first multiplexer, a second multiplexer, a first sampling circuit and a second sampling circuit. The first multiplexer receives the at least one timing control signal and outputs the at least one timing control signal to the first sampling circuit. The first sampling circuit samples the at least one timing control signal to obtain the maximum value of the draw current values ​​at the specific time points and transmits the maximum value to the subtractor. The second multiplexer receives the at least one timing control signal and outputs the at least one timing control signal to the second sampling circuit. The second sampling circuit samples the at least one timing control signal to obtain the minimum value of the draw current values ​​at the specific time points and transmits the minimum value to the subtractor.

4. The electronic device according to claim 3, wherein: The first sampling circuit includes a first sampler, a second comparator and a first register. The second comparator includes two input terminals and an output terminal. The first sampler is connected to one of the input terminals of the second comparator. The first register is connected to the other input terminal and the output terminal of the second comparator. The first sampler samples the draw current value at the specific time point of each cycle of the at least one timing control signal and transmits the draw current value obtained by each sampling to the second comparator. The first register transmits a first temporary value to the second comparator. The second comparator compares the draw current value with the first temporary value. When the draw current value is greater than the first temporary value, the output terminal outputs the draw current value to the first register. The first register replaces the current value of the first temporary value with the draw current value.

5. The electronic device according to claim 3, wherein: The second sampling circuit includes a second sampler, a third comparator and a second register. The third comparator includes two input terminals and an output terminal. The second sampler is connected to one of the input terminals of the third comparator. The second register is connected to the other input terminal and the output terminal of the third comparator. The second sampler samples the draw current value at the specific time point in each cycle of the at least one timing control signal and transmits the draw current value obtained by each sampling to the third comparator. The second register transmits a second temporary value to the third comparator. The third comparator compares the draw current value with the second temporary value. When the draw current value is less than the second temporary value, the output terminal outputs the draw current value to the second register. The second register replaces the current value of the second temporary value with the draw current value.

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