Electromagnetic interference suppression circuit, source driver, display panel and electronic device

Abstract

Embodiments of the present application disclose an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device. The electromagnetic interference suppression circuit includes a clock recovery circuit, a demultiplexing module, a logic circuit, and a latch. The clock recovery circuit is configured to receive an external serial data and extract a clock recovery signal. The demultiplexing module is configured to convert the serial data into parallel data according to the clock recovery signal. The logic circuit is configured to receive the parallel data and a control signal, and perform logic processing on the control signal. The latch is configured to receive and latch the logically processed control signal and the parallel data. The solution of the present application can optimize signals through the collaborative processing of the demultiplexing module and the logic circuit, thereby effectively reducing electromagnetic interference.

Description

Technical Field

[0001] The present application relates to the technical field of display circuits, and particularly to an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device. Background Art

[0002] In traditional display panel driving, generally, a source driver receives a timing control signal sent from a timing control circuit (Timing Controller, T-CON) and outputs a voltage to the TFT panel. However, each integrated circuit in a TV module can cause an electromagnetic interference (EMI) effect. To reduce the EMI effect caused by the source driver, in the prior art, generally, a spread spectrum clock (SSC) signal is generated by the timing control circuit and sent to the source driver. By adjusting the modulation rate (MR) and modulation frequency (MF) of the spread spectrum clock, the best EMI reduction effect can be achieved.

[0003] However, this method has significant drawbacks. As the modulation rate and modulation frequency of the spread spectrum clock increase, the design of the timing control circuit requires a larger area and higher power consumption to implement. Similarly, when the MR or MF of the SSC signal received by the source driver increases, its circuit design is also required to have higher efficiency to ensure correct decoding of display data, which will also increase the area and power consumption of the circuit. With the improvement of TV resolution and refresh rate, the data transmission rate also increases. This poses a huge challenge to the circuit design of the timing control circuit and the source driver in terms of power consumption and area. Since power consumption is proportional to the EMI effect, in response to higher data transmission rates and SSCs, the circuit power consumption will increase significantly, thereby exacerbating the EMI effect. Summary of the Invention

[0004] Embodiments of the present application provide an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device. Through the collaborative processing of a demultiplexing module and a logic circuit, signal optimization can be achieved, thereby effectively reducing electromagnetic interference.

[0005] Embodiments of the present application provide an electromagnetic interference suppression circuit, including a clock recovery circuit, a demultiplexing module, a logic circuit, and a latch;

[0006] The clock recovery circuit is configured to receive external serial data and extract a clock recovery signal;

[0007] The demultiplexing module is configured to convert serial data into parallel data according to the clock recovery signal;

[0008] The logic circuit is configured to receive the parallel data and a control signal, and perform logic processing on the parallel data and the control signal;

[0009] The latch is used to receive and latch the data after logical processing.

[0010] In one embodiment, the electromagnetic interference suppression circuit further includes a timing control circuit;

[0011] The timing control circuit is used to generate a timing control signal and send it to the clock recovery circuit;

[0012] The clock recovery circuit is specifically used to generate a clock recovery signal synchronized with the frequency and phase of the timing control signal.

[0013] In one embodiment, the clock recovery circuit is further used to send the clock recovery signal to the logic circuit;

[0014] The demultiplexing module is further used to receive the clock offset signal returned by the logic circuit and convert the serial data into parallel data according to the clock offset signal.

[0015] In one embodiment, the clock recovery circuit includes a first clock recovery circuit and a second clock recovery circuit;

[0016] The first clock recovery circuit is used to send a first clock recovery signal to the logic circuit;

[0017] The second clock recovery circuit is used to send a second clock recovery signal to the logic circuit.

[0018] In one embodiment, the demultiplexing module includes a first demultiplexing module, a second demultiplexing module, and a multiplexer;

[0019] The first demultiplexing module is used to receive the first clock offset signal returned by the logic circuit;

[0020] The second demultiplexing module is used to receive the second clock offset signal returned by the logic circuit;

[0021] The multiplexer is used to convert the serial data into parallel data according to the first clock offset signal or the second clock offset signal.

[0022] In one embodiment, the latch includes a first latch, a second latch, a third latch, and a fourth latch;

[0023] The first latch and the second latch are used to receive and latch the control signal and the parallel data after logical processing;

[0024] The third latch and the fourth latch are used to receive other control signals and latch them together with the control signal and the parallel data.

[0025] In one embodiment, the electromagnetic interference suppression circuit further includes a first bidirectional shift register and a second bidirectional shift register;

[0026] The first bidirectional shift register and the second bidirectional shift register are configured to perform bidirectional shift processing on the received control signal and send the control signal after the bidirectional shift processing to the first latch and the second latch.

[0027] An embodiment of the present application further provides a source driver, which includes the electromagnetic interference suppression circuit provided in any one of the embodiments of the present application.

[0028] An embodiment of the present application further provides a display panel, which includes the source driver provided in the embodiment of the present application.

[0029] An embodiment of the present application further provides an electronic device, which includes the display panel provided in the embodiment of the present application.

[0030] The electromagnetic interference suppression circuit provided in the embodiment of the present application includes a clock recovery circuit, a demultiplexing module, a logic circuit, and a latch. The clock recovery circuit is configured to receive external serial data and extract a clock recovery signal. The demultiplexing module is configured to convert the serial data into parallel data according to the clock recovery signal. The logic circuit is configured to receive the parallel data and a control signal and perform logic processing on the control signal. The latch is configured to receive and latch the control signal and the parallel data after the logic processing. Through the collaborative processing of the demultiplexing module and the logic circuit, the solution of the present application can optimize the signal, thereby effectively reducing electromagnetic interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 is the first structural schematic diagram of the electromagnetic interference suppression circuit provided in the embodiment of the present application;

[0033] Figure 2 is the second structural schematic diagram of the electromagnetic interference suppression circuit provided in the embodiment of the present application;

[0034] Figure 3 is the signal flow schematic diagram of the electromagnetic interference suppression circuit provided in the embodiment of the present application;

[0035] Figure 4 is the structural schematic diagram of the logic circuit in the electromagnetic interference suppression circuit provided in the embodiment of the present application. Detailed implementation manners

[0036] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0037] It should be noted that in this document, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0038] It should be understood that although the steps in the flowcharts in the embodiments of the present application are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless expressly stated herein, there is no strict order limitation for the execution of these steps, and they may be executed in other orders. Moreover, at least some of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and their execution order is not necessarily sequential, but may be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0039] Referring to "embodiments" in this document means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0040] The embodiments of the present application provide an electromagnetic interference suppression circuit, such as Figure 1As shown, the electromagnetic interference suppression circuit includes a clock recovery circuit 101, a demultiplexing module 102, a logic circuit 103, and a latch 104 connected in sequence.

[0041] In one embodiment, the clock recovery circuit 101 (CDR) is used to receive external serial data and extract a clock recovery signal. It utilizes a phase-locked loop (PLL) or other technologies to recover the clock by detecting the external serial data and performing conversion. Then, the clock recovery circuit 101 outputs the clock recovery signal to the demultiplexing module 102 (Demux). Among them, the external serial data is modulated or encoded during transmission to meet requirements such as the transmission medium. For example, in a high-speed data transmission scenario, it can be a serial bit stream encoded at a certain rate and format.

[0042] It should be noted that a phase-locked loop (PLL) is a feedback control system mainly used to generate an output signal synchronized with the frequency and phase of the input signal. In the clock recovery circuit, the main purpose of the PLL is to extract an accurate clock signal from the input data signal. The PLL mainly consists of three parts: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). Among them, the role of the phase detector is to compare the phase difference between the input signal and the VCO output signal. When there is a phase difference between the input signal and the VCO output signal, the phase detector generates an error signal proportional to the phase difference. The loop filter is used to filter the error signal output by the phase detector. Its main role is to remove the high-frequency components in the error signal to make the signal smoother. The voltage-controlled oscillator adjusts its output frequency according to the voltage signal output by the loop filter. If the voltage signal output by the loop filter increases, the output frequency of the VCO will increase; conversely, the output frequency of the VCO will decrease. In the clock recovery circuit, the input data signal contains clock information. The PLL continuously adjusts the output frequency and phase of the VCO to synchronize it with the clock information in the input data signal.

[0043] The demultiplexing module 102 is located after the clock recovery circuit. It receives the clock recovery signal extracted from the clock recovery circuit 101 and the external incoming serial data, and converts the serial data into parallel data according to the clock recovery signal. At the same time, it is connected to the logic circuit 103 (Logic Circuit) and outputs the processed data to the logic circuit for further processing.

[0044] The logic circuit 103, located at the central core position of the entire circuit, receives the parallel data converted by the demultiplexing module and also receives other control signals. The logic circuit 103 includes various logic gates, such as AND gates, OR gates, NOT gates, XOR gates, as well as a data processing unit. It receives the parallel data and control signals, performs data processing operations such as encoding, decoding, and filtering on the parallel data, and simultaneously performs corresponding logical operations through the logic gates according to the control signals. During the signal transmission and processing, electromagnetic interference caused by signal processing is reduced by optimizing logical operations and data processing.

[0045] The latches 104 are distributed after the logic circuit. They receive the outputs from the logic circuit, including the logically processed control signals and parallel data. The key function of the latches 104 is that under specific triggering conditions (such as the rising edge or falling edge of a clock signal, or the active level triggering of certain specific control signals), they can latch the input logically processed control signals and parallel data, that is, maintain the current state of these signals and data unchanged until the next triggering condition arrives. For example, after receiving the relevant data and control signals from the logic circuit, the latches 104 will save this information at an appropriate triggering moment, preventing the data from changing due to unstable factors in the circuit (such as noise interference, timing fluctuations, etc.) during the transmission process, thereby providing a stable and reliable data source for the subsequent circuit, ensuring the stable and accurate operation of the entire circuit system, and also helping to suppress the impact of electromagnetic interference on the data.

[0046] Please continue to refer to Figure 2 , the electromagnetic interference suppression circuit may further include a timing control circuit 105. The timing control circuit 105 is used to generate timing control signals and send them to the clock recovery circuit. The clock recovery circuit is used to generate a clock recovery signal synchronized with the frequency and phase of the timing control signal.

[0047] In this embodiment, the clock recovery circuit is further used to send a clock recovery signal to the logic circuit 103. The demultiplexing module is further used to receive the clock offset signal returned by the logic circuit 103 and convert the serial data into parallel data according to the clock offset signal.

[0048] Further, the clock recovery circuit may include a first clock recovery circuit 1011 and a second clock recovery circuit 1012. The first clock recovery circuit 1011 may be configured to send a first clock recovery signal to the logic circuit 103, and the second clock recovery circuit 1012 may be configured to send a second clock recovery signal to the logic circuit 103. Correspondingly, the demultiplexing module may specifically include a first demultiplexing module 1021, a second demultiplexing module 1022, and a multiplexer. The first demultiplexing module 1021 may be configured to receive a first clock offset signal returned by the logic circuit 103, the second demultiplexing module 1022 may be configured to receive a second clock offset signal returned by the logic circuit 103, and the multiplexer may be configured to convert serial data into parallel data according to the first clock offset signal or the second clock offset signal.

[0049] In one embodiment, the above latch may include a first latch 1041, a second latch 1042, a third latch 1043, and a fourth latch 1044;

[0050] The first latch 1041 and the second latch 1042 may be configured to receive and latch the logically processed control signal and parallel data. The third latch 1043 and the fourth latch 1044 may be configured to receive other control signals and latch them together with the control signal and parallel data.

[0051] In this embodiment, the electromagnetic interference suppression circuit may further include a first bidirectional shift register 1061 and a second bidirectional shift register 1062. The first bidirectional shift register 1061 and the second bidirectional shift register 1062 may be configured to perform bidirectional shift processing on the received control signal and send the control signal after bidirectional shift processing to the first latch 1041 and the second latch 1042.

[0052] The following combines Figure 3 to illustrate the signal flow of the electromagnetic interference suppression circuit. The first clock recovery circuit and the second clock recovery circuit may extract clock recovery signals from the input serial data using internal mechanisms. For example, in Figure 3In it, the first clock recovery circuit and the second clock recovery circuit respectively extract clock recovery signals such as CDR_3UI_CLK0 and CDR_3UI_CLK1 based on the corresponding input data. These signals accurately reflect the clock characteristics of the input serial data and provide a basis for the subsequent circuit to process the data at the correct rhythm. In this embodiment, by sending the above clock recovery signals to the logic circuit, the demultiplexing module can receive the clock offset signals returned by the logic circuit (such as Demux_resetn_p0 and Demux_resetn_p1), and after processing by the clock offset signals, the electromagnetic interference impact caused by signal processing can be reduced.

[0053] Continue to refer to Figure 3 , the core function of the demultiplexing module is to decompose the input serial data according to its rhythm law under the drive of the clock recovery signal. Taking the first demultiplexing module as an example, under the control of the CDR_CLK0 clock signal, it divides the serial data input from the first input port according to a certain bit width (for example, CDR_DATA0[17:0] output in the figure, which means that the serial data is sequentially decomposed into a 18-bit parallel data form). Similarly, the second demultiplexing module will also perform a similar operation on the serial data input from the second input port under the control of CDR_CLK1, and convert it into parallel data such as CDR_DATA1[17:0], so as to realize the conversion of the data format, facilitate the subsequent circuit to perform parallel processing, and improve the data processing efficiency. It should be noted that Figure 3 The CDR_DATA0[17:0] and CDR_DATA1[17:0] signals in are only for illustrative purposes. In the actual processing process, the first demultiplexing module and the second demultiplexing module will transfer the clock signal and multiple DATA signals synchronously.

[0054] In one embodiment, the logic circuit receives the parallel data (such as CDR_DATA0[17:0], CDR_DATA1[17:0]) converted from the demultiplexing module, and also receives other control signals (such as Figure 3 BISR_STA, BISR_CLKA, BISR_CLKB, etc. in .

[0055] It should be noted that the logic circuit internally contains various logic gates (AND gates, OR gates, NOT gates, etc.) and logic units, and can perform diverse logical operations and processing on the input parallel data and control signals. For example, according to the states (high level or low level) of different control signals, operations such as selection, combination, and operation on the parallel data are carried out. For instance, it may be determined whether to invert certain data bits in CDR_DATA0[17:0] according to the state of the BISR_STA signal; or logical processing such as merging or splitting two groups of parallel data is performed based on the cooperation of BISR_CLKA and BISR_CLKB, with the aim of enabling the data to flow to the next step according to the expected functions and timing requirements of the circuit.

[0056] Latches (such as the first latch, the second latch, the third latch, and the fourth latch, etc.) are distributed after the logic circuit. They receive the outputs from the logic circuit, including the control signals and parallel data after logical processing (such as relevant data signals like DB0[7:0], DB2[7:0], DB4[7:0], DB6[7:0] and the corresponding control signals). The outputs of the latches will further be connected to subsequent possible circuit modules or serve as the final output ports to provide stable data and signals outward.

[0057] In this embodiment, since the reset operation of the demultiplexer will change the output timing of the data. Under normal circumstances, the data output of pair0 / 1 has a certain pattern, and through the reset operation of the demultiplexer, the data output of pair0 / 1 can be offset (skew change). This offset will change the transmission characteristics of the signal, thereby reducing the generated electromagnetic interference (EMI).

[0058] Furthermore, the first latch and the second latch are mainly used for temporary storage and retention of data. They receive signals from the logic circuit (Logic Circuit), such as data signals like DB0[7:0], DB2[7:0], DB4[7:0], DB6[7:0] and relevant control signals. Triggered by specific clocks or control signals, these input data are latched to ensure the stability and accuracy of the data during transmission, prevent data loss or errors, and at the same time provide stable data input for subsequent circuits (such as the third latch and the fourth latch), playing the role of data buffering and isolation.

[0059] The third latch and the fourth latch are also used for data storage and retention. They receive the output signals from the first latch and the second latch and possible other control signals (such as Figure 3Among them are Latch2_pulse_A and Latch2_pulse_B). Under the action of corresponding control signals, the data is further stabilized and temporarily stored, providing a reliable data source for subsequent circuit operations or outputs. These latches work together in the circuit. By temporarily storing and holding the data, they ensure that the data can be accurately and stably transmitted and processed in a complex circuit environment, and are an important part of the circuit for realizing data storage and timing control.

[0060] In addition, Figure 3 The bidirectional shift register in it can not only temporarily store the data transmitted from the logic circuit (such as DB0[7:0], DB2[7:0], DB4[7:0], DB6[7:0], etc.), but also perform bidirectional shift operations on the data according to control signals (such as BISR_STA, BISR_CLKA, BISR_CLKB, etc.). This means that the data can be shifted either to the left or to the right. This flexibility makes the transmission and processing of data in the circuit more diverse and efficient. For example, the data can be shifted bit by bit to the left for a certain operation or data format conversion, while in other cases, it may be necessary to shift to the right. At the same time, since different circuit modules may have different requirements for the data format and transmission method, the bidirectional shift register can re-arrange and format the data through shift operations to make it adapt to the interface requirements of the subsequent circuit. For example, convert parallel data to serial data, or convert serial data to parallel data for effective communication and data exchange with other devices or circuits.

[0061] For example, in this embodiment, after the first demultiplexing module and the second demultiplexing module send the signals CDR_CLK0 and CDR_CLK1 to the logic circuit, the logic circuit can generate corresponding control signals and parallel data according to CDR_CLK0, specifically including BISR_STA, BISR_CLKA, DB0[7:0], DB2[7:0], DB4[7:0], DB6[7:0] and Latch2_pulse_A. Correspondingly, the logic circuit can generate corresponding control signals and parallel data according to CDR_CLK1, specifically including BISR_STB, BISR_CLKB, DB1[7:0], DB3[7:0], DB5[7:0], DB7[7:0] and Latch2_pulse_B. Therefore, based on the above CDR_CLK0 and CDR_CLK1 signals, a misalignment signal will be generated to effectively reduce the electromagnetic interference between the signals.

[0062] Furthermore, through the electromagnetic interference suppression circuit provided in this embodiment, different timing control signals are first generated by the Scan line and sent to the demultiplexing module, so that there is a time displacement effect on the CDR_CLK0, CDR_DATA0[17:0], CDR_CLK1, and CDR_DATA1[17:0] output by the demultiplexing module. These signals are sent to the logic circuit for processing. The signals BISR_STA, BISR_CLKA, DB0[7:0], DB2[7:0], DB4[7:0], DB6[7:0], Latch2_pulse_A generated by the signals CDR_CLK0 and CDR_CLK1, and the signals BISR_STB, BISR_CLKB, DB1[7:0], DB3[7:0], DB5[7:0], DB7[7:0], Latch2_pulse_B also have a time displacement effect, thereby reducing the electromagnetic interference impact during the entire signal transmission process from the first / second demultiplexing module to the logic circuit to the first / second latch to the third / fourth latch.

[0063] Therefore, the above electromagnetic interference suppression circuit can send the CDR_3UI_CLK0, CDR_3UI_CLK1 generated by the first / second clock recovery circuit and the timing control signals generated by the display scan line to the first / second demultiplexing module, so that the CDR_CLK0, CDR_CLK0, CDR_DATA0[17:0], and CDR_DATA1[17:0] output by the above first / second demultiplexing module can generate different offset effects according to the display scan line. In addition, the electromagnetic interference suppression circuit can also send the above CDR_CLK0, CDR_CLK0, CDR_DATA0[17:0], and CDR_DATA1[17:0] to the logic circuit, so that the clock signals and parallel data output to the first / second latch or the third / fourth latch also have an offset effect, thereby reducing electromagnetic interference.

[0064] In one embodiment, please further refer to Figure 4, the logic circuit may specifically include a first timing control circuit 1031, a first processing circuit 1032, a second processing circuit 1033, and a second timing control circuit 1034. Among them, the above-mentioned first timing control circuit 1031 and second timing control circuit 1034 can be used to receive the clock recovery signals output by the first / second clock recovery circuits, and then perform timing control on them to generate specific clock offset signals and return them to the first / second demultiplexing modules. The first processing circuit 1032 and the second processing circuit 1033 are mainly used to receive the parallel data converted by the first / second demultiplexing modules, and at the same time, they can also transmit the scan line counter data to the first timing control circuit 1031 and the second timing control circuit 1034. The first processing circuit 1032 and the second processing circuit 1033 use internal logic gates and data processing units to perform data processing such as encoding, decoding, and filtering on the parallel data, and at the same time perform corresponding logical operations according to the control signals to make the data meet the requirements of the subsequent circuits. The processed results will be transmitted to the first / second / third / fourth latches.

[0065] As described above, the electromagnetic interference suppression circuit proposed in the embodiment of the present application includes a clock recovery circuit, a demultiplexing module, a logic circuit, and a latch. The clock recovery circuit is used to receive external serial data and extract clock recovery signals. The demultiplexing module is used to convert the serial data into parallel data according to the clock recovery signals. The logic circuit is used to receive the parallel data and control signals, and perform logical processing on the control signals. The latch is used to receive and latch the control signals and parallel data after logical processing. Through the collaborative processing of the demultiplexing module and the logic circuit, the solution of the present application can optimize the signal, thereby effectively reducing electromagnetic interference.

[0066] In addition, the embodiment of the present application also provides a source driver, and the source driver includes the electromagnetic interference suppression circuit provided by the embodiment of the present application.

[0067] The embodiment of the present application also provides a display panel, and the display panel includes the source driver provided by the embodiment of the present application.

[0068] The embodiment of the present application also provides an electronic device, and the electronic device includes the display panel provided by the embodiment of the present application.

[0069] The division of each unit in the above electromagnetic interference suppression circuit is only for illustrative purposes. In other embodiments, the above electromagnetic interference suppression circuit may be divided into different units as needed to complete all or part of the functions of the above electromagnetic interference suppression circuit. That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, such as the mutual combination of technical features between embodiments, or directly or indirectly applied in other related technical fields, is similarly included in the patent protection scope of the present application.

[0070] Although the present application has been shown and described with respect to one or more implementations, those skilled in the art will envision equivalent variations and modifications based on a reading and understanding of this specification and the drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the described component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of this specification shown herein.

[0071] In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0072] In the present application, the term "exemplary" is used to mean "serving as an example, illustration, or explanation". Any embodiment described as "exemplary" in the present application is not necessarily to be construed as more preferred or more advantageous than other embodiments. The above description is given in order to enable any person skilled in the art to implement and use the present application. In the above description, various details are set forth for purposes of explanation. It should be understood that those of ordinary skill in the art may recognize that the present application may be implemented without these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail so as not to obscure the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope that conforms to the principles and features disclosed in the present application.

Claims

1. An electromagnetic interference suppression circuit, characterized in that: It includes a clock recovery circuit, a demultiplexing module, a logic circuit, and a latch; The clock recovery circuit is used to receive external serial data and extract a clock recovery signal, and send the clock recovery signal to the logic circuit. The clock recovery circuit includes a first clock recovery circuit and a second clock recovery circuit. The first clock recovery circuit is used to send a first clock recovery signal to the logic circuit, and the second clock recovery circuit is used to send a second clock recovery signal to the logic circuit. The demultiplexing module is used to receive the clock offset signal returned by the logic circuit, and convert the serial data into parallel data according to the clock offset signal. The demultiplexing module includes a first demultiplexing module, a second demultiplexing module and a multiplexer. The first demultiplexing module is used to receive the first clock offset signal returned by the logic circuit, the second demultiplexing module is used to receive the second clock offset signal returned by the logic circuit, and the multiplexer is used to convert the serial data into parallel data according to the first clock offset signal or the second clock offset signal. The logic circuit includes a plurality of logic gates and a data processing unit, and is used to receive the parallel data and the control signal, process the parallel data through the data processing unit, and perform corresponding logic operations through the logic gates according to the control signal; The latch is used to receive and latch the data after the logic processing.

2. The electromagnetic interference suppression circuit as claimed in claim 1, characterized in that: The electromagnetic interference suppression circuit also includes a timing control circuit; The timing control circuit is used to generate a timing control signal and send it to the clock recovery circuit; The clock recovery circuit is specifically used to generate a clock recovery signal that is synchronized with the frequency and phase of the timing control signal.

3. The electromagnetic interference suppression circuit according to claim 1, characterized in that: The latch comprises a first latch, a second latch, a third latch and a fourth latch; The first latch and the second latch are used to receive and latch the control signal after the logic processing and the parallel data; The third latch and the fourth latch are used to receive other control signals and latch the control signals together with the parallel data.

4. The electromagnetic interference suppression circuit according to claim 3, characterized in that: The electromagnetic interference suppression circuit also includes a first bidirectional shift register and a second bidirectional shift register; The first bidirectional shift register and the second bidirectional shift register are used to perform bidirectional shift processing on the received control signal, and send the control signal after the bidirectional shift processing to the first latch and the second latch.

5. A source driver, characterized in that: The source driver includes the electromagnetic interference suppression circuit according to any one of claims 1 to 4.

6. A display panel, characterized in that: The display panel includes the source driver according to claim 5.

7. An electronic device, characterized in that: The electronic device comprises the display panel according to claim 6.

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