A method for reading and writing test of a memory device, an electronic device and a storage medium

Abstract

The present application discloses a read-write test method, an electronic device and a storage medium for a memory, including: establishing a communication connection with the memory to be tested; obtaining a plurality of test subsequences; setting corresponding write addresses for each test subsequence according to a preset address interval; writing the corresponding test subsequences into the memory buffer according to a preset write order, writing the test subsequences in the memory buffer into the memory to be tested according to the write addresses corresponding to the test sequences, and performing a cleaning operation on the memory buffer to clear the data in the memory buffer until all the test subsequences are written into the memory to be tested; again, sequentially obtaining a plurality of read subsequences from the memory to be tested through the memory buffer and according to the write addresses in the write order; comparing the read subsequences with the test subsequences to generate a test result. The present application can efficiently perform read-write tests on the memory while ensuring test accuracy.

Description

Technical Field

[0001] This application relates to the technical field of memory testing, and particularly to a read-write test method for a memory device, an electronic device, and a storage medium. Background Art

[0002] In the process of research and development, production, and maintenance of contemporary computer systems and electronic devices, accurate testing of memory read-write performance is crucial. As a key component for data storage and interaction, the read-write performance of memory directly affects the operating efficiency, response speed, and stability of the entire system.

[0003] Currently, when conducting read-write tests on memory, the mainstream approach mainly involves using a main control board with a memory buffer (Cache) to operate on the memory device to be tested. Generally, there are two completely different test methods:

[0004] First, open the memory buffer of the CPU for read-write testing. In this mode, when the CPU executes read-write instructions, it first queries the memory buffer (Cache). If the required data has been cached therein (i.e., cache hit), the data can be directly and quickly obtained from the memory buffer or written into the memory buffer, greatly improving the read-write speed. However, this method has significant drawbacks. Due to the intervention of the memory buffer, the test process often overly depends on the performance of the memory buffer, making the obtained test results difficult to accurately reflect the true read-write characteristics of the memory device to be tested. A large number of read-write operations are actually completed inside the memory buffer, and only a small number of cases where the memory buffer is not hit will truly trigger access to the memory device to be tested. This leads to the inability of testers to accurately know the actual read-write capabilities of the memory device to be tested without the assistance of the memory buffer, thus lacking a reliable basis when evaluating memory quality, screening and adapting memory products, and troubleshooting memory underlying faults.

[0005] Second, close the memory buffer of the CPU to perform read-write testing. At this time, a direct read-write channel is established between the CPU and the memory device to be tested, and each read-write operation actually acts on the memory device to be tested, ensuring that the test results can truly present the performance state of the memory device itself. However, the drawbacks of this method are also obvious. Due to the lack of the caching effect of the memory buffer, the CPU must wait for the memory device to be tested to complete the data reading, writing, and corresponding processing processes, resulting in an extremely slow test process. This not only greatly extends the test cycle, increases the R & D cost and time cost, and the problem of low efficiency is particularly prominent, but also for some system tests with high real-time requirements, the overly slow test speed may lead to the inability to accurately capture the dynamic performance changes of the memory under high-speed operation of the system. Summary of the Invention

[0006] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a read-write test method for a memory device, an electronic device, and a storage medium, which can efficiently perform read-write tests on the memory device while ensuring test accuracy.

[0007] In a first aspect, this application provides a read-write test method for a memory device, which is applied to a test master chip. The test master chip includes a memory buffer, and the method includes:

[0008] Establish a communication connection with the memory device to be tested;

[0009] Obtain a plurality of test subsequences; wherein the length of the test subsequence is less than or equal to the length of the memory buffer;

[0010] Set a corresponding write address for each of the test subsequences at a preset address interval;

[0011] Write the corresponding test subsequence into the memory buffer in a preset write order, write the test subsequence in the memory buffer into the memory device to be tested according to the write address corresponding to the test sequence, and perform a cleaning operation on the memory buffer until all the test subsequences are written into the memory device to be tested; wherein the cleaning operation is used to clear the data in the memory buffer;

[0012] Again, in the write order, sequentially obtain a plurality of read subsequences from the memory device to be tested through the memory buffer and according to the write address;

[0013] Compare the read subsequence with the corresponding test subsequence to generate a test result.

[0014] The read and write test method for a memory according to an embodiment of the first aspect of the present application has at least the following beneficial effects: First, relying on a test master chip with a memory buffer, a stable communication connection is established with the memory to be tested. Then, a number of test subsequences are obtained. Specifically, it is specified that the length of the test subsequence is less than or equal to the length of the memory buffer, so as to avoid the situation of data loss during writing caused by overflow due to excessive data volume. According to a preset address interval, a corresponding write address is set for each test subsequence. Subsequently, according to the preset write order, the test subsequences are first written into the memory buffer. The memory buffer plays a role in accelerating data transmission, and using its relatively high-speed read and write characteristics, it speeds up the transfer of data from the master chip to the memory buffer. Immediately afterwards, according to the set write address, the test subsequences in the memory buffer are written into the memory to be tested. After each write, a cleaning operation is immediately performed on the memory buffer, that is, the data in the memory buffer is completely cleared. Repeat this process until all the test subsequences are accurately written into the memory to be tested. Again, in accordance with the previous write order, a number of read subsequences are respectively obtained from the memory to be tested through the memory buffer and the corresponding write addresses. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which prompts the read operation to directly face the memory to be tested, forcing the read and write operations to interact more directly with the memory to be tested, making the write test process no longer rely solely on the memory buffer, but truly involve the write operations on different address areas of the memory to be tested, so as to accurately test the write performance of the memory to be tested. During the read test, due to the previous cleaning operation, the test master chip can only read data from the memory to be tested, which also ensures the authenticity of the read performance test. The present application improves the efficiency of the write test by using the memory buffer on the premise of ensuring test accuracy.

[0015] According to some embodiments of the first aspect of the present application, the obtaining a number of test subsequences includes:

[0016] Obtain a test sequence;

[0017] Perform a cutting process on the test sequence according to the length of the memory buffer to obtain a number of the test subsequences;

[0018] Generate the write order for each of the test subsequences according to the arrangement order of the test sequence.

[0019] According to some embodiments of the first aspect of the present application, the comparing the read subsequences with the corresponding test subsequences to generate a test result includes:

[0020] Combine a number of the read subsequences according to the write order to obtain a read sequence;

[0021] The read sequence is compared with the test sequence to generate a test result.

[0022] According to some embodiments of the first aspect of the present application, before the step of comparing the read subsequence with the corresponding test subsequence to generate a test result, the step further includes:

[0023] Adjusting the address interval multiple times, and updating the write address corresponding to each test subsequence according to the adjusted address interval;

[0024] Erasing the data in the memory to be tested;

[0025] writing the test subsequences into the memory device under test in sequence through the memory buffer again according to the write order and based on the new write address, and performing a flushing operation on the memory buffer after each test subsequence is written into the memory device under test;

[0026] Again, according to the write order, sequentially through the memory buffer and according to the new write address, sequentially acquiring a plurality of the read subsequences from the memory to be tested;

[0027] The comparing the read subsequence with the corresponding test subsequence to generate a test result includes:

[0028] The read subsequences obtained according to different address intervals are compared with the corresponding test subsequences to generate a test result.

[0029] According to some embodiments of the first aspect of the present application, the adjusting the address interval multiple times includes:

[0030] Obtain the storage capacity of the memory to be tested;

[0031] Determining the number of adjustments and the increment interval according to the storage capacity;

[0032] The address interval is adjusted multiple times according to the number of adjustments, and the address interval is increased each time according to the incremental interval.

[0033] According to some embodiments of the first aspect of the present application, comparing the read subsequence with the corresponding test subsequence to generate a test result includes:

[0034] When the read subsequence does not match the corresponding test subsequence, determining a corresponding abnormal address according to the test subsequence;

[0035] Obtaining an abnormal address range according to the abnormal address and the length of the corresponding test subsequence;

[0036] Generate a test result according to the abnormal address range.

[0037] According to some embodiments of the first aspect of the present application, the generating a test result according to the abnormal address range includes:

[0038] Obtain the storage capacity of the memory to be tested;

[0039] Obtain an abnormal capacity according to the total length of all the abnormal address ranges;

[0040] Calculate an abnormal ratio according to the abnormal capacity and the storage capacity;

[0041] Generate the test result according to the abnormal address range and the abnormal ratio.

[0042] According to some embodiments of the first aspect of the present application, it further includes:

[0043] Obtain the writing time for all test subsequences to be written into the memory to be tested through the memory buffer, and the reading time for reading all the reading subsequences through the memory buffer;

[0044] Obtain a writing speed according to the writing time and the total length of the test subsequences;

[0045] Obtain a reading speed according to the reading time and the total length of the reading subsequences;

[0046] Generate a processing speed evaluation result according to the writing speed and a preset writing threshold, and the reading speed and a preset reading threshold.

[0047] In a second aspect, the present application further provides an electronic device, including:

[0048] At least one memory; [[ID=3|7]]

[0049] At least one processor;

[0050] At least one program;

[0051] The program is stored in the memory, and the processor executes at least one of the programs to implement the read-write test method for the memory according to any embodiment of the second aspect.

[0052] In a third aspect, the present application further provides a computer-readable storage medium, and the computer-readable storage medium stores computer-executable signals for executing the read-write test method for the memory according to any one of the first aspect.

[0053] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0054] Additional aspects and advantages of the present application will become apparent and be readily understood in conjunction with the description of the embodiments in the following drawings, in which:

[0055] Figure 1 Flowchart of the read / write test method for the memory provided for the first embodiment of the present application;

[0056] Figure 2 For the present application Figure 1 Flowchart regarding step S110;

[0057] Figure 3 For the present application Figure 1 Flowchart of the first embodiment regarding step S160;

[0058] Figure 4 For the present application Figure 1 Flowchart before step S160;

[0059] Figure 5 For the present application Figure 4 Flowchart regarding step S410;

[0060] Figure 6 For the present application Figure 1 Flowchart of the second embodiment regarding step S160;

[0061] Figure 7 For the present application Figure 6 Flowchart regarding step S630;

[0062] Figure 8 Flowchart of the read / write test method for the memory provided for the second embodiment of the present application. Detailed Description of the Embodiments

[0063] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0064] In the description of the present application, it should be understood that with respect to the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc., it is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0065] In the description of the present application, if the first and second are described for the purpose of distinguishing technical features, it should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0066] In the description of the present application, unless otherwise clearly defined, terms such as setting, installation, connection, etc. should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0067] In the process of research, development, production and maintenance of contemporary computer systems and electronic devices, accurate testing of memory read and write performance is crucial. As a key component for data storage and interaction, the read and write performance of memory directly affects the operating efficiency, response speed and stability of the entire system.

[0068] Currently, when performing read and write tests on memory, the mainstream methods mainly involve operating the memory device to be tested using a main control board with a memory buffer (Cache). Generally, there are two completely different testing methods:

[0069] First, open the memory buffer of the CPU for read and write testing. In this mode, when the CPU executes read and write instructions, it will first query the memory buffer (Cache). If the required data has been cached therein (i.e., cache hit), the data can be directly and quickly obtained from the memory buffer or the data can be written into the memory buffer, greatly improving the read and write speed. However, this method has significant drawbacks. Due to the intervention of the memory buffer, the testing process often overly relies on the performance of the memory buffer, making the obtained test results difficult to accurately reflect the true read and write characteristics of the memory device to be tested. A large number of read and write operations are actually completed inside the memory buffer, and only a small number of cases where the memory buffer is not hit will actually trigger access to the memory device to be tested. This results in the tester being unable to accurately know the actual read and write capabilities of the memory device to be tested without the assistance of the memory buffer, thus lacking a reliable basis when evaluating memory quality, screening and adapting memory products, and troubleshooting memory underlying faults.

[0070] Second, close the memory buffer of the CPU to perform read and write tests. At this time, a direct read and write channel is established between the CPU and the memory device to be tested. Each read and write operation actually acts on the memory device to be tested, ensuring that the test results can truly present the performance state of the memory device itself. However, the drawbacks of this method are also obvious. Due to the lack of the caching function of the memory buffer, the CPU must wait for the memory device to be tested to complete the data reading, writing, and corresponding processing processes, resulting in an extremely slow entire test process. This not only greatly extends the test cycle, increases the R & D cost and time cost, and the problem of low efficiency is particularly prominent, but also for some system tests with high real-time requirements, the too slow test speed may lead to the inability to accurately capture the dynamic performance changes of the memory under high-speed operation of the system.

[0071] Based on this, the present application provides a read and write test method for a memory device, an electronic device, and a storage medium to solve the above-mentioned technical problems. The technical solutions provided by the present application will be elaborated in detail one by one below.

[0072] In the first aspect, the present application provides a read and write test method for a memory device, which is applied to a test master chip. The test master chip includes a memory buffer. The read and write test method includes:

[0073] Step S110: Establish a communication connection with the memory device to be tested;

[0074] Step S120: Obtain a plurality of test subsequences; wherein, the length of the test subsequence is less than or equal to the length of the memory buffer;

[0075] Step S130: Set corresponding write addresses for each test subsequence at a preset address interval;

[0076] Step S140: Write the corresponding test subsequences into the memory buffer in a preset write order, write the test subsequences in the memory buffer into the memory device to be tested according to the write addresses corresponding to the test subsequences, and perform a cleaning operation on the memory buffer until all the test subsequences are written into the memory device to be tested; wherein, the cleaning operation is used to clear the data in the memory buffer;

[0077] Step S150: Again, in the write order, sequentially obtain a plurality of read subsequences from the memory device to be tested through the memory buffer and according to the write addresses;

[0078] Step S160: Compare the read subsequences with the corresponding test subsequences to generate a test result.

[0079] In steps S110 to S160, first, relying on a test master chip with a memory buffer, a stable communication connection is established with the memory under test. Then, a number of test subsequences are obtained, and it is specifically limited that the length of the test subsequence is less than or equal to the length of the memory buffer, so as to avoid situations such as data loss during writing due to data volume overflow. According to a preset address interval, a corresponding write address is set for each test subsequence. Subsequently, in accordance with the preset write order, the test subsequences are first written into the memory buffer. The memory buffer plays a role in accelerating data transmission, and by using its relatively high-speed read and write characteristics, it speeds up the data flow from the master chip to the memory buffer. Immediately afterwards, according to the set write address, the test subsequences in the memory buffer are written into the memory under test. After each write, an immediate cleaning operation is performed on the memory buffer, that is, the data in the memory buffer is completely cleared. Repeat this process until all the test subsequences are accurately written into the memory under test. Again, in accordance with the previous write order, several read subsequences are respectively obtained from the memory under test through the memory buffer and the corresponding write address. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which prompts the read operation to directly face the memory under test, forcing the read and write operations to interact more directly with the memory under test, making the write test process no longer rely solely on the memory buffer, but truly involve the write operations on different address areas of the memory under test, so as to accurately test the write performance of the memory under test. During the read test, due to the previous cleaning operation, the test master chip can only read data from the memory under test, which also ensures the authenticity of the read performance test. This application improves the efficiency of the write test by using the memory buffer while ensuring the test accuracy.

[0080] Refer to Figure 2 , it can be understood that in step S110, it may include but is not limited to the following steps:

[0081] Step S210: Obtain the test sequence;

[0082] Step S220: Cut the test sequence according to the length of the memory buffer to obtain a number of test subsequences;

[0083] Step S230: Generate the write order for each test subsequence according to the arrangement order of the test sequence.

[0084] In steps S210 to S230, the test sequence is cut into test subsequences according to the length of the memory buffer, which not only makes full use of the storage space of the memory buffer, avoids the risk of buffer overflow caused by excessive data volume, but also can assist data writing with the relatively efficient transmission performance of the memory buffer, thereby optimizing the efficiency of the entire test process. Generating the writing order of each test subsequence according to the arrangement order of the test sequence provides a clear logical order for the entire test process. In the writing test stage, strictly writing the test subsequences into the memory buffer and the memory under test in this order can ensure that the data is written in an orderly manner, facilitating tracing and troubleshooting when problems occur.

[0085] Refer to Figure 3 , it can be understood that in step S160, it may include but is not limited to the following steps:

[0086] Step S310: Combine several read subsequences according to the writing order to obtain a read sequence;

[0087] Step S320: Compare the read sequence with the test sequence to generate a test result.

[0088] In steps S310 to S320, during the memory read and write process, due to the complexity of the data storage and reading mechanism, the read data may be scattered or the order may be different from that during writing. By combining according to the writing order, the complete state of the original data after being read from the memory can be restored to the greatest extent, making it comparable with the original test sequence in format and order. The test result generated through this detailed comparison method can not only reflect whether the memory under test can correctly store and read data, but also further reflect the data read and write quality under different writing orders, data patterns, storage locations, etc.

[0089] It can be understood that before step S160, it may also include but is not limited to the following steps:

[0090] Step S410: Adjust the address interval multiple times, and update the writing address corresponding to each test subsequence according to the adjusted address interval;

[0091] Step S420: Erase the data in the memory under test;

[0092] Step S430: Write the test subsequences into the memory under test in sequence again through the memory buffer and according to the new writing address, and perform a cleaning operation on the memory buffer after each test subsequence is written into the memory under test;

[0093] Step S440: Again, in the writing order, sequentially obtain a number of read subsequences from the memory under test through the memory buffer and according to the new writing addresses one by one.

[0094] Correspondingly, in step S160, it may include but is not limited to the following steps:

[0095] Step S450: Compare the read subsequences obtained according to different address intervals with the corresponding test subsequences to generate a test result.

[0096] In steps S410 to S450, by adjusting the address interval multiple times and updating the writing address, various different data storage distribution situations can be simulated. In practical applications, the storage methods of data in memory are diverse. Some data may be closely arranged, while some may be sparsely distributed. Round - robin testing enables the memory under test to undergo read - write tests under different "data layouts", so as to comprehensively evaluate the read - write performance of the memory under various possible storage scenarios. Different address intervals will change the positional relationship of the test subsequences in the memory, and this change helps to explore the boundary conditions of the memory performance. For example, when the address interval is very small, the extreme performance of the memory when processing continuous data blocks may be tested; as the address interval increases, the performance of the memory in dealing with scattered data can be observed, including whether there are local performance bottlenecks or the performance change rules in certain special address intervals, so as to more deeply understand the performance characteristics of the memory.

[0097] It can be understood that the multiple adjustments of the address interval in step S410 may include but are not limited to the following steps:

[0098] Step S510: Obtain the storage capacity of the memory under test;

[0099] Step S520: Determine the number of adjustments and the increment interval according to the storage capacity;

[0100] Step S530: Adjust the address interval multiple times according to the number of adjustments, and the address interval adjusted each time increases according to the increment interval.

[0101] In steps S510 to S530, by obtaining the storage capacity of the memory to be tested to determine the number of adjustments and the increment interval, this method enables the test process to be adaptively adjusted according to the actual size of the memory. For memories with small capacities, it may not require excessive adjustment times and large increment intervals to comprehensively test their performance; while for memories with large capacities, correspondingly increasing the adjustment times and increment intervals can ensure that data can cover a wider storage area, thereby achieving precise testing of memories with different capacities. For example, a small-capacity embedded memory may only require a small number of adjustment times (such as 3 - 5 times) and a small increment interval to test the read and write performance of each storage area; while a large-capacity server memory may require more adjustment times (such as 10 - 20 times) and a large increment interval to fully evaluate its performance under different data distributions. This adaptive adjustment method avoids over-testing or under-testing situations, can reduce unnecessary test rounds while ensuring comprehensive testing of the memory performance, thereby improving the test efficiency. Compared with a fixed adjustment method that does not consider the memory capacity, it can arrange test resources more pertinently according to the specific capacity characteristics of the memory, saving test time and costs.

[0102] It can be understood that in step S160, it may include but is not limited to the following steps:

[0103] Step S610: When the read subsequence does not match the corresponding test subsequence, determine the corresponding abnormal address according to the test subsequence;

[0104] Step S620: Obtain the abnormal address range according to the abnormal address and the length of the corresponding test subsequence;

[0105] Step S630: Generate a test result according to the abnormal address range.

[0106] In steps S610 to S630, when the read subsequence does not match the test subsequence, the corresponding abnormal address can be determined according to the test subsequence, which enables the precise location of the position where the read and write error occurs. Further, according to the abnormal address and the length of the test subsequence, the abnormal address range can be obtained, which can more comprehensively evaluate the area affected by the fault.

[0107] It can be understood that in step S630, it may include but is not limited to the following steps:

[0108] Step S710: Obtain the storage capacity of the memory to be tested;

[0109] Step S720: Obtain the abnormal capacity according to the total length of all abnormal address ranges;

[0110] Step S730: Calculate the abnormal ratio based on the abnormal capacity and the storage capacity.

[0111] Step S740: Generate a test result based on the abnormal address range and the abnormal ratio.

[0112] In steps S710 to S740, by obtaining the storage capacity of the memory device to be tested and getting the abnormal capacity according to the total length of all abnormal address ranges, this process transforms the memory read / write error from a simple location information into a quantifiable capacity concept. Further, calculate the abnormal ratio based on the abnormal capacity and the storage capacity, and present the read / write performance problem of the memory device in the form of a ratio. This abnormal ratio can provide a unified measurement standard between memory devices with different capacities, facilitating horizontal comparison of memory devices. Generate a test result based on the abnormal address range and the abnormal ratio, so that the test result includes both the specific location information where the error occurs and the quantitative evaluation of the overall performance problem. Engineers can locate design defects based on the detailed location information and the overall ratio; in the production process, quality control personnel can set reasonable quality standards according to the abnormal ratio to determine whether the product is qualified; during use, users can decide whether to continue using the memory device based on the test result, or take measures to deal with possible problems.

[0113] It can be understood that in the read / write test method of the memory device provided in this application, it may further include but is not limited to the following steps:

[0114] Step S810: Obtain the write time when all test subsequences are written into the memory device to be tested through the memory buffer, and the read time when all read subsequences are read through the memory buffer.

[0115] Step S820: Obtain the write speed based on the write time and the total length of the test subsequences.

[0116] Step S830: Obtain the read speed based on the read time and the total length of the read subsequences.

[0117] Step S840: Generate a processing speed evaluation result based on the write speed and the preset write threshold, and the read speed and the preset read threshold.

[0118] In steps S810 to S840, the read and write speeds of the memory directly affect the response speed and fluency of the system. By obtaining the write time and read time to calculate the write speed and read speed respectively, the read and write performance of the memory can be quantitatively evaluated from the speed dimension. According to the write speed and the preset write threshold, and the read speed and the preset read threshold, a processing speed evaluation result is generated. By setting the corresponding thresholds and comparing the measured speeds, it can be intuitively judged whether the memory meets the speed requirements of a specific application scenario, thus providing a strong basis for the selection and adaptation of the memory.

[0119] In a second aspect, the present application also provides an electronic device, including: at least one memory, at least one processor, and at least one program. The program is stored in the memory, and the processor executes one or more programs to implement the above-mentioned read and write test method for the memory.

[0120] In this electronic device, first, relying on a test master chip with a memory buffer, a stable communication connection is established with the memory to be tested. Then, a number of test subsequences are obtained, and it is specifically limited that the length of the test subsequence is less than or equal to the length of the memory buffer, so as to avoid the situation of data loss during writing caused by overflow due to excessive data volume. According to the preset address interval, a corresponding write address is set for each test subsequence. Subsequently, in accordance with the preset write order, the test subsequences are first written into the memory buffer. The memory buffer plays a role in accelerating data transmission, and using its relatively high-speed read and write characteristics, it speeds up the flow of data from the master chip to the memory buffer. Immediately afterwards, according to the set write address, the test subsequences in the memory buffer are written into the memory to be tested. After each write is completed, a cleaning operation is immediately performed on the memory buffer, that is, the data in the memory buffer is completely cleared. Repeat this process until all the test subsequences are accurately written into the memory to be tested. Again, in accordance with the previous write order, several read subsequences are respectively obtained from the memory to be tested through the memory buffer and the corresponding write address. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which promotes the read operation to directly face the memory to be tested, forcing the read and write operations to interact more directly with the memory to be tested, making the write test process no longer rely solely on the memory buffer, but truly involve the write operations on different address areas of the memory to be tested, so as to accurately test the write performance of the memory to be tested. During the read test, due to the previous cleaning operation, the test master chip can only read data from the memory to be tested, which also ensures the authenticity of the read performance test. The present application improves the efficiency of the write test by using the memory buffer on the premise of ensuring test accuracy.

[0121] The memory may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store relevant data of the read / write test method of the above-mentioned memory, etc. In addition, the memory may include a high-speed random access memory and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processing module through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0122] One or more signals are stored in the memory and, when executed by one or more processors, perform the read / write test method of the memory in any of the above method embodiments.

[0123] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which when executed by one or more processors, enables the one or more processors to perform the read / write test method of the memory in the above method embodiments.

[0124] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] Through the description of the above embodiments, those of ordinary skill in the art can understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable signals, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically contains computer-readable signals, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0126] It should be understood that in this application, "at least one item)" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following items)" or its similar expression refers to any combination of these items, including any combination of a single item) or multiple items). For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0127] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0128] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0129] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0130] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of this application. And the aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks or optical discs and other various media that can store programs.

[0131] The above has described the embodiments of this application in detail with reference to the drawings. However, this application is not limited to the above embodiments. Within the knowledge scope of ordinary technical personnel in the technical field to which this application belongs, various changes can also be made without departing from the purpose of this application.

Claims

1. A read and write test method for a memory device, characterized in that: Applied to testing a main control chip, the main control chip includes a memory buffer, and the read-write test method includes: Establishing a communication connection with the memory to be tested; Acquire a plurality of test subsequences; wherein the length of the test subsequence is less than or equal to the length of the memory buffer; According to a preset address interval, setting a corresponding write address for each test subsequence; Writing the corresponding test subsequences into the memory buffer in accordance with a preset writing order, writing the test subsequences in the memory buffer into the memory device under test according to the write addresses corresponding to the test subsequences, and performing a flushing operation on the memory buffer until all the test subsequences have been written into the memory device under test; wherein the flushing operation is used to clear data in the memory buffer; Again, according to the write order, sequentially through the memory buffer and according to the write address, a plurality of read subsequences are obtained from the memory device to be tested; The read subsequence is compared with the corresponding test subsequence to generate a test result.

2. The memory read / write test method according to claim 1, wherein: The obtaining of several test subsequences includes: Get the test sequence; Splitting the test sequence according to the length of the memory buffer to obtain a plurality of test subsequences; The writing sequence for each of the test subsequences is generated according to the arrangement order of the test sequence.

3. The memory read / write test method according to claim 2, wherein: The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: Combining a plurality of the read subsequences according to the write order to obtain a read sequence; The read sequence is compared with the test sequence to generate a test result.

4. The read / write test method of a memory device according to claim 1, wherein: Before the step of comparing the read subsequence with the corresponding test subsequence to generate a test result, the method further includes: Adjusting the address interval multiple times, and updating the write address corresponding to each test subsequence according to the adjusted address interval; Erasing the data in the memory to be tested; writing the test subsequences into the memory device under test in sequence through the memory buffer again according to the write order and based on the new write address, and performing a flushing operation on the memory buffer after each test subsequence is written into the memory device under test; Again, according to the write order, sequentially through the memory buffer and according to the new write address, sequentially acquiring a plurality of the read subsequences from the memory to be tested; The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: The read subsequences obtained according to different address intervals are compared with the corresponding test subsequences to generate a test result.

5. The read / write test method of a memory device according to claim 4, wherein: The adjusting the address interval multiple times includes: Obtain the storage capacity of the memory to be tested; Determining the number of adjustments and the increment interval according to the storage capacity; The address interval is adjusted multiple times according to the number of adjustments, and the address interval is increased each time according to the incremental interval.

6. The memory read / write test method according to claim 1, wherein: The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: When the read subsequence does not match the corresponding test subsequence, determining a corresponding abnormal address according to the test subsequence; Obtaining an abnormal address range according to the abnormal address and the length of the corresponding test subsequence; A test result is generated according to the abnormal address range.

7. The read / write test method of a memory device according to claim 6, wherein: Generating a test result according to the abnormal address range includes: Obtain the storage capacity of the memory to be tested; Obtaining an abnormal capacity according to the total length of all the abnormal address ranges; Calculating an abnormality ratio according to the abnormal capacity and the storage capacity; The test result is generated according to the abnormal address range and the abnormal ratio.

8. The read / write test method of a memory device according to claim 1, wherein: Also includes: Obtaining the write time of all the test subsequences writing into the memory to be tested through the memory buffer, and the read time of all the read subsequences reading from the memory buffer; Obtaining a write speed according to the write time and the total length of the test subsequence; Obtaining a reading speed according to the reading time and the total length of the read subsequence; A processing speed evaluation result is generated according to the write speed and a preset write threshold, and the read speed and a preset read threshold.

9. An electronic device, characterized in that: include: at least one memory; at least one processor; at least one program; The programs are stored in the memory, and the processor executes at least one of the programs to implement the read and write test method for a memory device according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable signals, and the computer-executable signals are used to execute the read and write test method for a memory device according to any one of claims 1 to 8.

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