A memory chip testing system and testing method

Abstract

The present invention provides a memory chip testing system and testing method, wherein the testing system includes a host, a chip test socket, a first interface module, a second interface module, and a bridge chip module; the chip test socket is used to mount a chip to be tested; the first interface module and the second interface module are used to connect to the host; the bridge chip module is used to obtain a test data packet written by the host and perform protocol conversion on the test data packet between the data packet format of the chip to be tested and the data packet format of the first interface module or the second interface module; the bridge chip module is used to adjust the read and write performance of the chip to be tested to different read and write speed levels to detect the read and write performance of the chip to be tested. The present invention uses the host to determine the integrity of the test data packet after reading and writing by the memory chip, thereby determining the read and write performance of the chip to be tested corresponding to the read and write speed, thereby solving the problem that traditional testing platforms cannot fully meet the read and write performance testing requirements of memory chips after iteration.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chip testing, and in particular to a memory chip testing system and a testing method. Background Art

[0002] With the widespread adoption of UFS (Universal Flash Storage) chips in end products such as TVs, set-top boxes, tablets, and mobile phones, the performance and reliability requirements for UFS chips are becoming increasingly stringent. Crucially, ensuring the stability and reliability of data stored in UFS is paramount. UFS chips consist of an ARM CPU as a controller and NAND Flash. The ARM CPU runs the controller software, commonly known as firmware. The firmware's primary functions include managing bad blocks, garbage collection, and providing early warnings, improving performance and lifespan, and ensuring reliable operation of the NAND Flash. With the widespread adoption of UFS and other storage chips in mobile phones, tablets, and wearable devices, client demands for UFS storage performance are increasing. Ensuring UFS performance stability in all application scenarios is a critical concern for every storage vendor.

[0003] With the evolution and iteration of the UFS protocol, the speeds of UFS2.1, UFS2.2, UFS3.1, UFS4.0, and UFS5.0 are getting faster and faster. The current card readers on the market basically only meet the test requirements of UFS2.1 and UFS2.2 speeds, and lack support for the higher speeds of UFS3.1, UFS4.0, and UFS5.0. For module manufacturers, there is a lack of high-speed testing tools. Based on the actual product testing needs, this paper proposes an overall testing system solution that can solve the current dilemma and meet the needs of UFS storage manufacturers for high-speed testing tools.

[0004] With the widespread use of UFS storage chips in terminal products, storage chip manufacturers need testing tools that can test UFS storage performance. Traditional platforms cannot fully meet the performance testing requirements of iterative storage chips.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention and does not constitute any limitation to the present invention. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a memory chip testing system and testing method to solve the problem that traditional testing platforms cannot fully meet the read and write performance testing requirements of iterative memory chips.

[0007] The present invention provides a memory chip testing system, comprising:

[0008] Host;

[0009] Chip test socket, used to install the chip to be tested;

[0010] The first interface module and the second interface module are connected to the host and the bridge chip module respectively;

[0011] A bridge chip module, which connects to the chip under test by connecting to the chip test socket. The bridge chip module obtains a test data packet sent by the host, performs protocol conversion on the test data packet between the data packet format of the chip under test and the data packet format of the first interface module or the second interface module, and then writes the converted test data packet to the chip under test. The bridge chip module then reads the test data packet from the chip under test, converts the data packet format, and sends it to the host.

[0012] Among them, the host determines whether the test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with the test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; the bridge chip module adjusts the read and write performance of the chip under test to different read and write speed levels, and converts the data packet format between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host.

[0013] In one embodiment of the present invention, the bridge chip module identifies the first interface module or the second interface module connected to the host, and adjusts the read and write performance of the first interface module or the second interface module to the highest read and write speed through the host according to the host's read and write performance adjustment command.

[0014] In one embodiment of the present invention, the bridge chip module includes:

[0015] Central processing unit;

[0016] A memory access unit, configured to read a test data packet of the chip under test and write the test data packets of the first interface module and the second interface module into the chip under test;

[0017] a memory buffer unit, configured to receive and store the test data packets read and written by the memory access unit;

[0018] The protocol conversion unit is used to convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip under test.

[0019] In one embodiment of the present invention, the central processing unit performs an initialization operation on the chip under test loaded into the chip test socket, and determines a corresponding read / write speed level according to the specifications of the chip under test.

[0020] In one embodiment of the present invention, the memory access unit includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads the test data packet of the chip to be tested and writes the read test data packet of the chip to be tested into the memory buffer unit. The write data memory access unit writes the test data packet of the first interface module and the second interface module into the memory buffer unit.

[0021] In one embodiment of the present invention, the protocol conversion unit removes the protocol field from the test data packet in the memory buffer unit and retains its original data field, and then packages the original data field to form a new data packet format, so that the test data packet can be converted between the data packet format of the chip to be tested and the data packet format of the first interface module or the second interface module.

[0022] In one embodiment of the present invention, the central processing unit is used to write the test data packet of the first interface module or the second interface module into the memory buffer unit through the write data memory access unit, and convert the test data packet from the data packet format of the first interface module or the second interface module into the data packet format of the chip to be tested through the protocol conversion unit.

[0023] In one embodiment of the present invention, the central processing unit is used to read the test data packet of the chip under test into the memory buffer unit through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module through the protocol conversion unit.

[0024] The present invention also provides a method for testing a memory chip, comprising:

[0025] Detecting whether the module connected to the host is the first interface module or the second interface module through the bridge chip module, and detecting the chip to be tested installed in the chip test socket;

[0026] Obtain a test data packet sent by the host, convert the test data packet between the data packet format of the first interface module or the second interface module and the data packet format of the chip under test through the bridge chip module, write the converted test data packet to the chip under test, then read the test data packet written to the chip under test, convert its data packet format and send it to the host;

[0027] Determining, by the host, whether a test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with a test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test;

[0028] The read and write performance of the chip under test is adjusted to different read and write speed levels through the bridge chip module, and the data packet format conversion is performed between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host.

[0029] The present invention provides a memory chip testing system and method that allows a host computer to control the read and write speed of a memory chip, thereby increasing the speed to a higher level. Furthermore, the host computer determines the integrity of test data packets after reading and writing data through the memory chip, thereby determining the read and write performance of the chip under test at the corresponding read and write speed. This system can rapidly test the read and write performance of multiple memory products in different test environments, improving testing efficiency.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that a person skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0032] Figure 1 This is an architectural diagram of the memory chip testing system of the present invention;

[0033] Figure 2 This is an architectural diagram of the bridge chip module in the present invention;

[0034] Figure 3 A schematic diagram of the data packet format of the USB protocol data packet in the present invention;

[0035] Figure 4 Schematic diagram of the data packet format of the PCIE protocol data packet in the present invention;

[0036] Figure 5 Schematic diagram of the data packet format of the UFS protocol data packet in the present invention;

[0037] Figure 6 This is a flow chart of the storage chip testing method of the present invention.

[0038] In the figure: 10, host; 20, chip test socket; 30, first interface module; 40, second interface module; 50, bridge chip module; 60, indication module; 51, central processing unit; 52, memory access unit; 53, memory buffer unit; 54, protocol conversion unit; 55, interface unit; 56, power management unit; 57, serial interface unit; 58, speed indication unit. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention by means of specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and examples can be combined with each other unless they conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, not to limit the scope of protection of the present invention.

[0040] See also Figures 1 to 6 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as position and quantitative relationship quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0041] See also Figure 1The present invention provides a memory chip test system, comprising a host 10, a chip test socket 20, a first interface module 30, a second interface module 40, and a bridge chip module 50; the chip test socket 20 is used to mount a chip to be tested; the first interface module 30 and the second interface module 40 are connected to the host 10 and the bridge chip module 50 respectively; the bridge chip module 50 is connected to the chip to be tested by connecting to the chip test socket 20, and the bridge chip module 50 obtains a test data packet sent by the host 10, performs protocol conversion on the test data packet between the data packet format of the chip to be tested and the data packet format of the first interface module 30 or the second interface module 40, and then transmits the converted test data packet to the host 10. The test data packet is written into the chip under test, and then the test data packet in the chip under test is read out, and its data packet format is converted and sent to the host 10; wherein, the host 10 determines whether the test data packet sent by the host 10 to the chip under test through the first interface module 30 or the second interface module 40 is consistent with the test data packet sent by the chip under test to the host 10 through the first interface module 30 or the second interface module 40, so as to detect the read and write performance of the chip under test; the bridge chip module 50 adjusts the read and write performance of the chip under test to different read and write speed levels, and performs data packet format conversion between the test data packet sent from the host 10 to the chip under test and the test data packet sent from the chip under test to the host 10.

[0042] Specifically, in an embodiment of the present invention, the host 10, such as a computer, serves as an interactive terminal for operating the test system, and forms a connection with the bridge chip module 50 through a first interface module 30, such as a high-speed serial computer expansion bus standard PCIE (Peripheral Component Interconnect Express) interface, or a second interface module 40, such as a universal serial bus USB (Universal Serial Bus) interface, to write and read test data packets. Similarly, the number of multi-channel threads of the multi-core CPU in the host 10 can also be used to meet the multi-channel queue MCQ (Multi-Channel Queue) test of the universal flash memory UFS (Univeral Flash Storage) to improve its storage performance and concurrent processing capabilities, and ensure that the UFS storage particles, that is, the extreme performance of the chip to be tested, are tested. The chip test socket 20 is used to install the storage chip to be tested, such as UFS, to test the read and write performance. As shown in the attached figure Figure 1-2As shown, in some embodiments, the chip test socket 20 can be expanded into a four-way UFS Socket channel. In other embodiments, there can be four UFS chip test sockets 20 connected to the bridge chip module 50. These four chip test sockets 20 can simultaneously connect 1 to 4 USF test chips for testing to meet the testing requirements of different memory chip particle numbers and capacities. The corresponding interfaces of the first interface module 30 and the second interface module 40, such as PCIE 4.0 and USB 4.0, have higher read and write speeds than UFS 4.0, which serve as read and write performance redundancy for the test chip, such as the UFS 4.0 memory chip. The bridge chip module 50, that is, the bridge conversion chip, can be customized to be a chip MULTI BRIDGE that integrates multiple bridge functions. It can connect different types of buses and interfaces in the computer system to realize data transmission and protocol conversion. It is used to realize the mutual conversion between different high-speed interface protocols in the high read and write speed UFS to PCIE or USB bridge conversion chip after iteration.

[0043] Please see the attached Figure 1 As shown, in one embodiment of the present invention, the test system also includes an indicator module 60, which can be an indicator proportional light G1-G5, indicating the current UFS read and write performance adjustment Tuning speed level, which is used to intuitively feedback the read and write speed level of the chip under test.

[0044] That is to say, in an embodiment of the present invention, the test system of the storage chip can be understood as a UFS / USB / PCIE protocol adapter card device. By setting the read and write speeds of different protocols, the test data packet written by the host 10 is converted between the data packet formats of different interface protocols and storage protocols. When the test data packet passes through the read and write process between the UFS / USB / PCIE protocols, the integrity of the data content in the test data packet is still maintained, which indicates the performance reliability of the storage chip at the current read and write speed. The host 10 controls the read and write speed of the storage chip's read and write performance and increases it to a higher read and write speed. The host 10 judges the integrity of the test data packet after reading and writing through the storage chip, thereby determining the read and write performance of the chip to be tested corresponding to the read and write speed.

[0045] In one embodiment, the host 10 is configured to send a read / write performance adjustment instruction to the first interface module 30, wherein the maximum read / write speed of the first interface module 30 is greater than the maximum read / write speed of the second interface module 40. When both the first interface module 30 and the second interface module 40 are present, that is, when both a PCIE interface and a USB interface are present, the speed of the PCIE interface is typically adjusted first because the PCIE interface generally provides higher bandwidth and lower latency. For high-performance applications, such as hardware with high data transfer rates, such as a chip under test, adjusting the speed of the PCIE interface ensures that the performance components in the test system are operating optimally. In test system application scenarios, the read / write speed requirements of the USB interface are prioritized after the PCIE interface. This ensures the highest read / write speed performance requirements of the test system. The bridge chip module 50 identifies the first interface module 30 or the second interface module 40 connected to the host 10 and, based on the read / write performance adjustment instruction from the host 10, adjusts the read / write performance of the first interface module 30 or the second interface module 40 to the maximum read / write speed through the host 10. During the reading and writing process of the test data packets between the host 10 and the chip to be tested, for example, the first interface module 30 and the second interface module 40 correspond to the two interface protocol types of PCIE and USB respectively, and utilize their higher read and write performance than the chip to be tested, such as the UFS storage chip. After the connection is achieved through the host 10, the read and write performance of the two interface protocols needs to be adjusted to the highest read and write speed accordingly. For example, the host 10 identifies the hardware versions of the two interface protocols, adapts the driver and firmware updates, and performs corresponding configuration optimization to meet the read and write speed performance test requirements of the chip to be tested.

[0046] See also Figure 2In one embodiment, the bridge chip module 50 includes a central processing unit 51, a memory access unit 52, a memory buffer unit 53, and a protocol conversion unit 54. The memory access unit 52 is used to read test data packets from the chip under test and write test data packets from the first interface module 30 and the second interface module 40 to the chip under test; the memory buffer unit 53 is used to receive and store the test data packets read and written by the memory access unit 52; and the protocol conversion unit 54 is used to convert the data packet format of the chip under test into the data packet format of the first interface module 30 or the second interface module 40, and convert the data packet format of the first interface module 30 or the second interface module 40 into the data packet format of the chip under test. The central processing unit 51 initializes the chip under test loaded into the chip test socket 20 and determines the corresponding read and write speed level based on the specifications of the chip under test. The memory access unit 52 includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads the test data packet of the chip to be tested and writes the read test data packet of the chip to be tested into the memory buffer unit 53. The write data memory access unit writes the test data packet of the first interface module 30 and the second interface module 40 into the memory buffer unit 53.

[0047] Specifically, in an embodiment of the present invention, the central processing unit 51 can be a processor chip that adopts the RISC-V (Reduced Instruction Set Computer - Five, the fifth generation of simplified instruction set computer) instruction set architecture, which is responsible for the internal configuration management of the entire bridge chip module 50. By adopting a processor chip with the RISC-V instruction set architecture to manage the data flow of the test system, perform protocol conversion and processing control tasks, it can be customized according to the needs of the test system, add or remove instruction set extensions, thereby optimizing performance and power consumption. At the same time, the open source nature of the RISC-V instruction set architecture eliminates the need to pay high license fees, thereby reducing chip costs; it can also be modified and optimized according to the specific needs of the test system, and quickly iterate the design; and it is compatible with various interfaces and protocols, supporting a variety of application scenarios.

[0048] More specifically, the central processing unit 51 initializes the read and write performance adjustment Tuning for the UFS storage chip identified as being installed on the chip test socket 20. According to the different specifications SPEC of the storage particles stored in the UFS storage chip, the chip to be tested, that is, the storage chip, can be adjusted and set from its read and write speed level Gear1 to Gear2, Gear3, Gear4 or Gear5, that is, the read and write performance corresponding to the Gear1-Gear5 (gear 1-gear 5) read and write speed levels can be tested respectively.

[0049] In this embodiment of the present invention, the memory access unit 52 uses its Remote Direct Memory Access (RDMA) and Write-Data Memory Access (WDMA) modules to read and write test data packets in the bridge chip module 50 between the first interface module 30 or the second interface module 40 and the chip under test, respectively. The read and written test data packets are then sent to the memory buffer unit 53 (SRAM buffer). Similarly, the use of the memory buffer unit 53 enables the memory access unit 52 to convert between different protocols more quickly, ensuring that read and write speeds reach the maximum speed of the protocol, thus meeting the test system's requirements for read and write performance testing.

[0050] See also Figure 2 As shown, in an embodiment of the present invention, the bridge chip module 50 also includes a power management unit 56, a serial interface unit 57, a speed indication unit 58 and multiple interface units 55; the power management unit 56 is used to manage the power of the bridge chip module 50, the serial interface unit 57 is used to output debug log information, the speed indication unit 58 is used to detect the speed of the chip to be tested after performance adjustment, and the corresponding indication module 60, and the multiple interface units 55 are used to connect with the first interface module 30, the second interface module 40 and the chip test socket 20 respectively.

[0051] See also Figures 1 to 5 In one embodiment, the protocol conversion unit 54 removes the protocol field from the test data packet in the memory buffer unit 53 and retains its original data field, then packages the original data field to form a new data packet format, so that the test data packet can be converted between the data packet format of the chip under test and the data packet format of the first interface module 30 or the second interface module 40. The central processing unit 51 is used to write the test data packet of the first interface module 30 or the second interface module 40 into the memory buffer unit 53 through the write data memory access unit, and convert the test data packet from the data packet format of the first interface module 30 or the second interface module 40 into the data packet format of the chip under test through the protocol conversion unit 54. The central processing unit 51 is used to read the test data packet of the chip under test into the memory buffer unit 53 through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module 30 or the second interface module 40 through the protocol conversion unit 54.

[0052] Specifically, in the embodiment of the present invention, the protocol conversion unit 54 (Protocol Conversion-1 / ProtocolConversion-2) includes two parts that bidirectionally convert the test data packet between the data packet format of the first interface module 30, such as PCIE protocol data packet, or the second interface module 40, such as USB protocol data packet, and the data packet format of the chip under test, such as UFS protocol data packet. Figures 1 to 5 As shown, the main difference between the data packet formats of the first interface module 30 such as PCIE protocol data packet, the second interface module 40 such as USB protocol data packet and the chip under test such as UFS protocol data packet is that they follow different protocol specifications.

[0053] More specifically, in the attached Figure 3 In the USB protocol data packet format, the data packet format content may include: packet start SOP (Start-Of-Packet), synchronization SYNC (Synchronization), data packet content Packet Content, packet end EOP (End-Of-Packet), packet identifier PID (Packet Identifier), address, frame number, data and cyclic redundancy check CRC (Cyclic Redundancy Check). Some packet identifiers PID carry addresses, some carry frame numbers, and some carry data, and their addresses / frame numbers / data do not appear at the same time.

[0054] In the attached Figure 4 In the data packet format of the PCIE protocol data packet, the data packet format may include: transaction layer data packet TLP (Transaction Layer Packet), start, sequence, header, data payload, end-to-end cyclic redundancy check ECRC (End-to-End Cyclic Redundancy Check), link layer cyclic redundancy check LCRC (Link-layer Cyclic Redundancy Check) and end End. In the field of the transaction layer data packet TLP, the digital units corresponding to each field are double words DW (Double Word) and byte B (Byte); double words DW usually refer to two adjacent words in the computer field. It is a data storage unit. The number of bytes varies under different architectures. In a common 32-bit system, 1 double word is 4 bytes (Byte); Byte B is a unit of measurement used in computer information technology to measure storage capacity. 1 byte is equal to 8 bits (bit).

[0055] In the attached Figure 5 In the data packet format of the UFS protocol data packet, the data packet format content may include: Bit, Byte, Operation Code, Read Protection RDPROTECT, Disable Page Out DPO (Disable Page Out), Force Unit Access FUA (Force Unit Access), Read Attributes Response Command RARC (Read Attributes Response Command), Obsolete (obsolete), Most Significant Bit MSB (Most Significant Bit), Logical Block Address LOGICAL BLOCK ADDRESS, Least Significant Bit LSB (Least Significant Bit), Reserved, Group Number GROUP NUMBER, Transfer Length TRANSFER LENGTH, and Control CONTROL field contents.

[0056] By combining different definitions of the start, address, data, checksum, end, and attribute fields of these protocol data packets, in this embodiment of the present invention, test data packets can be interpreted as identical across different modules. Whether there are differences in the test data packets is determined by host 10. Specifically, protocol conversion unit 54 (Protocol Conversion-1) removes the protocol fields from the UFS protocol data packets stored in memory buffer unit 53, retaining the original data (DATA), and then packages the corresponding original data into PCIE protocol data packets or USB protocol data packets. Protocol conversion unit 54 (Protocol Conversion-2) removes the protocol fields from the PCIE protocol data packets or USB protocol data packets stored in memory buffer unit 53, retaining the original data, and then packages the corresponding original data into UFS protocol data packets.

[0057] See also Figure 6 The present invention also provides a method for testing a memory chip, comprising:

[0058] S10, detecting, through the bridge chip module 50, whether the first interface module 30 or the second interface module 40 is connected to the host 10, and detecting the chip to be tested loaded into the chip test socket 20;

[0059] S20: Obtain a test data packet sent by the host 10, convert the test data packet between the data packet format of the first interface module 30 or the second interface module 40 and the data packet format of the chip under test through the bridge chip module 50, write the converted test data packet to the chip under test, then read the test data packet written to the chip under test, convert the data packet format and send it to the host 10;

[0060] S30, determining, by the host 10, whether a test data packet written by the host 10 to the chip under test through the first interface module 30 or the second interface module 40 is consistent with a test data packet sent by the chip under test to the host through the first interface module 30 or the second interface module 40, and the test data packet written by the host 10, so as to detect the read and write performance of the chip under test;

[0061] S40, using the bridge chip module 50 to adjust the read and write performance of the chip under test to different read and write speed levels, and converting the data packet format between the test data packet written from the host 10 to the chip under test and the test data packet sent from the chip under test to the host 10.

[0062] Specifically, in an embodiment of the present invention, the test method of the memory chip is mainly for converting different high-speed interface protocols of UFS / USB / PCIE, so as to facilitate the UFS product to use PC-side multi-threading for extreme speed testing. The bridge chip module 50 serves as the calculation and control core in the memory chip test method, and is the execution unit for test data packet read and write processing and program running. The bridge chip module 50 can adjust the read and write speed performance of the chip to be tested on the chip test socket 20 and the first interface module 30 and the second interface module 40 according to the instructions of the host 10, and collect the accuracy of the data packet format conversion of the test data packet of the chip to be tested under the set read and write speed performance by comparing the written test data packet with the read test data packet. The bridge chip module 50 can be used to detect the read and write performance of the chip to be tested.

[0063] More specifically, in one embodiment of the present invention, step S10 may include a two-part test process. In the first part of the test process, corresponding to steps (1)-(3), respectively, the test system using the test method is a UFS / USB / PCIE protocol adapter card device. Step (1) can be represented as the four chip test sockets 20UFS Socket in the UFS / USB / PCIE protocol adapter card device can be placed with 1 / 2 / 3 / 4 different combinations of test chips, namely UFS storage particles. Step (2) can be represented as the UFS / USB / PCIE protocol adapter card device is inserted into the gold finger interface of the host 10PC end through the first interface module 30, namely the PCIE interface. Step (3) can be represented as the host 10PC-UI sending the read and write performance adjustment PCIE Tuning command of the first interface module 30, and after identifying the UFS / USB / PCIE protocol adapter card device, tuning the PCIE to the highest speed, and then jumping to step (9). In the second part of the test process, corresponding to steps (9) and (10), step (9) can be represented as the bridge chip module 50Bridge IC checking whether the first interface module 30 such as PCIE or the second interface module 40 such as USB is inserted into the host 10PC end, and performing tuning in conjunction with the host 10PC end until the highest speed of PCIE or USB is achieved. Step (10) can be represented as the bridge chip module 50Bridge IC powering on and initializing. The central processing unit 51 of the RISC-V instruction set architecture is used internally to configure the internal modules and send a command to check whether the chip to be tested, i.e., the UFS storage particle, is present in the UFS Socket.

[0064] In one embodiment of the present invention, step S20 may include a two-part test process. In the first part of the test process, corresponding to steps (4)-(6), step (4) can be represented as the upper-layer software on the host 10PC-UI side sending a write command for a large block of random data, and then jumping to step (12). Step (5) can be represented as the upper-layer software on the host 10PC-UI side sending a read command for a large block of random data, and then jumping to step (14). Step (6) can be represented as the upper-layer software on the host 10PC-UI side comparing the read data with the write data. In the second part of the test process, corresponding to steps (12)-(15), step (12) can be represented as the test data packet of the host 10PC-UI passing through the PCIE Interface interface, and then writing the PCIE data packet format or the USB data packet format into the memory buffer unit 53SRAM Buffer through the write data memory access unit WDMA in the bridge chip module 50. Step (13) can be represented as the protocol conversion unit 54Protocol Conversion-2 parsing the PCIE data packet format or the USB data packet format, packaging it to generate the UFS data packet format, and sending it to the corresponding chip to be tested, that is, the universal flash storage channels 1 / 2 / 3 / 4 (UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4) installed in the four chip test sockets 20. Step (14) can be represented as the central processing unit 51 using the RISC-V instruction set architecture reading the test data packets stored in the UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4 installed in the four chip test sockets 20 into the memory unit SRAM Buffer through the remote direct memory access unit RDMA in the bridge chip module 50. Step (15) can be represented as the protocol conversion unit 54Protocol Conversion-1 converting the data packet format of UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4 installed in the four chip test sockets 20 into the data packet format of PCIE or USB.

[0065] In one embodiment of the present invention, step S30 may include a two-part test process. In the first part of the test process, corresponding to steps (7)-(8), step (7) may be represented as judging whether the comparison of read data and write data is consistent through the host 10. If so, it can jump to step (8), otherwise it can jump to step (16). Step (8) may be represented as inserting the UFS / USB / PCIE protocol adapter device into the USB interface of the PC via USB, and then jumping to step (9). In the second part of the test process, corresponding to steps (16)-(17), step (16) may be represented as performing data analysis and checking on the comparison error between read data and write data in the host 10 as the root cause of the data error, and performing repair verification. Step (17) may be represented as judging whether the problem has been repaired. If so, it can jump to step (3), otherwise it can jump to step (16).

[0066] In one embodiment of the present invention, step S40 may include step (11), which is represented by the central processing unit 51 using the RISC-V instruction set architecture initializing Tuning for the inspected UFS storage chip, and selecting the read and write speed level from Gear1 to Gear2 or Gear3 or Gear4 or Gear5 for adjustment according to the different SPEC specifications of the storage particles in the chip to be tested.

[0067] In summary, the present invention provides a test system and test method for a memory chip, which, by setting the read and write speeds of different protocols, cooperates with the test data packet written by the host to be converted between the data packet formats of different interface protocols and storage protocols, and when the test data packet is read and written between the UFS / USB / PCIE protocols, the integrity of the data content in the test data packet is still maintained, that is, the performance reliability of the memory chip under the current read and write speed is indicated, the read and write speed of the memory chip read and write performance is controlled by the host, and promoted to a higher read and write speed, and the integrity of the test data packet after reading and writing by the memory chip is judged by the host, thereby determining the read and write performance of the corresponding read and write speed of the chip to be tested. The present invention is simple to operate and has strong reusability. It can quickly detect the read and write performance of multiple storage products in different test environments, thereby improving test efficiency.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A memory chip testing system, characterized in that: include: Host; Chip test socket, used to install the chip to be tested; The first interface module and the second interface module support the PCIE protocol and the USB protocol respectively, and are connected to the host and the bridge chip module respectively; a bridge chip module, wherein the bridge chip module is connected to the chip test socket to achieve connection with the chip under test, the bridge chip module obtains a test data packet sent by the host, performs protocol conversion on the test data packet between a data packet format of the chip under test and a data packet format of the first interface module or the second interface module, writes the converted test data packet to the chip under test, and then reads the test data packet from the chip under test, converts the data packet format, and sends it to the host; Among them, the host determines whether the test data packet sent by the host to the chip under test through the first interface module or the second interface module is consistent with the test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; the bridge chip module adjusts the read and write performance of the chip under test to the corresponding read and write speed level according to the protocol version of the chip under test, and performs data packet format conversion between the test data packet sent from the host to the chip under test and the test data packet sent from the chip under test to the host; the bridge chip module dynamically selects the interface type according to the protocol version of the chip under test, and enables the corresponding protocol conversion and speed level based on the selected interface type.

2. The test system according to claim 1, wherein: The bridge chip module identifies the first interface module or the second interface module connected to the host, and adjusts the read and write performance of the first interface module or the second interface module to the highest read and write speed through the host according to the read and write performance adjustment command of the host.

3. The test system according to claim 2, wherein: The bridge chip module includes: Central processing unit; a memory access unit, configured to read a test data packet of the chip under test and write the test data packets of the first interface module and the second interface module into the chip under test; a memory buffer unit, configured to receive and store the test data packets read and written by the memory access unit; The protocol conversion unit is used to convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip under test.

4. The test system according to claim 3, characterized in that: The central processing unit performs an initialization operation on the chip to be tested which is loaded into the chip test socket, and determines a corresponding reading and writing speed level according to the specification of the chip to be tested.

5. The test system according to claim 3, characterized in that: The memory access unit includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads the test data packet of the chip to be tested and writes the read test data packet of the chip to be tested into the memory buffer unit. The write data memory access unit writes the test data packet of the first interface module and the second interface module into the memory buffer unit.

6. The test system according to claim 3, wherein: The protocol conversion unit removes the protocol field from the test data packet in the memory buffer unit and retains its original data field, and then packages the original data field to form a new data packet format, so that the test data packet can be converted between the data packet format of the chip to be tested and the data packet format of the first interface module or the second interface module.

7. The test system according to claim 5, characterized in that: The central processing unit is used to write the test data packet of the first interface module or the second interface module into the memory buffer unit through the write data memory access unit, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip to be tested through the protocol conversion unit.

8. The test system according to claim 5, wherein: The central processing unit is used to read the test data packet of the chip under test into the memory buffer unit through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module through the protocol conversion unit.

9. A method for testing a memory chip, characterized in that: include: Detecting whether the module connected to the host is the first interface module or the second interface module through the bridge chip module, and detecting the chip to be tested installed in the chip test socket; Obtaining a test data packet sent by the host, converting the test data packet between the data packet format of the first interface module or the second interface module and the data packet format of the chip under test through the bridge chip module, then writing the converted test data packet to the chip under test, then reading the test data packet written to the chip under test, converting its data packet format and sending it to the host; Determining, by the host, whether a test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with a test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; The bridge chip module adjusts the read and write performance of the chip under test to the corresponding read and write speed level according to the protocol version of the chip under test, and performs data packet format conversion between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host. The bridge chip module dynamically selects the interface type according to the protocol version of the chip under test, and enables the corresponding protocol conversion and speed level based on the selected interface type.

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