Control Method, Device and Electronic Device for Testing Memory Chip Coupling Faults

Abstract

The present application discloses a control method, device, and electronic device for memory chip coupling fault testing, including: obtaining a distribution structure in a chip to be tested; dividing storage units into a plurality of test areas, and determining a first test sequence between the test areas and a second test sequence for each storage unit; obtaining a first test sequence and a second test sequence; writing the first test sequence into the first test area, and writing the second test sequence into the other test areas at once; after all test areas are written, reading the target test sequence from each test area respectively according to the first test sequence and the second test sequence; comparing the target test sequence with the corresponding first test sequence or second test sequence according to the first test sequence to determine the coupling fault type. The present application can improve the efficiency of troubleshooting memory chip coupling faults and ensure the quality and reliability of memory chips.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a control method, device, and electronic device for memory chip coupling fault testing. Background Art

[0002] In today's digital age, memory chips are widely used in various electronic devices, and their performance and reliability are crucial. However, due to the close layout and electrical characteristics of the memory cells within the chip, memory chips are prone to coupling failures during use. This failure can cause signal interference between memory cells, leading to errors in data storage and reading, seriously impacting the normal operation of the device. Existing memory chip testing methods struggle to accurately and efficiently determine the type and location of coupling failures, failing to meet the demand for high-reliability memory chip testing. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a control method, device, and electronic device for memory chip coupling fault testing, which can improve the efficiency of memory chip coupling fault troubleshooting and ensure the quality and reliability of memory chips.

[0004] In a first aspect, the present application provides a control method for memory chip coupling fault testing, comprising:

[0005] Obtaining the distribution structure of the memory cells in the chip under test;

[0006] Dividing the storage cells into a plurality of test areas according to the distribution structure, and determining a first test order between the test areas and a second test order for each of the storage cells; wherein the number of the storage cells in each test area is the same;

[0007] Obtaining a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the areas to be tested and corresponds to the length of the second test sequence;

[0008] According to the first test order and the second test order, the first test sequence is written into the first of the areas to be tested, and the second test sequence is written into the other areas to be tested at one time;

[0009] After all the test areas have been written, the target test sequence is obtained by reading from each of the test areas according to the first test sequence and the second test sequence;

[0010] According to the first test order, the target test sequence is compared with the corresponding first test sequence or the second test sequence to determine the coupling fault type.

[0011] According to the control method for memory chip coupling fault testing of the first embodiment of the present application, there are at least the following beneficial effects: first, the distribution structure of the memory cells in the chip to be tested is obtained, and based on this, the memory cells are divided into several test areas, and the number of memory cells in each test area is ensured to be the same. A first test sequence and a second test sequence are determined between the test areas and for each memory cell. A first test sequence and a second test sequence are obtained to be written into the test areas, and the length of the first test sequence corresponds to the memory cells in each test area and also corresponds to the length of the second test sequence, to ensure that the memory cells in each test area are fully covered, providing a guarantee for comprehensive testing. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area and the second test sequence is written into the other test areas in sequence. After all the test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the coupling fault type is determined through comparative analysis. By rationally dividing the test area and determining a detailed test sequence, each memory cell can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it is possible to accurately determine which test area or even which memory cell has a coupling fault, thereby improving the efficiency of troubleshooting memory chip coupling faults and ensuring the quality and reliability of the memory chip.

[0012] According to some embodiments of the first aspect of the present application, obtaining a first test sequence and a second test sequence to be written into the area to be tested includes:

[0013] Acquire a first test sequence to be written into the area to be tested;

[0014] Complement the first test sequence to obtain the second test sequence.

[0015] According to some embodiments of the first aspect of the present application, dividing the storage unit into a plurality of areas to be tested according to the distribution structure includes:

[0016] determining a region length according to the distribution structure;

[0017] According to the region length, the region is divided in ascending order of the addresses of the storage units in the distribution structure to form a plurality of regions to be tested.

[0018] According to some embodiments of the first aspect of the present application, determining a first test order between the regions to be tested and a second test order for each of the memory cells includes:

[0019] determining the first test order among the areas to be tested according to the address of the first storage unit in each area to be tested;

[0020] The second test order of each of the memory cells is determined according to the addresses of the memory cells in the same area to be tested.

[0021] According to some embodiments of the first aspect of the present application, comparing the target test sequence with the corresponding first test sequence or the second test sequence to determine the coupling fault type includes:

[0022] Compare the target test sequence with the corresponding first test sequence or the second test sequence bit by bit, and record abnormal address bits;

[0023] The coupling fault type is determined according to the distribution of the abnormal address bits.

[0024] According to some embodiments of the first aspect of the present application, determining the coupling fault type according to the distribution of the abnormal address bits includes:

[0025] When the address adjacent to the abnormal address bit is not the abnormal address bit, determining that the coupling fault type is a single bit upset fault;

[0026] When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, determining that the coupling fault type is a multi-bit upset fault;

[0027] When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

[0028] According to some embodiments of the first aspect of the present application, after the step of comparing the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine the coupling fault type, the method further includes:

[0029] changing the first test sequence and the second test sequence;

[0030] performing repeated write and read tests on the chip under test according to the new first test sequence and the second test sequence;

[0031] Obtaining the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence;

[0032] If the coupling fault type of the current time is inconsistent with the coupling fault type of the previous time, re-changing the first test sequence and the second test sequence, and re-performing the write and read tests on the chip under test;

[0033] If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

[0034] In a second aspect, the present application further provides a control device for memory chip coupling fault testing, comprising:

[0035] A first acquiring unit, configured to acquire a distribution structure of storage units in the chip to be tested;

[0036] a determining unit, configured to divide the storage cells into a plurality of test areas according to the distribution structure, and determine a first test order between the test areas and a second test order for each of the storage cells; wherein the number of the storage cells in each test area is the same;

[0037] a second acquiring unit, configured to acquire a first test sequence and a second test sequence to be written into each of the areas to be tested; wherein the length of the first test sequence corresponds to the storage unit of each area to be tested and corresponds to the length of the second test sequence;

[0038] a writing unit, configured to write the first test sequence into the first of the areas to be tested, and write the second test sequence into the other areas to be tested at once, according to the first test sequence and the second test sequence;

[0039] a reading unit, configured to, after all the test areas have been written, read the target test sequence from each of the test areas according to the first test sequence and the second test sequence;

[0040] A comparison unit is configured to compare the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine a coupling fault type.

[0041] In a third aspect, the present application further provides an electronic device, comprising:

[0042] at least one memory;

[0043] at least one processor;

[0044] at least one program;

[0045] The program is stored in the memory, and the processor executes at least one of the programs to implement the control method for memory chip coupling fault testing as described in any one of the embodiments of the first aspect.

[0046] In a fourth aspect, the present application further provides a computer-readable storage medium, which stores a computer-executable signal, and the computer-executable signal is used to execute the control method for memory chip coupling fault testing as described in any embodiment of the first aspect.

[0047] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Additional aspects and advantages of the present application will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0049] Figure 1 A flowchart of a control method for memory chip coupling fault testing provided by some embodiments of the present application;

[0050] Figure 2 For this application Figure 1 Flowchart regarding step S130;

[0051] Figure 3 For this application Figure 1 A flowchart of an embodiment of step S120;

[0052] Figure 4 For this application Figure 1 Flowchart of another embodiment of step S120;

[0053] Figure 5 For this application Figure 1 Flowchart regarding step S160;

[0054] Figure 6 For this application Figure 5 Flowchart about step S520;

[0055] Figure 7 For this application Figure 5 Flowchart after step S160. DETAILED DESCRIPTION

[0056] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0057] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0058] In the description of this application, if there is a description of first or second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0059] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0060] In today's digital age, memory chips are widely used in various electronic devices, and their performance and reliability are crucial. However, due to the close layout and electrical characteristics of the memory cells within the chip, memory chips are prone to coupling failures during use. This failure can cause signal interference between memory cells, leading to errors in data storage and reading, seriously impacting the normal operation of the device. Existing memory chip testing methods struggle to accurately and efficiently determine the type and location of coupling failures, failing to meet the demand for high-reliability memory chip testing.

[0061] Based on this, the present application provides a control method, device and electronic device for memory chip coupling fault testing to solve the above-mentioned technical problems. The technical solutions provided by the present application are described in detail one by one below.

[0062] First, refer to Figure 1 , the present application provides a control method for memory chip coupling fault testing, including but not limited to the following steps:

[0063] Step S110: obtaining the distribution structure of the memory cells in the chip to be tested;

[0064] Step S120: Dividing the memory cells into a plurality of test regions according to the distribution structure, and determining a first test sequence between the test regions and a second test sequence for each memory cell; wherein the number of memory cells in each test region is the same;

[0065] Step S130: Acquire a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to each memory cell in the area to be tested and corresponds to the length of the second test sequence;

[0066] Step S140: writing the first test sequence into the first area to be tested and writing the second test sequence into the other areas to be tested at once according to the first test order and the second test order;

[0067] Step S150: After all the test areas have been written, the target test sequence is obtained by reading from each test area according to the first test sequence and the second test sequence.

[0068] Step S160: According to the first test order, the target test sequence is compared with the corresponding first test sequence or second test sequence to determine the coupling fault type.

[0069] In steps S110 to S160, the distribution structure of the memory cells in the chip to be tested is first obtained. Based on this, the memory cells are divided into several test areas, ensuring that the number of memory cells in each test area is the same. The first test sequence between the test areas and the second test sequence for each memory cell are determined. A first test sequence and a second test sequence are obtained to be written into the test areas. The length of the first test sequence corresponds to the memory cells in each test area and also corresponds to the length of the second test sequence to ensure that the memory cells in each test area can be fully covered, providing a guarantee for comprehensive testing. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area and the second test sequence is written into the other test areas in sequence. After all test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the type of coupling fault is determined through comparative analysis. By rationally dividing the test area and determining a detailed test sequence, each memory cell can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it is possible to accurately determine which test area or even which memory cell has a coupling fault, thereby improving the efficiency of troubleshooting memory chip coupling faults and ensuring the quality and reliability of the memory chip.

[0070] By using different test sequences (primary and secondary) for different test areas, the characteristics of coupling faults can be better identified when the target test sequence is subsequently read and compared with the original test sequence. If data from different areas differs, the use of different test sequences makes it easier to determine which area has failed and what type of fault it is.

[0071] Reference Figure 2 It is understood that step S130 may include but is not limited to the following steps:

[0072] Step S210: obtaining a first test sequence to be written into the test area;

[0073] Step S220: Complement the first test sequence to obtain a second test sequence.

[0074] In steps S210 to S220, by complementing the first test sequence to obtain a second test sequence, the memory cells can be tested from both positive and negative perspectives. For example, if the first test sequence detects a certain type of coupling fault after being written to the memory cell, then the second test sequence (the complement of the first test sequence) may detect a different type of coupling fault after being written. Because coupling faults between memory cells may manifest differently under different data modes (original code and complement), this allows for more comprehensive detection of various possible coupling fault types. Coupling faults in memory chips can be caused by a variety of factors, such as different circuit layouts and signal interference methods. A single test sequence may only detect some fault types. By setting up a first test sequence and a second test sequence, and particularly by complementing the first test sequence to obtain the second test sequence, a wider range of data storage and reading conditions can be simulated.

[0075] Reference Figure 3 It is understood that, in step S120 of "dividing the storage unit into a plurality of test areas according to the distribution structure", the following steps may be included but not limited to:

[0076] Step S310: determining the region length according to the distribution structure;

[0077] Step S320: dividing the region into several regions to be tested according to the region length and in the ascending order of the addresses of the storage units in the distribution structure.

[0078] First, the distribution structure of the memory cells within the memory chip is analyzed. This distribution structure includes information such as the arrangement and physical layout of the memory cells within the chip. For example, memory cells may be arranged in a row-column matrix, or they may be organized differently within different memory modules. Based on this distribution information and in conjunction with the test objectives and requirements, the region length is determined. After determining the region length, the region is divided according to the ascending order of the memory cell addresses, forming several test regions. Dividing the regions according to ascending address order makes the testing process highly logical and systematic, allowing testers to test each test region sequentially according to address order, without missing or duplicating test regions. Furthermore, determining the region length based on the chip's distribution structure better aligns the test region division with the chip's actual physical structure.

[0079] Reference Figure 4 In step S120 of “determining a first test order between the test areas and a second test order for each memory cell”, the following steps may be included but not limited to:

[0080] Step S410: determining a first test order among the test areas according to the address of the first memory cell in each test area;

[0081] Step S420: determining a second test order for each memory cell according to the addresses of the memory cells in the same test area.

[0082] In step S410, the address of the first memory cell in each test area is checked. Since the test areas have been divided according to the ascending order of memory cell addresses, the addresses of the first memory cells are also in order. For example, assume there are three test areas, the first memory cell address of the first test area is 0, the first memory cell address of the second test area is 100, and the first memory cell address of the third test area is 200. According to the order of addresses from smallest to largest, the first test order can be determined as follows: test the first test area first, then the second, and finally the third.

[0083] In step S420, within the same test area, the test order is also determined based on the memory cell addresses. Because each memory cell has its own address, these addresses also increase in sequence within a test area. For example, within a test area, the memory cell addresses range from 100 to 109. Therefore, in ascending order of addresses, the memory cell with address 100 is tested first, followed by 101, and so on, until the test order for all memory cells in the test area is determined.

[0084] Reference Figure 5It is understood that step S160 may include but is not limited to the following steps:

[0085] Step S510: performing bit-by-bit comparison of the target test sequence with the corresponding first test sequence or second test sequence, and recording abnormal address bits;

[0086] Step S520: Determine the coupling fault type according to the distribution of abnormal address bits.

[0087] In steps S510 to S520, the target test sequence is compared with the corresponding first or second test sequence, starting with the start bit of each sequence. For example, if the target test sequence is "1010" and the first test sequence is "1000," a bit-by-bit comparison from left to right will reveal that the third bit is different. After completing the bit-by-bit comparison and recording the abnormal address bits, the distribution of these abnormal address bits is analyzed to determine the type of coupling fault. By comparing and recording the abnormal address bits bit by bit, the specific storage unit where the coupling fault occurred can be accurately found.

[0088] Reference Figure 6 It is understood that step S520 may include but is not limited to the following steps:

[0089] Step S610: when the address adjacent to the abnormal address bit is not an abnormal address bit, determining that the coupling fault type is a single-bit flip fault;

[0090] Step S620: When the address adjacent to the abnormal address bit is an abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, determining that the coupling fault type is a multi-bit upset fault;

[0091] Step S630: When the address adjacent to the abnormal address bit is an abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

[0092] In step S610, the neighboring addresses of each abnormal address bit are checked in the recorded abnormal address bit information. For example, for the abnormal address bit set {3, 7, 12}, the neighboring addresses 2, 4, 6, 8, 11, and 13 are checked to see if they are also in the abnormal address bit set. If the neighboring addresses of each abnormal address bit are not abnormal address bits, then it can be determined that the fault is a single-bit flip fault, that is, the data of only a single storage unit has flipped, and there are no simultaneous failures of adjacent storage units.

[0093] In step S620, the adjacent addresses of the abnormal address bit are also checked. When it is found that the adjacent address of the abnormal address bit is also an abnormal address bit, it is necessary to further calculate the overlap ratio of the target test sequence and the first test sequence or the second test sequence. The overlap ratio can be calculated by counting the number of identical bits in the two sequences and then dividing it by the total length of the sequence. For example, the target test sequence is "1010", the first test sequence is "0000", the number of identical bits is 0, the total length is 4, and the overlap ratio is 0. If this overlap ratio is less than or equal to the preset ratio threshold, it is determined to be a multi-bit flip fault. This indicates that multiple adjacent storage unit data have been flipped, and the flipped result is quite different from the original sequence.

[0094] In step S630, if the adjacent address of the abnormal address bit is an abnormal address bit, and after calculating the overlap ratio, it is found that this overlap ratio is greater than the preset ratio threshold, it is determined to be a data shift fault, which means that the data of the storage unit may have shifted due to coupling or other reasons, but the overall data similarity remains high. This may be caused by address line errors, abnormal read / write control signals, or timing coupling issues between storage units, indicating that a timing error occurred during data transmission or storage.

[0095] Reference Figure 7 It is understandable that after step S160, the following steps may also be included but not limited to:

[0096] Step S710: changing the first test sequence and the second test sequence;

[0097] Step S720: Repeated writing and reading tests are performed on the chip under test according to the new first test sequence and the second test sequence;

[0098] Step S730: Obtain the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence;

[0099] Step S740: If the current coupling fault type is inconsistent with the previous coupling fault type, the first test sequence and the second test sequence are changed again, and the write and read tests are performed again on the chip under test;

[0100] Step S750: If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

[0101] In steps S710 to S750, after completing the first round of comparisons between the target test sequence and the first and second test sequences and determining the coupling fault type, the first and second test sequences are altered. This alteration can occur in a variety of ways, such as randomly flipping the bits of the original sequence, rearranging the sequence, or generating a new sequence according to a specific algorithm. For example, if the original first test sequence is "1010," it can be changed to "0110" using a random algorithm. Based on the new first and second test sequences, the chip under test is again subjected to write and read tests. Following the previously determined first and second test sequences, the new first test sequence is written to the corresponding test area, and the new second test sequence is written to the other test areas. After writing is complete, the new target test sequence is read from each test area to obtain the new target test sequence. The new target test sequence is then compared with the new first or second test sequence, and the coupling fault type is determined according to the previously determined comparison rules, such as bit-by-bit comparison and based on the abnormal address bit distribution to determine the current coupling fault type. The current coupling fault type is then compared with the previous coupling fault type. If the two do not match, the previously determined coupling fault type may be inaccurate. The first and second test sequences are then changed, and the write and read tests are repeated on the chip under test, repeating the process. If the two match, the coupling fault type is reliable after multiple tests and is output. By changing the test sequence multiple times and repeating the test, memory chip coupling faults can be detected from different perspectives. Different test sequences can simulate different data storage and transmission scenarios, thereby more comprehensively covering various possible coupling fault conditions.

[0102] In a second aspect, the present application further provides a control device for memory chip coupling fault testing, comprising:

[0103] A first acquiring unit, configured to acquire a distribution structure of storage units in the chip to be tested;

[0104] a determining unit, configured to divide the storage cells into a plurality of test areas according to the distribution structure, and determine a first test order between the test areas and a second test order for each storage cell; wherein the number of storage cells in each test area is the same;

[0105] a second acquiring unit, configured to acquire a first test sequence and a second test sequence to be written into each area to be tested; wherein the length of the first test sequence corresponds to a storage unit in each area to be tested and corresponds to the length of the second test sequence;

[0106] A writing unit, configured to write the first test sequence into the first area to be tested and write the second test sequence into the other areas to be tested at once according to the first test sequence and the second test sequence;

[0107] A reading unit is configured to read the target test sequence from each area to be tested according to the first test sequence and the second test sequence after all the areas to be tested have been written;

[0108] The comparison unit is used to compare the target test sequence with the corresponding first test sequence or second test sequence according to the first test order to determine the coupling fault type.

[0109] The specific implementation of the control device for the memory chip coupling fault test is substantially the same as the specific embodiment of the control method for the memory chip coupling fault test described above, and will not be described in detail herein.

[0110] In a third aspect, the present application also provides an electronic device comprising: at least one memory, at least one processor and at least one program, wherein the program is stored in the memory, and the processor executes one or more programs to implement the above-mentioned control method for memory chip coupling fault testing.

[0111] In this electronic device, the distribution structure of the memory cells in the chip to be tested is first obtained. Based on this, the memory cells are divided into several test areas, ensuring that the number of memory cells in each test area is the same. The first test sequence between the test areas and the second test sequence for each memory cell are determined. A first test sequence and a second test sequence are obtained to be written into the test areas. The length of the first test sequence corresponds to the memory cells in each test area, and also corresponds to the length of the second test sequence, to ensure that the memory cells in each test area can be completely covered, providing a guarantee for comprehensive testing. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area, and the second test sequence is written into the other test areas in sequence. After all test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the type of coupling fault is determined through comparative analysis. By rationally dividing the test area and determining a detailed test sequence, each memory cell can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it is possible to accurately determine which test area or even which memory cell has a coupling fault, thereby improving the efficiency of troubleshooting memory chip coupling faults and ensuring the quality and reliability of the memory chip.

[0112] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store relevant data of the control method for the above-mentioned memory chip coupling fault test, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the processing module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0113] One or more signals are stored in a memory, and when executed by one or more processors, the control method for memory chip coupling fault testing in any of the above method embodiments is executed.

[0114] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program is executed by one or more processors, enabling the one or more processors to execute the control method for memory chip coupling fault testing in the above method embodiment.

[0115] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected based on actual needs to achieve the objectives of this embodiment.

[0116] From the above description of the embodiments, one skilled in the art will appreciate that all or some of the steps and systems of the methods disclosed above can be implemented as software, firmware, hardware, or any suitable combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable signals, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable signals, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0117] It should be understood that in this application, "at least one item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following ()" or similar expressions refers to any combination of these items, including any combination of single items () or plural items (). For example, at least one of a, b or c () can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0121] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store programs.

[0122] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A control method for memory chip coupling fault testing, characterized in that: include: Obtaining the distribution structure of storage cells in the chip under test; Dividing the storage cells into a plurality of test areas according to the distribution structure, and determining a first test order between the test areas and a second test order for each of the storage cells; wherein the number of the storage cells in each test area is the same; Obtaining a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the areas to be tested and corresponds to the length of the second test sequence; According to the first test order and the second test order, the first test sequence is written into the first of the areas to be tested, and the second test sequence is written into the other areas to be tested at one time; After all the test areas have been written, the target test sequence is obtained by reading from each of the test areas according to the first test sequence and the second test sequence; According to the first test order, the target test sequence is compared with the corresponding first test sequence or the second test sequence to determine the coupling fault type; The step of comparing the target test sequence with the corresponding first test sequence or the second test sequence to determine the coupling fault type includes: Compare the target test sequence with the corresponding first test sequence or the second test sequence bit by bit, and record abnormal address bits; When the address adjacent to the abnormal address bit is not the abnormal address bit, determining that the coupling fault type is a single bit upset fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, determining that the coupling fault type is a multi-bit upset fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

2. The control method for memory chip coupling fault test according to claim 1, characterized in that: The acquiring of the first test sequence and the second test sequence to be written into the area to be tested includes: Acquire a first test sequence to be written into the area to be tested; Complement the first test sequence to obtain the second test sequence.

3. The control method for memory chip coupling fault test according to claim 1, characterized in that: The storage unit is divided into a plurality of test areas according to the distribution structure, including: determining a region length according to the distribution structure; According to the region length, the region is divided in ascending order of the addresses of the storage units in the distribution structure to form a plurality of regions to be tested.

4. The control method for memory chip coupling fault test according to claim 3, characterized in that: The determining of a first test order between the test areas and a second test order for each of the storage cells includes: determining the first test order among the areas to be tested according to the address of the first storage unit in each area to be tested; The second test order of each of the memory cells is determined according to the addresses of the memory cells in the same area to be tested.

5. The control method for memory chip coupling fault test according to claim 1, characterized in that: After the step of comparing the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine the coupling fault type, the method further includes: changing the first test sequence and the second test sequence; performing repeated write and read tests on the chip under test according to the new first test sequence and the second test sequence; Obtaining the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence; If the coupling fault type of the current time is inconsistent with the coupling fault type of the previous time, re-changing the first test sequence and the second test sequence, and re-performing the write and read tests on the chip under test; If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

6. A control device for memory chip coupling fault testing, characterized in that: include: A first acquiring unit, configured to acquire a distribution structure of storage units in the chip to be tested; a determining unit, configured to divide the storage cells into a plurality of test areas according to the distribution structure, and determine a first test order between the test areas and a second test order for each of the storage cells; wherein the number of the storage cells in each test area is the same; a second acquiring unit, configured to acquire a first test sequence and a second test sequence to be written into each of the areas to be tested; wherein the length of the first test sequence corresponds to the storage unit of each area to be tested and corresponds to the length of the second test sequence; a writing unit, configured to write the first test sequence into the first of the areas to be tested, and write the second test sequence into the other areas to be tested at once, according to the first test sequence and the second test sequence; a reading unit, configured to, after all the test areas have been written, read the target test sequence from each of the test areas according to the first test sequence and the second test sequence; a comparing unit, configured to compare the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order, to determine a coupling fault type; The comparison unit is further configured to: Compare the target test sequence with the corresponding first test sequence or the second test sequence bit by bit, and record abnormal address bits; When the address adjacent to the abnormal address bit is not the abnormal address bit, determining that the coupling fault type is a single bit upset fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, determining that the coupling fault type is a multi-bit upset fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

7. An electronic device, characterized in that: include: at least one memory; at least one processor; at least one program; The programs are stored in the memory, and the processor executes at least one of the programs to implement the control method for memory chip coupling fault testing according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable signals, and the computer-executable signals are used to execute the control method for memory chip coupling fault testing according to any one of claims 1 to 5.

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