Chip packaging method, chip packaging module and electronic equipment

Abstract

The invention provides a chip packaging method, a chip packaging module and electronic equipment. The method comprises the steps that a first packaging layer embedded with a first bonding pad layer, at least one first circuit layer and a second bonding pad layer which are electrically connected layer by layer is formed on a wafer, the first side of the first packaging layer makes contact with the wafer, the first bonding pad layer is formed on the first side of the first packaging layer, and the second bonding pad layer is formed on the second side of the first packaging layer; the first circuit layer is exposed from the second side of the first packaging layer, and the line width of the circuit in the first circuit layer is smaller than or equal to 2 microns; a second packaging layer is formed on the second side of the first packaging layer, third bonding pad layers and at least one second circuit layer are embedded in the second packaging layer, the third bonding pad layers are electrically connected layer by layer, the third bonding pad layers are electrically connected with the second bonding pad layers, and the minimum line width of the circuits in the second circuit layer is larger than that of the circuits in the first circuit layer; and removing the wafer in contact with the first side of the first packaging layer, exposing the first bonding pad layer, and electrically connecting the chip to the first bonding pad layer to obtain the chip packaging module.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip packaging technology, and in particular to a chip packaging method, a chip packaging module and an electronic device. Background Art

[0002] With the development of microelectronics industry technology, improving integration has become an important way for chips to break through performance bottlenecks. An important direction for the current progress of chip technology is the integration of chip packaging. Some chip packaging solutions in related technologies have high manufacturing costs and high process complexity while improving the integration of chip packaging. Therefore, a new technical solution is urgently needed to reduce the cost and process complexity of chip packaging. Summary of the invention

[0003] The embodiments of the present application provide a chip packaging method, a chip packaging module and an electronic device.

[0004] According to a first aspect of an embodiment of the present application, a chip packaging method is provided, including:

[0005] A first packaging layer is formed on a wafer, wherein a first pad layer, at least one first circuit layer and a second pad layer are embedded and electrically connected layer by layer, wherein the first packaging layer includes a first side and a second side opposite to each other in a thickness direction, the first side of the first packaging layer contacts the wafer, the first pad layer is formed on the first side of the first packaging layer, the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer, and the line width of the circuit in the first circuit layer is less than or equal to 2 um;

[0006] On the second side of the first packaging layer, a second packaging layer is formed in which a third pad layer and at least one second circuit layer are embedded, the third pad layer is electrically connected to the second pad layer, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer;

[0007] The wafer in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to obtain a chip packaging module.

[0008] According to a second aspect of an embodiment of the present application, a chip packaging module is provided, wherein the chip packaging module is packaged by the method described in any one of the first aspects.

[0009] According to a third aspect of the embodiments of the present application, a chip packaging module is provided, including:

[0010] chip;

[0011] A first packaging layer comprises a first side and a second side opposite to each other in a thickness direction, and is embedded with a first pad layer, at least one first circuit layer and a second pad layer, which are electrically connected layer by layer, wherein the first pad layer is located on a first side of the first packaging layer and is electrically connected to the chip, and the second pad layer is located on a second side of the first packaging layer;

[0012] A second packaging layer is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer, and the third pad layer is electrically connected to the second pad layer;

[0013] The line width of the circuit in the first circuit layer is less than or equal to 2 um, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer.

[0014] According to a fourth aspect of an embodiment of the present application, there is provided an electronic device, comprising: a chip packaging module as described in any one of the second aspect or the third aspect.

[0015] The technical solution in the embodiment of the present application can form a first packaging layer on a wafer, in which a first pad layer, at least one first circuit layer and a second pad layer are embedded with layer-by-layer electrical connections, the first packaging layer includes a first side and a second side opposite to each other in the thickness direction, the first side of the first packaging layer is in contact with the wafer, the first pad layer is formed on the first side of the first packaging layer, the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer, the line width of the line in the first circuit layer is less than or equal to 2um, and then on the second side of the first packaging layer, a second packaging layer is formed in which a third pad layer and at least one second circuit layer are embedded with layer-by-layer electrical connections, the third pad layer is electrically connected to the second pad layer, the minimum line width of the line in the second circuit layer is greater than the minimum line width of the line in the first circuit layer, and then the wafer in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to effectively obtain a chip packaging module. Therefore, through the above technical scheme, on the one hand, the present application does not need to use the through silicon via (TSV) process, and can effectively realize chip packaging and effectively obtain the chip packaging module, thereby reducing the manufacturing cost, and compared with the related technical scheme using the through silicon via process, effectively reducing the process complexity; on the other hand, using the technical scheme of the present application, the line width of the line in the first circuit layer is set to be less than or equal to 2um, and the minimum line width of the line in the second circuit layer is made larger than the minimum line width of the line in the first circuit layer, so that the line width of the line in the first circuit layer can be ensured to be small, which is convenient for realizing high-density lines and interconnections, and is beneficial to improving the integration of the chip packaging module; on the other hand, since the chip packaging scheme is to electrically connect the chip to the first pad layer after the first packaging layer and the second packaging layer are manufactured and connected, compared with the situation where the chip is electrically connected to the first pad layer first, it is beneficial to avoid the situation where the chip is scrapped together due to damage to any one of the first packaging layer and the second packaging layer, thereby helping to further reduce the process cost and ensure the yield of the chip packaging module finally obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0017] Figure 1 A schematic structural diagram of a chip packaging module obtained by a chip packaging solution in the related art is shown.

[0018] Figure 2 Schematic diagrams of chip packaging modules of some examples in the present application are shown.

[0019] Figure 3 The flowcharts of some exemplary chip packaging methods in the present application are shown.

[0020] Figure 4 Some optional flow charts of step S104 in the present application are shown.

[0021] Figure 5 Some optional flow charts of step S1042 in the present application are shown.

[0022] Figure 6a to Figure 6i Some optional schematic diagrams of the preparation process of the chip packaging module in this application are shown.

[0023] Figure 7 A schematic block diagram of an electronic device illustrating some examples in the present application is shown.

[0024] Description of reference numerals:

[0025] 100. Chip packaging module; 1. First packaging layer; 10. Wafer; 11. First pad layer; 111. First pad; 12. First circuit layer; 13. Second pad layer; 131. Second pad; 2. Second packaging layer; 21. Third pad layer; 211. Third pad; 22. Second circuit layer; 23. Fourth pad layer; 231. Fourth pad; 24. Electrical connection block; 201. First plastic sealing dielectric layer; 202. Second plastic sealing dielectric layer; 203. Third plastic sealing dielectric layer; 3. Chip; 4. Conductive block; 5. Protective layer; 200. Electronic device. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0027] With the development of microelectronics industry technology, improving integration has become an important way for chips to break through performance bottlenecks. An important direction for the current chip technology progress is the integration of chip packaging. Some chip packaging solutions in related technologies have high manufacturing costs and high process complexity while improving the integration of chip packaging.

[0028] For example, in the 2.5D or 3D packaging technology of the related art, one way to integrate chips with different process steps is to improve the integration through a silicon interposer (Silicon Interposer) adapter board. During the packaging process, the silicon interposer can be used as a connection layer between the chip and the packaging substrate. For example, taking the CoWoS (Chip on Wafer on Substrate) technical solution as an example, when a silicon interposer is used for chip packaging, the chip is generally welded to the circuit layer formed on one side of the silicon interposer, and the through silicon via (TSV) technology is required to electrically connect the circuit layer formed on the silicon interposer with the circuit layer of the packaging substrate on the other side of the silicon interposer. For example, Figure 1 The structure diagram of a chip packaging module obtained by a chip packaging solution in the related art is shown. Figure 1 An example of a stacked structure may be a CoWoS (Chip on Wafer on Substrate) technology solution. Figure 1 As shown, chip a and chip b are connected to the circuit layer formed on the upper surface of the silicon interposer through soldering, and the circuit layer includes interconnected metal circuits of various sizes made by wafer-level manufacturing process, and the final circuit interconnection is electrically connected to the lower surface of the silicon interposer through the silicon via (TSV) set in the silicon interposer, and then the interconnection with the circuit of the packaging substrate is realized through the solder structure. However, since such a silicon interposer has the characteristics of through silicon via (TSV) technology, and since the aspect ratio of the through silicon via TSV generally exceeds 10:1, its manufacturing technology is quite difficult, making the entire manufacturing cost high and the process complexity high.

[0029] However, including but not limited to Figure 1 The CoWoS technology solution uses a silicon interposer. Due to its characteristics of through-silicon via (TSV) technology, the entire manufacturing cost is high and the process complexity is high. In addition, with CoWoS technology, although the silicon interposer can be used to meet the needs of high-density metal wire interconnection, and the process technology is compatible with the manufacturing process of the wafer itself, and under the CoWoS technology solution, the chip is integrated with the silicon interposer, and then finally shipped as a module to the downstream packaging factory for welding with the packaging substrate. In this module, if the silicon interposer is damaged due to process deviations of the silicon interposer itself (such as defects in through-silicon vias TSV, etc.) or short circuits of the interconnects, the chip will be directly scrapped, which will further cause the entire process cost to be high. And because of such a process architecture, it is impossible to ensure the yield of the product well, so the cost of packaging integration is also very obvious.

[0030] In view of this, the present application provides a chip packaging solution to at least partially improve the above problems. It should be understood that the chip packaging solution of the present solution does not use through silicon vias (TSV) to achieve, which can at least partially avoid the above problems. Figure 1 The defects of the technical solution shown are overcome, and the manufacturing cost and process complexity of the chip packaging module are effectively reduced, and the integration of the obtained chip packaging module is effectively improved.

[0031] The specific implementation of the technical solution of the embodiment of the present application is described below in conjunction with the accompanying drawings. It should be noted that for the convenience of illustration in each of the drawings, each structure may not be drawn according to the actual scale. Each of the drawings does not serve as any limitation to the embodiment of the present application.

[0032] Here, the main structure of the chip packaging module 100 obtained by packaging in the embodiment of the present application is briefly introduced, so as to facilitate the specific description of the chip packaging method below. Figure 2 In the example shown, the chip packaging module 100 prepared by the preparation method of the first aspect of the embodiment of the present application comprises: a chip 3, a first packaging layer 1 and a second packaging layer 2. The first packaging layer 1 comprises a first side and a second side opposite to each other in the thickness direction, and is embedded with a first pad layer 11, at least one first circuit layer 12 and a second pad layer 13 which are electrically connected layer by layer. The first pad layer 11 is located on the first side of the first packaging layer 1 and is electrically connected to the chip 3, and the second pad layer 13 is located on the second side of the first packaging layer 1; the second packaging layer 2 is embedded with a third pad layer 21 which is electrically connected layer by layer and at least one second circuit layer 22, and the third pad layer 21 is electrically connected to the second pad layer 13; the line width of the circuit in the first circuit layer is less than or equal to 2um, and the minimum line width of the circuit in the second circuit layer 22 is greater than the minimum line width of the circuit in the first circuit layer 12.

[0033] It should be understood that the type of chip 3 is not limited in the present application, and it can be any chip. For example, it can include but is not limited to processor chips (for example, but not limited to GPU (Graphics Processing Unit), CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), etc.), storage chips (for example, but not limited to HBM (High Bandwidth Memory) chips, ROM (Read-Only Memory) chips, RAM (Random Access Memory) chips, FLASH memory (Flash Memory) chips, EEPROM (Electrically Erasable Programmable Read-Only Memory) chips, EPROM (Erasable Programmable Read-Only Memory) chips), system-level chips (also known as system on chip, System on Chip, referred to as SoC), etc., or other analog circuit chips or digital circuit chips. The number of chips 3 is not limited in the present application, and one or more chips 3 may be electrically connected to the first pad layer 11. Figure 2 In the example shown, the first pad layer 11 is electrically connected to two chips 3 .

[0034] Alternatively, if Figure 2 As shown, the first pad layer 11 may include a plurality of first pads 111, and the plurality of first pads 111 may be used to realize electrical connection with different pads of the chip 3. Figure 2As shown, the second pad layer 13 includes a plurality of second pads 131, and the third pad layer 21 includes a plurality of third pads 211, and the plurality of second pads 131 can be electrically connected to the plurality of third pads 211 respectively. It should be noted that the number of first pads 111 can be designed as required, and the shapes and sizes of the plurality of first pads 111 can be the same or different, which is not limited here. The number of second pads 131 can be designed as required, and is not limited here, and the shapes and sizes of the plurality of first pads 111 can be the same or different. The number of third pads 211 can be designed as required, and the shapes and sizes of the plurality of third pads 211 can be the same or different, which is not limited here.

[0035] It should be understood that Figure 2 It is understood that in the first encapsulation layer 1 and the second encapsulation layer 2 obtained in the present application, the first encapsulation layer 1 can be regarded as a silicon interposer, and does not need to rely on the through silicon via process, and the second encapsulation layer 2 can be regarded as a packaging substrate. Figure 1 The CoWoS technology solutions shown have significant differences in chip packaging process and product structure.

[0036] Figure 3 The flowchart of the chip packaging method of some examples in this application is shown. Figure 3 As shown, the chip packaging method includes steps S102, S104 and S106, specifically:

[0037] S102: A first packaging layer is formed on a wafer and is provided with a first pad layer, at least one first circuit layer and a second pad layer which are electrically connected layer by layer, wherein the first packaging layer includes a first side and a second side opposite to each other in a thickness direction, the first side of the first packaging layer is in contact with the wafer, the first pad layer is formed on the first side of the first packaging layer, the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer, and the line width of the circuit in the first circuit layer is less than or equal to 2um.

[0038] When understanding the relevant contents of step S102, you can also combine Figure 6a Schematic diagram for understanding.

[0039] The chip packaging method of the present application may first form a first packaging layer 1 on a wafer 10. Optionally, the wafer 10 here may refer to a silicon wafer. The wafer may be of any size as required, for example, including but not limited to a 6-inch wafer, an 8-inch wafer, a 12-inch wafer, etc.

[0040] The first encapsulation layer 1 can be formed by any suitable encapsulation material. Optionally, the first encapsulation layer 1 can be formed by an encapsulation material suitable for subsequent manufacturing of circuits using a wafer-level manufacturing process. For example, in some optional embodiments, the material of the first encapsulation layer 1 can be SiO2, i.e., silicon dioxide. That is, the first encapsulation layer is formed on the wafer in step S102 of the present application, and the first encapsulation layer 1 in the form of a SiO2 layer can be formed on the wafer 10. For example, at least one of the process methods including but not limited to PECVD (Plasma-Enhanced Chemical Vapor Deposition), HDPCVD (High-Density Plasma Chemical Vapor Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), etc. can be used to grow SiO2 on the wafer 10 to form the first encapsulation layer 1 in the form of a SiO2 layer.

[0041] It should be understood that the first packaging layer 1 in the form of a SiO2 layer, on the one hand, can be used as an insulating layer to effectively meet some insulation requirements between the subsequently formed layer structures (i.e., the first pad layer 11, at least one first circuit layer 12 and the second pad layer 13); on the other hand, by adopting the first packaging layer 1 in the form of a SiO2 layer, when forming the first circuit layer 12, it is easier to make the line width of the circuit therein less than or equal to 2um, thereby improving the integration of the encapsulated chip packaging module.

[0042] One or more first circuit layers 12 may be embedded in the first packaging layer 1. Optionally, the first packaging layer 1 may be embedded with 1 to 10 first circuit layers 12. Of course, more first circuit layers 12 may be provided as needed. For example Figure 2 In the example, the first packaging layer 1 is embedded with two first circuit layers 12.

[0043] The first pad layer 11 in the present application may include a plurality of first pads 111, and the specific number can be designed as needed. It should be understood that when there are multiple layers of the first circuit layer 12, the circuit structure between each layer of the first circuit layer 12 may have a substantially identical circuit structure, or may be a completely different circuit structure. The circuit structure in each layer of the first circuit layer 12 is not limited in the present application, and can be designed according to actual needs. The second pad layer 13 in the present application may include a plurality of second pads 131, and the specific number can be designed as needed. The first packaging layer 1 formed on the wafer 10 includes a first side and a second side opposite to each other in the thickness direction, the first side of the first packaging layer 1 contacts the wafer 10, the first pad layer 11 is formed on the first side of the first packaging layer 1, and can be used to electrically connect to the chip later, the second pad layer 13 is formed on the second side of the first packaging layer 1, and is exposed from the second side of the first packaging layer 1, and can be used to electrically connect to the third pad layer 21 later.

[0044] Alternatively, if Figure 6a As shown, the second side of the first encapsulation layer 1 may be opened by any physical or chemical process to expose the first pad layer 11 .

[0045] The first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 formed in the present application are electrically connected layer by layer. For example, for example, there are two first circuit layers 12 between the first side and the second side opposite to each other in the thickness direction of the first packaging layer 1, then the formed first pad layer 11 is electrically connected to the first first circuit layer 12, and the second first circuit layer 12 is electrically connected to the formed second pad layer 13. Other situations can be understood by analogy with this example and will not be repeated here.

[0046] It can be understood that the first pad layer 11 is electrically connected to the first circuit layer 12, which may mean that at least the first pad 111 in the first pad layer 11 is electrically connected to at least part of the circuits in the first circuit layer 12. The first circuit layer 12 is electrically connected to the first circuit layer 12, which may mean that at least part of the circuits in the first circuit layer 12 are electrically connected to at least part of the circuits in the first circuit layer 12. The first circuit layer 12 is electrically connected to the second pad layer 13, which may mean that at least part of the circuits in the first circuit layer 12 are electrically connected to at least the second pad 131 in the second pad layer 13.

[0047] Optionally, the first pad layer 11, at least one first circuit layer 12 and the second pad layer 13 are electrically connected layer by layer, which can be achieved by providing an electrical connection structure between two adjacent layers. The electrical connection structure is not specifically limited here.

[0048] In the present application, any feasible method can be used to prepare the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13. In some optional embodiments, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13, which are electrically connected layer by layer, can be manufactured by a wafer-level manufacturing process. It should be understood that in the present application, a high-density interconnection line can be easily manufactured by a wafer-level manufacturing process, so that the line width of the line of the first circuit layer 12 can be made into a size of 2um, thereby improving the integration of the chip packaging module obtained by packaging.

[0049] Moreover, since the wafer-level manufacturing process does not involve the manufacture of transistors in this step, only circuit manufacturing and interconnection are carried out, it can ensure convenience and help reduce the difficulty of the process.

[0050] Optionally, the first pad layer 11, at least one first circuit layer 12 and the second pad layer 13 may be made of at least one metal material of copper and aluminum, or may be made of other metal materials or other feasible conductive materials.

[0051] For example, in some optional examples, when aluminum is used, the aluminum layer can be produced by sputtering, evaporation and other processes; when copper is used, a titanium-copper seed metal layer can be sputtered, and then a copper layer can be grown on the seed metal layer by electroplating, and finally produced according to the Damascus process.

[0052] Optionally, the line width of the line in the first circuit layer 12 in the present application can be 100nm-2um. Through the wafer-level manufacturing process, the above line width range can be relatively simple to achieve. In some embodiments, the line width in the first circuit layer 12 can be 100nm-1um. Such a line width range can make the chip packaging module have a better integration.

[0053] S104: On the second side of the first packaging layer, a second packaging layer is formed in which a third pad layer with layer-by-layer electrical connections and at least one second circuit layer are embedded. The third pad layer is electrically connected to the second pad layer, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer.

[0054] When understanding the relevant contents of step S104, you can also combine Figure 6b to Figure 6g Schematic diagram for understanding.

[0055] The above step S102 sets the line width of the line in the first circuit layer 12 to be less than or equal to 2um, and then through step S104, the minimum line width of the line in the second circuit layer 22 is made larger than the minimum line width of the line in the first circuit layer 12, thereby ensuring that the line width of the line in the first circuit layer 12 is small, facilitating the realization of high-density circuits and interconnections, and helping to improve the integration of the chip packaging module.

[0056] One or more second circuit layers 22 may be embedded in the second packaging layer 2. Optionally, the second packaging layer 2 may be embedded with 1 to 10 second circuit layers 22. Of course, more second circuit layers 22 may be provided as needed. Figure 2 In the example of FIG. 1 , the second packaging layer 2 is embedded with three second circuit layers 22 .

[0057] It should be understood that when there are multiple layers of second circuit layers 22, the circuit structures between each layer of second circuit layers 22 may be substantially the same circuit structure, or may be completely different circuit structures. The present application does not limit the circuit structure in each layer of second circuit layers 22, and may be designed according to actual needs. The third pad layer 21 in the present application may include multiple third pads 211, and the specific number may be designed as needed.

[0058] The third pad layer 21 and at least one second circuit layer 22 formed in the present application are electrically connected layer by layer. For example, in the second packaging layer 2, three second circuit layers 22 are embedded, and the third pad layer 21 is electrically connected to the first circuit layer 12, and the second second circuit layer 22 is electrically connected to the third second circuit layer 22. Other situations can be understood by analogy with this example, and will not be repeated here.

[0059] It can be understood that the third pad layer 21 is electrically connected to the second circuit layer 22, which may mean that at least the third pad 211 in the third pad layer 21 is electrically connected to at least part of the circuits in the second circuit layer 22. The second circuit layer 22 is electrically connected to the second circuit layer 22, which may mean that at least part of the circuits in the second circuit layer 22 are electrically connected to at least part of the circuits in the second circuit layer 22.

[0060] Optionally, the third pad layer 21 and at least one second circuit layer 22 may be made of at least one metal material of copper and aluminum, or may be made of other metal materials or other feasible conductive materials.

[0061] Optionally, the second encapsulation layer 2 in the present application may be a plastic encapsulation dielectric layer. It may be made of any suitable plastic encapsulation material. For example, it includes but is not limited to at least one of epoxy molding compound (EMC), polyimide (PI) material, etc. The second encapsulation layer 2 in the form of a plastic encapsulation dielectric layer has good performance, is easy to manufacture, and has low process complexity.

[0062] Optionally, step S104 in the present application may be implemented by a manufacturing process different from that of step S102. For example, the wafer-level manufacturing process is used in step S102, but step S104 may not use the wafer-level manufacturing process.

[0063] The specific implementation of step S104 is not limited in this application. Figure 4 As shown in the flowchart, step S104 includes steps S1042, S1044, S1046 and S1048, specifically:

[0064] S1042: forming a conductive component on the second pad layer exposed from the second side of the first packaging layer, and forming a first molding dielectric layer exposing the conductive component on the second side of the first packaging layer.

[0065] The first plastic sealing dielectric layer 201 in the present application can be made of any plastic sealing material. Optionally, the material of the first plastic sealing dielectric layer 201 can be epoxy molding compound (Epoxy Molding Compound, EMC). EMC material has low cost, convenient plastic sealing operation, high production efficiency, good high temperature resistance, good electrical insulation, and good heat dissipation performance, and can effectively meet the plastic sealing performance requirements. And EMC material can also meet the needs of making circuits. Optionally, the first plastic sealing dielectric layer 201 can also select polyimide (Polyimide, PI) material. Alternatively, other materials that can meet the needs can also be used.

[0066] Optionally, the first molding medium layer 201 may be made by an injection molding process using an injection mold, and the injection molding process may include but is not limited to a C-mold injection molding process or a T-mold injection molding process.

[0067] The conductive components in the present application can be made of any conductive material, for example, a metal material, including but not limited to at least one of titanium, copper, aluminum, silver, etc. (single metal or multi-metal stack), or an alloy of at least two.

[0068] Optionally, a conductive component may be formed on the second pad layer 13 exposed from the second side of the first packaging layer 1 by at least one of a sputtering process, an evaporation process, and an electroplating process. By forming the conductive component in such a process, the formed conductive component can be electrically connected to the second pad layer 13 without soldering, thereby avoiding the disadvantage of unstable packaging structure caused by soldering, thereby improving the reliability of the chip packaging module and effectively reducing the packaging cost.

[0069] The specific structure of the conductive component is not limited in the present application. For example, optionally, the second pad layer 13 includes a plurality of second pads 131, the third pad layer 21 includes a plurality of third pads 211, and the conductive component may include a plurality of conductive blocks 4. In some optional embodiments, such as Figure 5 As shown in the flowchart, the above step S1042 includes steps S1042A and S1042B, specifically:

[0070] S1042A: forming a plurality of conductive blocks 4 on the plurality of second pads 131 of the second pad layer 13 correspondingly, such that ends of the conductive blocks 4 away from the second pads 131 extend beyond the second side of the first packaging layer 1 .

[0071] For example, you can combine Figure 6b to understand the relevant contents of step S1042A.

[0072] Optionally, the end of the conductive block 4 away from the second pad 131 exceeds the second side of the first packaging layer 1 by 5 um to 100 um. Figure 6b As shown, Figure 6b H1 in the figure shows the excess distance between the end of the conductive block 4 away from the second pad 131 and the second side of the first packaging layer 1, 5um≤H1≤100um. This range is conducive to ensuring that the subsequent conductive block 4 is stably electrically connected to the prepared third pad 211, so that the second pad 131 can be electrically connected to the third pad 211 through the conductive block 4. Of course, a specific value can be selected as needed. In some examples, for example, H1 can be 5um, 10um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, etc.

[0073] The plurality of conductive blocks 4 may be formed in any manner. For example, some feasible implementations may be to form a whole metal layer on the second side of the first packaging layer 1 by at least one of a sputtering process, an evaporation process, an electroplating process, and the like, and to form the metal layer on the plurality of second pads 131, and then to etch the metal layer to retain the required portion of the metal layer connected to the second pads 131 to form the conductive blocks 4. In other embodiments, the metal layer may also be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like.

[0074] Optionally, the conductive block 4 may be made of at least one of titanium, copper, aluminum, silver, etc. (single metal or multi-metal laminate), or an alloy of at least two of them. For example, taking a single metal as an example, the conductive block 4 may be a copper block. For example, taking a multi-metal laminate as an example, the conductive block 4 may be a titanium-copper metal laminate. For example, taking an alloy as an example, the conductive block 4 may be a titanium-copper alloy.

[0075] S1042B: forming a first molding dielectric layer 201 covering the plurality of conductive blocks 4 on the second side of the first packaging layer 1 , and grinding the first molding dielectric layer 201 so that the first molding dielectric layer 201 exposes at least a portion of the plurality of conductive blocks 4 .

[0076] For example, you can combine Figure 6c and Figure 6d to understand the relevant contents of step S1042B.

[0077] Optionally, the prepared chip packaging module structure (including the wafer 10, the first packaging layer 1, the conductive blocks 4, etc.) can be placed as a whole in the mold cavity of a wafer-level or panel-level injection mold, and then a plastic packaging material (such as EMC plastic, etc.) is used for injection molding (such as C-mold or T-mold injection molding process, etc.) to obtain a first plastic packaging dielectric layer 201 covering the second side of the first packaging layer 1 and the plurality of conductive blocks 4. In this way, the plurality of conductive blocks 4 can be covered by the first plastic packaging dielectric layer 201.

[0078] Afterwards, the surface of the first plastic encapsulation dielectric layer 201 away from the second pad 131 may be ground, so that the ground first plastic encapsulation dielectric layer 201 exposes at least part of the plurality of conductive blocks 4. The grinding process here may be to grind the first plastic encapsulation dielectric layer 201 while grinding part of the conductive blocks 4, or may not grind the conductive blocks 4, and the operation may be performed according to actual conditions.

[0079] Based on this, in the present application, through the optional implementation of the above steps S1042A~S1042B, the first plastic encapsulation dielectric layer 201 and the conductive components including multiple conductive blocks 4 can be effectively prepared, and the multiple conductive blocks 4 can be effectively exposed through the first plastic encapsulation dielectric layer 201 to facilitate the subsequent preparation of multiple third pads 211 of the third pad layer 21, so as to facilitate the electrical connection of the second pad layer 13 and the third pad layer 21 through the conductive blocks 4.

[0080] S1044: forming a third pad layer connected to the exposed conductive component on the first plastic encapsulation dielectric layer, so that the third pad layer is electrically connected to the second pad layer through the conductive component.

[0081] For example, you can combine Figure 6e The schematic diagram can be used to understand the relevant content of step S1044.

[0082] The third pad layer 21 may be made of at least one of copper and aluminum, or may be made of other metal materials or other feasible conductive materials.

[0083] The specific implementation of step S1044 is not limited in the present application. For example, based on the optional embodiments of steps S1042A to S1042B above, the third pad layer 21 may include a plurality of third pads 211, and the plurality of conductive blocks 4 may be used to electrically connect the plurality of second pads 131 and the plurality of third pads 211 correspondingly. Optionally, step S1044 includes: correspondingly forming a plurality of third pads 211 of the third pad layer 21 on the exposed plurality of conductive blocks 4, so that the plurality of third pads 211 of the third pad layer 21 are electrically connected to the plurality of second pads 131 of the second pad layer 13 through the plurality of conductive blocks 4, respectively.

[0084] The plurality of third pads 211 may be formed in any manner. For example, some feasible implementations may be to form a whole metal layer on the side of the first plastic encapsulation dielectric layer 201 where the conductive blocks 4 are exposed by at least one of a sputtering process, an evaporation process, an electroplating process, etc., and to form the metal layer on the plurality of conductive blocks 4, and then to etch the metal layer to retain the required portion of the metal layer connected to the conductive blocks 4 to form the third pads 211. In other embodiments, the metal layer may also be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0085] It should be understood that in the above optional scheme, the third pad 211 can be directly formed on the conductive block 4, and the conductive block 4 is also directly formed on the second pad 131, so that when the third pad 211 forms an electrical connection with the second pad 131 through the conductive block 4, there is no need to use solder while ensuring the stability of the electrical connection. Therefore, the disadvantage of unstable packaging structure caused by soldering can be avoided, thereby improving the reliability of the chip packaging module and effectively reducing the packaging cost.

[0086] S1046: forming multiple layers of second molding dielectric layers on the first molding dielectric layer in sequence, and forming a second circuit layer between every two adjacent second molding dielectric layers, and electrically connecting the third pad layer and the obtained at least one second circuit layer layer by layer.

[0087] For example, you can combine Figure 6f The schematic diagram can be used to understand the relevant content of step S1046.

[0088] The second molding dielectric layer 202 in the present application can be made of any molding material. Optionally, the material of the second molding dielectric layer 202 can be epoxy molding compound (EMC). Optionally, the second molding dielectric layer 202 can also be made of polyimide (PI). Alternatively, other materials that can meet the requirements can also be used.

[0089] Optionally, the second molding medium layer 202 may be made by an injection molding process using an injection mold, and the injection molding process may include, but is not limited to, a C-mold injection molding process or a T-mold injection molding process.

[0090] In the present application, a second circuit layer 22 is formed between every two adjacent second plastic encapsulation dielectric layers 202, and the preparation can be carried out in a positional order. For example, the first second plastic encapsulation dielectric layer 202 is prepared first, then the second circuit layer 22 is prepared, and then the second second plastic encapsulation dielectric layer 202 is prepared. Other situations can be deduced in this way.

[0091] Optionally, the third pad layer 21 and the obtained at least one second circuit layer 22 are electrically connected layer by layer, which can be achieved by providing an electrical connection structure between two adjacent layers. The electrical connection structure is not specifically limited here.

[0092] S1048: forming a second encapsulation layer based on the first molding medium layer and the multiple second molding medium layers.

[0093] After the first molding medium layer 201 and the multi-layer second molding medium layer 202 are prepared, the first molding medium layer 201 and the multi-layer second molding medium layer 202 can be used as part of the second packaging layer 2, so as to facilitate the formation of the second packaging layer 2. Figure 6g to understand with examples.

[0094] For example, in some cases, the second encapsulation layer 2 may be composed of the first encapsulation dielectric layer 201 and the multi-layer second encapsulation dielectric layer 202. For another example, in other cases, the second encapsulation layer 2 may be composed of the first encapsulation dielectric layer 201, the multi-layer second encapsulation dielectric layer 202 and other encapsulation structure layers (such as the third encapsulation dielectric layer 203 described below). Figure 6g It can be set as needed and is not specifically limited here.

[0095] Based on this, through the optional implementation of the above steps S1042 to S1048, on the one hand, a second packaging layer 2 embedded with a third pad layer 21 and at least one second circuit layer 22 with layer-by-layer electrical connection can be effectively prepared, and the electrical connection of multiple third pads 211 of the third pad layer 21 with multiple second pads 131 of the second pad layer 13 can be effectively ensured; on the other hand, the above optional technical scheme is the sequential superposition of the preparation processes of multiple second pads 131, multiple conductive blocks 4, and multiple third pads 211, so that the electrical connection between the multiple second pads 131 and the multiple conductive blocks 4, and the electrical connection between the multiple conductive blocks 4 and the multiple third pads 211 are more stable, the electrical connection performance is better, and the electrical connection can be formed without relying on solder, so that the solder interface between the first packaging layer 1 and the second packaging layer 2 can be avoided, thereby avoiding the disadvantage of unstable packaging structure caused by soldering, thereby improving the reliability of the chip packaging module and effectively reducing the packaging cost.

[0096] In some optional embodiments, the first molding medium layer 201 and the second molding medium layer 202 may be formed of the same molding material, thereby making the overall structure and properties of the formed second packaging layer 2 more uniform and the packaging stability better.

[0097] For example, the first molding dielectric layer 201 and the second molding dielectric layer 202 can both be made of epoxy resin molding compound (EMC plastic) so that the second packaging layer 2 has better overall high temperature resistance, better electrical insulation, better heat dissipation performance, and better molding performance.

[0098] It is understandable that the second circuit layer 22 embedded in the second packaging layer 2 to be formed in the present application may be one layer or multiple layers. Regarding steps S1046 and S1048, several optional embodiments for different situations will be described below.

[0099] In some optional embodiments, if the second packaging layer 2 to be formed is embedded with a second circuit layer 22, then: step S1046 may include steps S1046A2 to S1046A4, specifically:

[0100] S1046A2: At least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding dielectric layer 202 is formed on the first molding dielectric layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21, and the first second molding dielectric layer 202 is ground so that the first second molding dielectric layer 202 exposes the electrical connection block 24 formed on the third pad layer 21.

[0101] Therefore, through step S1046A2, the first second plastic encapsulation medium layer 202 can be prepared first.

[0102] In the present application, the electrical connection block 24 is used to electrically connect two adjacent layers of structures. According to actual circuit design requirements, a suitable number of electrical connection blocks 24 can be formed at suitable positions on the third pad layer 21 (for example, on any one or more third pads 211) to electrically connect the third pad layer 21 with the adjacent second circuit layer 22 in the subsequent process.

[0103] The electrical connection block 24 may be formed in any manner. For example, in some feasible implementations, a whole metal layer may be formed on the third pad layer 21 by at least one of a sputtering process, an evaporation process, an electroplating process, and the like, and then the metal layer is etched to retain some required portions of the metal layer to form the electrical connection block 24, and the retained electrical connection block 24 is electrically connected to at least one third pad 211 of the third pad layer 21. In other embodiments, the metal layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like.

[0104] Optionally, the chip packaging module structure prepared up to this step can be placed as a whole in the mold cavity of a wafer-level or panel-level injection mold, and then a plastic material (such as EMC plastic, etc.) is used for injection molding (such as C-mold or T-mold injection molding process, etc.) to obtain a first second plastic packaging medium layer 202 that covers the side of the first plastic packaging medium layer 201 away from the first packaging layer 1. In this way, the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21 can also be covered by the first second plastic packaging medium layer 202.

[0105] Afterwards, the surface of the first second plastic encapsulation dielectric layer 202 away from the third pad layer 21 may be ground, so that the ground first second plastic encapsulation dielectric layer 202 exposes the electrical connection block 24 formed on the third pad layer 21. The grinding process here may be to grind the second plastic encapsulation dielectric layer 202 while grinding a portion of the electrical connection block 24, or may not grind the electrical connection block 24, and the operation may be performed according to actual conditions.

[0106] S1046A4: On the first second molding dielectric layer 202, a first second circuit layer 22 electrically connected to the electrical connection block 24 formed on the third pad layer 21 is formed, and a second second molding dielectric layer 202 covering the first second circuit layer 22 is formed.

[0107] Therefore, through step S1046A4, the first second circuit layer 22 and the second second plastic encapsulation dielectric layer 202 can be prepared in sequence.

[0108] The second circuit layer 22 may be formed in any manner. For example, some feasible implementations may be to form a whole metal layer on the first second plastic encapsulation dielectric layer 202 by at least one of a sputtering process, an evaporation process, an electroplating process, etc., and then to etch the metal layer to retain some required parts of the metal layer to form the first second circuit layer 22, and the retained first second circuit layer 22 is electrically connected to the electrical connection block 24 formed on the third pad layer 21. In other embodiments, the metal layer may also be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0109] Optionally, the second circuit layer 22 may be made of at least one of copper and aluminum, or may be made of other metal materials or other feasible conductive materials.

[0110] Afterwards, the chip packaging module structure prepared up to this step can be placed as a whole in the mold cavity of a wafer-level or panel-level injection mold, and then a plastic encapsulation material (such as EMC plastic, etc.) is used for injection molding (such as C-mold or T-mold injection molding process, etc.) to obtain a second layer of second plastic encapsulation dielectric layer 202 covering the first layer of second circuit layer 22.

[0111] Based on this, the present application includes the above-mentioned steps S1046A2 to S1046A4, which can effectively form multiple layers of second molding dielectric layers 202 on the first molding dielectric layer 201 in sequence, and effectively form a second circuit layer 22 between every two adjacent second molding dielectric layers 202, and make the third pad layer 21 and the at least one second circuit layer 22 obtained electrically connected layer by layer, thereby facilitating the preparation of the second packaging layer 2.

[0112] Optionally, based on steps S1046A2 to S1046A4, in step S1048, the second encapsulation layer 2 may be formed by the first molding medium layer 201 and two second molding medium layers 202. This situation may be suitable for situations where the fourth pad layer 23 (described below) is not required.

[0113] In some optional embodiments, the chip packaging scheme of the embodiment of the present application may also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can meet the need for wiring the second packaging layer 2 with other external circuit structures. Optionally, step S1046A4 may include: forming a first layer of second circuit layer 22 electrically connected to the electrical connection block 24 formed on the third pad layer 21 on the first layer of second plastic encapsulation dielectric layer 202, forming at least one electrical connection block 24 on the first layer of second circuit layer 22, and forming a second layer of second plastic encapsulation dielectric layer 202 covering the first layer of second circuit layer 22 and the electrical connection block 24 formed on the first layer of second circuit layer 22. The chip packaging method of the present application also includes: grinding the second second molding dielectric layer 202 so that the second second molding dielectric layer 202 exposes the electrical connection block 24 formed on the first second circuit layer 22; forming a fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the first second circuit layer 22 on the formed second second molding dielectric layer 202, and forming a third molding dielectric layer 203 covering the fourth pad layer 23, and opening the third molding dielectric layer 203 to expose at least part of the fourth pad layer 23 through the opening. On this basis, step S1048 may include: forming a second packaging layer 2 based on the first molding dielectric layer 201, the multiple second molding dielectric layers 202 and the third molding dielectric layer 203.

[0114] Based on this, through the above-mentioned optional embodiments, a fourth pad layer 23 electrically connected to the second circuit layer 22 can be embedded in the obtained second packaging layer 2, and at least a portion of the fourth pad layer 23 can be exposed through an opening, so that the connecting circuit can be exposed from the other side of the module for easy connection, so as to meet the requirement of electrically connecting the packaged chip packaging module 100 with other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23, and realize double-sided electrical connection of the circuits in the chip packaging module (that is, the packaged circuits are electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0115] Optionally, an opening is provided in the third plastic encapsulation dielectric layer 203, which may be an opening on a side of the third plastic encapsulation dielectric layer 203 away from the first packaging layer 1, so that the fourth pad layer 23 is exposed from this side through the opening, which can meet the need for electrical connection with other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) on the side of the second packaging layer 2 away from the first packaging layer 1, and can achieve double-sided electrical connection of the circuits in the chip packaging module, so as to facilitate the use of the chip packaging module 100.

[0116] It should be understood that the electrical connection block 24 and its optional formation method, grinding treatment, etc. have been explained in the previous text, which can be understood by referring to the previous text, and similar content will not be repeated here.

[0117] Optionally, the fourth pad layer 23 may include a plurality of fourth pads 231, and the number may be set according to actual needs. The fourth pad layer 23 is electrically connected to the second circuit layer 22, which may mean that at least part of the fourth pads 231 of the fourth pad layer 23 is electrically connected to at least part of the circuits in the second circuit layer 22. The electrical connection block 24 formed on the second circuit layer 22 may be designed as one or more as needed, and the specific connection position may also be set as needed, without any limitation here.

[0118] The third plastic encapsulation dielectric layer 203 in the present application can be made of any plastic encapsulation material. Optionally, the material of the third plastic encapsulation dielectric layer 203 can be epoxy molding compound (EMC). Optionally, the third plastic encapsulation dielectric layer 203 can also be made of polyimide (PI). Alternatively, other materials that can meet the requirements can also be used.

[0119] Optionally, the third molding medium layer 203 may be made by an injection molding process using an injection mold, and the injection molding process may include, but is not limited to, a C-mold injection molding process or a T-mold injection molding process.

[0120] Optionally, the third plastic sealing dielectric layer 203 and the first plastic sealing dielectric layer 201 and the second plastic sealing dielectric layer 202 can be formed by the same plastic sealing material. Thus, the overall structure and properties of the formed second encapsulation layer 2 can be more uniform, and the encapsulation stability is also better. For example, the first plastic sealing dielectric layer 201, the second plastic sealing dielectric layer 202, and the third plastic sealing dielectric layer 203 can all be made of epoxy resin molding compound (EMC plastic), so that the second encapsulation layer 2 has better overall high temperature resistance, better electrical insulation, better heat dissipation performance, and better plastic sealing performance.

[0121] For example, after the electrical connection block 24 is formed on the first second circuit layer 22, the chip packaging module structure prepared up to this step can be placed as a whole in the mold cavity of a wafer-level or panel-level injection mold, and then a plastic encapsulation material (such as EMC plastic, etc.) is used for injection molding (such as C-mold or T-mold injection molding process, etc.) to obtain a second second plastic encapsulation dielectric layer 202 that covers the first second circuit layer 22 and the electrical connection block 24 formed thereon. Afterwards, the surface of the second second plastic encapsulation dielectric layer 202 away from the first packaging layer 1 can be ground, so that the second second plastic encapsulation dielectric layer 202 after grinding exposes the electrical connection block 24 formed on the first second circuit layer 22. The grinding process here can be to grind the second plastic encapsulation dielectric layer 202 while grinding a part of the electrical connection block 24, or it can be not to grind the electrical connection block 24, and it can be operated according to the actual situation. After the electrical connection block 24 formed on the first layer of the second circuit layer 22 is exposed, the chip packaging module structure prepared up to this step can be placed in the mold cavity of a wafer-level or panel-level injection mold, and then a plastic material (such as EMC plastic, etc.) is used for injection molding (such as C-mold or T-mold injection molding process, etc.) to obtain the third plastic sealing medium layer 203. Afterwards, the third plastic sealing medium layer 203 can be opened by any physical or chemical process to expose the fourth pad layer 23. It should be understood that the above process is only an example and is not intended to limit the embodiments of the present application.

[0122] In some other optional embodiments, if the second packaging layer 2 to be formed is embedded with two second circuit layers 22, then: step S1046 may include steps S1046B2 to S1046B6, specifically:

[0123] S1046B2: At least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding dielectric layer 202 is formed on the first molding dielectric layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21, and the first second molding dielectric layer 202 is ground so that the first second molding dielectric layer 202 exposes the electrical connection block 24 formed on the third pad layer 21.

[0124] Thus, through step S1046B2, the first second plastic encapsulation medium layer 202 can be prepared. Step S1061B2 can be understood by referring to step S1046A2, and the two are similar, so they will not be described again here.

[0125] S1046B4: On the first layer of the second molding dielectric layer 202, a first layer of the second circuit layer 22 electrically connected to the electrical connection block 24 formed on the third pad layer 24 is formed, at least one electrical connection block 24 is formed on the first layer of the second circuit layer 22, and a second layer of the second molding dielectric layer 202 covering the first layer of the second circuit layer 22 and the electrical connection block 24 formed on the first layer of the second circuit layer 22 is formed, and then the second layer of the second molding dielectric layer 202 is ground so that the second layer of the second molding dielectric layer 202 exposes the electrical connection block 24 formed on the first layer of the second circuit layer 22.

[0126] Therefore, through step S1046B4, the first second circuit layer 22 and the second second plastic encapsulation dielectric layer 202 can be prepared in sequence.

[0127] S1046B6: On the second layer of the second molding dielectric layer 202, a second layer of the second circuit layer 22 is formed which is electrically connected to the electrical connection block 24 formed on the first layer of the second circuit layer 22, and a third layer of the second molding dielectric layer 202 is formed which covers the second layer of the second circuit layer 22, thereby obtaining a total of 2 layers of the second circuit layer 22 and 3 layers of the second molding dielectric layer 202.

[0128] Thus, through step S1046B6, the second second circuit layer 22 and the third second molding dielectric layer 202 can be prepared successively, so that two second circuit layers 22 and three second molding dielectric layers 202 can be obtained in total.

[0129] Based on this, the present application includes the above-mentioned steps S1046B2 to S1046B6, which can effectively form multiple layers of second molding dielectric layers 202 on the first molding dielectric layer 201 in sequence, and effectively form a second circuit layer 22 between every two adjacent second molding dielectric layers 202, and make the third pad layer 21 and the at least one second circuit layer 22 obtained electrically connected layer by layer, thereby facilitating the preparation of the second packaging layer 2.

[0130] Optionally, based on steps S1046B2 to S1046B6, in step S1048, the second encapsulation layer 2 may be formed by the first molding medium layer 201 and three second molding medium layers 202. This situation may be suitable for situations where the fourth pad layer 23 (described below) is not required.

[0131] In some optional embodiments, the chip packaging scheme of the embodiment of the present application may also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can meet the need for wiring the second packaging layer 2 with other external circuit structures. Optionally, step S1046B6 may include: forming a second layer of second circuit layer 22 on the second layer of second plastic encapsulation dielectric layer 202, which is electrically connected to the electrical connection block 24 formed on the first layer of second circuit layer 22, forming at least one electrical connection block 24 on the second layer of second circuit layer 22, and forming a third layer of second plastic encapsulation dielectric layer 202 that covers the second layer of second circuit layer 22 and the electrical connection block 24 formed on the second layer of second circuit layer 22. The chip packaging method of the present application also includes: grinding the third second molding medium layer 202 so that the third second molding medium layer 202 exposes the electrical connection block 24 formed on the second second circuit layer 22; forming a fourth pad layer electrically connected to the electrical connection block 24 formed on the second second circuit layer 22 on the formed third second molding medium layer 202, and forming a third molding medium layer 203 covering the fourth pad layer 23, and opening the third molding medium layer 203 to expose at least part of the fourth pad layer 23 through the opening. On this basis, step S1048 may include: forming a second packaging layer 2 based on the first molding medium layer 201, the third second molding medium layer 202 and the third molding medium layer 203.

[0132] Based on this, through the above-mentioned optional embodiments, a fourth pad layer 23 electrically connected to the second circuit layer 22 of the second layer can be embedded in the obtained second packaging layer 2, and at least a portion of the fourth pad layer 23 can be exposed through an opening, so that the connecting circuit can be exposed from the other side of the module for easy connection, so as to meet the requirement of electrically connecting the packaged chip packaging module 100 with other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23, and realize double-sided electrical connection of the circuits in the chip packaging module (that is, the packaged circuits can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0133] It should be understood that similar explanations have been given above regarding the third plastic encapsulation dielectric layer 203 and the fourth pad 231 , and can be understood by referring to the above contents, and similar contents will not be repeated here.

[0134] In some further optional embodiments, if the second packaging layer 2 to be formed is embedded with n layers of second circuit layers 22, n≥3, then: S1046 may include steps S1046C2 to S1046C8, specifically:

[0135] S1046C2: at least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding dielectric layer 202 is formed on the first molding dielectric layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21, and the first second molding dielectric layer 202 is ground so that the first second molding dielectric layer 202 exposes the electrical connection block 24 formed on the third pad layer 21.

[0136] Thus, through step S1046C2, the first second plastic encapsulation medium layer 202 can be prepared. Step S1061C2 can be understood by referring to step S1046A2, and the two are similar, so they will not be described again here.

[0137] S1046C4: On the first layer of the second molding dielectric layer 202, a first layer of the second circuit layer 22 electrically connected to the electrical connection block 24 formed on the third pad layer 21 is formed, at least one electrical connection block 24 is formed on the first layer of the second circuit layer 22, and a second layer of the second molding dielectric layer 202 is formed to cover the first layer of the second circuit layer 22 and the electrical connection block 24 formed on the first layer of the second circuit layer 22, and then the second layer of the second molding dielectric layer 202 is ground so that the second layer of the second molding dielectric layer 202 exposes the electrical connection block 24 formed on the first layer of the second circuit layer 22.

[0138] Therefore, through step S1046C4, the first second circuit layer 22 and the second second plastic encapsulation dielectric layer 202 can be prepared in sequence.

[0139] S1046C6: Repeat the following steps in sequence to obtain the 2nd to n-1st second circuit layers 22 and the 3rd to nth second plastic sealing dielectric layers 202: "On the i-th second plastic sealing dielectric layer 202, form the i-th second circuit layer 22 electrically connected to the electrical connection block 24 formed on the i-1st second circuit layer 22, form at least one electrical connection block 24 on the i-th second circuit layer 22, and form the i+1st second plastic sealing dielectric layer 202 covering the i-th second circuit layer 22 and the electrical connection block 24 formed on the i-th second circuit layer 22, and then grind the i+1st second plastic sealing dielectric layer 202 so that the i+1st second plastic sealing dielectric layer 202 exposes the electrical connection block 24 formed on the i-th second circuit layer 22, 2≤i≤n-1".

[0140] Thus, through step S1046C6, the second circuit layer 22, the third second plastic encapsulation dielectric layer 202, the third second circuit layer 22, the fourth second plastic encapsulation dielectric layer 202, ..., the n-1th second circuit layer 22, and the nth second plastic encapsulation dielectric layer 202 can be prepared in sequence.

[0141] S1046C8: On the nth second molding dielectric layer 202, an nth second circuit layer 22 electrically connected to the electrical connection block 24 formed on the n-1th second circuit layer 22 is formed, and an n+1th second molding dielectric layer 202 covering the nth second circuit layer 22 is formed, thereby obtaining a total of n second circuit layers 22 and n+1 second molding dielectric layers 202.

[0142] Thus, through step S1046C8, the nth second circuit layer 22 and the n+1th second molding dielectric layer 202 can be prepared successively, so that n second circuit layers 22 and n+1 second molding dielectric layer 202 can be obtained in total.

[0143] Based on this, the present application includes the above-mentioned steps S1046C2 to S1046C8, which can effectively form multiple layers of second molding dielectric layers 202 on the first molding dielectric layer 201 in sequence, and effectively form a second circuit layer 22 between every two adjacent second molding dielectric layers 202, and make the third pad layer 21 and the at least one second circuit layer 22 obtained electrically connected layer by layer, thereby facilitating the preparation of the second packaging layer 2.

[0144] Optionally, based on steps S1046C2 to S1046C8, in step S1048, the second encapsulation layer 2 may be formed by the first molding dielectric layer 201 and the n+1 second molding dielectric layer 202. This situation may be suitable for situations where the fourth pad layer 23 (described below) is not required.

[0145] In some optional embodiments, the chip packaging scheme of the embodiment of the present application may also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can meet the need for wiring the second packaging layer 2 with other external circuit structures. Optionally, step S1046C8 may include: forming an n-th second circuit layer 22 electrically connected to the electrical connection block 24 formed on the n-1-th second circuit layer 22 on the n-th second plastic encapsulation dielectric layer 202, forming at least one electrical connection block 24 on the n-th second circuit layer 22, and forming an n+1-th second plastic encapsulation dielectric layer 202 covering the n-th second circuit layer 22 and the electrical connection block 24 formed on the n-th second circuit layer 22. The chip packaging method of the present application also includes: grinding the n+1-th second molding dielectric layer 202 so that the n+1-th second molding dielectric layer 202 exposes the electrical connection block 24 formed on the n-th second circuit layer 22; forming a fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the n-th second circuit layer 22 on the formed n+1-th second molding dielectric layer 202, and forming a third molding dielectric layer 203 covering the fourth pad layer 23, and opening the third molding dielectric layer 203 to expose at least part of the fourth pad layer 23 through the opening. On this basis, step S1048 may include: forming a second packaging layer 2 based on the first molding dielectric layer 201, the multiple second molding dielectric layers 202 and the third molding dielectric layer 203.

[0146] Based on this, through the above-mentioned optional embodiments, a fourth pad layer 23 electrically connected to the nth second circuit layer 22 can be embedded in the obtained second packaging layer 2, and at least a portion of the fourth pad layer 23 can be exposed through an opening, so that the connecting circuit can be exposed from the other side of the module for easy connection, so as to meet the requirement of electrically connecting the packaged chip packaging module 100 with other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23, and realize double-sided electrical connection of the circuits in the chip packaging module (that is, the packaged circuits can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0147] It should be understood that similar explanations have been given above regarding the third plastic encapsulation dielectric layer 203 and the fourth pad 231 , and can be understood by referring to the above contents, and similar contents will not be repeated here.

[0148] For example, you can combine Figure 6g For understanding, take an example, in which n=3, 3 second circuit layers and 4 second plastic encapsulation dielectric layers 202 are prepared, and 1 third plastic encapsulation dielectric layer 203 is prepared, thus forming a second packaging layer 2 including 1 first plastic encapsulation dielectric layer 201, 4 second plastic encapsulation dielectric layers 202 and 1 third plastic encapsulation dielectric layer 203.

[0149] Optionally, the thickness of the second encapsulation layer 2 formed in the present application may be in the range of 200um to 500um, so that the second encapsulation layer 2 has good structural stability and is also convenient for the implementation of subsequent steps. Figure 6g H2 in the figure shows the thickness of the second encapsulation layer 2, 200um≤H2≤500um. Within the above range, it can be selected as needed, such as 200um, 250um, 300um, 350um, 400um, 450um, 500um, etc.

[0150] It should be understood that Figure 2 It is understood that in the first packaging layer 1 and the second packaging layer 2 obtained through the above steps, the first packaging layer 1 can be regarded as a silicon interposer, and does not need to rely on the through silicon via process, and the second packaging layer 2 can be regarded as a packaging substrate. Figure 1 The CoWoS technology solutions shown have significant differences.

[0151] Optionally, as mentioned above in the present application, the second encapsulation layer 2 (which may include the first plastic encapsulation dielectric layer 201 and the second plastic encapsulation dielectric layer 202, and may further include the third plastic encapsulation dielectric layer 203) may be made of EMC material, which is beneficial to making the warping of the second encapsulation layer 2 of the chip encapsulation module 100 more balanced, with better mechanical strength and better heat dissipation performance. In addition, the second encapsulation layer 2 can be used as the insulating layer of the second circuit layer 22 using EMC material, and the insulation effect is better. Moreover, the use of EMC material makes it easier for this solution to use wafer-level / panel-level packaging technology, which is convenient for realizing wafer-level or panel-level circuit integration. By adding this feature, it is also convenient to remove the wafer 10 in the subsequent step S106.

[0152] It should be noted that the thickness of any two layers among the first plastic encapsulation dielectric layer 201, the multi-layer second plastic encapsulation dielectric layer 202, and the third plastic encapsulation dielectric layer 203 can be the same, or can be different, and can be designed as needed. In the present application, the thickness of the second encapsulation layer 2 can be the same as or different from the thickness of the first encapsulation layer 1, and can be selected as needed.

[0153] S106: At least partially remove the wafer in contact with the first side of the first packaging layer to expose the first pad layer, and electrically connect the chip to the first pad layer to obtain a chip packaging module.

[0154] When understanding the relevant content of step S106, you can also combine Figure 6h to Figure 6i Schematic diagram for understanding.

[0155] The wafer 10 may be completely removed, or only a portion of the wafer 10 on the plurality of first pads 111 of the first pad layer 11 may be removed so as to expose the plurality of first pads 111 of the first pad layer 11 .

[0156] Optionally, the chip 3 may be electrically connected to the first pad layer 11 by soldering to obtain a chip packaging module 100 .

[0157] Optionally, when actually implementing step S106, for ease of operation, the semi-finished product obtained in step S104 may be turned over, and the wafer 10 may be further processed (eg, Figure 6h and its example description). For example, a grinding and polishing process can be used to remove the wafer 10 (the wafer 10 can be completely removed, or only a portion of the wafer 10 can be removed). Taking the wafer 10 as a silicon wafer as an example, since the material of the silicon wafer and the material of the first packaging layer 1 (such as SiO2) are different, the wafer 10 can be easily removed with the assistance of processes such as grinding, corrosion, chemical mechanical polishing (CMP), dry etching, etc.

[0158] Optionally, the thickness of the second packaging layer 2 can be in the range of 200um to 500um, so that the thickness rigidity can support the first packaging layer 1 between the second packaging layer 2 and the wafer 10, thereby facilitating the step of removing the wafer 10 and ensuring structural stability.

[0159] For example, refer to Figure 2 or Figure 6h As shown, an example is shown in which the wafer 10 is completely removed and multiple first pads 111 of the first pad layer 11 are exposed. It can be seen that the first packaging layer 1 and the second packaging layer are well combined, and the first circuit layer 12 embedded in the first packaging layer 1 retains a high-density interconnection circuit with a line width of less than 2um. In this optional example, the first packaging layer 1 can be regarded as a silicon interposer, and does not need to rely on the silicon through-hole process. The second packaging layer 2 can be regarded as a packaging substrate. It can also be seen that the first packaging layer 1 and the second packaging layer 2 are sequentially superimposed on the manufacturing process. The second pad layer 13 of the first packaging layer 1 and the third pad layer 21 of the second packaging layer 2 do not rely on solder for electrical connection. Therefore, there is no solder interface between the first packaging layer 1 and the second packaging layer 2, so it can have considerable benefits for the packaging process, which can not only save process costs, but also improve the reliability of the chip packaging module 100 obtained by packaging.

[0160] Based on this, based on the technical scheme of the above steps S102 to S106 in the embodiment of the present application, a first packaging layer embedded with a first pad layer electrically connected layer by layer, at least one first circuit layer and a second pad layer can be formed on a wafer, the first packaging layer includes a first side and a second side opposite to each other in the thickness direction, the first side of the first packaging layer contacts the wafer, the first pad layer is formed on the first side of the first packaging layer, the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer, the line width of the line in the first circuit layer is less than or equal to 2um, and then on the second side of the first packaging layer, a second packaging layer embedded with a third pad layer electrically connected layer by layer and at least one second circuit layer is formed, the third pad layer is electrically connected to the second pad layer, the minimum line width of the line in the second circuit layer is greater than the minimum line width of the line in the first circuit layer, and then the wafer in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to effectively obtain a chip packaging module. Therefore, through the above technical scheme, on the one hand, the present application does not need to use the through silicon via (TSV) process, and can effectively realize chip packaging and effectively obtain the chip packaging module, thereby reducing the manufacturing cost, and compared with the related technical scheme using the through silicon via process, effectively reducing the process complexity; on the other hand, using the technical scheme of the present application, the line width of the line in the first circuit layer is set to be less than or equal to 2um, and the minimum line width of the line in the second circuit layer is made larger than the minimum line width of the line in the first circuit layer, so that the line width of the line in the first circuit layer can be ensured to be small, which is convenient for realizing high-density lines and interconnections, and is beneficial to improving the integration of the chip packaging module; on the other hand, since the chip packaging scheme is to electrically connect the chip to the first pad layer after the first packaging layer and the second packaging layer are manufactured and connected, compared with the situation where the chip is electrically connected to the first pad layer first, it is beneficial to avoid the situation where the chip is scrapped together due to damage to any one of the first packaging layer and the second packaging layer, thereby helping to further reduce the process cost and ensure the yield of the chip packaging module finally obtained.

[0161] In some optional embodiments, a first shape dimension of the first encapsulation layer 1 in a direction perpendicular to its thickness is the same as a second shape dimension of the second encapsulation layer 2 in a direction perpendicular to its thickness.

[0162] As a result, the shape and size of the first encapsulation layer 1 and the second encapsulation layer 2 in the direction perpendicular to the thickness can be equal. For example, taking the first encapsulation layer 1 and the second encapsulation layer 2 as both or approximately rectangular parallelepiped shapes, the shape and size perpendicular to the thickness direction can also be considered as the shape and size in the length and width directions. Assuming that the thickness is Z, the length is X, and the width is Y, the first shape and size and the second shape and size can be the same as the XY size of the first encapsulation layer 1 and the XY size of the second encapsulation layer 2. For example, to give an example that is easy to understand, the first shape and size of the first encapsulation layer 1 can be a rectangular shape with a length × width of 5mm × 5mm, and the second shape and size of the second encapsulation layer 2 can also be a rectangular shape with a length × width of 5mm × 5mm, and the first shape and size and the second shape and size are the same. The same can be applied to regular shapes or irregular shapes.

[0163] By designing the packaging method of this solution into such a style, it is convenient to integrate the second packaging layer 2 and the first packaging layer 1 first and then connect the chip 3, which is equivalent to integrating the silicon interposer and the packaging substrate first and then connecting the chip. Figure 1 Like the CoWoS technical solution in the , the chip is first integrated with the silicon interposer, and then shipped as a module to the downstream packaging factory for welding with the packaging substrate. Therefore, the CoWoS technical solution can avoid the following problems: process deviation of the silicon interposer itself (such as defects in through silicon vias TSV, etc.) or damage caused by short circuit of the interconnection line, resulting in the scrapping of the chip, high process cost, and inability to guarantee product yield. Based on this, it is beneficial for the technical solution to connect the chip 3 while ensuring that the first packaging layer 1 and the second packaging layer 2 are not damaged, effectively avoiding the situation where the chip 3 is scrapped due to damage to either the first packaging layer 1 or the second packaging layer 2, thereby helping to reduce process costs and ensure the yield of the final chip packaging module 100.

[0164] In some optional embodiments, the first encapsulation layer 1 and the second encapsulation layer 2 are cut and formed as one piece so that the first shape size and the second shape size are the same. Thus, by cutting and forming as one piece, the first shape size of the first encapsulation layer 1 and the second shape size of the second encapsulation layer 2 can be effectively ensured to be the same.

[0165] Optionally, when the first encapsulation layer 1 and the second encapsulation layer 2 are cut and formed as one piece, the process may be performed after at least a portion of the wafer 10 is removed.

[0166] In other embodiments, the first shape dimension of the first encapsulation layer 1 in a direction perpendicular to its thickness is smaller than the second shape dimension of the second encapsulation layer 2 in a direction perpendicular to its thickness. As a result, the volume of the first encapsulation layer 1 can be reduced, thereby reducing the volume and weight of the chip encapsulation module 100. For example, the first shape dimension of the first encapsulation layer 1 can be a rectangular shape with a length × width of 3mm × 3mm, and the second shape dimension of the second encapsulation layer 2 can be a rectangular shape with a length × width of 5mm × 5mm. The same can be applied to regular or irregular shapes. For example, such a structure can be obtained by adding a process, such as first cutting and molding the first encapsulation layer 1, and then cutting and molding the second encapsulation layer to obtain such a structure.

[0167] In some optional embodiments, the chip packaging method in the present application further includes: forming a protective layer 5 covering at least part of the chip 3 on the first side of the first packaging layer 1 in the thickness direction. (It may also be combined with Figure 6i Schematic diagram for understanding)

[0168] Based on this, the protective layer 5 can be used to physically protect at least part of the chip 3 to achieve electrical isolation and environmental isolation. While electrically insulating, it also isolates the influence of external water, oxygen and other adverse environmental factors, thereby facilitating the normal operation of the chip 3, effectively ensuring its lifespan, and effectively improving the reliability of the packaged chip packaging module 100, thereby improving the performance of the chip 3 and the chip packaging module 100.

[0169] Optionally, the protective layer 5 can completely cover the chip 3. Obviously, this can provide more comprehensive protection for the chip 3 and better improve the performance of the chip 3 and the chip packaging module 100.

[0170] The protective layer 5 can be made of any material, for example, a plastic packaging material of an epoxy resin system, an inorganic oxide system, or an organic polyimide (PI) material. Alternatively, it can be made of other materials when necessary.

[0171] It should be understood that, from the technical solution of the present application above, there is no need to make a large amount of equipment investment in the silicon interposer. At present, from the perspective of the leading wafer foundries at home and abroad, in order to enter the field of advanced packaging, each has invested a lot of manpower and material resources. However, the optional technical solution of the present application only uses part of the process technology of wafer manufacturing to perfectly inherit the high-density and small-size line characteristics of the wafer manufacturing process, and can realize the basis of high-speed and low-latency communication between chips. From the product architecture characteristics of the final chip packaging module 100, the technical solution achieves the same line interconnection density, and its high-speed and low-latency technical effects can be comparable to the CoWoS technical solution, but the realized processing cost is only one-tenth of the CoWoS technical solution. It can be said that it can significantly reduce the cost of the chip packaging manufacturing solution.

[0172] It should be understood that the above description is merely some optional embodiments of the chip packaging solution of the embodiment of the present application, and is not any limitation to the embodiment of the present application.

[0173] In order to facilitate further understanding of the chip packaging solution of the application embodiment, Figure 6a to Figure 6i The overall process of an example chip packaging solution is described. This example can be used to make Figure 2 The chip packaging module 100 is shown.

[0174] like Figure 6a As shown, a first packaging layer 1 is formed on a wafer 10, and is embedded with a first pad layer 11, at least one first circuit layer 12 (for example, it can be multiple first circuit layers 12), and a second pad layer 13 that are electrically connected layer by layer. The first packaging layer 1 includes a first side and a second side that are opposite to each other along the thickness direction. The first side of the first packaging layer 1 is in contact with the wafer 10, the first pad layer 11 is formed on the first side of the first packaging layer 1, and the second pad layer 13 is formed on the second side of the first packaging layer 1 and exposed from the second side of the first packaging layer 1, and the line width of the line in the first circuit layer 12 is less than or equal to 2um; the first pad layer 11 includes multiple first pads 111, and the second pad layer 13 includes multiple second pads 131; the first packaging layer 1 can be embedded with multiple layers of the first circuit layer 12; the first packaging layer 1 is a SiO2 layer formed on the wafer 10; the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 are manufactured by a wafer-level manufacturing process.

[0175] like Figure 6b As shown, a plurality of conductive blocks 4 are correspondingly formed on the plurality of second pads 131 exposed from the second side of the first packaging layer 1, so that the ends of the conductive blocks 4 away from the second pads 131 extend beyond the second side of the first packaging layer 1, and the excess distance H1 satisfies 5um≤H1≤100um.

[0176] like Figure 6cAs shown, a first molding dielectric layer 201 covering the plurality of conductive blocks 4 is formed on the second side of the first packaging layer 1; the first molding dielectric layer 201 is made of EMC material.

[0177] like Figure 6d As shown, the first molding medium layer 201 is ground so that the first molding medium layer 201 exposes at least part of the plurality of conductive blocks 4 .

[0178] like Figure 6e As shown, multiple third pads 211 of the third pad layer 21 are correspondingly formed on the exposed multiple conductive blocks 4, so that the multiple third pads 211 of the third pad layer 21 are electrically connected to the multiple second pads 131 of the second pad layer 13 through the multiple conductive blocks 4 respectively.

[0179] like Figure 6fAs shown, the second packaging layer 2 to be formed is embedded with n layers of second circuit layers 22, n≥3 (when understood here, n=3 in the figure), at least one electrical connection block 24 is formed on the third pad layer 21, and a first second plastic encapsulation dielectric layer 202 is formed on the first plastic encapsulation dielectric layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21, and the first second plastic encapsulation dielectric layer 202 is ground so that the first second plastic encapsulation dielectric layer 202 exposes the electrical connection block 24 formed on the third pad layer 21; on the first second plastic encapsulation dielectric layer 202, a connection block 24 formed on the third pad layer 21 is formed. 1, forming at least one electrical connection block 24 on the first second circuit layer 22, and forming a second second plastic encapsulation dielectric layer 202 covering the first second circuit layer 22 and the electrical connection block 24 formed on the first second circuit layer 22, and then grinding the second second plastic encapsulation dielectric layer 202 so that the second second plastic encapsulation dielectric layer 202 exposes the electrical connection block 24 formed on the first second circuit layer 22; and then repeating the following steps in sequence to obtain the second to n-1 second circuit layers 22 and the third to n-1 second plastic encapsulation dielectric layers 202: "In the i-th On the second plastic encapsulation dielectric layer 202, an i-th second circuit layer 22 electrically connected to the electrical connection block 24 formed on the i-1th second circuit layer 22 is formed, at least one electrical connection block 24 is formed on the i-th second circuit layer 22, and an i+1-th second plastic encapsulation dielectric layer 202 covering the i-th second circuit layer 22 and the electrical connection block 24 formed on the i-th second circuit layer 22 is formed, and then the i+1-th second plastic encapsulation dielectric layer 202 is ground so that the i+1-th second plastic encapsulation dielectric layer 202 exposes the electrical connection block 24 formed on the i-th second circuit layer 22, 2≤i≤n-1”; on the n-th second plastic encapsulation dielectric layer 202, at least one electrical connection block 24 is formed on the i-th second circuit layer 22, and at least one electrical connection block 24 is formed on the i-th second circuit layer 22. On the sealing dielectric layer 202, an n-th second circuit layer 22 electrically connected to the electrical connection block 24 formed on the n-1-th second circuit layer 22 is formed, at least one electrical connection block 24 is formed on the n-th second circuit layer 22, and an n+1-th second plastic sealing dielectric layer 202 covering the n-th second circuit layer 22 and the electrical connection block 24 formed on the n-th second circuit layer 22 is formed, thereby obtaining n-th second circuit layers 22 and n+1-th second plastic sealing dielectric layers 202 (if n=3 in the example in the figure, 3-th second circuit layers 22 and 4-th second plastic sealing dielectric layers 202 are obtained in total); the second plastic sealing dielectric layer 202 uses EMC material. (It should be understood that for ease of understanding, the regions of each plastic sealing dielectric layer are roughly indicated by dotted lines in each schematic diagram. In addition, the second packaging layer 2 to be formed can also be embedded with 1 or 2 layers of second circuit layers 22. The specific implementation method has been described in the previous text and will not be repeated here with a separate example.)

[0180] like Figure 6gAs shown, the n+1-th second molding dielectric layer 202 is ground so that the n+1-th second molding dielectric layer 202 exposes the electrical connection block 24 formed on the n-th second circuit layer 22; a fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the n-th second circuit layer 22 is formed on the formed n+1-th second molding dielectric layer 202, and a third molding dielectric layer 203 covering the fourth pad layer 23 is formed, and an opening is formed on the third molding dielectric layer 203 to expose at least part of the fourth pad layer 23 through the opening; a second encapsulation layer 2 is formed based on the first molding dielectric layer 201, multiple layers of the second molding dielectric layer 202 and the third molding dielectric layer 203; the third molding dielectric layer 203 uses EMC material; the thickness H2 of the second encapsulation layer 2 is in the range of 200um to 500um.

[0181] like Figure 6h As shown, Figure 6g The module structure obtained in the steps shown is turned over, and the wafer 10 is removed to expose the plurality of first pads 111 of the first pad layer 11 .

[0182] like Figure 6i As shown, at least one chip 3 is electrically connected to a plurality of first pads 111 (such as Figure 6i As shown, two chips 3 can be taken as an example, and electrically connected by soldering, and then a protection layer 5 covering the chip 3 is made to obtain a chip packaging module 100.

[0183] It should be understood that Figure 6a to Figure 6i The examples shown are not intended to limit the embodiments of the present application in any way. In addition, the examples are described briefly and can be understood in conjunction with the relevant descriptions of the previous embodiments.

[0184] According to a second aspect of an embodiment of the present application, a chip packaging module 100 is provided, which is packaged by the chip packaging method of the first aspect.

[0185] It should be understood that since the chip packaging module 100 of the second aspect is obtained by the chip packaging method of the first aspect, the chip packaging module 100 does not rely on the through silicon via (TSV) process, so the manufacturing cost is low and the manufacturing process complexity is low; and since the line width of the line in the first circuit layer 12 is set to be less than or equal to 2um, the minimum line width of the line in the second circuit layer 22 is greater than the minimum line width of the line in the first circuit layer 12, thereby ensuring that the line width of the line in the first circuit layer 12 is small, which is convenient for realizing high-density lines and interconnections, so that the chip packaging module 100 has a high degree of integration; in addition, the chip packaging module 100 obtained by the chip packaging method is conducive to avoiding the situation where the chip 3 is scrapped together due to damage to any one of the first packaging layer 1 and the second packaging layer 2 during preparation, thereby helping to further reduce the process cost, and the prepared chip packaging module 100 can also have a good yield.

[0186] According to the third aspect of the embodiment of the present application, referring to Figure 2 As shown, a chip packaging module 100 is provided, which includes: a chip 3, a first packaging layer 1 and a second packaging layer 2; the first packaging layer 1 includes a first side and a second side opposite to each other in the thickness direction, and is embedded with a first pad layer 11 electrically connected layer by layer, at least one first circuit layer 12 and a second pad layer 13, the first pad layer 11 is located on the first side of the first packaging layer 1 and is electrically connected to the chip 3, and the second pad layer 13 is located on the second side of the first packaging layer 1; the second packaging layer 2 is embedded with a third pad layer 21 electrically connected layer by layer and at least one second circuit layer 22, the third pad layer 21 is electrically connected to the second pad layer 13; wherein the line width of the line in the first circuit layer is less than or equal to 2um, and the minimum line width of the line in the second circuit layer 22 is greater than the minimum line width of the line in the first circuit layer 12.

[0187] Based on this, the chip packaging module 100 in the present application may not rely on the through silicon via (TSV) process, so the manufacturing cost is low and the manufacturing process complexity is low; and, since the line width of the line in the first circuit layer 12 is set to be less than or equal to 2um, the minimum line width of the line in the second circuit layer 22 is greater than the minimum line width of the line in the first circuit layer 12, thereby ensuring that the line width of the line in the first circuit layer 12 is small, which is convenient for realizing high-density lines and interconnections, so that the chip packaging module 100 has a high degree of integration; in addition, the chip packaging module 100 is not prone to the situation where the chip 3 is scrapped together due to damage to either the first packaging layer 1 or the second packaging layer 2, which is conducive to further reducing the process cost, and the chip packaging module 100 can also have a good yield.

[0188] Optionally, refer to Figure 2As shown, the first pad layer 11 may include a plurality of first pads 111 , and the second pad layer 13 may include a plurality of second pads 131 . The third pad layer 21 may include a plurality of third pads 211 .

[0189] It should be understood that the first pad layer 11, the first circuit layer 12, the second pad layer 13, the third pad layer 21, the second circuit layer 22, the fourth pad layer 23 and other related contents have been explained in the previous text and can be understood in conjunction with the previous text, so they will not be repeated here.

[0190] Optionally, the line width of the circuit in the first circuit layer 12 in the present application may be in the range of 100 nm to 2 um. Such a line width range can well improve the integration of the chip packaging module.

[0191] Optionally, the line width of the circuit in the first circuit layer 12 in the present application may be in the range of 100 nm to 1 um. Such a line width range can well improve the integration of the chip packaging module.

[0192] In some optional embodiments, the first encapsulation layer 1 is a SiO2 layer.

[0193] Based on this, the first packaging layer 1 in the form of a SiO2 layer can, on the one hand, be used as an insulating layer to effectively meet some insulation requirements between the various layer structures (i.e., the first pad layer 11, at least one first circuit layer 12 and the second pad layer 13); on the other hand, by adopting the first packaging layer 1 in the form of a SiO2 layer, when forming the first circuit layer 12, it is easier to make the line width therein less than or equal to 2um, thereby realizing high-density circuits, thereby improving the integration of the chip packaging module 100.

[0194] In some optional embodiments, the second encapsulation layer 2 is a plastic encapsulation dielectric layer. The second encapsulation layer 2 in the form of a plastic encapsulation dielectric layer has good performance, is easy to manufacture, and has low process complexity.

[0195] In some optional embodiments, the material of the molding dielectric layer is epoxy molding compound (EMC material) and / or polyimide.

[0196] The plastic sealing dielectric layer (i.e., the second packaging layer 2) adopts EMC material, which has low cost, convenient plastic sealing operation, high production efficiency, good high temperature resistance, good electrical insulation, and good heat dissipation performance, and can effectively meet the plastic sealing performance requirements. And EMC materials can also meet the needs of making circuits. The use of EMC materials is conducive to making the warping of the second packaging layer 2 of the chip packaging module 100 more balanced, better mechanical strength, and better heat dissipation performance. In addition, the second packaging layer 2 can be used as the insulation layer of the second circuit layer 22 using EMC materials, and the insulation effect is better. In addition, the use of EMC materials makes this solution easier to use wafer-level / panel-level packaging technology, which is convenient for realizing wafer-level or panel-level circuit integration.

[0197] In some optional embodiments, referring to Figure 2 As shown, the thickness H2 of the second encapsulation layer 2 satisfies 200um to 500um. This thickness range can make the second encapsulation layer 2 have good structural stability. Within the above range, it can be selected as needed, such as 200um, 250um, 300um, 350um, 400um, 450um, 500um, etc.

[0198] In the present application, the number of layers of the first circuit layer 12 can be set as required, and no limitation is imposed here. In some optional embodiments, the first packaging layer 1 is embedded with 1 to 10 layers of the first circuit layer 12. For example Figure 2 In the example, the first packaging layer 1 is embedded with two first circuit layers 12.

[0199] In the present application, the number of layers of the second circuit layer 22 can be set as required, and no limitation is imposed here. In some optional embodiments, the second packaging layer 2 is embedded with 1 to 10 layers of the second circuit layer 22. For example Figure 2 In the example of FIG. 1 , the second packaging layer 2 is embedded with three second circuit layers 22 .

[0200] In some optional embodiments, at least one electrical connection block 24 is provided between each two adjacent layers of the third pad layer 21 and the at least one second circuit layer 22, and the two adjacent layers are electrically connected through the at least one electrical connection block 24. Thus, a stable electrical connection between the two adjacent layers can be achieved through the electrical connection block 24.

[0201] In some optional embodiments, a first shape dimension of the first encapsulation layer 1 in a direction perpendicular to its thickness is the same as a second shape dimension of the second encapsulation layer 2 in a direction perpendicular to its thickness.

[0202] With this structural style, when manufacturing the chip packaging module 100, the second packaging layer 2 and the first packaging layer 1 can be integrated first and then the chip 3 can be connected. In other words, the silicon interposer can be integrated with the packaging substrate first and then the chip can be connected. Figure 1Like the CoWoS technical solution in the , the chip is first integrated with the silicon interposer, and then shipped as a module to the downstream packaging factory for welding with the packaging substrate. Therefore, the CoWoS technical solution can avoid the following problems: process deviation of the silicon interposer itself (such as defects in through silicon vias TSV, etc.) or damage caused by short circuit of the interconnection line, resulting in the scrapping of the chip, high process cost, and inability to guarantee product yield. Based on this, it is beneficial to make it possible to connect the chip 3 while ensuring that the first packaging layer 1 and the second packaging layer 2 are not damaged when manufacturing the chip packaging module 100, so that the chip packaging module 100 is not prone to the situation where any one of the first packaging layer 1 and the second packaging layer 2 is damaged, resulting in the scrapping of the chip 3, thereby helping to reduce process costs and ensure the yield of the chip packaging module 100.

[0203] In some optional embodiments, the first shape dimension of the first packaging layer 1 in a direction perpendicular to its thickness is smaller than the second shape dimension of the second packaging layer 2 in a direction perpendicular to its thickness. Thus, the volume of the first packaging layer 1 can be reduced, thereby reducing the volume and weight of the chip packaging module 100.

[0204] In some optional embodiments, referring to Figure 2 As shown, the chip packaging module 100 further includes a protection layer 5 covering at least a portion of the chip 3 .

[0205] Based on this, the protective layer 5 can be used to physically protect at least part of the chip 3 to achieve electrical isolation and environmental isolation. While electrically insulating, it also isolates the influence of external water, oxygen and other adverse environmental factors, thereby facilitating the normal operation of the chip 3, effectively ensuring its lifespan, and effectively improving the reliability of the packaged chip packaging module 100, thereby improving the performance of the chip 3 and the chip packaging module 100.

[0206] Optionally, refer to Figure 2 As shown, the protective layer 5 can completely cover the chip 3. Obviously, this can provide more comprehensive protection for the chip 3 and better improve the performance of the chip 3 and the chip packaging module 100.

[0207] The protective layer 5 can be made of any material, for example, a plastic packaging material of an epoxy resin system, an inorganic oxide system, or an organic polyimide (PI) material. Alternatively, it can be made of other materials when necessary.

[0208] In some optional embodiments, referring to Figure 2 As shown, the second packaging layer 2 is also embedded with a fourth pad layer 23, which is exposed to the outside of the second packaging layer 2 through an opening on the second packaging layer 2, and the third pad layer, at least one second circuit layer and the fourth pad layer 23 are electrically connected layer by layer.

[0209] Based on this, the fourth pad layer 23 can meet the needs of electrical connection between the chip packaging module 100 and other external circuit structures (such as circuit boards, other chips, electronic devices, etc.), and can realize double-sided electrical connection of the circuits in the chip packaging module (that is, the packaged circuits can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0210] Optionally, refer to Figure 2 As shown, the fourth pad layer 23 may include a plurality of fourth pads 231 .

[0211] In some optional embodiments, the chip packaging module 100 also includes a conductive component; the second side of the first packaging layer 1 is bonded to the second packaging layer 2 to form a plurality of receiving grooves, and the second pad layer 13 and the third pad layer 21 are at least partially located in the receiving grooves; the conductive component is seamlessly filled in at least one of the receiving grooves and electrically connects the second pad layer 13 and the third pad layer 21.

[0212] Based on this, the conductive component can effectively ensure the stability of the electrical connection between the second pad layer 13 and the third pad layer 21, improve the electrical connection performance, and can form an electrical connection without relying on solder, so that the solder interface between the first packaging layer 1 and the second packaging layer 2 can be avoided, thereby avoiding the disadvantage of unstable packaging structure caused by soldering, thereby improving the reliability of the chip packaging module 100 and effectively reducing the packaging cost.

[0213] In some optional embodiments, the second pad layer 13 includes a plurality of second pads 131, the third pad layer 21 includes a plurality of third pads 211, and the conductive component includes a plurality of conductive blocks 4; the plurality of second pads 131 are respectively at least partially located in the corresponding receiving grooves, and the plurality of third pads 211 are respectively at least partially located in the corresponding receiving grooves; the plurality of conductive blocks 4 are respectively seamlessly filled in the corresponding receiving grooves, and electrically connect the second pads 131 and the third pads 211 located in the receiving grooves.

[0214] Based on this, the conductive block 4 can effectively ensure the stability of the electrical connection between the second pad 131 of the second pad layer 13 and the third pad 211 of the third pad layer 21, improve the electrical connection performance, and can form an electrical connection without relying on solder, so that the solder interface between the first packaging layer 1 and the second packaging layer 2 can be avoided, thereby avoiding the disadvantage of unstable packaging structure caused by soldering, thereby improving the reliability of the chip packaging module 100 and effectively reducing the packaging cost.

[0215] It should be understood that, regarding the various optional embodiments of the chip packaging module 100 of the third aspect, the relevant contents are also described in some detail in the aforementioned chip packaging method embodiment of the first aspect, and therefore, they can also be understood in conjunction with the contents in the aforementioned chip packaging method embodiment of the first aspect.

[0216] According to the fourth aspect of the embodiment of the present application, referring to Figure 7 As shown, an electronic device 200 is provided, comprising: the chip packaging module 100 provided by the second aspect or the third aspect mentioned above.

[0217] Optionally, the electronic device 200 may be any electronic device, including but not limited to a mobile phone, a computer, etc. It should be understood that the above is only an example application and does not constitute any limitation to the embodiments of the present application.

[0218] It can be understood that the above description of various aspects of the embodiments of the present application is merely some optional exemplary descriptions of the technical solutions of the embodiments of the present application, and does not constitute any limitation on the embodiments of the present application.

[0219] The optional implementation modes of the embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the embodiments of the present application are not limited thereto. It should be noted that, for the convenience of explaining the embodiments of the present application, the various drawings of the embodiments of the present application are not necessarily drawn according to the actual proportions, which are only used to facilitate the explanation of the technical solution and are not used for any restriction on the embodiments of the present application. Within the technical concept of the embodiments of the present application, the technical solutions of the embodiments of the present application can be subjected to a variety of simple modifications. The various technical features included in the various different embodiments of the embodiments of the present application can be combined in any suitable manner. In order to avoid unnecessary repetition, the embodiments of the present application will not be described separately for various possible combinations. However, these simple modifications and combinations should also be regarded as the contents disclosed in the embodiments of the present application, and all belong to the protection scope of the embodiments of the present application.

[0220] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". It should be noted that the concepts of "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units. It should be noted that the modifications of "one" and "multiple" mentioned in this application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0221] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging method, comprising: A first packaging layer embedded with a first pad layer electrically connected layer by layer, at least one first circuit layer and a second pad layer is formed on a wafer, wherein the first packaging layer includes a first side and a second side opposite to each other in a thickness direction, the first side of the first packaging layer contacts the wafer, the first pad layer is formed on the first side of the first packaging layer, the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer, and the line width of the circuit in the first circuit layer is less than or equal to 2 um; On the second side of the first packaging layer, a second packaging layer is formed in which a third pad layer and at least one second circuit layer are embedded, the third pad layer is electrically connected to the second pad layer, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer; The wafer in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to obtain a chip packaging module.

2. The method according to claim 1, wherein: The first pad layer, at least one first circuit layer and the second pad layer which are electrically connected layer by layer are manufactured by a wafer-level manufacturing process.

3. The method according to claim 1, wherein: The forming of the first packaging layer on the wafer comprises: forming the first packaging layer in the form of a SiO2 layer on the wafer.

4. The method according to claim 1, wherein: The second packaging layer having a third pad layer and at least one second circuit layer embedded therein and electrically connected layer by layer is formed on the second side of the first packaging layer, comprising: Forming a conductive component on the second pad layer exposed from the second side of the first packaging layer, and forming a first molding dielectric layer exposing the conductive component on the second side of the first packaging layer; Forming a third pad layer connected to the exposed conductive component on the first plastic encapsulation dielectric layer, so that the third pad layer is electrically connected to the second pad layer through the conductive component; Sequentially forming multiple layers of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent second molding dielectric layers, and electrically connecting the third pad layer and the obtained at least one second circuit layer layer by layer; The second encapsulation layer is formed based on the first molding medium layer and the multiple second molding medium layers.

5. The method according to claim 4, wherein: The second pad layer includes a plurality of second pads, the third pad layer includes a plurality of third pads, and the conductive component includes a plurality of conductive blocks; The step of forming a conductive component on the second pad layer exposed from the second side of the first packaging layer, and forming a first plastic encapsulation dielectric layer exposing the conductive component on the second side of the first packaging layer, comprises: forming a plurality of conductive blocks on the plurality of second pads of the second pad layer, so that the ends of the conductive blocks away from the second pads extend beyond the second side of the first packaging layer; forming a first plastic encapsulation dielectric layer covering the plurality of conductive blocks on the second side of the first packaging layer, and grinding the first plastic encapsulation dielectric layer so that the first plastic encapsulation dielectric layer exposes at least part of the plurality of conductive blocks; The third pad layer connected to the exposed conductive component is formed on the first plastic encapsulation dielectric layer so that the third pad layer is electrically connected to the second pad layer through the conductive component, including: correspondingly forming multiple third pads of the third pad layer on the exposed multiple conductive blocks so that the multiple third pads of the third pad layer are electrically connected to the multiple second pads of the second pad layer through the multiple conductive blocks respectively.

6. The method according to claim 4, wherein: If the second packaging layer to be formed is embedded with a second circuit layer, then: The method of sequentially forming a plurality of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent second molding dielectric layers, and electrically connecting the third pad layer and the obtained at least one second circuit layer layer layer by layer, comprises: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation dielectric layer is formed on the first plastic encapsulation dielectric layer to cover the third pad layer and the electrical connection block formed on the third pad layer, and the first second plastic encapsulation dielectric layer is ground so that the first second plastic encapsulation dielectric layer exposes the electrical connection block formed on the third pad layer; On the first second molding medium layer, a first second circuit layer electrically connected to the electrical connection block formed on the third pad layer is formed, and a second second molding medium layer covering the first second circuit layer is formed.

7. The method according to claim 6, wherein: The step of forming, on the first second plastic encapsulation dielectric layer, a first second circuit layer electrically connected to the electrical connection block formed on the third pad layer, and forming a second second plastic encapsulation dielectric layer covering the first second circuit layer comprises: forming, on the first second plastic encapsulation dielectric layer, a first second circuit layer electrically connected to the electrical connection block formed on the third pad layer, forming at least one electrical connection block on the first second circuit layer, and forming a second second plastic encapsulation dielectric layer covering the first second circuit layer and the electrical connection block formed on the first second circuit layer; The method further includes: grinding the second second molding medium layer so that the second second molding medium layer exposes the electrical connection block formed on the first second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the first second circuit layer on the formed second second molding medium layer, forming a third molding medium layer covering the fourth pad layer, and opening the third molding medium layer to expose at least part of the fourth pad layer through the opening; The forming of the second encapsulation layer based on the first molding medium layer and the multi-layer second molding medium layer includes: forming the second encapsulation layer based on the first molding medium layer, the multi-layer second molding medium layer and the third molding medium layer.

8. The method according to claim 4, wherein: If the second packaging layer to be formed is embedded with two second circuit layers, then: The method of sequentially forming a plurality of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent second molding dielectric layers, and electrically connecting the third pad layer and the obtained at least one second circuit layer layer layer by layer, comprises: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation dielectric layer is formed on the first plastic encapsulation dielectric layer to cover the third pad layer and the electrical connection block formed on the third pad layer, and the first second plastic encapsulation dielectric layer is subjected to grinding treatment so that the first second plastic encapsulation dielectric layer exposes the electrical connection block formed on the third pad layer; On the first second plastic encapsulation dielectric layer, a first second circuit layer electrically connected to the electrical connection block formed on the third pad layer is formed, at least one electrical connection block is formed on the first second circuit layer, and a second second plastic encapsulation dielectric layer is formed to cover the first second circuit layer and the electrical connection block formed on the first second circuit layer, and then the second second plastic encapsulation dielectric layer is ground so that the second second plastic encapsulation dielectric layer exposes the electrical connection block formed on the first second circuit layer; On the second layer of second plastic encapsulation dielectric layer, a second layer of second circuit layer electrically connected to the electrical connection block formed on the first layer of second circuit layer is formed, and a third layer of second plastic encapsulation dielectric layer covering the second layer of second circuit layer is formed, thereby obtaining a total of 2 layers of second circuit layers and 3 layers of second plastic encapsulation dielectric layers.

9. The method according to claim 8, wherein: The step of forming a second layer of second circuit layer electrically connected to the electrical connection block formed on the first layer of second circuit layer on the second layer of second molding dielectric layer, and forming a third layer of second circuit layer covering the second layer of second circuit layer, comprises: forming a second layer of second circuit layer electrically connected to the electrical connection block formed on the first layer of second circuit layer on the second layer of second molding dielectric layer, forming at least one electrical connection block on the second layer of second circuit layer, and forming a third layer of second circuit layer covering the second layer of second circuit layer and the electrical connection block formed on the second layer of second circuit layer; The method further includes: grinding the third second molding medium layer so that the third second molding medium layer exposes the electrical connection block formed on the second second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the second second circuit layer on the formed third second molding medium layer, forming a third molding medium layer covering the fourth pad layer, and opening the third molding medium layer to expose at least part of the fourth pad layer through the opening; The forming of the second encapsulation layer based on the first molding medium layer and the multiple second molding medium layers includes: forming the second encapsulation layer based on the first molding medium layer, three second molding medium layers and a third molding medium layer.

10. The method according to claim 4, wherein: If the second packaging layer to be formed is embedded with n second circuit layers, n≥3, then: The method of sequentially forming a plurality of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent second molding dielectric layers, and electrically connecting the third pad layer and the obtained at least one second circuit layer layer layer by layer, comprises: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation dielectric layer is formed on the first plastic encapsulation dielectric layer to cover the third pad layer and the electrical connection block formed on the third pad layer, and the first second plastic encapsulation dielectric layer is subjected to grinding treatment so that the first second plastic encapsulation dielectric layer exposes the electrical connection block formed on the third pad layer; On the first second plastic encapsulation dielectric layer, a first second circuit layer electrically connected to the electrical connection block formed on the third pad layer is formed, at least one electrical connection block is formed on the first second circuit layer, and a second second plastic encapsulation dielectric layer is formed to cover the first second circuit layer and the electrical connection block formed on the first second circuit layer, and then the second second plastic encapsulation dielectric layer is ground so that the second second plastic encapsulation dielectric layer exposes the electrical connection block formed on the first second circuit layer; Repeat the following steps in order to obtain the 2nd to n-1st second circuit layers and the 3rd to nth second plastic encapsulation dielectric layers: on the i-th second plastic encapsulation dielectric layer, form the i-th second circuit layer electrically connected to the electrical connection block formed on the i-1st second circuit layer, form at least one electrical connection block on the i-th second circuit layer, and form the i+1st second plastic encapsulation dielectric layer covering the i-th second circuit layer and the electrical connection block formed on the i-th second circuit layer, and then grind the i+1st second plastic encapsulation dielectric layer so that the i+1st second plastic encapsulation dielectric layer exposes the electrical connection block formed on the i-th second circuit layer, 2≤i≤n-1; On the nth second plastic encapsulation dielectric layer, an nth second circuit layer electrically connected to the electrical connection block formed on the n-1th second circuit layer is formed, and an n+1th second plastic encapsulation dielectric layer covering the nth second circuit layer is formed, thereby obtaining a total of n second circuit layers and n+1 second plastic encapsulation dielectric layers.

11. The method according to claim 10, wherein: The method of forming an n-th second circuit layer electrically connected to the electrical connection block formed on the n-1-th second circuit layer on the n-th second plastic encapsulation dielectric layer, and forming an n+1-th second plastic encapsulation dielectric layer covering the n-th second circuit layer, comprises: forming an n-th second circuit layer electrically connected to the electrical connection block formed on the n-1-th second circuit layer on the n-th second plastic encapsulation dielectric layer, forming at least one electrical connection block on the n-th second circuit layer, and forming an n+1-th second plastic encapsulation dielectric layer covering the n-th second circuit layer and the electrical connection block formed on the n-th second circuit layer; The method further includes: grinding the n+1th second plastic encapsulation dielectric layer so that the n+1th second plastic encapsulation dielectric layer exposes the electrical connection block formed on the nth second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the nth second circuit layer on the formed n+1th second plastic encapsulation dielectric layer, forming a third plastic encapsulation dielectric layer covering the fourth pad layer, and opening the third plastic encapsulation dielectric layer to expose at least part of the fourth pad layer through the opening; The forming of the second encapsulation layer based on the first molding medium layer and the multi-layer second molding medium layer includes: forming the second encapsulation layer based on the first molding medium layer, the multi-layer second molding medium layer and the third molding medium layer.

12. The method according to claim 5, wherein: An end of the conductive block away from the second pad extends beyond the second side of the first packaging layer by 5 um to 100 um.

13. The method according to any one of claims 4 to 12, wherein: The step of forming a conductive component on the second pad layer exposed from the second side of the first packaging layer comprises: A conductive component is formed on the second pad layer exposed from the second side of the first packaging layer by at least one of a sputtering process, an evaporation process, and an electroplating process.

14. The method according to any one of claims 4 to 12, wherein: The first molding medium layer and the second molding medium layer are formed by using the same molding material.

15. The method according to claim 14, wherein: The plastic packaging material is epoxy resin molding compound and / or polyimide.

16. The method according to any one of claims 1 to 12, wherein: A first shape dimension of the first encapsulation layer in a direction perpendicular to the thickness thereof is the same as a second shape dimension of the second encapsulation layer in a direction perpendicular to the thickness thereof.

17. The method according to claim 16, wherein: The first encapsulation layer and the second encapsulation layer are cut and formed as one piece, so that the first shape and the second shape are of the same size.

18. The method according to any one of claims 1 to 12, wherein: The method further includes: forming a protection layer covering at least a portion of the chip on a first side of the first packaging layer in a thickness direction.

19. A chip packaging module, wherein the chip packaging module is packaged by the method according to any one of claims 1 to 18.

20. A chip packaging module, comprising: chip; A first packaging layer comprises a first side and a second side opposite to each other in a thickness direction, and is embedded with a first pad layer, at least one first circuit layer and a second pad layer, which are electrically connected layer by layer, wherein the first pad layer is located on a first side of the first packaging layer and is electrically connected to the chip, and the second pad layer is located on a second side of the first packaging layer; A second packaging layer is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer, and the third pad layer is electrically connected to the second pad layer; The line width of the circuit in the first circuit layer is less than or equal to 2 um, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer.

21. The chip packaging module according to claim 20, wherein: The chip packaging module meets at least one of the following conditions: The first encapsulation layer is a SiO2 layer; The second encapsulation layer is a plastic encapsulation dielectric layer; The thickness of the second encapsulation layer meets 200um to 500um; The first packaging layer is embedded with 1 to 10 first circuit layers; The second packaging layer is embedded with 1 to 10 second circuit layers; At least one electrical connection block is provided between each two adjacent layers of the third pad layer and at least one second circuit layer, and the two adjacent layers are electrically connected through the at least one electrical connection block; A first shape dimension of the first encapsulation layer in a direction perpendicular to its thickness is the same as a second shape dimension of the second encapsulation layer in a direction perpendicular to its thickness; A first shape dimension of the first encapsulation layer in a direction perpendicular to its thickness is smaller than a second shape dimension of the second encapsulation layer in a direction perpendicular to its thickness; The chip packaging module further includes a protective layer covering at least a portion of the chip; The second packaging layer is also embedded with a fourth pad layer, which is exposed to the outside of the second packaging layer through an opening on the second packaging layer, and the third pad layer, at least one second circuit layer and the fourth pad layer are electrically connected layer by layer.

22. The chip packaging module according to claim 21, wherein: The material of the plastic sealing dielectric layer is epoxy resin molding compound and / or polyimide.

23. The chip packaging module according to any one of claims 20 to 22, wherein: The chip packaging module also includes a conductive component; The second side of the first encapsulation layer is attached to the second encapsulation layer to form a plurality of receiving grooves, and the second pad layer and the third pad layer are at least partially located in the receiving grooves; The conductive component is seamlessly filled in at least one receiving groove and electrically connects the second pad layer and the third pad layer.

24. The chip packaging module according to claim 23, wherein: The second pad layer includes a plurality of second pads, the third pad layer includes a plurality of third pads, and the conductive component includes a plurality of conductive blocks; The plurality of second solder pads are respectively at least partially located in the corresponding receiving grooves, and the plurality of third solder pads are respectively at least partially located in the corresponding receiving grooves; The plurality of conductive blocks are seamlessly filled in the corresponding receiving grooves respectively, and electrically connect the second pad and the third pad located in the receiving grooves.

25. An electronic device comprising: A chip packaging module as described in any one of claims 19 to 24.

Images