A CTDSM circuit with arbitrary periodic overshoot loop delay compensation

Abstract

The present application belongs to the technical field of analog integrated circuits, and particularly relates to a CTDSM circuit with arbitrary period overshoot loop delay compensation. The present application delays the output signal Y of the CTDSM from 1 to m, feeds the quantization results of the first n channels of the CTDSM which have been completely quantized to the input end of the TIADC in an analog domain, feeds the quantization results of the channels which have not been completely quantized to the output end of the TIADC in a digital domain, and then sums the analog domain output code word A, the digital domain compensation code word (D1-Dm-n) and the signal C2 to obtain the output signal Y of the entire CTDSM circuit, thereby finally completing the compensation of m unit period overshoot loop delays and greatly reducing the difficulty of circuit timing design. The input signal X is summed and connected to the input end of ADDER0 through the delay signals COA1 to COAm-n which are obtained by delaying the input signal X from 1 to m-n, so as to reduce the signal swing input to the input end of the TIADC.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of analog integrated circuits, and particularly relates to a CTDSM circuit with arbitrary period excess loop delay compensation. BACKGROUND

[0002] Continuous-Time Delta-Sigma Modulator (CTDSM) has been widely researched and applied in the field of analog integrated circuits due to its high precision and high bandwidth. The quantizer in CTDSM is usually realized by cascading ADC and DAC. Due to the resolution limit of the quantizer, a certain period of time is needed to complete the conversion, resulting in a delay in the output sequence. The DAC works after the ADC, so it can only be driven by the clock signal later, further increasing the delay. The excess loop delay (ELD) in CTDSM will lead to system instability.

[0003] Suppose a first-order CTDSM with Non Return to Zero (NRZ) encoding, where there is an excess loop delay of t d , the system is shown in the attached Figure 1 , the noise transfer function (NTF) of the CTDSM system can be expressed as:

[0004]

[0005] It can be seen that compared with the CTDSM without excess loop delay, the system has two more poles, and the pole position is related to t d , when t d is larger, the system is more unstable, when t d is larger than one period, the system is in an unstable state.

[0006] For the problem of excess loop delay compensation, a design method of direct feedback path around the quantizer is proposed in the literature, which is shown in the attached Figure 2 . This design method introduces a feedback path at the output of the quantizer, which also passes through t d delay to the input of the quantizer, and introduces a feedback path to offset the excess loop delay.

[0007] However, the above scheme is only applicable to the case where the over-shoot loop delay is less than one period. If the CTDSM selects a time-interleaved (TI) ADC with multiple input channels as the quantizer, the over-shoot loop delay will be greater than one period. If the above compensation scheme of direct feedback is used to compensate the over-shoot loop delay of the TI ADC, the un-fully quantized signal will be fed back to the input, resulting in system instability. For example, if the TI ADC has two channels and the over-shoot loop delay is compensated, the input of the quantizer is:

[0008] D[n]=X[n]-Y[n-1]-Y[n-2]

[0009] Where D[n] is the input signal of the nth period quantizer, X[n] is the discretized signal of the first-order CTDSM input signal after loop filtering in the nth period, and Y[n] is the output signal of the nth period quantizer.

[0010] As can be seen, in the nth period, the output values of the quantizer in the (n-1)th period and the (n-2)th period need to be fed back. However, for a two-channel TI ADC, the (n-1)th period is still in the quantization stage and cannot feed back the correct output signal, resulting in an error in the overall circuit. This limits the development of CTDSM in the high-speed and high-precision field. Therefore, how to compensate for the over-shoot loop delay of more than one period is a problem that needs to be solved in the research of high-performance CTDSM. SUMMARY

[0011] In view of the above problems or deficiencies, the present application provides a CTDSM circuit for compensating for over-shoot loop delay of any period, which is suitable for TI ADCs with any number of channels as CTDSM quantizers. By introducing multiple feedback paths that meet the design conditions from the quantizer output to the quantizer input, the over-shoot loop delay is compensated.

[0012] A CTDSM circuit for compensating for over-shoot loop delay of any period, which is composed of the following six modules, as shown in Figure 3 The modules include module 001, module 002, module 003, module 004, module 005 and module 006.

[0013] If the number of channels of the TI ADC used as the quantizer of the CTDSM is m, the CTDSM will have m periods of over-shoot loop delay. According to the working principle of the TI ADC, when sampling in the (m+1)th period, the m channels all have different degrees of quantization results. Assuming that the first n channels of the m channels have been fully quantized, and the remaining channels have not been fully quantized but have generated different degrees of quantization code words.

[0014] The module 001 includes three parts of adder ADDERx, loop filter and sampling switch connected in sequence. The adder ADDERx is connected with the input signal X of the whole CTDSM circuit and the output signal D of the module 004 as the input of the module 001 m ; the output of the sampling switch is connected with the input end of the module 002 as the output of the module 001. The module 001 performs difference operation on the input signals X and D m through the adder ADDERx, and realizes discretization through the sampling switch after loop filtering.

[0015] The module 002 is composed of n+1 adders, which are connected in sequence from ADDER0 to ADDERn. The input of the adder ADDER0 is connected with the output of the module 001 (sampling switch) and the output signal C1 of the module 003, the input of the adder ADDER1 is connected with the output of ADDER0 and the output signal D m of the module 004, the input of the adder ADDER2 is connected with the output of ADDER1 and the output signal D m-1 of the module 004, …, the input of the adder ADDERn is connected with the output of ADDERn-1 and the output signal D m-n+1 of the module 004; the output of the adder ADDERn is connected with the input of the module 005 as the output of the module 002.

[0016] The module 003 is composed of m-n unit period delay modules (Z -1 ), m-n coarse ADCs (coarse precision analog-to-digital converter) and a summer SUMMER0. The coarse ADC architecture can be realized by using high-speed low-precision ADC such as flash ADC; wherein m is the total channel number of the TIADC, and n is the number of channels that have been completely quantized in the TIADC at the m+1 working period.

[0017] The input signal of the module 003 is the input signal X of the whole CTDSM circuit. The input of the first unit period delay module is connected with the input signal X of the whole CTDSM circuit, and the signal XD1 obtained by delaying the signal X by 1 unit period is obtained; the input of the second unit period delay module is connected with XD1, and the signal XD2 obtained by delaying the signal X by 2 unit periods is obtained; …, the input of the m-n unit period delay module is connected with XD m-n-1 , and the signal XD m-n obtained by delaying the signal X by m-n unit periods is obtained.

[0018] And a coarse ADC is connected after each unit period delay module, and the quantized signals COA1 to COA m-n are obtained in sequence one by one corresponding to XD1 to XDm-n .

[0019] The input of the summer SUMMER0 is the quantized signals COA1 to COA m-n The quantized signals COA1 to COA m-n The output of the summer SUMMER0 is divided into two paths, the first path C1 is connected to the input of the module 002 (adder ADDER0) and the second path C2 is connected to the input of the summer SUMMER1 in the module 006.

[0020] The module 004 is composed of m unit period delay modules (Z -1 ) connected in sequence, which forms a delay circuit with m delay periods. The input of the module 004 is the output signal Y of the whole CTDSM circuit. The signal Y is delayed by the module 004 with m-n+1 to m unit period delays. After the m-n+1 unit period delay module, the signal Y is output as the signal D m-n+1 with m-n+1 delay periods; after the m-1 unit period delay module, the signal Y is output as the signal D m-1 with m-1 delay periods; and after the m unit period delay module, the signal Y is output as the signal D m with m delay periods. The output signals D m of the module 004 are also connected to the input of the module 001 (adder ADDERx). The function of the module 004 is to delay the input signal Y with m-n+1 to m unit period delays and output the signals D m-n+1 to D m .

[0021] The module 005 is composed of m channels of TIADCs. The input of the module 005 is the output of the module 002 and the output of the module 005 is connected to the input of the module 006.

[0022] The module 006 is composed of m-n unit period delay modules and a summer SUMMER1. The m-n unit period delay modules are connected in sequence, which forms a delay path with m-n delay periods.

[0023] The delay path delays the signal Y with 1 to m-n unit period delays. The input of the first unit period delay module is the signal Y and the output is the signal D1 which is the signal Y delayed by 1 unit period; the input of the second unit period delay module is the signal D1 and the output is the signal D2 which is the signal Y delayed by 2 unit periods; and so on. The input of the m-n unit period delay module is the signal D m-n-1 and the output is the signal D m-n which is the signal Y delayed by m-n unit periods.

[0024] The input of the summer SUMMER1 (the input of module 006) is connected with the output signal A of module 005, the 2nd output signal C2 of module 003 and the signals D1 to Dm of the delay path. m-n The signals A, C2 and D1 to Dm are summed up by the summer SUMMER1. The output of the summer SUMMER1 is the output signal Y of the whole CTDSM circuit. m-n

[0025] Further, the module 002 performs difference operation between the output signal of module 001 and the signal C1 to obtain the output of ADDER0, then performs difference operation between the output signal of ADDER0 and the signal D1 to obtain the output of ADDER1, then performs difference operation between the output signal of ADDER1 and the signal D2 to obtain the output of ADDER2, and repeats the above steps until the output of ADDERn is obtained. The output signal of ADDERn is the output signal of module 002, which is connected with the input of module 005. m m-1

[0026] Further, the loop filter adopts the cascade integrator with feedback CIFB or the cascade integrator with feedforward CIFF.

[0027] From the working principle of TIADC, it is assumed that the TIADC has m channels. When the sampling in the (m+1)th period is performed, in the CTDSM circuit, if the quantization result of the CTDSM corresponding to the channel p (p is a positive integer and p≤m) is to be fed back to the input or output of the TIADC, it can be equivalent to feed back the output signal of the whole CTDSM circuit in the pth period to the input or output of the TIADC, that is, to feed back the output signal Y of the whole CTDSM circuit after being delayed for (m-p+1) unit periods to the input or output of the TIADC, so that the feedback operation of the quantization results among the channels of the TIADC can be converted into the delay feedback operation of the output signal Y of the whole CTDSM circuit.

[0028] According to the present application, the output signal Y of the CTDSM is delayed for (m-n+1) unit periods, and the quantization result of the CTDSM corresponding to the channel which has been completely quantized in the current working period is fed back to the input of the TIADC in the analog domain, that is, the delayed signal Dm-n+1 to Dm of the signal Y is obtained by delaying the signal Y for (m-n+1) unit periods. m-n+1 m ​​​​The output signal Y of the CTDSM is delayed by 1 to m unit cycle delays, the quantization results of the CTDSM corresponding to the first n channels which have been completely quantized are fed back to the input end of the TIADC, and the quantization results of the CTDSM corresponding to the channels which have not been completely quantized are fed back to the output end of the TIADC to compensate for the overloop delay. m-n The output signal Y of the CTDSM is delayed by 1 to m unit cycle delays, the quantization results of the CTDSM corresponding to the first n channels which have been completely quantized are fed back to the input end of the TIADC, and the quantization results of the CTDSM corresponding to the channels which have not been completely quantized are fed back to the output end of the TIADC to compensate for the overloop delay. m-n The output signal Y of the CTDSM is delayed by 1 to m unit cycle delays, the quantization results of the CTDSM corresponding to the first n channels which have been completely quantized are fed back to the input end of the TIADC, and the quantization results of the CTDSM corresponding to the channels which have not been completely quantized are fed back to the output end of the TIADC to compensate for the overloop delay.

[0029] In summary, the output signal Y of the CTDSM is delayed by 1 to m unit cycle delays, the quantization results of the CTDSM corresponding to the first n channels which have been completely quantized are fed back to the input end of the TIADC, and the quantization results of the CTDSM corresponding to the channels which have not been completely quantized are fed back to the output end of the TIADC to compensate for the overloop delay. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The first order CTDSM circuit with overloop delay is shown in Fig. 1. d The first order CTDSM circuit with overloop delay is shown in Fig. 1.

[0031] Figure 2 The first order CTDSM circuit with overloop delay is shown in Fig. 1.

[0032] Figure 3 The first order CTDSM circuit with overloop delay is shown in Fig. 1.

[0033] Figure 4 The first order CTDSM circuit with overloop delay is shown in Fig. 1.

[0034] Figure 5A schematic diagram of the loop filter architecture used in the embodiments. DETAILED DESCRIPTION

[0035] The application is further described in detail below with reference to the accompanying drawings and embodiments.

[0036] An arbitrary period over-shoot loop delay compensation CTDSM circuit, as shown in the accompanying Figure 4 , has two period over-shoot loop delays for a 2-channel time-interleaved noise-shaping successive approximation register analog-to-digital converter (TINSSARADC) as the core of the CTDSM in the embodiment. The loop filter architecture used by the CTDSM is a cascade integrator with feed-forward (CIFF) structure, and its system block diagram is shown in the accompanying Figure 5 .

[0037] First, let the input of the CTDSM circuit be signal X, the output of the CTDSM circuit be Y, the input of the TINSSARADC be signal D, the output signal of the TINSSARADC be F, and the quantization noise of the TINSSARADC be E.

[0038] It is known that the sampling expression of the input signal in the first-order CTDSM with a period over-shoot loop delay t d is as follows:

[0039]

[0040] Where τ is the number of periods of the delay, which is a positive integer.

[0041] According to the accompanying Figure 4 , equation 1 is as follows:

[0042]

[0043] Equation 2 is as follows:

[0044]

[0045] D + E·(1-Z -1 ) = F (2)

[0046] Equation 3 is as follows:

[0047] F + X - Y·Z -1 = Y (3)

[0048] Substituting equation 1 and equation 2 into equation 3, we get:

[0049]

[0050] Y = Z -1X+(1-Z -1 ) 2 E

[0051] Finally, the signal transfer function of the CTDSM circuit is Z -1 , and the noise transfer function is (1-Z -1 ) 2 .

[0052] It can be seen from the above embodiment that the output signal Y of the CTDSM is delayed by a number of periods from 1 to m, the CTDSM quantization results corresponding to the first n channels which have been completely quantized are fed back to the input end of the TIADC in an analog domain, the CTDSM quantization results corresponding to the channels which have not been completely quantized are fed back to the output end of the TIADC in a digital domain, then the analog domain output code word A and the digital domain compensation code word (D1-Dm-n) and the signal C2 are summed to obtain the output signal Y of the entire CTDSM circuit, and finally the compensation of the m unit period overflow loop delay is completed, and the circuit timing design difficulty is greatly reduced. The input signal X of the entire CTDSM circuit is summed and connected to the input end of ADDER0 through the delayed signals COA1 to COAm-n which are delayed by a number of unit periods from 1 to m-n, so as to reduce the signal swing input to the input end of the TIADC. The present application effectively compensates for the overflow loop delay of any period in the CTDSM with the TIADC as the quantizer, improves the stability of the CTDSM circuit, and provides support for the development of the CTDSM in the high-speed and high-precision field.

Claims

1. A CTDSM circuit with arbitrary periodic overshoot loop delay compensation, characterized by: The module 001, the module 002, the module 003, the module 004, the module 005 and the module 006 are included. The module 001 comprises three parts of an adder ADDERx, a loop filter and a sampling switch connected in sequence; the adder ADDERx is connected with the input signal X of the whole CTDSM circuit and the output signal D of the module 004 as the input of the module 001 m ; the output of the sampling switch is connected with the input end of the module 002 as the output of the module 001; the module 001 performs difference operation on the input signals X and D m through the adder ADDERx, and realizes discretization through the sampling switch after loop filtering. The module 002 is composed of n+1 adders, the adders are sequentially cascaded from ADDER0 to ADDERn; wherein the input of the adder ADDER0 is connected with the output of the module 001 and the output signal C1 of the module 003, the input of the adder ADDER1 is connected with the output of the ADDER0 and the output signal D of the module 004 m , the input of the adder ADDER2 is connected with the output of the ADDER1 and the output signal D of the module 004 m-1 , ……the input of the adder ADDERn is connected with the output of the ADDERn-1 and the output signal D of the module 004 m-n+1 ; the output of the adder ADDERn is connected with the input of the module 005 as the output of the module 002. The module 003 is composed of m-n unit cycle delay modules, m-n coarse ADCs and a summer SUMMER0; wherein m is the total channel number of the TIADC, and n is the channel number of the TIADC that has been completely quantized at the m+1 working cycle; The input signal of the module 003 is the input signal X of the whole CTDSM circuit; the input of the first unit period delay module is connected with the input signal X of the whole CTDSM circuit, so as to obtain the signal XD1 which is the signal X delayed by one unit period; the input of the second unit period delay module is connected with XD1, so as to obtain the signal XD2 which is the signal X delayed by two unit periods; and the input of the m-nth unit period delay module is connected with XD m-n-1 , so as to obtain the signal XD m-n which is the signal X delayed by m-n unit periods. And after each unit cycle delay module, a coarse ADC is connected to obtain signals XD1 to XD m-n Quantized signals COA1 to COA m-n ; The input of the summer SUMMER0 is the quantized signal COA1 to COA m-n The quantized signal COA1 to COA m-n The output signal C1 and C2 are outputted after summation, wherein the first output signal C1 is connected to the input of the module 002, and the second output signal C2 is connected to the input of the summer SUMMER1 in the module 006. The module 004 is sequentially cascaded by m unit period delay modules to obtain a delay circuit with m delay periods; the input of the module 004 is connected to the output signal Y of the whole CTDSM circuit, and the signal Y is subjected to unit period delay with the number of delay periods increasing from m-n+1 to m; after the m-n+1 unit period delay module, the signal Y obtains an output signal D with m-n+1 delay periods m-n+1 ; after the m-1 unit period delay module, the signal Y obtains an output signal D with m-1 delay periods m-1 ; after the m unit period delay module, the signal Y obtains an output signal D with m delay periods m ; the module 004 subjects the input signal Y to unit period delay with the number of delay periods increasing from m-n+1 to m to obtain the output signal D m-n+1 to D m ; The module 005 is composed of m channel TIADCs, the input of the module 005 is connected with the output of the module 002, and the output signal A of the module 005 is connected with the input of the module 006; The module 006 is composed of m-n unit cycle delay modules and a summer SUMMER1, the m-n unit cycle delay modules are sequentially cascaded to obtain a delay path with a delay cycle number of m-n; The delay path delays the signal Y by a unit period from 1 to m-n; the input of the first unit period delay module is connected with the signal Y, and the signal D1 which is the signal Y delayed by one unit period is obtained; the input of the second unit period delay module is connected with the signal D1, and the signal D2 which is the signal Y delayed by two unit periods is obtained; the input of the m-n unit period delay module is connected with the signal D m-n-1 , and the signal D m-n which is the signal Y delayed by m-n unit periods is obtained. The input of the summer SUMMER1 is connected to the output signal A of the module 005, to the second output signal C2 of the module 003 and to the signals D1 to Dn of the delay path output m-n and performs a summation operation on the signals A, C2 and D1 to Dn; the output of the summer SUMMER1 is the output signal Y of the entire CTDSM circuit. m-n and performs a summation operation on the signals A, C2 and D1 to Dn; the output of the summer SUMMER1 is the output signal Y of the entire CTDSM circuit.

2. The CTDSM circuit of claim 1, wherein: The module 002 differentiates the output signal of the module 001 and the C1 signal to obtain the output of ADDER0, and then differentiates the output signal of ADDER0 and the D m signal to obtain the output of ADDER1, and then differentiates the output signal of ADDER1 and the D m-1 signal to obtain the output of ADDER2, and repeats the above steps until the output of ADDERn is obtained. The output signal of ADDERn is the output signal of the module 002, which is connected to the input of the module 005.

3. The CTDSM circuit of claim 1, wherein: The loop filter adopts a cascaded integrator with feedback CIFB or a cascaded integrator with feedforward CIFF.

4. The CTDSM circuit for arbitrary period overshoot loop delay compensation as described in claim 1, characterized in that: The coarse ADC is implemented by using a flash ADC.

5. The CTDSM circuit of claim 1, wherein, The specific engineering process is as follows: At the m+1 cycle sampling, the channel number of the TIADC that has been completely quantized is n. The m-n channels, channel 1 to channel m-n, are connected to the inputs of ADDER0 summed with the input signal of the CTDSM corresponding to the sampling time, i.e. the input signal X of the entire CTDSM circuit is delayed by a unit period from 1 to m-n to obtain the delayed quantized signal COA1 to COA m-n are connected to the inputs of ADDER0 summed, to limit the signal swing to the input of the TI ADC; The CTDSM quantization result corresponding to the channel which has been completely quantized in the current working period is fed back to the input end of the TIADC in the analog domain, that is, the signal Y is delayed by the delay signal D obtained by increasing the unit period from m-n+1 to m m-n+1 to D m the input end of the TIADC; Meanwhile, the CTDSM quantization result corresponding to the channel which is not quantized completely in the current working period is fed back to the output end of the TIADC in the form of digital domain, that is, the delay signals D1 to Dm-n obtained by delaying the signal Y by unit period from 1 to m-n m-n to the output end of the TIADC; the summer SUMMER1 of module 006 performs summation operation on the signal A, the signal C2 and the delay signals D1 to Dm-n; and the output of the summer SUMMER1 is the output signal Y of the whole CTDSM circuit. m-n to the output end of the TIADC; the summer SUMMER1 of module 006 performs summation operation on the signal A, the signal C2 and the delay signals D1 to Dm-n; and the output of the summer SUMMER1 is the output signal Y of the whole CTDSM circuit.

Images