Coding and decoding method and device

Abstract

The invention provides a coding and decoding method and device, and relates to the technical field of media, and the coding method comprises the steps: carrying out the coding operation of a plurality of display images and a plurality of CRR images, so as to obtain a code stream. And authenticating the to-be-authenticated data according to the first information to obtain first tree top abstract data. And performing signature calculation on the first tree top abstract data according to the second information to obtain a digital signature. And packaging the digital signature into an authentication data set. Wherein the code stream comprises a security parameter set and an authentication data set, the security parameter set comprises first information and second information, the first information is used for representing an algorithm adopted for generating a tree top abstract, and the second information is used for representing an algorithm adopted for performing digital signature. The first tree top summary data is the tree top summary data of the coding end, the first tree top summary data comprises the tree top summary data of N main bit streams and / or M CRR slice bit streams, and N and M are positive integers.

Description

[0001] This application is a divisional application. The application number of the original application is 202311138721.4, and the original application date is September 1, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of media technology, and in particular to a coding and decoding method and device. Background Art

[0003] The third generation audio and video coding standard (AVS3) proposes a cross random access point reference (CRR) coding and decoding scheme based on library pictures. This scheme obtains the library picture from the existing video. The system layer is provided with a long term buffer for storing the reconstructed knowledge base picture. The reconstructed knowledge base picture at the encoding end is obtained by encoding the knowledge base picture, and the reconstructed knowledge base picture at the decoding end is obtained by decoding the knowledge base picture bit stream (i.e., CRR slice bit stream). When encoding the video sequence, the reconstructed knowledge base picture corresponding to the current frame is obtained from the long term buffer, and the reconstructed knowledge base is used as the reference picture to perform inter-frame prediction coding on the current frame, thereby obtaining the video bit stream and the knowledge base picture bit stream corresponding to each reconstructed knowledge base picture used in the encoding. The video bit stream includes a reference picture mark for each frame, and the reference picture mark indicates whether the reconstructed knowledge base picture is used as the reference picture when encoding the frame. The system layer of the decoder decodes each knowledge base image bit stream and stores the obtained reconstructed knowledge base image in the long-term buffer. When the decoder decodes the current image bit stream, it obtains the corresponding reconstructed knowledge base image from the long-term buffer and uses the reconstructed knowledge base as a reference image to perform inter-frame prediction decoding on the current video bit stream.

[0004] With the rapid development of network video surveillance technology, data security issues are becoming increasingly prominent. Therefore, how to improve the security of the CRR media content transmission process is one of the problems that technicians in this field need to solve urgently. Summary of the invention

[0005] The embodiment of the present application provides a coding method and a device, which can improve the security of the CRR media content transmission process. To achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a coding method, the method comprising: performing a coding operation on a plurality of display images and the plurality of CRR images to obtain a code stream. Authenticating the data to be authenticated according to the first information to obtain first tree-top summary data. Performing a signature calculation on the first tree-top summary data according to the second information to obtain a digital signature. Encapsulating the digital signature into an authentication data set. The code stream comprises a security parameter set and an authentication data set, the security parameter set comprises first information and second information, the first information is used to indicate an algorithm used to generate a tree-top summary, and the second information is used to indicate an algorithm used to perform a digital signature. The first tree-top summary data is the tree-top summary data of the encoding end, and the first tree-top summary data comprises tree-top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0007] It can be seen that the method provided in the embodiment of the present application can perform signature authentication on the main bit stream obtained by display image encoding and / or the slice bit stream obtained by CRR image encoding, so that the receiving end can determine the integrity and authenticity of the transmitted bit stream based on the signature authentication data, thereby improving the security of the CRR media content transmission process.

[0008] In addition, in some online scenarios / offline storage scenarios, the location of the CRR slices may change flexibly, and the authentication operation is strongly related to the location and order of the network abstraction layer. If the CRR slices are not independently authenticated at this time, it is very likely that the encoding and decoding ends will fail to pass the signature verification. However, using the embodiment of the present application, the CRR bit stream can be authenticated separately, thereby avoiding the problem that the encoding and decoding ends cannot pass the signature verification due to the inability to authenticate the CRR bit stream separately.

[0009] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0010] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag=0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag=1 indicates that the current authentication data belongs to a CRR slice, and all CRR slices are constrained to be authenticated.

[0011] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0012] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0013] In a possible implementation, the authentication data set further includes fifth information, and the fifth information is used to indicate a CRR image corresponding to an authentication range of the specified current authentication data set.

[0014] Exemplarily, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to which CRR image the authentication range of the current authentication data set belongs. This parameter can be parsed only when is_crr_flag=1.

[0015] In a possible implementation, the data signature may be encoded; and the encoded data signature may be encapsulated into the authentication data set.

[0016] Exemplarily, the data signature may be Base64 encoded, and the Base64 encoded data signature may be encapsulated into the authentication data set.

[0017] In a possible implementation, the CRR image may be segmented to obtain a plurality of CRR slices; the plurality of CRR slices may be interleaved and arranged between the plurality of display images to obtain a sequence of images to be encoded; and the CRR slices and the display images in the sequence of images to be encoded may be encoded in sequence to obtain the code stream.

[0018] In a possible implementation, the code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

[0019] It should be noted that encoding the display image and the CRR image into the same code stream can reduce the design and deployment cost of the overall encoding and decoding system.

[0020] In a second aspect, the present application provides a decoding method, the method comprising: obtaining a code stream, the code stream being obtained by encoding multiple display images and multiple CRR images, the code stream comprising a security parameter set and an authentication data set, the security parameter set comprising first information and second information, the first information being used to indicate an algorithm used to generate a tree top summary, the second information being used to indicate an algorithm used to perform a digital signature, and the authentication data set comprising a digital signature. Decoding the digital signature according to the second information to obtain first tree top summary data, the first tree top summary data being tree top summary data of an encoding end, the first tree top summary data comprising tree top summary data of N main bit streams and / or M CRR slice bit streams, N and M being positive integers. Authenticating authentication data corresponding to the authentication data set according to the first information to obtain second tree top summary data, the second tree top summary data being tree top summary data of a decoding end, the first tree top summary data comprising tree top summary data of N main bit streams and / or M CRR slice bit streams. Verifying the authentication data according to the first tree top summary and the second tree top summary data.

[0021] In a possible implementation, the digital signature may be decoded; and the decoded digital signature may be decoded according to the second information to obtain the first tree top summary data.

[0022] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0023] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0024] In a third aspect, the present application provides an encoding method, the method comprising: performing encoding operations on multiple display images and the multiple CRR images to obtain a bitstream, the bitstream comprising a security parameter set, the security parameter set comprising a video encryption key, and encrypting the bitstream according to the video encryption key.

[0025] In a possible implementation, the payload data of the code stream may be encrypted according to the video encryption key, where the payload data includes at least one of a sequence parameter set SPS, a picture parameter set PPS, a main bitstream, and a CRR slice bitstream.

[0026] In a fourth aspect, the present application provides a decoding method, which includes: obtaining a code stream, the code stream is obtained by encoding multiple display images and the multiple CRR images, the code stream includes a security parameter set, and the security parameter set includes a video encryption key; decrypting the code stream according to the video encryption key; and determining a reconstructed image based on the decoded code stream.

[0027] In a possible implementation, the payload data of the code stream may be decrypted according to the video encryption key, where the payload data includes at least one of an SPS, a PPS, a main bit stream, and a CRR slice bit stream.

[0028] In a fifth aspect, the present application provides an encoding device, which includes: an encoding unit and an authentication unit. The encoding unit is used to perform encoding operations on multiple display images and the above-mentioned multiple CRR images to obtain a code stream, the above-mentioned code stream includes a security parameter set and an authentication data set, the above-mentioned security parameter set includes first information and second information, the above-mentioned first information is used to indicate the algorithm used to generate the tree top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature. The authentication unit is used to authenticate the data to be authenticated according to the above-mentioned first information to obtain first tree top summary data, the above-mentioned first tree top summary data is the tree top summary data of the encoding end, and the above-mentioned first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, N and M are positive integers. The authentication unit is also used to perform signature calculation on the above-mentioned first tree top summary data according to the above-mentioned second information to obtain a digital signature. The authentication unit is also used to encapsulate the above-mentioned digital signature into the above-mentioned authentication data set.

[0029] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0030] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag=0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag=1 indicates that the current authentication data belongs to a CRR slice, and all CRR slices are constrained to be authenticated.

[0031] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0032] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0033] In a possible implementation, the authentication data set further includes fifth information, and the fifth information is used to indicate a CRR image corresponding to an authentication range of the specified current authentication data set.

[0034] Exemplarily, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to which CRR image the authentication range of the current authentication data set belongs. This parameter can be parsed only when is_crr_flag=1.

[0035] In a possible implementation, the authentication unit is specifically used to: encode the data signature; and encapsulate the encoded data signature into the authentication data set.

[0036] In a possible implementation, the encoding unit is specifically used to: divide the above-mentioned CRR image to obtain multiple CRR slices; interleave the above-mentioned multiple CRR slices between the above-mentioned multiple display images to obtain a sequence of images to be encoded; and sequentially encode the above-mentioned CRR slices and the above-mentioned display images in the above-mentioned sequence of images to be encoded to obtain the above-mentioned code stream.

[0037] In a possible implementation, the code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

[0038] In a sixth aspect, the present application provides a decoding device, which includes: a transceiver unit and an authentication unit. The transceiver unit is used to obtain a code stream, the code stream includes a security parameter set and an authentication data set, the security parameter set includes first information and second information, the first information is used to indicate the algorithm used to generate the tree top summary, the second information is used to indicate the algorithm used to perform the digital signature, and the authentication data set includes a digital signature. The authentication unit is used to decode the digital signature according to the second information to obtain first tree top summary data, the first tree top summary data is the tree top summary data of the encoding end, the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, N and M are positive integers. The authentication unit is also used to authenticate the authentication data corresponding to the authentication data set according to the first information to obtain second tree top summary data, the second tree top summary data is the tree top summary data of the decoding end, and the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams. The authentication unit is further used to verify the authentication data according to the first tree top summary and the second tree top summary data.

[0039] In a possible implementation manner, the authentication unit is specifically configured to: decode the digital signature; and decode the decoded digital signature according to the second information to obtain the first tree top summary data.

[0040] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0041] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0042] In a seventh aspect, the present application provides an encoding device, comprising: an encoding unit and an encryption unit. The encoding unit is used to perform an encoding operation on multiple display images and the multiple CRR images to obtain a code stream, wherein the code stream includes a security parameter set, and the security parameter set includes a video encryption key. The encryption unit is used to encrypt the code stream according to the video encryption key.

[0043] In a possible implementation, the encryption unit is specifically used to: encrypt the payload data of the above-mentioned code stream according to the above-mentioned video encryption key, and the above-mentioned payload data includes at least one of the sequence parameter set SPS, the picture parameter set PPS, the main bit stream and the CRR slice bit stream.

[0044] In an eighth aspect, the present application provides a decoding device, the device comprising: a transceiver unit, a decryption unit and a reconstruction unit. The transceiver unit is used to obtain a bitstream, the bitstream includes a security parameter set, and the security parameter set includes a video encryption key. The decryption unit is used to decrypt the bitstream according to the video encryption key. The reconstruction unit is used to determine a reconstructed image according to the decoded bitstream.

[0045] In a possible implementation, the decryption unit is specifically used to: decrypt the payload data of the code stream according to the video encryption key, and the payload data includes at least one of SPS, PPS, main bit stream and CRR slice bit stream.

[0046] In the ninth aspect, the present application provides a coding device, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by one or more processors, the one or more processors implement a method as described in any one of the first aspects.

[0047] In the tenth aspect, the present application provides a decoding device, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by the one or more processors, the one or more processors implement the method as described in any one of the second aspects.

[0048] In an eleventh aspect, an embodiment of the present application further provides a chip, comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is used to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.

[0049] Optionally, the above chip may also be an integrated circuit.

[0050] In a twelfth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, wherein the computer program includes methods for implementing the method described in the above-mentioned first aspect or any possible implementation thereof.

[0051] In a thirteenth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the first aspect or any possible implementation thereof.

[0052] In a fourteenth aspect, the present application provides an electronic device, comprising: a processing circuit and an interface circuit; wherein the interface circuit is used to couple with a memory outside the encoding and decoding device and provide a communication interface for the processing circuit to access the memory; the processing circuit is used to execute program instructions in the memory to implement the method described in the first aspect or any possible implementation thereof.

[0053] In the specific implementation process, the electronic device may be a chip, the input circuit may be an input pin, the output circuit may be an output pin, and the processing circuit may be a transistor, a gate circuit, a trigger, and various logic circuits. The input signal received by the input circuit may be received and input by, for example, but not limited to, a receiver, and the signal output by the output circuit may be, for example, but not limited to, output to a transmitter and transmitted by the transmitter, and the input circuit and the output circuit may be the same circuit, which is used as an input circuit and an output circuit at different times. The embodiments of the present application do not limit the specific implementation methods of the processor and various circuits.

[0054] In one implementation, the electronic device may be a wireless communication device, that is, a computer device that supports wireless communication functions. Specifically, the wireless communication device may be a terminal such as a smart phone, or a wireless access network device such as a base station. The system chip may also be referred to as a system on chip (SoC), or simply as an SoC chip. The communication chip may include a baseband processing chip and a radio frequency processing chip. The baseband processing chip is sometimes also referred to as a modem or a baseband chip. The radio frequency processing chip is sometimes also referred to as a radio frequency transceiver or a radio frequency chip. In a physical implementation, some or all of the chips in the communication chip may be integrated inside the SoC chip. For example, the baseband processing chip is integrated in the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip. The interface circuit may be a radio frequency processing chip in a wireless communication device, and the processing circuit may be a baseband processing chip in a wireless communication device.

[0055] In another implementation, the electronic device may be a part of a wireless communication device, such as an integrated circuit product such as a system chip or a communication chip. The interface circuit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip or the chip system. The processor may also be embodied as a processing circuit or a logic circuit.

[0056] The encoding and decoding device, computer storage medium, computer program product and chip provided in this embodiment are all used to execute the encoding and decoding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the encoding and decoding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1a An exemplary block diagram of a decoding system provided in an embodiment of the present application;

[0058] Figure 1b An exemplary block diagram of a video decoding system provided in an embodiment of the present application;

[0059] Figure 2 An exemplary block diagram of a video encoder provided in an embodiment of the present application;

[0060] Figure 3 An exemplary block diagram of a video decoder provided in an embodiment of the present application;

[0061] Figure 4 An exemplary schematic diagram of a candidate image block provided in an embodiment of the present application;

[0062] Figure 5 An exemplary block diagram of a video decoding device provided in an embodiment of the present application;

[0063] Figure 6 An exemplary block diagram of a device provided in an embodiment of the present application;

[0064] Figure 7 A schematic diagram of a video sequence provided in an embodiment of the present application;

[0065] Figure 8 A schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0066] Fig. 9 A schematic diagram of a coding and decoding process provided in an embodiment of the present application;

[0067] Fig.10 A flowchart of a decoding method provided in an embodiment of the present application;

[0068] Fig.11 A schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0069] Fig.12 A flowchart of a decoding method provided in an embodiment of the present application;

[0070] Fig.13 A schematic diagram of the structure of an encoding device provided in an embodiment of the present application;

[0071] Fig.14 A schematic diagram of the structure of a decoding device provided in an embodiment of the present application;

[0072] Fig.15 A schematic diagram of the structure of another encoding device provided in an embodiment of the present application;

[0073] Fig.16 A schematic diagram of the structure of another decoding device provided in an embodiment of the present application;

[0074] Fig.17 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0075] Fig.18 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0077] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0078] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0079] Data encoding and decoding includes two parts: data encoding and data decoding. Data encoding is performed on the source side (or commonly referred to as the encoder side), and generally includes processing (e.g., compressing) the original data to reduce the amount of data required to represent the original data (thereby more efficiently storing and / or transmitting). Data decoding is performed on the destination side (or commonly referred to as the decoder side), and generally includes inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of the data involved in the embodiments of the present application should be understood as the "encoding" or "decoding" of the data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0080] In the case of lossless data encoding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming no transmission loss or other data loss during storage or transmission). In the case of lossy data encoding, further compression is performed by quantization, etc. to reduce the amount of data required to represent the original data, but the decoder side cannot completely reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than the quality of the original data.

[0081] The embodiments of the present application can be applied to video data and other data with compression / decompression requirements. The following takes the encoding of video data (referred to as video encoding) as an example to illustrate the embodiments of the present application. Other types of data (such as image data, audio data, integer data and other data with compression / decompression requirements) can refer to the following description, and the embodiments of the present application will not be repeated. It should be noted that, compared with video encoding, the encoding process of audio data and integer data does not need to divide the data into blocks, but the data can be directly encoded.

[0082] Video coding generally refers to processing a sequence of images to form a video or video sequence. In the field of video coding, the terms "picture", "frame" or "image" can be used as synonyms.

[0083] Several video coding standards belong to the category of "lossy hybrid video codecs" (i.e., combining spatial and temporal prediction in the pixel domain with 2D transform coding in the transform domain for applying quantization). Each image in a video sequence is usually divided into a set of non-overlapping blocks, which are usually encoded at the block level. In other words, the encoder usually processes, i.e., encodes the video at the block (video block) level, for example, by generating a prediction block through spatial (intra-frame) prediction and temporal (inter-frame) prediction; subtracting the prediction block from the current block (currently processed / to be processed block) to obtain a residual block; transforming the residual block in the transform domain and quantizing the residual block to reduce the amount of data to be transmitted (compressed), while the decoder side applies the inverse processing part relative to the encoder to the encoded or compressed block to reconstruct the current block for representation. In addition, the encoder needs to repeat the processing steps of the decoder so that the encoder and the decoder generate the same predictions (e.g., intra-frame predictions and inter-frame predictions) and / or reconstructed pixels for processing, i.e., encoding subsequent blocks.

[0084] In the following embodiment of the decoding system 10, the encoder 20 and the decoder 30 are based on Figures 1a to 3 Give a description.

[0085] Figure 1a An exemplary block diagram of a decoding system 10 provided in an embodiment of the present application, for example, a video decoding system 10 (or simply a decoding system 10) that can utilize the techniques of the embodiments of the present application. The video encoder 20 (or simply an encoder 20) and the video decoder 30 (or simply a decoder 30) in the video decoding system 10 represent devices that can be used to perform various techniques according to various examples described in the embodiments of the present application.

[0086] like Figure 1a As shown, the decoding system 10 includes a source device 12, which is used to provide encoded image data 21 such as encoded images to a destination device 14 for decoding the encoded image data 21.

[0087] The source device 12 includes an encoder 20 , and may additionally or optionally include an image source 16 , a preprocessor (or a preprocessing unit) 18 such as an image preprocessor, and a communication interface (or a communication unit) 22 .

[0088] The image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer-animated images or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images). The above-mentioned image source may be any type of memory or storage for storing any of the above-mentioned images.

[0089] In order to distinguish the processing performed by the pre-processor (or pre-processing unit) 18 , the image (or image data) 17 may also be referred to as a raw image (or raw image data) 17 .

[0090] The preprocessor 18 is used to receive the original image data 17 and preprocess the original image data 17 to obtain a preprocessed image (or preprocessed image data) 19. For example, the preprocessing performed by the preprocessor 18 may include trimming, color format conversion (e.g., from RGB to YCbCr), color adjustment, or denoising. It is understood that the preprocessing unit 18 may be an optional component.

[0091] The video encoder (or encoder) 20 is used to receive the pre-processed image data 19 and provide the encoded image data 21 (hereinafter referred to as Figure 2 etc. for further description).

[0092] The communication interface 22 in the source device 12 can be used to receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device through the communication channel 13 for storage or direct reconstruction.

[0093] The destination device 14 includes a decoder 30 and, in addition or alternatively, may include a communication interface (or communication unit) 28 , a post-processor (or post-processing unit) 32 , and a display device 34 .

[0094] The communication interface 28 in the destination device 14 is used to receive the encoded image data 21 (or any other processed version) directly from the source device 12 or from any other source device such as a storage device, for example, the storage device is a encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0095] The communication interface 22 and the communication interface 28 can be used to send or receive encoded image data (or encoded data) 21 through a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, or through any type of network, such as a wired network, a wireless network or any combination thereof, any type of private network and public network or any type of combination thereof.

[0096] For example, the communication interface 22 may be used to encapsulate the encoded image data 21 into a suitable format such as a message, and / or use any type of transmission coding or processing to process the encoded image data for transmission over a communication link or network.

[0097] The communication interface 28 corresponds to the communication interface 22 , for example, and can be used to receive transmission data and process the transmission data using any type of corresponding transmission decoding or processing and / or decapsulation to obtain the encoded image data 21 .

[0098] Both the communication interface 22 and the communication interface 28 can be configured as follows Figure 1a A unidirectional communication interface, or a bidirectional communication interface, indicated by an arrow pointing from the source device 12 to the corresponding communication channel 13 of the destination device 14, and can be used to send and receive messages, etc. to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as encoded image data transmission, etc.

[0099] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide decoded image data (or decoded image data) 31 (hereinafter referred to as Figure 3 etc. for further description).

[0100] The post-processor 32 is used to post-process the decoded image data 31 (also called reconstructed image data) such as the decoded image to obtain the post-processed image data 33 such as the post-processed image. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., from YCbCr to RGB), color adjustment, cropping or resampling, or any other processing for generating the decoded image data 31 for display by the display device 34 or the like.

[0101] The display device 34 is used to receive the post-processed image data 33 to display the image to a user or viewer, etc. The display device 34 can be or include any type of display for displaying the reconstructed image, such as an integrated or external display screen or display. For example, the display screen can include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), a digital light processor (DLP), or any other type of display screen.

[0102] The decoding system 10 also includes a training engine 25, which is used to train the encoder 20 (especially the entropy coding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy coding on the image block to be encoded according to the estimated probability distribution. For a detailed description of the training engine 25, please refer to the following method test example.

[0103] although Figure 1a The source device 12 and the destination device 14 are shown as independent devices, but the device embodiment may also include the source device 12 and the destination device 14 or the functions of the source device 12 and the destination device 14 at the same time, that is, the source device 12 or the corresponding function and the destination device 14 or the corresponding function at the same time. In these embodiments, the source device 12 or the corresponding function and the destination device 14 or the corresponding function can be implemented using the same hardware and / or software or by separate hardware and / or software or any combination thereof.

[0104] According to the description, Figure 1a The presence and (exact) division of different units or functions in the source device 12 and / or the destination device 14 shown may vary depending on the actual device and application, which will be obvious to the skilled person.

[0105] Please refer to Figure 1b , Figure 1b An exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application, wherein the encoder 20 (eg, the video encoder 20) or the decoder 30 (eg, the video decoder 30) or both may be configured as follows: Figure 1bThe processing circuitry in the video decoding system 40 shown may be implemented, for example, by one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding dedicated processors, or any combination thereof. Figure 2 and Figure 3 , Figure 2 An exemplary block diagram of a video encoder provided in an embodiment of the present application is shown in FIG. Figure 3 An exemplary block diagram of a video decoder provided in an embodiment of the present application. The encoder 20 may be implemented by a processing circuit 46 to include a reference Figure 2 The various modules discussed in encoder 20 and / or any other encoder system or subsystem described herein. Decoder 30 may be implemented by processing circuit 46 to include reference Figure 3 The various modules discussed in the decoder 30 and / or any other decoder systems or subsystems described herein. The processing circuitry 46 described above may be used to perform the various operations discussed below. Figure 5 As shown, if part of the technology is implemented in software, the device can store the software instructions in a suitable non-transitory computer-readable storage medium, and use one or more processors to execute the instructions in hardware, thereby performing the technology of the embodiment of the present application. One of the video encoder 20 and the video decoder 30 can be integrated into a single device as part of a combined codec (encoder / decoder, CODEC), such as Figure 1b shown.

[0106] The source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or fixed device, such as a notebook or laptop computer, a mobile phone, a smart phone, a tablet or a tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may not use or use any type of operating system. The source device 12 and the destination device 14 may also be devices in a cloud computing scenario, such as a virtual machine in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 may be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.

[0107] The source device 12 and the destination device 14 may install virtual scene applications (applications, APPs) such as virtual reality (VR) applications, augmented reality (AR) applications, or mixed reality (MR) applications, and may run VR applications, AR applications, or MR applications based on user operations (such as clicks, touches, slides, shakes, voice control, etc.). The source device 12 and the destination device 14 may collect images / videos of any object in the environment through cameras and / or sensors, and then display virtual objects on the display device based on the collected images / videos. The virtual objects may be virtual objects in VR scenes, AR scenes, or MR scenes (i.e., objects in the virtual environment).

[0108] It should be noted that in the embodiment of the present application, the virtual scene application in the source device 12 and the destination device 14 can be a built-in application of the source device 12 and the destination device 14 themselves, or it can be an application provided by a third-party service provider and installed by the user. There is no specific limitation on this.

[0109] In addition, the source device 12 and the destination device 14 may be installed with a real-time video transmission application, such as a live broadcast application. The source device 12 and the destination device 14 may collect images / videos through cameras and then display the collected images / videos on a display device.

[0110] In some cases, Figure 1a The video decoding system 10 shown is merely exemplary, and the techniques provided in the embodiments of the present application may be applicable to video encoding settings (e.g., video encoding or video decoding), which do not necessarily include any data communication between the encoding device and the decoding device. In other examples, the data is retrieved from a local memory, sent over a network, and so on. The video encoding device can encode the data and store the data in a memory, and / or the video decoding device can retrieve the data from the memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but only encode data to a memory and / or retrieve and decode data from a memory.

[0111] Please refer to Figure 1b , Figure 1b An exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application is shown in FIG. Figure 1b As shown, the video decoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder / decoder implemented by a processing circuit 46), an antenna 42, one or more processors 43, one or more memory storages 44 and / or a display device 45.

[0112] like Figure 1b As shown, imaging device 41, antenna 42, processing circuit 46, video encoder 20, video decoder 30, processor 43, memory storage 44 and / or display device 45 can communicate with each other. In different examples, video decoding system 40 can include only video encoder 20 or only video decoder 30.

[0113] In some instances, antenna 42 may be used to transmit or receive a coded bit stream of video data. In addition, in some instances, display device 45 may be used to present video data. Processing circuit 46 may include application-specific integrated circuit (ASIC) logic, graphics processor, general purpose processor, etc. Video decoding system 40 may also include an optional processor 43, which may similarly include application-specific integrated circuit (ASIC) logic, graphics processor, general purpose processor, etc. In addition, memory storage 44 may be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In a non-limiting example, memory storage 44 may be implemented by cache memory. In other instances, processing circuit 46 may include memory (e.g., cache, etc.) for implementing image buffers, etc.

[0114] In some examples, video encoder 20 implemented by logic circuits may include an image buffer (e.g., implemented by processing circuit 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuit 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video encoder 20 implemented by processing circuit 46 to implement reference Figure 2 and / or the various modules discussed in connection with any other encoder system or subsystem described herein. Logic circuits may be used to perform the various operations discussed herein.

[0115] In some examples, video decoder 30 may be implemented in a similar manner by processing circuitry 46 to implement reference Figure 3The various modules discussed in connection with video decoder 30 and / or any other decoder system or subsystem described herein may be included in the video decoder 30 implemented by logic circuitry. In some examples, video decoder 30 implemented by logic circuitry may include an image buffer (implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (implemented by processing circuitry 46, for example). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video decoder 30 implemented by processing circuitry 46 to implement the video decoder 30 implemented by processing circuitry 46. Figure 3 and / or the various modules discussed above for any other decoder system or subsystem described herein.

[0116] In some examples, antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data related to the encoded video frames discussed herein, indicators, index values, mode selection data, etc., such as data related to the encoded partitions (e.g., transform coefficients or quantized transform coefficients, (as discussed) optional indicators, and / or data defining the encoded partitions). Video decoding system 40 may also include video decoder 30 coupled to antenna 42 and used to decode the encoded bitstream. Display device 45 is used to present the video frames.

[0117] It should be understood that for the examples described with reference to the video encoder 20 in the embodiments of the present application, the video decoder 30 can be used to perform the reverse process. With respect to the signaling syntax elements, the video decoder 30 can be used to receive and parse such syntax elements and decode the related video data accordingly. In some examples, the video encoder 20 can entropy encode the syntax elements into an encoded video bitstream. In such examples, the video decoder 30 can parse such syntax elements and decode the related video data accordingly.

[0118] For ease of description, the embodiments of the present application are described with reference to the universal video coding (VVC) reference software or the high-efficiency video coding (HEVC) developed by the video coding joint working group (joint collaboration team on video coding, JCT-VC) of the ITU-T video coding experts group (VCEG) and the ISO / IEC motion picture experts group (MPEG). Those of ordinary skill in the art understand that the embodiments of the present application are not limited to HEVC or VVC.

[0119] Encoders and encoding methods

[0120] like Figure 2As shown, the video encoder 20 includes an input terminal (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy coding unit 270, and an output terminal (or output interface) 272. The mode selection unit 260 may include an inter-frame prediction unit 244, an intra-frame prediction unit 254, and a segmentation unit 262. The inter-frame prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). Figure 2 The illustrated video encoder 20 may also be referred to as a hybrid video encoder or a hybrid video codec-based video encoder.

[0121] See also Figure 2 The inter-frame prediction unit is a trained target model (also called a neural network) that processes an input image or an image region or an image block to generate a prediction value of the input image block. For example, the neural network for inter-frame prediction is used to receive an input image or an image region or an image block, and generate a prediction value of the input image or an image region or an image block.

[0122] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208 and the mode selection unit 260 constitute the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter-frame prediction unit 244 and the intra-frame prediction unit 254 constitute the backward signal path of the encoder, wherein the backward signal path of the encoder 20 corresponds to the signal path of the decoder (see Figure 3 The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded image buffer 230, the inter-frame prediction unit 244 and the intra-frame prediction unit 254 also constitute a “built-in decoder” of the video encoder 20.

[0123] Images and Image Segmentation (Images and Blocks)

[0124] The encoder 20 may be configured to receive, via an input 201 or the like, an image (or image data) 17, e.g., an image in a sequence of images forming a video or a video sequence. The received image or image data may also be a pre-processed image (or pre-processed image data) 19. For simplicity, the following description uses image 17. Image 17 may also be referred to as a current image or an image to be encoded (particularly when the current image is to be distinguished from other images in video encoding, such as previously encoded images and / or decoded images in the same video sequence, i.e., a video sequence also including the current image).

[0125] A (digital) image is or can be considered as a two-dimensional array or matrix of pixels with intensity values. The pixels in the array can also be called pixels (pixel or pel) (short for picture elements). The number of pixels in the array or image in the horizontal and vertical directions (or axes) determines the size and / or resolution of the image. In order to represent color, three color components are usually used, that is, the image can be represented as or include three pixel arrays. In the RBG format or color space, the image includes corresponding red, green and blue pixel arrays. However, in video coding, each pixel is usually represented in a brightness / chrominance format or color space, such as YCbCr, including a brightness component indicated by Y (sometimes also represented by L) and two chrominance components represented by Cb and Cr. The brightness (luma) component Y represents the brightness or grayscale level intensity (for example, the two are the same in grayscale images), while the two chrominance (abbreviated as chroma) components Cb and Cr represent the chrominance or color information components. Accordingly, an image in YCbCr format includes a luminance pixel array of luminance pixel values ​​(Y) and two chrominance pixel arrays of chrominance values ​​(Cb and Cr). An image in RGB format can be converted or transformed into YCbCr format and vice versa, a process also referred to as color conversion or transformation. If the image is black and white, the image may include only a luminance pixel array. Accordingly, an image may be, for example, a luminance pixel array in a monochrome format or a luminance pixel array and two corresponding chrominance pixel arrays in 4:2:0, 4:2:2 and 4:4:4 color formats.

[0126] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit ( Figure 2), for dividing the image 17 into a plurality of (usually non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC) or coding tree blocks (CTB), or coding tree units (CTU) in the H.265 / HEVC and VVC standards. The partitioning unit may be used to use the same block size for all images in a video sequence and a corresponding grid of defined block sizes, or to change the block size between images or subsets of images or groups of images, and to partition each image into corresponding blocks.

[0127] In other embodiments, the video encoder may be configured to directly receive a block 203 of the image 17, for example, one, several or all blocks constituting the image 17. The image block 203 may also be referred to as a current image block or an image block to be encoded.

[0128] Like image 17, image block 203 is also or can be considered as a two-dimensional array or matrix composed of pixels with intensity values ​​(pixel values), but image block 203 is smaller than image 17. In other words, block 203 may include one pixel array (e.g., a brightness array in the case of monochrome image 17 or a brightness array or chrominance array in the case of a color image) or three pixel arrays (e.g., one brightness array and two chrominance arrays in the case of a color image 17) or any other number and / or type of arrays according to the color format adopted. The number of pixels in the horizontal and vertical directions (or axes) of block 203 defines the size of block 203. Accordingly, the block can be an M×N (M columns×N rows) pixel array, or an M×N transform coefficient array, etc.

[0129] In one embodiment, Figure 2 The video encoder 20 shown is used to encode the image 17 block by block, for example, encoding and prediction are performed on each block 203.

[0130] In one embodiment, Figure 2 The illustrated video encoder 20 may also be used to partition and / or encode an image using slices (also referred to as video slices), wherein an image may be partitioned or encoded using one or more slices (usually non-overlapping). Each slice may include one or more blocks (e.g., coding tree units CTUs) or one or more groups of blocks (e.g., coding tiles in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0131] In one embodiment, Figure 2The video encoder 20 shown can also be used to partition and / or encode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), wherein an image can be partitioned or encoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTU) or one or more coding blocks, etc., wherein each coding block may be in a rectangular shape, etc., and may include one or more complete or partial blocks (e.g., CTU).

[0132] Residual calculation

[0133] The residual calculation unit 204 is used to calculate the residual block 205 (the prediction block 265 is described in detail later) based on the image block (or original block) 203 and the prediction block 265 in the following manner: for example, the pixel value of the prediction block 265 is subtracted from the pixel value of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0134] Transform

[0135] The transform processing unit 206 is used to perform discrete cosine transform (DCT) or discrete sine transform (DST) on the pixel values ​​of the residual block 205 to obtain transform coefficients 207 in the transform domain. The transform coefficients 207 may also be called transform residual coefficients, representing the residual block 205 in the transform domain.

[0136] The transform processing unit 206 may be used to apply an integerized approximation of the DCT / DST, such as the transform specified for H.265 / HEVC. This integerized approximation is typically scaled by a factor compared to an orthogonal DCT transform. In order to maintain the norm of the residual block processed by the forward transform and the inverse transform, other scaling factors are used as part of the transform process. The scaling factor is typically selected based on certain constraints, such as whether the scaling factor is a power of 2 for the shift operation, the bit depth of the transform coefficients, a trade-off between accuracy and implementation cost, etc. For example, a specific scaling factor is specified for the inverse transform on the encoder 20 side by the inverse transform processing unit 212 (and for the corresponding inverse transform on the decoder 30 side by, for example, the inverse transform processing unit 312), and correspondingly, a corresponding scaling factor may be specified for the forward transform on the encoder 20 side by the transform processing unit 206.

[0137] In one embodiment, the video encoder 20 (correspondingly, the transform processing unit 206) may be used to output transform parameters such as one or more transform types, for example, directly output or output after encoding or compression by the entropy coding unit 270, for example, so that the video decoder 30 may receive and use the transform parameters for decoding.

[0138] Quantification

[0139] The quantization unit 208 is used to quantize the transform coefficient 207 by, for example, scalar quantization or vector quantization to obtain a quantized transform coefficient 209 . The quantized transform coefficient 209 may also be referred to as a quantized residual coefficient 209 .

[0140] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient during quantization, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP). For example, for scalar quantization, different degrees of scaling may be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to a finer quantization, while a larger quantization step size corresponds to a coarser quantization. A suitable quantization step size may be indicated by a quantization parameter (QP). For example, a quantization parameter may be an index of a predefined set of suitable quantization step sizes. For example, a smaller quantization parameter may correspond to fine quantization (a smaller quantization step size), a larger quantization parameter may correspond to coarse quantization (a larger quantization step size), and vice versa. Quantization may include dividing by a quantization step size, while a corresponding or inverse dequantization performed by an inverse quantization unit 210 or the like may include multiplying by a quantization step size. Embodiments according to some standards, such as HEVC, may be used to determine a quantization step size using a quantization parameter. In general, the quantization step size may be calculated using a fixed-point approximation of an equation containing division according to the quantization parameter. Other scaling factors may be introduced for quantization and dequantization to recover the norm of the residual block that may be modified due to the scaling used in the fixed-point approximation of the equations for the quantization step size and the quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization may be combined. Alternatively, a custom quantization table may be used and indicated from the encoder to the decoder in the bitstream, etc. Quantization is a lossy operation, where the larger the quantization step size, the greater the loss.

[0141] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) may be configured to output a quantization parameter (QP), for example, directly output or output after being encoded or compressed by the entropy coding unit 270, for example, so that the video decoder 30 may receive and use the quantization parameter for decoding.

[0142] Dequantization

[0143] The inverse quantization unit 210 is used to perform inverse quantization of the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211, for example, performing an inverse quantization scheme of the quantization scheme performed by the quantization unit 208 according to or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, corresponding to the transform coefficients 207, but due to the loss caused by quantization, the dequantized coefficients 211 are usually not completely the same as the transform coefficients.

[0144] Inverse Transform

[0145] The inverse transform processing unit 212 is used to perform an inverse transform of the transform performed by the transform processing unit 206, such as an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST), to obtain a reconstructed residual block 213 (or a corresponding dequantized coefficient 213) in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 213.

[0146] reconstruction

[0147] The reconstruction unit 214 (e.g., the summer 214) is used to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the pixel domain, for example, by adding the pixel point values ​​of the reconstructed residual block 213 and the pixel point values ​​of the prediction block 265.

[0148] Filtering

[0149] The loop filter unit 220 (or simply "loop filter" 220) is used to filter the reconstruction block 215 to obtain the filter block 221, or is generally used to filter the reconstructed pixel points to obtain the filtered pixel point value. For example, the loop filter unit is used to smoothly perform pixel conversion or improve video quality. The loop filter unit 220 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chromascaling (LMCS) (i.e., an adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Figure 2 2 is shown as a loop filter, but in other configurations, the loop filter unit 220 can be implemented as a post-loop filter. The filter block 221 can also be called a filter reconstruction block 221.

[0150] In one embodiment, the video encoder 20 (correspondingly, the loop filter unit 220) may be used to output loop filter parameters (e.g., SAO filter parameters, ALF filter parameters, or LMCS parameters), for example, directly or after being entropy encoded by the entropy encoding unit 270, such that the decoder 30 may receive and use the same or different loop filter parameters for decoding.

[0151] Decoded Image Buffer

[0152] The decoded picture buffer (DPB) 230 may be a reference picture memory for storing reference picture data for use by the video encoder 20 when encoding video data. The DPB 230 may be formed by any of a variety of memory devices, such as a dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of storage devices. The decoded picture buffer 230 may be used to store one or more filter blocks 221. The decoded picture buffer 230 may also be used to store other previous filter blocks of the same current picture or a different picture such as a previous reconstructed picture, such as a previously reconstructed and filtered block 221, and may provide a complete previously reconstructed, i.e., decoded picture (and corresponding reference blocks and pixels) and / or a partially reconstructed current picture (and corresponding reference blocks and pixels), such as for inter-frame prediction. The decoded image buffer 230 may also be used to store one or more unfiltered reconstructed blocks 215, or generally to store unfiltered reconstructed pixels, for example, reconstructed blocks 215 that have not been filtered by the loop filter unit 220, or reconstructed blocks or reconstructed pixels that have not undergone any other processing.

[0153] Mode selection (segmentation and prediction)

[0154] The mode selection unit 260 includes a segmentation unit 262, an inter-frame prediction unit 244, and an intra-frame prediction unit 254 for obtaining a decoded image from the decoded image buffer 230 or other buffers (eg, column buffers, Figure 2 The decoder 200 (not shown) receives or obtains original image data such as the original block 203 (current block 203 of the current image 17) and reconstructed image data, for example, filtered and / or unfiltered reconstructed pixels or reconstructed blocks of the same (current) image and / or one or more previously decoded images. The reconstructed image data is used as reference image data required for prediction such as inter-frame prediction or intra-frame prediction to obtain a prediction block 265 or a prediction value 265.

[0155] The mode selection unit 260 may be used to determine or select a partition for the current block (including no partition) and prediction mode (eg, intra-frame or inter-frame prediction mode), generate a corresponding prediction block 265 , calculate the residual block 205 , and reconstruct the reconstruction block 215 .

[0156] In one embodiment, the mode selection unit 260 may be used to select a segmentation and prediction mode (e.g., from prediction modes supported or available by the mode selection unit 260), the prediction mode providing the best match or minimum residual (minimum residual means better compression in transmission or storage), or providing minimum signaling overhead (minimum signaling overhead means better compression in transmission or storage), or considering or balancing both of the above. The mode selection unit 260 may be used to determine the segmentation and prediction mode based on rate distortion optimization (RDO), i.e., selecting the prediction mode that provides minimum rate distortion optimization. The terms "best", "lowest", "optimal", etc. herein do not necessarily mean "best", "lowest", "optimal" in general, but may also refer to situations where termination or selection criteria are met, for example, values ​​exceeding or falling below a threshold or other restrictions may result in a "suboptimal selection" but reduce complexity and processing time.

[0157] In other words, the partitioning unit 262 may be used to partition an image in a video sequence into a sequence of coding tree units (CTUs), and the CTU 203 may be further partitioned into smaller block portions or sub-blocks (again forming blocks), for example, by iteratively using quad-tree partitioning (QT), binary-tree partitioning (BT) or triple-tree partitioning (TT) or any combination thereof, and for example, performing prediction on each of the block portions or sub-blocks, wherein the mode selection comprises selecting a tree structure of the partition block 203 and selecting a prediction mode to be applied to each of the block portions or sub-blocks.

[0158] The segmentation (eg, performed by segmentation unit 262) and prediction processes (eg, performed by inter-prediction unit 244 and intra-prediction unit 254) performed by video encoder 20 are described in detail below.

[0159] segmentation

[0160] The segmentation unit 262 may segment (or divide) an image block (or CTU) 203 into smaller parts, such as small blocks in a square or rectangular shape. For an image with three pixel arrays, a CTU consists of N×N luminance pixel blocks and two corresponding chrominance pixel blocks. The maximum allowed size of a luminance block in a CTU is specified as 128×128 in the developing universal video coding (VVC) standard, but may be specified as a value different from 128×128 in the future, such as 256×256. The CTUs of an image may be concentrated / grouped into slices / coding block groups, coding blocks, or bricks. A coding block covers a rectangular area of ​​an image, and a coding block may be divided into one or more bricks. A brick consists of multiple CTU rows within a coding block. A coding block that is not segmented into multiple bricks may be called a brick. However, a brick is a true subset of a coding block and is therefore not called a coding block. VVC supports two coding block group modes, namely raster scan slice / coding block group mode and rectangular slice mode. In raster scan CBG mode, a slice / CBG contains a sequence of CBs in a raster scan of CBs of an image. In rectangular slice mode, a slice contains multiple bricks of an image, which together form a rectangular region of the image. The bricks within a rectangular slice are arranged in the order of the bricks in the slice's raster scan. These smaller blocks (also called sub-blocks) can be further split into smaller parts. This is also called tree partitioning or hierarchical tree partitioning, where a root block at root tree level 0 (hierarchy level 0, depth 0), etc., can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchy level 1, depth 1). These blocks can be split into two or more blocks at the next lower level, such as tree level 2 (hierarchy level 2, depth 2), etc., until the partitioning ends (because the end criteria are met, such as reaching the maximum tree depth or minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree divided into two parts is called a binary tree (BT), a tree divided into three parts is called a ternary tree (TT), and a tree divided into four parts is called a quadtree (QT).

[0161] For example, a coding tree unit (CTU) may be or include a CTB of luma pixels, two corresponding CTBs of chroma pixels of an image with three pixel arrays, or a CTB of pixels of a monochrome image, or a CTB of pixels of an image encoded using three independent color planes and syntax structures (for encoding pixels). Accordingly, a coding tree block (CTB) may be an N×N pixel block, where N may be set to a certain value so that the component is divided into CTBs, which is segmentation. A coding unit (coding unit, CU) may be or include a coding block of luma pixels, two corresponding coding blocks of chroma pixels of an image with three pixel arrays, or a coding block of pixels of a monochrome image, or a coding block of pixels of an image encoded using three independent color planes and syntax structures (for encoding pixels). Accordingly, a coding block (CB) may be an M×N pixel block, where M and N may be set to a certain value so that the CTB is divided into coding blocks, which is segmentation.

[0162] For example, in an embodiment, a coding tree unit (CTU) may be divided into multiple CUs according to HEVC by using a quadtree structure represented as a coding tree. A decision is made at the leaf-CU level whether to use inter-frame (temporal) prediction or intra-frame (spatial) prediction to encode an image area. Each leaf-CU may be further divided into one, two, or four PUs according to the PU partition type. The same prediction process is used within a PU, and relevant information is transmitted to the decoder in units of PUs. After the prediction process is applied according to the PU partition type to obtain the residual block, the leaf-CU may be partitioned into transform units (TUs) according to other quadtree structures similar to the coding tree for the CU.

[0163] For example, in an embodiment, according to the latest video coding standard currently under development (referred to as Versatile Video Coding (VVC), a combined quadtree of nested multi-type trees (e.g., binary trees and ternary trees) is used to partition a segment structure for partitioning a coding tree unit. In the coding tree structure within the coding tree unit, the CU may be a square or a rectangle. For example, a coding tree unit (CTU) is first partitioned by a quadtree structure. The quadtree leaf nodes are further partitioned by a multi-type tree structure. The multi-type tree structure has four partition types: vertical binary tree partition (SPLIT_BT_VER), horizontal binary tree partition (SPLIT_BT_HOR), vertical ternary tree partition ( SPLIT_TT_VER) and horizontal ternary tree splitting (SPLIT_TT_HOR). The leaf nodes of the multi-type tree are called coding units (CUs), unless the CU is too large for the maximum transform length, such segmentation is used for prediction and transform processing without any other splitting. In most cases, this means that the block sizes of CUs, PUs, and TUs in the coding block structure of the quadtree nested multi-type tree are the same. This exception occurs when the maximum supported transform length is less than the width or height of the color components of the CU. VVC has established a unique signaling mechanism for the split division information in the coding structure with quadtree nested multi-type trees. In the signaling mechanism, the coding tree unit ( CTU) is first split by the quadtree structure as the root of the quadtree. Then each quadtree leaf node (when large enough) is further split into a multi-type tree structure. In the multi-type tree structure, the first flag (mtt_split_cu_flag) is used to indicate whether the node is further split. When the node is further split, the second flag (mtt_split_cu_vertical_flag) is used to indicate the division direction, and then the third flag (mtt_split_cu_binary_flag) is used to indicate whether the division is a binary tree division or a ternary tree division. According to mtt_split_cu_vertical The decoder can derive the multi-type tree splitting mode (MttSplitMode) of the CU based on the values ​​of ical_flag and mtt_split_cu_binary_flag based on predefined rules or tables. It should be noted that for certain designs, such as the 64×64 luminance block and 32×32 chrominance pipeline design in the VVC hardware decoder, TT splitting is not allowed when the width or height of the luminance coding block is greater than 64. TT splitting is also not allowed when the width or height of the chrominance coding block is greater than 32. The pipeline design divides the image into multiple virtual pipeline data units (VPDUs), each VPDU is defined as a non-overlapping unit in the image. In the hardware decoder, consecutive VPDUs are processed simultaneously in multiple pipeline stages. In most pipeline stages, the VPDU size is roughly proportional to the buffer size, so it is necessary to keep the VPDU small.In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, the ternary tree (TT) and binary tree (BT) partitioning may increase the VPDU size.

[0164] In addition, it should be noted that when a part of the tree node block exceeds the bottom or the right boundary of the image, the tree node block is forcibly divided until all the pixels of each coding CU are located within the image boundary.

[0165] For example, the intra sub-partitions (ISP) tool described above may vertically or horizontally divide the luma intra prediction block into two or four sub-partitions according to the block size.

[0166] In one example, mode select unit 260 of video encoder 20 may be used to perform any combination of the segmentation techniques described above.

[0167] As described above, the video encoder 20 is configured to determine or select the best or optimal prediction mode from a (predetermined) prediction mode set. The prediction mode set may include, for example, an intra-frame prediction mode and / or an inter-frame prediction mode.

[0168] Intra prediction

[0169] The intra-frame prediction mode set may include 35 different intra-frame prediction modes, for example, non-directional modes like DC (or mean) mode and plane mode, or directional modes as defined in HEVC, or may include 67 different intra-frame prediction modes, for example, non-directional modes like DC (or mean) mode and plane mode, or directional modes as defined in VVC. For example, several traditional angle intra-frame prediction modes are adaptively replaced with wide-angle intra-frame prediction modes for non-square blocks defined in VVC. For another example, in order to avoid the division operation of DC prediction, only the longer side is used to calculate the average value of non-square blocks. In addition, the intra-frame prediction result of the plane mode can also be modified using the position-dependent intraprediction combination (PDPC) method.

[0170] The intra prediction unit 254 is configured to generate an intra prediction block 265 by reconstructing pixels in adjacent blocks of the same current image according to an intra prediction mode in the intra prediction mode set.

[0171] The intra-frame prediction unit 254 (or generally the mode selection unit 260) is also used to output intra-frame prediction parameters (or generally information indicating the selected intra-frame prediction mode of the block) in the form of syntax elements 266 to the entropy coding unit 270 for inclusion in the encoded image data 21, so that the video decoder 30 can perform operations, such as receiving and using the prediction parameters for decoding.

[0172] The intra prediction modes in HEVC include DC prediction mode, plane prediction mode and 33 angle prediction modes, with a total of 35 candidate prediction modes. The current block can use the pixels of the reconstructed image blocks on the left and above as references for intra prediction. The image blocks in the surrounding area of ​​the current block used for intra prediction of the current block become reference blocks, and the pixels in the reference blocks are called reference pixels. Among the 35 candidate prediction modes, the DC prediction mode is applicable to the area with flat texture in the current block, and all pixels in this area use the average value of the reference pixels in the reference block as prediction; the plane prediction mode is applicable to image blocks with smoothly changing textures. The current block that meets this condition uses the reference pixels in the reference block for bilinear interpolation as the prediction of all pixels in the current block; the angle prediction mode uses the characteristics that the texture of the current block is highly correlated with the texture of the adjacent reconstructed image blocks, and copies the values ​​of the reference pixels in the corresponding reference block along a certain angle as the prediction of all pixels in the current block.

[0173] The HEVC encoder selects an optimal intra-frame prediction mode for the current block from 35 candidate prediction modes and writes the optimal intra-frame prediction mode into the video bitstream. To improve the coding efficiency of intra-frame prediction, the encoder / decoder derives three most likely modes from the optimal intra-frame prediction modes of the reconstructed image blocks in the surrounding area using intra-frame prediction. If the optimal intra-frame prediction mode selected for the current block is one of the three most likely modes, a first index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the three most likely modes; if the selected optimal intra-frame prediction mode is not one of the three most likely modes, a second index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the other 32 modes (other modes among the 35 candidate prediction modes except the aforementioned three most likely modes). The HEVC standard uses a 5-bit fixed-length code as the aforementioned second index.

[0174] The method by which the HEVC encoder derives the three most likely modes includes: selecting the optimal intra-frame prediction modes of the left adjacent image block and the upper adjacent image block of the current block and putting them into a set. If the two optimal intra-frame prediction modes are the same, only one is retained in the set. If the two optimal intra-frame prediction modes are the same and both are angle prediction modes, two angle prediction modes adjacent to the angle direction are selected to be added to the set; otherwise, the plane prediction mode, the DC mode, and the vertical prediction mode are selected in turn to be added to the set until the number of modes in the set reaches 3.

[0175] After the HEVC decoder performs entropy decoding on the bitstream, it obtains the mode information of the current block, which includes an indication flag indicating whether the optimal intra-frame prediction mode of the current block is among the three most likely modes, and the index of the optimal intra-frame prediction mode of the current block among the three most likely modes or the index of the optimal intra-frame prediction mode of the current block among the other 32 modes.

[0176] Inter prediction

[0177] In a possible implementation, the set of inter-prediction modes depends on the available reference picture (i.e., at least part of the previously decoded picture stored in the DBP 230 as mentioned above) and other inter-prediction parameters, for example, on whether to use the entire reference picture or only a part of the reference picture, such as a search window area around the area of ​​the current block, to search for the best matching reference block, and / or on whether to perform pixel interpolation such as half-pixel, quarter-pixel and / or 1 / 16 interpolation, for example.

[0178] In addition to the above prediction modes, skip mode and / or direct mode may also be employed.

[0179] For example, extended merge prediction, the merge candidate list of this mode consists of the following five candidate types in order: spatial MVP from spatially adjacent CUs, temporal MVP from collocated CUs, history-based MVP from FIFO tables, pairwise average MVP, and zero MV. Decoder side motion vector refinement (DMVR) based on bilateral matching can be used to increase the accuracy of the MV of the merge mode. Merge mode with MVD (MMVD) is derived from the merge mode with motion vector difference. The MMVD flag is sent immediately after the skip flag and merge flag are sent to specify whether the CU uses the MMVD mode. The CU-level adaptive motion vector resolution (AMVR) scheme can be used. AMVR supports encoding the MVD of the CU with different precisions. The MVD of the current CU is adaptively selected according to the prediction mode of the current CU. When the CU is encoded in merge mode, the combined inter / intraprediction (CIIP) mode can be applied to the current CU. The CIIP prediction is obtained by weighted averaging the inter-frame and intra-frame prediction signals. For affine motion compensated prediction, the affine motion field of the block is described by the motion information of 2 control points (4 parameters) or 3 control points (6 parameters) motion vectors. Subblock-based temporal motion vector prediction (SbTMVP) is similar to the temporal motion vector prediction (TMVP) in HEVC, but the motion vector of the sub-CU within the current CU is predicted. Bidirectional optical flow (BDOF), formerly known as BIO, is a simplified version that reduces calculations, especially in terms of the number of multiplications and the size of the multipliers. In the triangle partitioning mode, the CU is evenly divided into two triangular parts in two ways: diagonal partitioning and anti-diagonal partitioning. In addition, the bidirectional prediction mode is extended on the basis of simple averaging to support weighted averaging of two prediction signals.

[0180] The inter-frame prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both in Figure 2). The motion estimation unit may be configured to receive or acquire the image block 203 (the current image block 203 of the current image 17) and the decoded image 231, or at least one or more previously reconstructed blocks, for example, reconstructed blocks of one or more other / different previously decoded images 231, for motion estimation. For example, a video sequence may include the current image and the previously decoded image 231, or in other words, the current image and the previously decoded image 231 may be part of or form a sequence of images forming the video sequence.

[0181] For example, the encoder 20 may be configured to select a reference block from a plurality of reference blocks of the same or different images in a plurality of other images, and provide the reference image (or reference image index) and / or the offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to the motion estimation unit. The offset is also referred to as a motion vector (MV).

[0182] The motion compensation unit is used to obtain, for example, receive, inter-frame prediction parameters, and perform inter-frame prediction based on or using the inter-frame prediction parameters to obtain an inter-frame prediction block 246. The motion compensation performed by the motion compensation unit may include extracting or generating a prediction block based on a motion / block vector determined by motion estimation, and may also include performing interpolation with sub-pixel accuracy. Interpolation filtering can generate pixel points of other pixels from pixel points of known pixels, thereby potentially increasing the number of candidate prediction blocks that can be used to encode the image block. Once a motion vector corresponding to a PU of a current image block is received, the motion compensation unit can locate the prediction block pointed to by the motion vector in one of the reference image lists.

[0183] The motion compensation unit may also generate syntax elements associated with blocks and video slices for use by the video decoder 30 when decoding image blocks of the video slice. In addition, or as an alternative to slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may be generated or used.

[0184] In the process of obtaining a candidate motion vector list in an advanced motion vector prediction (AMVP) mode, motion vectors (MVs) that can be added to the candidate motion vector list as alternatives include MVs of image blocks that are spatially adjacent and temporally adjacent to the current block, wherein the MVs of the image blocks that are spatially adjacent may include the MV of a left candidate image block located on the left side of the current block and the MV of an upper candidate image block located above the current block. For example, please refer to Figure 4 , Figure 4 An exemplary schematic diagram of a candidate image block provided in an embodiment of the present application is as follows: Figure 4As shown, the set of left candidate image blocks includes {A0, A1}, the set of upper candidate image blocks includes {B0, B1, B2}, and the set of temporally adjacent candidate image blocks includes {C, T}. All three sets can be added to the candidate motion vector list as alternatives. However, according to the existing coding standard, the maximum length of the candidate motion vector list of AMVP is 2, so it is necessary to determine the MV of adding up to two image blocks to the candidate motion vector list from the three sets according to the prescribed order. The order can be to give priority to the set of left candidate image blocks {A0, A1} of the current block (consider A0 first, and then consider A1 if A0 is not available), then consider the set of upper candidate image blocks {B0, B1, B2} of the current block (consider B0 first, and then consider B1 if B0 is not available, and then consider B2 if B1 is not available), and finally consider the set of temporally adjacent candidate image blocks {C, T} of the current block (consider T first, and then consider C if T is not available).

[0185] After obtaining the above candidate motion vector list, the optimal MV is determined from the candidate motion vector list by the rate distortion cost (RDcost), and the candidate motion vector with the smallest RD cost is used as the motion vector predictor (MVP) of the current block. The rate distortion cost is calculated by the following formula:

[0186] J=SAD+λR

[0187] Wherein, J represents RD cost, SAD is the sum of absolute differences (SAD) between the pixel value of the predicted block obtained after motion estimation using the candidate motion vector and the pixel value of the current block, R represents the bit rate, and λ represents the Lagrange multiplier.

[0188] The encoder passes the index of the determined MVP in the candidate motion vector list to the decoder. Furthermore, a motion search can be performed in the neighborhood centered on the MVP to obtain the actual motion vector of the current block. The encoder calculates the motion vector difference (MVD) between the MVP and the actual motion vector, and also passes the MVD to the decoder. The decoder parses the index, finds the corresponding MVP in the candidate motion vector list based on the index, parses the MVD, and adds the MVD to the MVP to obtain the actual motion vector of the current block.

[0189] In the process of obtaining the candidate motion information list in the merging mode, the motion information that can be added to the candidate motion information list as an alternative includes the motion information of the image blocks that are spatially adjacent or temporally adjacent to the current block, wherein the image blocks that are spatially adjacent and the image blocks that are temporally adjacent can refer to Figure 4 , the candidate motion information corresponding to the spatial domain in the candidate motion information list comes from the five spatially adjacent blocks (A0, A1, B0, B1 and B2). If the spatially adjacent block is not available or is intra-predicted, its motion information will not be added to the candidate motion information list. The candidate motion information of the current block in the time domain is obtained by scaling the MV of the block at the corresponding position in the reference frame according to the picture order count (POC) of the reference frame and the current frame. First, determine whether the block at position T in the reference frame is available. If not, select the block at position C. After obtaining the above candidate motion information list, the optimal motion information is determined from the candidate motion information list through the RD cost as the motion information of the current block. The encoder passes the index value (denoted as mergeindex) of the position of the optimal motion information in the candidate motion information list to the decoder.

[0190] Entropy Coding

[0191] The entropy coding unit 270 is used to apply an entropy coding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context adaptive VLC scheme (CALVC), an arithmetic coding scheme, a binarization algorithm, a context adaptive binary arithmetic coding (CABAC), a syntax-based context-adaptive binary arithmetic coding (SBAC), a probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements to obtain coded image data 21 that can be output in the form of a coded bit stream 21 through an output terminal 272, so that the video decoder 30, etc. can receive and use the parameters for decoding. The coded bit stream 21 can be transmitted to the video decoder 30, or it can be stored in a memory for later transmission or retrieval by the video decoder 30.

[0192] Other structural variations of the video encoder 20 may be used to encode the video stream. For example, a non-transform based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames. In another implementation, the encoder 20 may have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.

[0193] Decoder and decoding method

[0194] like Figure 3 As shown, the video decoder 30 is used to receive the coded image data 21 (e.g., the coded bitstream 21) encoded by the encoder 20, and obtain a decoded image 331. The coded image data or bitstream includes information for decoding the coded image data, such as data representing image blocks of a coded video slice (and / or a coding block group or coding block) and related syntax elements.

[0195] exist Figure 3 In the example of FIG. 3 , decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., a summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter-frame prediction unit 344, and an intra-frame prediction unit 354. Inter-frame prediction unit 344 may be or include a motion compensation unit. In some examples, video decoder 30 may perform substantially the same as reference Figure 2 The decoding process of the video encoder 100 is the reverse of the encoding process described above.

[0196] As described above for encoder 20, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, loop filter 220, decoded picture buffer DPB 230, inter prediction unit 344, and intra prediction unit 354 also constitute a "built-in decoder" of video encoder 20. Accordingly, inverse quantization unit 310 may be functionally identical to inverse quantization unit 110, inverse transform processing unit 312 may be functionally identical to inverse transform processing unit 122, reconstruction unit 314 may be functionally identical to reconstruction unit 214, loop filter 320 may be functionally identical to loop filter 220, and decoded picture buffer 330 may be functionally identical to decoded picture buffer 230. Therefore, the explanation of the corresponding units and functions of video encoder 20 applies accordingly to the corresponding units and functions of video decoder 30.

[0197] Entropy decoding

[0198] The entropy decoding unit 304 is used to parse the bit stream 21 (or generally the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain the quantization coefficients 309 and / or the decoded encoding parameters ( Figure 3The entropy decoding unit 304 may be used to provide the inter-frame prediction parameters, intra-frame prediction parameters and / or other syntax elements to the mode application unit 360, and to provide other parameters to other units of the decoder 30. The video decoder 30 may receive syntax elements at the video slice and / or video block level. In addition, or as an alternative to slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may be received or used.

[0199] Dequantization

[0200] The inverse quantization unit 310 may be configured to receive a quantization parameter (QP) (or generally information related to inverse quantization) and a quantization coefficient from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304), and inverse quantize the decoded quantization coefficient 309 based on the quantization parameter to obtain an inverse quantization coefficient 311, which may also be referred to as a transform coefficient 311. The inverse quantization process may include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine a degree of quantization, and also determine a degree of inverse quantization that needs to be performed.

[0201] Inverse Transform

[0202] The inverse transform processing unit 312 may be configured to receive the dequantized coefficients 311, also referred to as transform coefficients 311, and apply a transform to the dequantized coefficients 311 to obtain a reconstructed residual block 213 in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 313. The transform may be an inverse transform, such as an inverse DCT, an inverse DST, an inverse integer transform, or a conceptually similar inverse transform process. The inverse transform processing unit 312 may also be configured to receive transform parameters or corresponding information from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304) to determine the transform applied to the dequantized coefficients 311.

[0203] reconstruction

[0204] The reconstruction unit 314 (eg, the summer 314 ) is used to add the reconstructed residual block 313 to the prediction block 365 to obtain the reconstructed block 315 in the pixel domain, for example, by adding the pixel point values ​​of the reconstructed residual block 313 and the pixel point values ​​of the prediction block 365 .

[0205] Filtering

[0206] The loop filter unit 320 (in or after the encoding loop) is used to filter the reconstruction block 315 to obtain a filter block 321, so as to smoothly perform pixel conversion or improve video quality, etc. The loop filter unit 320 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chromascaling (LMCS) (i.e., an adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Figure 3 3. Although shown as a loop filter in FIG. 3, in other configurations, the loop filter unit 320 may be implemented as a post-loop filter.

[0207] Decoded Image Buffer

[0208] The decoded video blocks 321 in one picture are then stored in a decoded picture buffer 330 which stores the decoded pictures 331 as reference pictures for subsequent motion compensation of other pictures and / or respective output displays.

[0209] The decoder 30 is used to output the decoded image 311 through the output terminal 312, etc., to display it to the user or for the user to view it.

[0210] predict

[0211] The inter-frame prediction unit 344 may be functionally the same as the inter-frame prediction unit 244 (particularly the motion compensation unit), and the intra-frame prediction unit 354 may be functionally the same as the inter-frame prediction unit 254, and may determine the division or segmentation and perform prediction based on the segmentation and / or prediction parameters or corresponding information received from the coded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304). The mode application unit 360 may be used to perform prediction (intra-frame or inter-frame prediction) of each block according to the reconstructed image, block or corresponding pixel point (filtered or unfiltered), and obtain a prediction block 365.

[0212] When the video slice is encoded as an intra coded (I) slice, the intra prediction unit 354 in the mode application unit 360 is used to generate a prediction block 365 for the image block of the current video slice based on the indicated intra prediction mode and data from the previously decoded block of the current image. When the video image is encoded as an inter coded (i.e., B or P) slice, the inter prediction unit 344 (e.g., motion compensation unit) in the mode application unit 360 is used to generate a prediction block 365 for the video block of the current video slice based on the motion vector and other syntax elements received from the entropy decoding unit 304. For inter prediction, these prediction blocks can be generated from one of the reference images in one of the reference image lists. The video decoder 30 can construct reference frame list 0 and list 1 using a default construction technique based on the reference images stored in the DPB 330. The same or similar processes may be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks) in addition to or as an alternative to slices (e.g., video slices), for example, a video may be encoded using I, P or B coding block groups and / or coding blocks.

[0213] The mode application unit 360 is used to determine prediction information for a video block of a current video slice by parsing motion vectors and other syntax elements, and use the prediction information to generate a prediction block for the current video block being decoded. For example, the mode application unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra-frame prediction or inter-frame prediction) for encoding a video block of a video slice, an inter-frame prediction slice type (e.g., a B slice, a P slice, or a GPB slice), construction information of one or more reference picture lists for the slice, a motion vector for each inter-frame coded video block of the slice, an inter-frame prediction state for each inter-frame coded video block of the slice, and other information to decode the video block in the current video slice. In addition to slices (e.g., video slices) or as an alternative to slices, the same or similar process can be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks), for example, a video can be encoded using I, P, or B coding block groups and / or coding blocks.

[0214] In one embodiment, Figure 3The video encoder 30 may also be configured to partition and / or decode an image using slices (also referred to as video slices), wherein an image may be partitioned or decoded using one or more slices (usually non-overlapping). Each slice may include one or more blocks (e.g., CTUs) or one or more groups of blocks (e.g., coding blocks in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0215] In one embodiment, Figure 3 The video decoder 30 shown can also be used to segment and / or decode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), wherein an image can be segmented or decoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTU) or one or more coding blocks, etc., wherein each coding block may be in a rectangular shape, etc., and may include one or more complete or partial blocks (e.g., CTU).

[0216] Other variations of the video decoder 30 may be used to decode the encoded image data 21. For example, the decoder 30 may generate an output video stream without the loop filter unit 320. For example, a non-transform based decoder 30 may directly dequantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 may have the dequantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0217] It should be understood that the processing result of the current step can be further processed in the encoder 20 and the decoder 30 and then output to the next step. For example, after interpolation filtering, motion vector derivation or loop filtering, the processing result of interpolation filtering, motion vector derivation or loop filtering can be further operated, such as clipping or shifting operation.

[0218] It should be noted that the derived motion vector of the current block (including but not limited to the control point motion vector of the affine mode, the sub-block motion vector of the affine, plane, ATMVP mode, the temporal motion vector, etc.) can be further operated. For example, the value of the motion vector is limited to a predefined range according to the representation bit of the motion vector. If the representation bit of the motion vector is bitDepth, the range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" represents the power. For example, if bitDepth is set to 16, the range is -32768 to 32767; if bitDepth is set to 18, the range is -131072 to 131071. For example, the value of the derived motion vector (e.g., the MV of 4 4×4 sub-blocks in an 8×8 block) is limited so that the maximum difference between the integer parts of the above 4 4×4 sub-block MVs does not exceed N pixels, for example, not more than 1 pixel. Two methods of limiting motion vectors according to bitDepth are provided here.

[0219] Although the above embodiments mainly describe video coding and decoding, it should be noted that the embodiments of the decoding system 10, the encoder 20 and the decoder 30 and other embodiments described herein can also be used for still image processing or coding and decoding, that is, the processing or coding and decoding of a single image in video coding and decoding that is independent of any previous or consecutive images. In general, if the image processing is limited to a single image 17, the inter-frame prediction unit 244 (encoder) and the inter-frame prediction unit 344 (decoder) may not be available. All other functions (also called tools or techniques) of the video encoder 20 and the video decoder 30 can also be used for still image processing, such as residual calculation 204 / 304, transformation 206, quantization 208, inverse quantization 210 / 310, (inverse) transformation 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354 and / or loop filtering 220 / 320, entropy encoding 270 and entropy decoding 304.

[0220] Please refer to Figure 5 , Figure 5 An exemplary block diagram of a video decoding device 500 provided in an embodiment of the present application. The video decoding device 500 is suitable for implementing the disclosed embodiments described herein. In one embodiment, the video decoding device 500 may be a decoder, such as Figure 1a The video decoder 30 in the embodiment may also be an encoder, for example Figure 1a The video encoder 20 in.

[0221] The video decoding device 500 includes: an input port 510 (or input port 510) and a receiving unit (Rx) 520 for receiving data; a processor, a logic unit or a central processing unit (CPU) 530 for processing data; for example, the processor 530 here can be a neural network processor 530; a transmitter unit (Tx) 540 and an output port 550 (or output port 550) for transmitting data; and a memory 560 for storing data. The video decoding device 500 may also include an optical-to-electrical (OE) component and an electrical-to-optical (EO) component coupled to the input port 510, the receiving unit 520, the transmitting unit 540 and the output port 550 for the output or input of optical signals or electrical signals.

[0222] The processor 530 is implemented by hardware and software. The processor 530 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 530 communicates with the input port 510, the receiving unit 520, the sending unit 540, the output port 550, and the memory 560. The processor 530 includes a decoding module 570 (e.g., a decoding module 570 based on a neural network). The decoding module 570 implements the embodiments disclosed above. For example, the decoding module 570 performs, processes, prepares, or provides various encoding operations. Therefore, the decoding module 570 provides substantial improvements to the functions of the video decoding device 500 and affects the switching of the video decoding device 500 to different states. Alternatively, the decoding module 570 is implemented with instructions stored in the memory 560 and executed by the processor 530.

[0223] The memory 560 includes one or more disks, tape drives, and solid-state hard disks, and can be used as an overflow data storage device for storing such programs when such programs are selected for execution, and for storing instructions and data read during program execution. The memory 560 can be volatile and / or non-volatile, and can be a read-only memory (ROM), a random access memory (RAM), a ternary content-addressable memory (TCAM), and / or a static random-access memory (SRAM).

[0224] Please refer to Figure 6 , Figure 6An exemplary block diagram of a device 600 provided in an embodiment of the present application, the device 600 can be used as Figure 1a Either or both of the source device 12 and the destination device 14 in .

[0225] The processor 602 in the device 600 may be a central processing unit. Alternatively, the processor 602 may be any other type of device or devices that are currently available or will be developed in the future and are capable of manipulating or processing information. Although a single processor such as the processor 602 shown in the figure may be used to implement the disclosed implementation, using more than one processor is faster and more efficient.

[0226] In one implementation, the memory 604 in the apparatus 600 may be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may be used as the memory 604. The memory 604 may include code and data 606 accessed by the processor 602 via a bus 612. The memory 604 may also include an operating system 608 and an application 610, wherein the application 610 includes at least one program that allows the processor 602 to perform the method described above. For example, the application 610 may include applications 1 to N, and also include a video decoding application that performs the method described above.

[0227] The apparatus 600 may also include one or more output devices, such as a display 618. In one example, the display 618 may be a touch-sensitive display that combines a display with a touch-sensitive element that may be used to sense touch input. The display 618 may be coupled to the processor 602 via the bus 612.

[0228] Although the bus 612 in the device 600 is described herein as a single bus, the bus 612 may include multiple buses. In addition, the auxiliary storage may be directly coupled to other components of the device 600 or accessed through a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Therefore, the device 600 may have a variety of configurations.

[0229] Before describing the embodiments of the present application, the concepts and terms used in the embodiments of the present application are first explained.

[0230] Reconstructed image: refers to the lossy image obtained by decoding the encoded image bit stream, which can be displayed and played. It exists at both the encoding end and the decoding end, and the reconstructed images in the encoding end and the decoding end are exactly the same. At the encoding end, the reconstructed image can be used as a reference image of the image to be encoded to perform inter-frame prediction encoding on the image to be encoded. At the decoding end, the reconstructed image can be used as a reference image of the image bit stream to be decoded to perform inter-frame prediction decoding on the image bit stream to be decoded.

[0231] RAP: Random access point in video encoding. The encoded video bitstream includes at least one RAP. When random access occurs, the video bitstream before the RAP can be skipped, and the subsequent image bitstream can be decoded from the RAP and the reconstructed video image output by the decoded output can be played. From the perspective of video playback, random access can be understood as dragging the progress bar of the player to achieve random video jumps when watching on-demand videos (or playing back videos locally); or when packet loss and a black screen occur when watching live broadcasts, the client will access the video stream and continue to play the video when the next RAP arrives. RAP is usually an intra-coded picture (I) frame. The I frame only uses the information inside the current frame for predictive coding to eliminate information redundancy in the spatial domain without relying on other frames.

[0232] RAS: RAS includes all images from one RAP to the next RAP. Images in a RAS are forward prediction (P) frames or bidirectional interpolated prediction (B) frames. P frames or B frames need to use coded images for temporal prediction to eliminate temporal redundancy.

[0233] For example, please refer to Figure 7 , Figure 7 A schematic diagram of a video sequence provided in an embodiment of the present application, Figure 7 11 video frames a1 to a11 are shown. Among them, a2, a6 and a10 are I frames and serve as RAP, all video frames between a2 and a6 are P frames and constitute RAS1, and all video frames between a6 and a10 are P frames and constitute RAS2. Figure 7 It can be seen that each P frame needs to be encoded with reference to the previous m video frames, where m is an integer greater than 1. For example, a3 can be encoded with reference to a2, and a4 can be encoded with reference to a2 and / or a3.

[0234] CRR coding: When encoding a video frame in one RAS, the video frames in other RASs except the RAS can be referenced for encoding.

[0235] In most videos (such as movies or TV shows), many picture scenes appear alternately, and the picture scenes displayed at different times may be similar. The interval duration between two adjacent similar picture scenes is usually long. Therefore, two adjacent similar picture scenes are in the same RAP but with a long interval, or the temporal correlation spans the RAP. For example, in video standards, the length of the RAS is generally specified as 1 s or 2 s, and the interval duration between two adjacent similar picture scenes is usually close to the length of the RAS (e.g., 0.7 s) or greater than the length of the RAS (e.g., 3 s). In addition, in video scenarios such as security monitoring, similar picture scenes usually appear for a long time. Therefore, there are also cases where two similar picture scenes are in the same RAP but with a long interval, or the temporal correlation spans the RAP.

[0236] Keystream: In cryptography, a keystream is a stream of characters containing random or pseudorandom characters, which is used to combine with the plaintext data stream to generate encrypted messages (ciphertext).

[0237] Network Abstraction Layer Unit (NALU): In video coding, all encoded data is encapsulated into individual NALUs for transmission. They all have a unified structure. Each NALU contains two parts: the NALU header and the NALU payload (RBSP). The length of the NALU header is fixed at two bytes, reflecting the content payload of the NALU; the length of the RBSP is an integer number of bytes, carrying the bitstream segment after video coding. Whether it is the SPS, PPS, or video coding data, it is encapsulated in the form of NALUs.

[0238] Picture Parameter Set and Sequence Parameter Set (PPS and SPS): They contain all the parameters required for encoding the entire sequence or the entire picture. In principle, in addition to the key parameters describing the characteristics of the encoded sequence, the SPS should also carry the control switches of most encoding tools and the corresponding encoding limit parameters. The scope of the parameters in the SPS is the entire encoded sequence, which means that during the entire video coding process, there is only one SPS, and the parameters in it are not allowed to change; for the PPS, in principle, some tool parameters are allowed to change at the frame level but not frequently, so the picture-level tool control parameters can be further repeated and sent in a lower PPS, which means that the parameters in the PPS are allowed to change with the change of picture characteristics. Usually, the scope of the PPS is n pictures (0 < n < all pictures).

[0239] SPS includes a set of global parameters of the video coding sequence, such as color space, size (width and height) of each frame, and coding level. PPS includes coding parameters for at least one frame, such as quantization matrix and filter parameters. The picture header includes coding parameters for one frame, such as frame number.

[0240] For example, for SPS, there may be one SPS before every N CRR slice bitstreams, or one SPS before the entire bitstream. For PPS, there may be one PPS before every multiple bitstreams. For picture header, there may be one picture header before the first CRR slice bitstream, and one slice header or segment header before other non-first CRR slice bitstreams.

[0241] The embodiment of the present application provides a coding and decoding method, which can improve the security of the CRR media content transmission process.

[0242] Please refer to Figure 8 , Figure 8 A schematic flow chart of an encoding method provided in an embodiment of the present application, which can be applied to an encoder, may include the following process:

[0243] S801. Perform encoding operation on multiple display images and multiple CRR images to obtain a code stream.

[0244] The code stream includes a security parameter set and an authentication data set. The security parameter set includes first information and second information. The first information is used to indicate the algorithm used to generate the tree top summary, and the second information is used to indicate the algorithm used to perform the digital signature.

[0245] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0246] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag=0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag=1 indicates that the current authentication data belongs to a CRR slice, and all CRR slices are constrained to be authenticated.

[0247] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0248] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0249] In a possible implementation, the authentication data set further includes fifth information, and the fifth information is used to indicate a CRR image corresponding to an authentication range of the specified current authentication data set.

[0250] Exemplarily, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to which CRR image the authentication range of the current authentication data set belongs. This parameter can be parsed only when is_crr_flag=1.

[0251] Exemplarily, as shown in Table 1, the security parameter set provided by the embodiment of the present application may include the following information.

[0252] Table 1

[0253]

[0254]

[0255] Where encryption_flag is equal to 1, indicating that encryption of picture coding slices, sequence parameter sets, picture parameter sets, or extended data units is supported, that is, the RBSP in the NAL unit may be encrypted. Encryption_flag is equal to 0, indicating that encryption of the RBSP in the NAL unit is not supported.

[0256] When authentication_flag is equal to 1, it means that the authentication of the whole frame image data content is supported. The NAL units for authentication include coded slices, and the sequence parameter set, picture parameter set, security parameter set and extended data unit transmitted in the frame. When the authentication of the above data content is supported, the absolute time extension information must be carried in the coded bitstream, and the authentication data carried in the coded bitstream should be Base64 encoded. The authentication data is transmitted through the NAL unit with nal_unit_type equal to 10. If there are coded slices, sequence parameter sets, picture parameter sets, security parameter sets, extended data units, etc. with authentication_idc equal to 1 in the image, the NAL units with authentication_idc equal to 1 in an image are arranged in decoding order and authenticated to generate the summary data of the image. When authentication_flag is equal to 0, it means that authentication of the image is not supported, and the coded bitstream should not contain NAL units with nal_unit_type equal to 10.

[0257] If spatial_svc_flag is equal to 1, the base layer image and enhancement layer image of the same frame are authenticated separately, the image parameter set and coding slice of the enhancement layer are authenticated as the enhancement layer, and the sequence parameter set, security parameter set and extended data unit are authenticated together with the image parameter set and coding slice of the base layer as the base layer.

[0258] vek_flag equal to 1 indicates that the video encryption key (VEK) is carried; equal to 0 indicates that the video encryption key (VEK) is not carried.

[0259] iv_flag equal to 1 indicates that the initial vector (IV) is carried; equal to 0 indicates that the initial vector (IV) is not carried.

[0260] camera_id is a 20-byte string indicating the camera ID of the image source.

[0261] vek_encryption_type indicates the algorithm used for key encryption. The specific correspondence is the same as encryption_type.

[0262] evek_length_minus1 is the length of the encrypted key minus 1, in bytes.

[0263] evek is the encrypted key used for encryption calculations, and its length is evek_length_minus1 plus 1 byte.

[0264] vkek_version length_minus1 is the length of the encryption key version number minus 1, in bytes.

[0265] vkek_version is the encryption key version number, and its length is vkek_version_length_minus1 plus 1 byte.

[0266] iv_length_minus1 is the initial vector length minus 1, in bytes.

[0267] iv is the initial vector, used for block encryption, and its length is iv_length_minus1 plus 1 byte.

[0268] encryption_type indicates the encryption algorithm used.

[0269] For example, as shown in Table 2, when the encryption_type value is 0, it indicates that the encryption algorithm used is the SM1 algorithm. When the encryption_type value is 1, it indicates that the encryption algorithm used is the SM4 algorithm.

[0270] Table 2

[0271] encryption_type Encryption Algorithm 0 SM1 1 SM4 2～15 reserve

[0272] hash_type indicates the algorithm used to generate the tree top digest.

[0273] Exemplarily, as shown in Table 3, when the value of hash_type is 0, it indicates that the algorithm used to generate the tree top summary is the SM3 algorithm.

[0274] Table 3

[0275]

[0276] signature_type indicates the algorithm used to digitally sign the summary data of the image.

[0277] Exemplarily, as shown in Table 4, when the value of signature_type is 0, it indicates that the algorithm for digitally signing the summary data of the image is the SM2 algorithm.

[0278] Table 4

[0279] signature_type Signature Algorithm 0 SM2 1～3 reserve

[0280] hash_discard_p_pictures equal to 1 indicates that non-IDR pictures are not authenticated; equal to 0 indicates that non-IDR pictures are authenticated. If hash_discard_p_pictures is not in the bitstream, its value is 1 by default. The authentication_idc of each NAL unit in the picture that is not authenticated shall be 0.

[0281] successive_hash_pictures_minus1 plus 1 indicates the number of consecutive pictures that are digitally signed in the decoding order, and these consecutive pictures are limited to one IDR picture interval. The value of successive_hash_pictures_minus1 should be 0 to 255.

[0282] If successive_hash_pictures_minus1 is greater than 0, first generate tree-type summary data for the summary data of SuccessiveHashPictures images in decoding order, and then digitally sign the tree-top summary data. For example, the tree-top summary data of n images is the summary data generated by the method indicated by hash_type after arranging the tree-top summary data of the first n-1 images and the summary data of the nth image.

[0283] camera_idc is a 19-byte string used to indicate the certificate identifier of the camera from which the image is obtained.

[0284] Exemplarily, as shown in Table 5, the authentication data set provided by the embodiment of the present application may include the following information.

[0285] Table 5

[0286]

[0287]

[0288] Among them, is_crr_flag indicates whether the current authentication data set belongs to the CRR image. is_crr_flag = 0, indicating that the current authentication data belongs to the main bit stream; is_crr_flag = 1, indicating that the current authentication data belongs to the CRR slice, constraining all CRR slices to be authenticated.

[0289] crr_picture_index specifies which CRR image the authentication range of the current authentication data set belongs to. This parameter can be parsed only when is_crr_flag=1.

[0290] frame_num indicates the image that should contain the authentication data. This image is the image whose frame_num is the same as the frame_num of the authentication data immediately before the authentication data NAL unit. When successive_hash_pictures_minus1 is equal to 0, frame_num indicates the image corresponding to the authentication data; when it is greater than 0, frame_num indicates the last of the consecutive SuccessiveHashPictures images.

[0291] The spatial_el_flag is equal to 1, indicating that the authentication data is the enhanced layer signature data, and the spactial_el_flag is equal to 0, indicating that the authentication data is the base layer signature data. If spactial_el_flag does not exist in the bitstream, its value is 0 by default.

[0292] authentication_data_length_minus1 plus 1 indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0293] authentication_data[i] is the i-th byte of the signature data.

[0294] For example, please refer to Fig. 9 , Fig. 9A schematic diagram of a coding and decoding process provided by an embodiment of the present application: The encoder encodes multiple display images and multiple CRR images to obtain a code stream and sends the code stream to the decoder. Fig. 9 In the example, three CRR slice bit streams b1 to b3 (n=3) and five main bit streams c1 to c5 are used for explanation. The decoder decodes the bit streams in the coded image bit stream in sequence to obtain five reconstructed display images c1′ to c5′ and reconstructed CRR images. The five reconstructed display images are used for display, and the reconstructed CRR images are only used as reference images when decoding the display image bit streams and are not used for display.

[0295] S802: Authenticate the data to be authenticated according to the first information to obtain first tree-top summary data.

[0296] The first tree top summary data is the tree top summary data of the encoding end, and the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0297] Exemplarily, if the first information, that is, hash_type, takes a value of 0, the SM3 algorithm can be used to authenticate the data to be authenticated (NALU data of N main bitstreams and / or M CRR slice bitstreams) to obtain the first tree top summary data. The NALU data includes the NALUheader and the RBSP of the NALU.

[0298] S803: Perform signature calculation on the first tree top summary data according to the second information to obtain a digital signature.

[0299] Exemplarily, if the second information, signature_type, takes a value of 0, the SM2 algorithm may be used to perform signature calculation on the first tree top summary data to obtain a digital signature (ie, video authentication data).

[0300] S804: Encapsulate the digital signature into the authentication data set.

[0301] In a possible implementation, the data signature may be encoded and the encoded data signature may be encapsulated into the authentication data set.

[0302] Exemplarily, the data signature can be Base64 encoded, and the Base64-encoded data signature can be encapsulated into the authentication data set as an independent NALU type. The authentication data set is constrained to have all relevant data of the most recent CRR image in front of it (SPS, PPS and CRR slice stream of the CRR image), or all relevant data of the N previous display images (SPS, PPS and corresponding display image stream of the display image).

[0303] Please refer to Fig.10 , Fig.10 A flowchart of a decoding method provided in an embodiment of the present application is provided. The method can be applied to a decoder. The method may include the following process:

[0304] S1001. Obtain code stream.

[0305] Among them, the above-mentioned code stream is obtained by encoding multiple display images and the multiple CRR images, the above-mentioned code stream includes a security parameter set and an authentication data set, the above-mentioned security parameter set includes first information and second information, the above-mentioned first information is used to indicate the algorithm used to generate the tree top summary, the above-mentioned second information is used to indicate the algorithm used for digital signature, and the above-mentioned authentication data set includes a digital signature.

[0306] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0307] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0308] S1002: Decode the digital signature according to the second information to obtain first tree top summary data.

[0309] The first tree top summary data is the tree top summary data of the encoding end, and the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0310] In a possible implementation, the digital signature may be decoded; and the decoded digital signature may be decoded according to the second information to obtain the first tree top summary data.

[0311] S1003. Authenticate the authentication data corresponding to the authentication data set according to the first information to obtain second tree-top summary data.

[0312] The second tree-top summary data is the tree-top summary data of the decoding end, and the first tree-top summary data includes the tree-top summary data of N main bit streams and / or M CRR slice bit streams.

[0313] S1004: Verify the authentication data according to the first treetop summary and the second treetop summary data.

[0314] Exemplarily, when the first tree-top summary data and the second tree-top summary data are consistent, it can be determined that the authentication data is complete and authentic (ie, the authentication data has not been tampered with).

[0315] As another example, when the first tree-top summary data and the second tree-top summary data are inconsistent, it can be determined that the authentication data is incomplete or untrue (ie, the authentication data may be tampered with).

[0316] Please refer to Fig.11 , Fig.11 A schematic flow chart of an encoding method provided in an embodiment of the present application, which can be applied to an encoder, may include the following process:

[0317] S1101 . Perform encoding operations on multiple display images and multiple CRR images to obtain code streams.

[0318] The above-mentioned code stream includes a security parameter set, and the above-mentioned security parameter set includes a video encryption key.

[0319] S1102: Encrypt the bit stream according to the video encryption key.

[0320] In a possible implementation manner, the payload data of the code stream may be encrypted according to a video encryption key.

[0321] The payload data includes at least one of a sequence parameter set SPS, a picture parameter set PPS, a main bitstream and a CRR slice bitstream.

[0322] Exemplarily, the encoder periodically randomly generates a 16-byte video encryption key (VEK). Then read the payload data to be encrypted in the code stream. The encoder randomly generates a 16-byte initial vector (IV). The currently used video encryption key (VEK) and initial vector (IV) are encrypted with the video key encryption key (VKEK) of the source, and the corresponding ciphertext is encapsulated into the NALU of the security parameter set. The output-feedback (OFB) mode of the agreed block encryption algorithm is adopted to generate a key stream with the video encryption key (VEK) and the initial vector (IV). The stream key is bit-aligned with the coded slice RBSP data to be encrypted, and then an XOR operation is performed to obtain the encrypted coded slice RBSP data. The encrypted RBSP data is encapsulated into a VCL_NALU, and the encryption_idc of the NALU is set to 1. If a new video encryption key (VEK) is activated or a new initial vector (IV) is used, the encapsulated security extension information NAL should be re-encoded first, and before the current output VLC_NAL to be encrypted.

[0323] Optionally, when this RBSP is the first coded slice data at the beginning of the picture group (GOP) and a new video encryption key (VEK) is available, the current video encryption key (VEK) can be invalidated and the new video encryption key (VEK) can be activated, otherwise the current video encryption key (VEK) continues to be used.

[0324] Please refer to Fig.12 , Fig.12 A flowchart of a decoding method provided in an embodiment of the present application is provided. The method can be applied to a decoder. The method may include the following process:

[0325] S1201. Obtain code stream.

[0326] The code stream is obtained by encoding the multiple display images and the multiple CRR images, and the code stream includes a security parameter set, and the security parameter set includes a video encryption key.

[0327] S1202: Decrypt the code stream according to the video encryption key.

[0328] In a possible implementation manner, the payload data of the code stream may be decrypted according to the video encryption key.

[0329] The above-mentioned payload data includes at least one of SPS, PPS, main bit stream and CRR slice bit stream.

[0330] Exemplarily, the ciphertext of the initial vector (IV) and the video encryption key (VEK) can be obtained from the security parameter set NAL, denoted as E(VEK), and E(VEK) can be decrypted with the video key encryption key (VKEK) to obtain the video encryption key (VEK). Read the coded slice RBSP data to be decrypted. Use the OFB mode of the agreed block encryption algorithm to generate a key stream using the video encryption key (VEK) and the initial vector (IV). The stream key is bit-aligned with the coded slice RBSP data to be decrypted, and an XOR operation is performed to obtain the decrypted coded slice RBSP data.

[0331] Optionally, when this RBSP is the first coded slice data at the beginning of the picture group (GOP) and a new video encryption key (VEK) is available, the current video encryption key (VEK) can be invalidated and the new video encryption key (VEK) can be activated, otherwise the current video encryption key (VEK) continues to be used.

[0332] S1203: Determine a reconstructed image according to the decoded bit stream.

[0333] The following will be combined Figures 13-16 A coding and decoding device for executing the coding and decoding method is introduced.

[0334] It is understandable that, in order to realize the above functions, the encoding device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0335] The embodiment of the present application can divide the functional modules of the encoding device according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0336] In the case of dividing each functional module into corresponding functional modules, Fig.13 A possible schematic diagram of the composition of the encoding device involved in the above embodiment is shown. Fig.13 As shown, the encoding device 1300 may include: an encoding unit 1301 and an authentication unit 1302.

[0337] The encoding unit 1301 is used to perform encoding operations on multiple display images and the above-mentioned multiple CRR images to obtain a code stream, wherein the above-mentioned code stream includes a security parameter set and an authentication data set, and the above-mentioned security parameter set includes first information and second information. The above-mentioned first information is used to indicate the algorithm used for generating the tree top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature.

[0338] The authentication unit 1302 is used to authenticate the data to be authenticated according to the first information to obtain first tree top summary data, where the first tree top summary data is the tree top summary data of the encoding end, and the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0339] The authentication unit 1302 is further configured to perform signature calculation on the first tree top summary data according to the second information to obtain a digital signature. The authentication unit is further configured to encapsulate the digital signature into the authentication data set.

[0340] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0341] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag=0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag=1 indicates that the current authentication data belongs to a CRR slice, and all CRR slices are constrained to be authenticated.

[0342] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0343] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0344] In a possible implementation, the authentication data set further includes fifth information, and the fifth information is used to indicate a CRR image corresponding to an authentication range of the specified current authentication data set.

[0345] Exemplarily, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to which CRR image the authentication range of the current authentication data set belongs. This parameter can be parsed only when is_crr_flag=1.

[0346] In a possible implementation, the authentication unit 1302 is specifically used to: encode the data signature; and encapsulate the encoded data signature into the authentication data set.

[0347] In a possible implementation, the encoding unit 1301 is specifically used to: divide the above-mentioned CRR image to obtain multiple CRR slices; interleave the above-mentioned multiple CRR slices between the above-mentioned multiple display images to obtain a sequence of images to be encoded; and sequentially encode the above-mentioned CRR slices and the above-mentioned display images in the above-mentioned sequence of images to be encoded to obtain the above-mentioned code stream.

[0348] In a possible implementation, the code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

[0349] The embodiment of the present application can divide the functional modules of the decoding device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0350] In the case of dividing each functional module into corresponding functional modules, Fig.14 A possible schematic diagram of the composition of the decoding device involved in the above embodiment is shown. Fig.14 As shown, the decoding device 1400 may include: a transceiver unit 1401 and an authentication unit 1402 .

[0351] The transceiver unit 1401 is used to obtain a code stream, the code stream includes a security parameter set and an authentication data set, the security parameter set includes first information and second information, the first information is used to indicate the algorithm used to generate the tree top summary, the second information is used to indicate the algorithm used for digital signature, and the authentication data set includes a digital signature.

[0352] The authentication unit 1402 is used to decode the digital signature according to the second information to obtain first tree top summary data, where the first tree top summary data is the tree top summary data of the encoding end, and the first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0353] The authentication unit 1402 is further configured to authenticate the authentication data corresponding to the authentication data set according to the first information to obtain second tree top summary data, where the second tree top summary data is the tree top summary data of the decoding end, and the first tree top summary data includes the tree top summary data of the N main bit streams and / or the M CRR slice bit streams.

[0354] The authentication unit 1402 is further configured to verify the authentication data according to the first tree-top summary and the second tree-top summary data.

[0355] In a possible implementation, the authentication unit 1402 is specifically configured to: decode the digital signature; and decode the decoded digital signature according to the second information to obtain first tree-top summary data.

[0356] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0357] In a possible implementation, the authentication data set further includes fourth information, and the fourth information is used to indicate the number of authenticated picture streams.

[0358] In the case of dividing each functional module into corresponding functional modules, Fig.15 Another possible schematic diagram of the composition of the encoding device involved in the above embodiment is shown. Fig.15 As shown, the encoding device 1500 may include: an encoding unit 1501 and an encryption unit 1502.

[0359] The encoding unit 1501 is used to perform encoding operations on multiple display images and the multiple CRR images to obtain a code stream, where the code stream includes a security parameter set, and the security parameter set includes a video encryption key.

[0360] The encryption unit 1502 is used to encrypt the code stream according to the video encryption key.

[0361] In a possible implementation, the encryption unit 1502 is specifically used to: encrypt the payload data of the above-mentioned code stream according to the above-mentioned video encryption key, and the above-mentioned payload data includes at least one of the sequence parameter set SPS, the picture parameter set PPS, the main bit stream and the CRR slice bit stream.

[0362] In the case of dividing each functional module into corresponding functional modules, Fig.16 Another possible schematic diagram of the composition of the decoding device involved in the above embodiment is shown. Fig.16 As shown, the decoding device 1600 may include: a transceiver unit 1601, a decryption unit 1602 and a reconstruction unit 1603.

[0363] The transceiver unit 1601 is used to obtain a bitstream, where the bitstream includes a security parameter set, and the security parameter set includes a video encryption key.

[0364] The decryption unit 1602 is used to decrypt the code stream according to the video encryption key.

[0365] The reconstruction unit 1603 is used to determine the reconstructed image according to the decoded code stream.

[0366] In a possible implementation, the decryption unit 1602 is specifically used to: decrypt the payload data of the above-mentioned code stream according to the above-mentioned video encryption key, and the above-mentioned payload data includes at least one of SPS, PPS, main bit stream and CRR slice bit stream.

[0367] An embodiment of the present application also provides an encoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the above-mentioned related method steps to implement the encoding method in the above-mentioned embodiment.

[0368] Optionally, the device may further include at least one memory, and the at least one memory is used to store the program code or instruction.

[0369] An embodiment of the present application also provides a decoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the above-mentioned related method steps to implement the decoding method in the above embodiment.

[0370] Optionally, the device may further include at least one memory, and the at least one memory is used to store the program code or instruction.

[0371] An embodiment of the present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an encoding device, the encoding device executes the above-mentioned related method steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0372] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0373] The embodiment of the present application also provides a coding and decoding device, which can be a chip, an integrated circuit, a component or a module. Specifically, the device may include a connected processor and a memory for storing instructions, or the device includes at least one processor for obtaining instructions from an external memory. When the device is running, the processor can execute instructions so that the chip executes the coding and decoding methods in the above-mentioned method embodiments.

[0374] Fig.17 1 shows a schematic diagram of the structure of a chip 1700. The chip 1700 includes one or more processors 1701 and an interface circuit 1702. Optionally, the chip 1700 may also include a bus 1703.

[0375] The processor 1701 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above encoding and decoding method may be completed by an integrated logic circuit of hardware in the processor 1701 or by instructions in the form of software.

[0376] Optionally, the processor 1701 may be a general purpose processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0377] The interface circuit 1702 can be used to send or receive data, instructions or information. The processor 1701 can use the data, instructions or other information received by the interface circuit 1702 to process, and can send the processing completion information through the interface circuit 1702.

[0378] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory (NVRAM).

[0379] Optionally, the memory stores executable software modules or data structures, and the processor can perform corresponding operations by calling operation instructions stored in the memory (the operation instructions can be stored in the operating system).

[0380] Optionally, the chip can be used in the encoding device or DOP involved in the embodiment of the present application. Optionally, the interface circuit 1702 can be used to output the execution result of the processor 1701. The encoding and decoding method provided by one or more embodiments of the embodiment of the present application can refer to the aforementioned embodiments, which will not be repeated here.

[0381] It should be noted that the corresponding functions of the processor 1701 and the interface circuit 1702 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0382] Fig.18 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 1800 may be a device or a chip or a functional module in the device. Fig.18 As shown, the electronic device 1800 includes a processor 1801 , a transceiver 1802 and a communication circuit 1803 .

[0383] The processor 1801 is used to execute any step of the method provided in the embodiment of the present application, and when executing processes such as receiving a coded image bit stream, the transceiver 1802 and the communication line 1803 may be selectively called to complete corresponding operations.

[0384] Furthermore, the electronic device 1800 may also include a memory 1804. The processor 1801, the memory 1804 and the transceiver 1802 may be connected via a communication line 1803.

[0385] The transceiver 1802 is used to communicate with other devices or other communication networks, and other communication networks may be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The transceiver 1802 may be a module, a circuit, a transceiver or any device capable of achieving communication.

[0386] The transceiver 1802 is mainly used for sending and receiving bit streams, etc., and may include a transmitter and a receiver, which respectively send and receive bit streams, etc.; operations other than sending and receiving bit streams, etc. are implemented by the processor, such as enabling at least one target channel in the channel group of the chip, etc.

[0387] The communication line 1803 is used to transmit information between the components included in the electronic device 1800.

[0388] In one design, the processor may be considered as the logic circuit and the transceiver may be considered as the interface circuit.

[0389] The memory 1804 is used to store instructions, where the instructions may be computer programs.

[0390] It should be noted that the memory 1804 can exist independently of the processor 1801, or can be integrated with the processor 1801. The memory 1804 can be used to store instructions or program codes or some data, etc. The memory 1804 can be located inside the electronic device 1800, or outside the electronic device 1800, without limitation. The processor 1801 is used to execute the instructions stored in the memory 1804 to implement the method provided in the above embodiment of the present application.

[0391] In one example, the processor 1801 may include one or more processors, such as Fig.18 Processor 0 and processor 1 in.

[0392] As an optional implementation, the electronic device 1800 includes multiple processors, for example, Fig.18In addition to the processor 1801, a processor 1807 may also be included.

[0393] As an optional implementation, the electronic device 1800 further includes an output device 1805 and an input device 1806. Exemplarily, the input device 1806 is a keyboard, a mouse, a microphone, a joystick, and the like, and the output device 1805 is a display screen, a speaker, and the like.

[0394] It should be noted that the electronic device 1800 may be a chip system or a Fig.18 Devices with similar structures in the chip system. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message name or parameter name in the message exchanged between the various devices in the embodiment of this application is only an example, and other names can also be used in the specific implementation without limitation. In addition, Fig.18 The components shown in the figure do not constitute a limitation on the electronic device 1800. Fig.18 In addition to the components shown, the electronic device 1800 may include Fig.18 More or fewer components may be shown, or certain components may be combined, or the components may be arranged differently.

[0395] The processor and transceiver described in the present application can be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0396] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes any of the methods described in the embodiments of the present application.

[0397] The embodiment of the present application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be completed by a computer or a device with encoding and decoding capabilities executing a computer program or instruction to control the relevant hardware. The computer program or the group of instructions can be stored in the above computer-readable storage medium. When the computer program or the group of instructions is executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be an internal storage unit of the control end of any of the above embodiments, such as a hard disk or memory of the control end. The above computer-readable storage medium can also be an external storage device of the above control end, such as a plug-in hard disk equipped on the above control end, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both the internal storage unit of the above control end and an external storage device. The above computer-readable storage medium is used to store the above computer program or instruction and other programs and data required by the above control end. The above computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0398] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0399] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0400] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0401] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0402] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0403] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0404] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A coding method, characterized in that: The method comprises: Performing encoding operations on multiple display images and multiple reference images to obtain a code stream, wherein the code stream includes a security parameter set and an authentication data set, wherein the security parameter set includes first information and second information, wherein the first information is used to indicate an algorithm used for authentication, and the second information is used to indicate an algorithm used for digital signature; Authenticate the data to be authenticated according to the first information to obtain first tree top summary data, where the first tree top summary data is tree top summary data of the encoding end, and the first tree top summary data includes tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers; Performing signature calculation on the first tree top summary data according to the second information to obtain a digital signature; The digital signature is encapsulated into the authentication data set.

2. The method according to claim 1, characterized in that The authentication data set also includes third information, and the third information is used to indicate whether the authentication data belongs to the CRR slice.

3. The method according to claim 1 or 2, characterized in that: The authentication data set also includes fourth information, and the fourth information is used to indicate the length of the signature data.

4. The method according to any one of claims 1 to 3, characterized in that The authentication data set also includes fifth information, and the fifth information is used to indicate a reference image corresponding to an authentication range of the specified current authentication data set.

5. The method according to any one of claims 1 to 4, characterized in that The code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

6. The method according to any one of claims 1 to 5, characterized in that The reference image includes a CRR image.

7. A decoding method, characterized in that: The method comprises: Acquire a code stream, wherein the code stream is obtained by encoding the plurality of display images and the plurality of knowledge images, the code stream comprising a security parameter set, authentication data and a digital signature, the security parameter set comprising first information and second information, the first information being used to indicate an algorithm used for authentication, and the second information being used to indicate an algorithm for digitally signing summary data of the image; Decoding the digital signature according to the second information to obtain first summary data, wherein the first summary data includes summary data of N display images and / or summary data of M knowledge images, where N and M are positive integers; Authenticating the authentication data according to the first information to obtain second summary data, the second summary data including summary data of N display images and / or summary data of M knowledge images; The authentication data is verified according to the first digest data and the second digest data.

8. The method according to claim 7, characterized in that The code stream further includes third information, and the third information is used to indicate whether the authentication data belongs to a knowledge image.

9. The method according to claim 7 or 8, characterized in that: The code stream also includes fourth information, and the fourth information is used to indicate the length of the signature data.

10. The method according to any one of claims 7 to 9, characterized in that The code stream further includes fifth information, and the fifth information is used to indicate the knowledge image corresponding to the authentication scope of the authentication data.

11. The method according to any one of claims 7 to 10, characterized in that The code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

12. The method according to any one of claims 7 to 11, characterized in that The reference image includes a CRR image.

13. A coding method, characterized in that: The method comprises: Performing encoding operation on multiple display images and the multiple reference images to obtain a code stream, wherein the code stream includes a security parameter set, and the security parameter set includes a video encryption key; The code stream is encrypted according to the video encryption key.

14. A decoding method, characterized in that: The method comprises: Acquire a bitstream, wherein the bitstream is obtained by encoding a plurality of display images and a plurality of reference images, wherein the bitstream includes a security parameter set, and the security parameter set includes a video encryption key; Decrypting the bitstream according to the video encryption key; The reconstructed image is determined according to the decoded bitstream.

15. A coding device, characterized in that: Comprising modules for executing the method as claimed in any one of claims 1 to 6.

16. A decoding device, characterized in that: Comprising means for executing the method as claimed in any one of claims 7 to 12.

17. A coding device, characterized in that: The device comprises a processor coupled to a memory, wherein the memory is used to store instructions. When the instructions are executed by the processor, the device performs the method according to any one of claims 1 to 6 or 13.

18. A decoding device, characterized in that: The device comprises a processor coupled to a memory, wherein the memory is used to store instructions. When the instructions are executed by the processor, the device performs the method according to any one of claims 7 to 12 or 14.

19. A computer-readable storage medium for storing a computer program, characterized in that: When the computer program is executed, the method according to any one of claims 1 to 14 is performed.

20. A computer program product, comprising instructions, characterized in that: When the instructions are executed, the method according to any one of claims 1 to 14 is performed.

21. A chip comprising at least one processor and a memory, characterized in that: The at least one processor executes a program or instruction stored in the memory, so that the information processing device implements the method according to any one of claims 1 to 14.

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