Data packet sending system and method, data packet receiving system and method

Abstract

Embodiments of the present application provide a data packet sending system and method, and a data packet receiving system and method. The data packet sending system includes: a multi-channel cross-coding circuit, used to perform cross-coding processing on multiple first data packets from multiple virtual channels to obtain a first coded signal; a multi-mode transmission processing circuit, connected to the multi-channel cross-coding circuit, used to perform a first equalization processing on the first coded signal to obtain a second coded signal; a first multi-channel selection circuit, connected to the multi-mode transmission processing circuit, used to select a first transmission channel in the multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and more specifically, to a system and method for sending a data packet, and a system and method for receiving a data packet. Background Art

[0002] In response to the growing number of processor cores and complex data sharing requirements, processors are moving towards a multi-core architecture. As the number of processor cores increases, processors need to support more nodes and better inter-chip communication interconnection to achieve higher parallel computing capabilities and processing performance. In addition, processors have higher requirements for memory access speed and data transmission bandwidth. In order to meet communication and interconnection requirements, traditional inter-chip interconnection architectures often consider increasing the number of parallel interconnection interfaces to improve performance, so as to speed up the overall processing speed by processing multiple tasks or data streams in parallel. At the same time, its interconnection method faces challenges in bandwidth and latency, especially when high-frequency signals are transmitted, signal attenuation and interference problems are more serious. At the same time, high-density interconnection also limits heat dissipation efficiency and affects the stability and reliability of the processor. In view of the shortcomings of traditional interconnection methods, it is necessary to optimize the inter-chip interconnection architecture.

[0003] Figure 2 The interconnection method in the traditional processor architecture is shown. The same interconnection structure is used in multiple interconnection links, including a transmission processing circuit, a transmission channel, and a reception processing circuit. The transmission channel is composed of one or more forms such as through silicon vias, a redistribution layer, or a PCB trace. Each interface has a corresponding transmission channel.

[0004] Traditional inter-chip interconnection links have problems such as high interconnection density, long transmission paths, and strong interference, which seriously affect the performance in terms of transmission rate, transmission time, and applicable scope. Moreover, with the increase in transmission frequency, high-density signal transmission will also cause problems such as high power consumption and low heat dissipation efficiency, increase the link bit error rate, and reduce the quality of the transmission signal, which in turn affects the stability and reliability of the processor, making it difficult to meet the application requirements of high computing power between the processor and storage.

[0005] In the related art, there is no effective solution to the technical problems such as strong interference in the inter-chip D2D interconnection link when the core processor accesses the storage data. Summary of the invention

[0006] The embodiments of the present application provide a system and method for sending a data packet, and a system and method for receiving a data packet, so as to at least solve the problem in the related art that a core processor has strong interference in an inter-chip D2D interconnection link when accessing stored data.

[0007] According to one embodiment of the present application, a data packet sending system is provided, which is arranged at a sending end and includes: a multi-channel cross-coding circuit, used to perform cross-coding processing on multiple first data packets from multiple virtual channels to obtain a first coded signal; a multi-mode transmission processing circuit, connected to the multi-channel cross-coding circuit, used to perform a first equalization processing on the first coded signal to obtain a second coded signal; a first multi-channel selection circuit, connected to the multi-mode transmission processing circuit, used to select a first transmission channel in the multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

[0008] In an exemplary embodiment, the data packet sending system also includes an arbitration circuit, and the arbitration circuit is used to: receive the second coded signal output by the multi-mode transmission processing circuit, and receive the third coded signal output by the multi-mode reception processing circuit of the receiving end; compare and analyze the second coded signal and the third coded signal to determine the transmission accuracy corresponding to the second coded signal; adjust the transmission mode of the first coded signal according to the transmission accuracy, wherein the transmission mode includes: signal selection, a first processing circuit, and a transmission channel, and the first processing circuit is used to perform a first equalization processing on the first coded signal.

[0009] In an exemplary embodiment, the arbitration circuit is also used to: determine whether the transmission accuracy is lower than a preset threshold; when the transmission accuracy is higher than the preset threshold, not adjust the transmission mode of the second coded signal; when the transmission accuracy is lower than the preset threshold, adjust the transmission mode of the first coded signal according to the error count value of the second coded signal, wherein the error count value is used to indicate the number of second coded signals with transmission errors.

[0010] In an exemplary embodiment, the arbitration circuit is also used to: convert the error count value into a binary signal value, wherein the binary signal value is an m+n-bit signal value, and m is a positive integer; send the high m-bit signal in the binary signal value to the multi-mode transmission processing circuit to instruct the multi-mode transmission processing circuit to perform a first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal, and send the binary signal value to the multi-mode reception processing circuit to instruct the multi-mode reception processing circuit to perform a second equalization processing on the second coded signal according to the binary signal value to obtain the third coded signal.

[0011] In an exemplary embodiment, the multi-mode transmission processing circuit is also used to: receive the high m-bit signal sent by the arbitration circuit; determine the signal selection of the first coded signal according to the first sub-signal in the high m-bit signal, and determine the first processing circuit corresponding to the first coded signal according to the second sub-signal in the high m-bit signal.

[0012] In an exemplary embodiment, the data packet sending system further includes a link detection unit, which is used to: detect the channel status of the n transmission channels and generate a channel status signal based on the n channel statuses, wherein the channel status includes an idle state and a busy state, and the channel status signal is an n-bit binary signal; and send the channel status signal to the arbitration circuit.

[0013] In an exemplary embodiment, the arbitration circuit is also used to: receive the channel status signal sent by the link detection unit; perform AND processing on the channel status signal and the low n bits of the binary signal value to obtain a processing result, and send the processing result to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second coded signal according to the processing result, wherein the processing result is an n-bit binary signal.

[0014] In an exemplary embodiment, the first multiplexer circuit is further configured to: receive the processing result sent by the arbitration circuit; and select the first transmission channel from the n transmission channels according to a high-level signal in the processing result.

[0015] According to another embodiment of the present application, a data packet receiving system is provided, which is arranged at a receiving end and includes: a second multi-way selection circuit, used to receive a second coded signal transmitted by a transmitting end through a first transmission channel in a multi-mode transmission channel, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; a multi-mode receiving and processing circuit, connected to the second multi-way selection circuit, used to perform a second equalization processing on the second coded signal to obtain a third coded signal; a multi-way cross-decoding circuit, connected to the multi-mode receiving and processing circuit, used to perform cross-decoding processing on the third coded signal to obtain multiple second data packets.

[0016] In an exemplary embodiment, the multi-mode receiving and processing circuit is also used to: receive a binary signal value sent by the arbitration circuit of the sending end, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; determine the signal selection of the second coded signal according to the first sub-signal in the high m-bit signal in the binary signal value, and determine the second processing circuit corresponding to the second coded signal according to the second sub-signal in the high m-bit signal, wherein the second processing circuit is used to perform second equalization processing on the second coded signal.

[0017] According to another embodiment of the present application, a method for sending a data packet is provided, which is applied to the above-mentioned data packet sending system, including: cross-coding multiple first data packets from multiple virtual channels to obtain a first coded signal; performing a first equalization process on the first coded signal to obtain a second coded signal; selecting a first transmission channel in a multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

[0018] In an exemplary embodiment, the method also includes: receiving a third coded signal output by the multi-mode receiving processing circuit of the receiving end; performing comparative analysis on the second coded signal and the third coded signal to determine the transmission accuracy corresponding to the second coded signal; and adjusting the transmission mode of the first coded signal according to the transmission accuracy, wherein the transmission mode includes: signal selection, a first processing circuit, and a transmission channel, and the first processing circuit is used to perform a first equalization processing on the first coded signal.

[0019] In an exemplary embodiment, the adjusting the transmission mode of the first coded signal according to the transmission accuracy includes: determining whether the transmission accuracy is lower than a preset threshold; when the transmission accuracy is higher than the preset threshold, not adjusting the transmission mode of the second coded signal; when the transmission accuracy is lower than the preset threshold, adjusting the transmission mode of the first coded signal according to an error count value of the second coded signal, wherein the error count value is used to indicate the number of second coded signals with transmission errors.

[0020] In an exemplary embodiment, the adjusting the transmission mode of the first coded signal according to the error count value of the second coded signal includes: converting the error count value into a binary signal value, wherein the binary signal value is an m+n-bit signal value, and m is a positive integer; sending the high m-bit signal in the binary signal value to the multi-mode transmission processing circuit to instruct the multi-mode transmission processing circuit to perform a first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal, and sending the binary signal value to the multi-mode reception processing circuit to instruct the multi-mode reception processing circuit to perform a second equalization processing on the second coded signal according to the binary signal value to obtain the third coded signal.

[0021] In an exemplary embodiment, the method further includes: determining a signal type of the first coded signal according to a first sub-signal in the upper m-bit signal, and determining a first processing circuit corresponding to the first coded signal according to a second sub-signal in the upper m-bit signal.

[0022] In an exemplary embodiment, the method further includes: detecting channel states of the n transmission channels, and generating a channel state signal according to the n channel states, wherein the channel state includes an idle state and a busy state, and the channel state signal is an n-bit binary signal.

[0023] In an exemplary embodiment, the method further includes: performing AND processing on the channel status signal and the lower n bits of the binary signal value to obtain a processing result, and sending the processing result to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second encoded signal according to the processing result, wherein the processing result is an n-bit binary signal.

[0024] In an exemplary embodiment, the method further includes: selecting the first transmission channel from the n transmission channels according to the high-level signal in the processing result.

[0025] According to another embodiment of the present application, a method for receiving a data packet is provided, which is applied to the above-mentioned data packet receiving system, including: receiving a second coded signal transmitted by a transmitting end through a first transmission channel in a multi-mode transmission channel, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; performing a second equalization process on the second coded signal to obtain a third coded signal; and performing a cross-decoding process on the third coded signal to obtain multiple second data packets.

[0026] In an exemplary embodiment, the method also includes: receiving a binary signal value sent by the arbitration circuit of the sending end, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; determining the signal selection of the second coded signal according to the first sub-signal in the high m-bit signal in the binary signal value, and determining the second processing circuit corresponding to the second coded signal according to the second sub-signal in the high m-bit signal, wherein the second processing circuit is used to perform second equalization processing on the second coded signal.

[0027] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0028] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0029] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0030] Through the present application, a data packet sending system is proposed, which includes: a multi-channel cross-coding circuit, which is used to perform cross-coding processing on multiple first data packets from multiple virtual channels to obtain a first coded signal; a multi-mode transmission processing circuit, which is connected to the multi-channel cross-coding circuit, and is used to perform a first equalization processing on the first coded signal to obtain a second coded signal; a first multi-channel selection circuit, which is connected to the multi-mode transmission processing circuit, and is used to select a first transmission channel in a multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel includes n transmission channels, and the n transmission channels include the first transmission channel, and n is a positive integer; adopting the above scheme, by adopting a cross-coding method based on time-sharing polling, the data packets are dispersedly transmitted in multiple links, so as to solve the problem of linear interference of signals and enhance the transmission reliability of the links; thereby solving the technical problems in the related art of strong interference and other problems existing in the inter-chip D2D interconnection link when the core processor accesses the stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a hardware structure block diagram of a computer terminal according to a method for sending a data packet in an embodiment of the present application;

[0032] Figure 2is a schematic diagram of an interconnection method of a processor architecture according to an embodiment of the present application;

[0033] Figure 3 is a structural block diagram of a data packet sending system according to an embodiment of the present application (I);

[0034] Figure 4 is a structural block diagram of a data packet sending system according to an embodiment of the present application (II);

[0035] Figure 5 is a structural block diagram of a data packet receiving system according to an embodiment of the present application;

[0036] Figure 6 It is a flowchart of an optional D2D interconnection link data transmission method according to an embodiment of the present application;

[0037] Figure 7 is a schematic structural diagram of an optional D2D interconnection link according to an embodiment of the present application;

[0038] Figure 8 is a schematic diagram of an optional multi-path cross-coding process according to an embodiment of the present application;

[0039] Fig. 9 is a schematic structural diagram of an optional arbitration circuit according to an embodiment of the present application;

[0040] Fig.10 is a schematic structural diagram of an optional transmitting end multi-mode processing circuit according to an embodiment of the present application;

[0041] Fig.11 is a schematic structural diagram of an optional receiving-end multi-mode processing circuit according to an embodiment of the present application;

[0042] Fig.12 is a schematic diagram of an optional multi-path cross decoding process according to an embodiment of the present application;

[0043] Fig.13 is a flowchart of an optional method for sending a data packet according to an embodiment of the present application;

[0044] Fig.14 This is a flowchart of an optional method for receiving a data packet according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal for determining a comprehensive evaluation index in an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0048] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the comprehensive evaluation index in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0049] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0050] The following is a further explanation of the technical terms used in this application to facilitate understanding of the technical solutions described in this application:

[0051] D2D: Die-to-Die, die to die;

[0052] NRZ: Non Return Zero, non-return to zero code;

[0053] PARM4: Pluse Amplitude Modulation 4, four-level pulse amplitude modulation;

[0054] FFE: Feed-forward Equalizer, feed-forward equalizer;

[0055] CTLE: Continuous Time Linear Equalizer, continuous time linear equalizer;

[0056] DFE: Decision Feedback Equalizer, decision feedback equalizer.

[0057] In this embodiment, a data packet sending system is provided, which is arranged at a sending end. Figure 3 is a structural block diagram of a system for sending a data packet according to an embodiment of the present application, such as Figure 3 As shown, the system includes:

[0058] A multi-channel cross-coding circuit 32, used for performing cross-coding processing on a plurality of first data packets from a plurality of virtual channels to obtain a first coded signal;

[0059] A multi-mode transmission processing circuit 34, connected to the multi-path cross coding circuit, configured to perform a first equalization process on the first coded signal to obtain a second coded signal;

[0060] The first multi-path selection circuit 36 ​​is connected to the multi-mode transmission processing circuit, and is used to select a first transmission channel in the multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to the receiving end, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

[0061] Through the above scheme, a data packet sending system is proposed, which includes: a multi-channel cross-coding circuit, which is used to perform cross-coding processing on multiple first data packets from multiple virtual channels to obtain a first coded signal; a multi-mode transmission processing circuit, which is connected to the multi-channel cross-coding circuit, and is used to perform a first equalization processing on the first coded signal to obtain a second coded signal; a first multi-channel selection circuit, which is connected to the multi-mode transmission processing circuit, and is used to select a first transmission channel in the multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel includes n transmission channels, and the n transmission channels include the first transmission channel, and n is a positive integer; by adopting the above scheme, by adopting a cross-coding method based on time-sharing polling, the data packets are dispersedly transmitted in multiple links, the problem of linear interference of signals is solved, and the transmission reliability of the link is enhanced; thereby solving the technical problems in the related art that when the core processor accesses storage data, there is strong interference and other problems in the inter-chip D2D interconnection link.

[0062] In an exemplary embodiment, the data packet sending system further includes an arbitration circuit 38, such as Figure 4 As shown, the arbitration circuit 38 is used to: receive the second coded signal output by the multi-mode transmission processing circuit, and receive the third coded signal output by the multi-mode reception processing circuit of the receiving end; compare and analyze the second coded signal and the third coded signal to determine the transmission accuracy corresponding to the second coded signal; adjust the transmission mode of the first coded signal according to the transmission accuracy, wherein the transmission mode includes: signal selection, a first processing circuit, and a transmission channel, and the first processing circuit is used to perform a first equalization processing on the first coded signal.

[0063] In this embodiment, the data packet sending system integrates a key component, the arbitration circuit 38, and its working process is as follows:

[0064] 1. Arbitration circuit receiving signal: Arbitration circuit 38 receives the second coded signal from the multi-mode transmission processing circuit, and simultaneously receives the third coded signal output from the multi-mode reception processing circuit of the receiving end. This shows that the arbitration circuit can monitor the signal status of the transmitting end and the receiving end, and is the core of the entire link control.

[0065] 2. Signal comparison and analysis: The arbitration circuit compares and analyzes the two coded signals. Its main task is to determine the accuracy of the second coded signal during transmission. The accuracy analysis is based on the quality of the signal, such as the bit error rate, which helps to understand the actual performance of the link.

[0066] 3. Transmission mode adjustment: Based on the transmission accuracy obtained through comparative analysis, the arbitration circuit can decide whether to adjust the signal selection, the first processing circuit selection, and the use of the transmission channel. Signal selection refers to the selection of NRZ encoding or PAM4 encoding; the adjustment of the first processing circuit involves whether to enable signal processing mechanisms such as pre-emphasis and FFE; the selection of the transmission channel ensures that the signal is transmitted through the best path to reduce delays and interference.

[0067] Through the arbitration circuit, the present application achieves the following beneficial effects:

[0068] 1. Enhanced link adaptability and reliability: The dynamic adjustment mechanism of the arbitration circuit enables the system to optimize the transmission mode according to the current link status, improves the stability and reliability of transmission, and maintains efficient data transmission even when network conditions change.

[0069] 2. Reduced bit error rate: By continuously monitoring and adjusting the signal processing method, the arbitration circuit can effectively reduce the bit error rate in the link and ensure the accuracy and integrity of signal transmission, which is crucial for high-bandwidth, low-latency storage access scenarios.

[0070] 3. Optimized signal processing and transmission path: The arbitration circuit can select the most suitable processing circuit and transmission channel according to the transmission characteristics of the signal, such as selecting a pre-emphasis circuit under an NRZ signal, or selecting an FFE circuit under a PAM4 signal. This intelligent selection improves the transmission efficiency and quality of the signal.

[0071] 4. Lightweight link management is achieved: By controlling the signal selection and sharing of transmission channels through arbitration circuits, the number of required links is reduced, the system complexity and power consumption are reduced, and lightweight inter-chip interconnection is achieved, which is particularly beneficial for processor scenarios with high-density integration and high computing power requirements.

[0072] In summary, by introducing the arbitration circuit, not only the key technical problems in signal transmission are solved, but also the performance and efficiency of the D2D interconnection link are significantly improved.

[0073] Optionally, the arbitration circuit 38 is also used to: determine whether the transmission accuracy is lower than a preset threshold; when the transmission accuracy is higher than the preset threshold, not adjust the transmission mode of the second coded signal; when the transmission accuracy is lower than the preset threshold, adjust the transmission mode of the first coded signal according to the error count value of the second coded signal, wherein the error count value is used to indicate the number of second coded signals with transmission errors.

[0074] In a further embodiment of the present application, the operation of the arbitration circuit 38 is not limited to the dynamic adjustment of the signal transmission mode, but it also has an intelligent threshold judgment mechanism for determining when to adjust the transmission mode and when to keep the current state unchanged. The specific workflow is as follows:

[0075] 1. Transmission accuracy evaluation: The arbitration circuit 38 continuously monitors the transmission accuracy of the second coded signal, that is, the quality of the signal after transmission on the link, especially the bit error rate of the signal. This evaluation is based on the comparison between the received second coded signal and the third coded signal to determine the actual performance of the link transmission.

[0076] 2. Preset threshold judgment: The arbitration circuit 38 is provided with a preset threshold, which is used as a criterion for judging the transmission accuracy. If the transmission accuracy of the second coded signal is higher than the preset threshold, it means that the current transmission mode is effective enough and no adjustment is required, which helps to maintain system stability and avoid unnecessary processing delays.

[0077] 3. Error count trigger adjustment: When the transmission accuracy is lower than the preset threshold, the arbitration circuit 38 further analyzes the error count of the second coded signal, that is, the number of second coded signals with transmission errors. This value directly reflects the severity of the problem in the link.

[0078] 4. Transmission mode adjustment decision: Based on the size of the error count value, the arbitration circuit 38 can decide to adjust the transmission mode of the first coded signal, including the selection of the signal type (such as NRZ or PAM4), the activation of the first processing circuit (such as pre-emphasis, FFE circuit, etc.) and the switching of the transmission channel to optimize signal transmission and reduce bit errors.

[0079] The description of this embodiment illustrates the intelligence and efficiency of the arbitration circuit in signal transmission control. It achieves fine control of the signal transmission method by dynamically judging the comparison between the transmission accuracy and the preset threshold and utilizing the error count value. This not only ensures the high transmission quality of the link, but also avoids the additional overhead caused by excessive adjustment, reflecting the flexibility and reliability of the present application scheme.

[0080] Optionally, the arbitration circuit 38 is also used to: convert the error count value into a binary signal value, wherein the binary signal value is an m+n-bit signal value, and m is a positive integer; send the high m-bit signal in the binary signal value to the multi-mode transmission processing circuit to instruct the multi-mode transmission processing circuit to perform a first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal; and send the binary signal value to the multi-mode reception processing circuit to instruct the multi-mode reception processing circuit to perform a second equalization processing on the second coded signal according to the binary signal value to obtain the third coded signal.

[0081] In another embodiment of the present application, the arbitration circuit is not only responsible for monitoring the transmission accuracy and adjusting the processing method, but also further refines this process by converting the error count value obtained by error detection into an m+n-bit binary signal value to accurately guide the signal processing of the transmitting and receiving ends. The specific process is as follows:

[0082] 1. Error count value conversion: The arbitration circuit first calculates the error count value of the second coded signal, which is the number of signal errors that occurred during the transmission process, reflecting the transmission quality of the link. Then, this error count value is converted into an m+n-bit binary signal value, where m and n are both positive integers, which are used to control the signal processing methods of the transmitter and the receiver respectively.

[0083] 2. The high m-bit signal controls the transmitter: The high m-bit signal in the converted binary signal value is sent to the multi-mode transmission processing circuit. This signal directly instructs the transmission circuit how to adjust the processing method of the first coded signal. For example, when the high-bit signal indicates a specific value, the transmitter can switch to the FFE circuit equalization processing under the PAM4 signal, or the pre-emphasis processing under the NRZ signal to reduce the attenuation and interference of the signal during transmission, and finally obtain a more stable and high-quality second coded signal.

[0084] 3. Complete binary signal value controls the receiving end: The arbitration circuit sends the complete m+n-bit binary signal value to the multi-mode receiving processing circuit of the receiving end. The receiving end determines how to process the second coded signal based on the received signal value and performs corresponding equalization processing to restore the third coded signal. In this way, the receiving end can select the optimal processing mode (such as DFE, CTLE+DFE, etc.) based on the information provided by the arbitration circuit, further compensate for the signal loss in the transmission channel, and ensure the accuracy and integrity of signal transmission.

[0085] This embodiment realizes intelligent and dynamic signal processing control of the transmitter and receiver through the conversion and transmission of binary signal values, and can accurately adjust the signal processing method according to the real-time status of the link, thereby effectively improving the signal transmission quality and efficiency of the D2D interconnection link, reducing the bit error rate, and ensuring the stability and reliability of data transmission between the processor and the storage device. This control mechanism is one of the key points in the technical solution of this application, and provides a flexible and efficient solution for handling complex signal transmission problems.

[0086] Optionally, the multi-mode transmission processing circuit 34 is also used to: receive the high m-bit signal sent by the arbitration circuit; determine the signal selection of the first coded signal according to the first sub-signal in the high m-bit signal, and determine the first processing circuit corresponding to the first coded signal according to the second sub-signal in the high m-bit signal.

[0087] In the embodiment of the present application, the multi-mode transmission processing circuit not only undertakes the modulation and equalization processing of the signal, but also has the ability to receive and analyze the control signal sent by the arbitration circuit, thereby performing intelligent pre-processing on the signal. The specific implementation process is as follows:

[0088] 1. Control signal reception: The multi-mode transmission processing circuit receives the high m-bit signal from the arbitration circuit, which contains the control information obtained by the arbitration circuit based on the transmission quality analysis of the second coded signal. The high m-bit signal is composed of different sub-signals, each of which is responsible for indicating a specific control function.

[0089] 2. Signal selection determination: The first sub-signal in the high m-bit signal is used to determine the signal selection of the first coded signal. Signal selection refers to selecting the encoding method of the signal, such as selecting between NRZ (Non Return to Zero) or PAM4 (Pulse Amplitude Modulation 4) signal encoding. The value of the first sub-signal directly indicates which signal encoding method the transmitting circuit uses to adapt to the status and requirements of the link and improve the reliability of signal transmission.

[0090] 3. Processing circuit selection: The second sub-signal in the high m-bit signal is used to determine the first processing circuit corresponding to the first coded signal. The selection of the processing circuit refers to deciding which signal equalization technology to use based on the link characteristics, such as pre-emphasis (Pre-Emphasis), FFE (Feed-Forward Equalizer), etc. The value of the second sub-signal indicates which equalization processing method is enabled by the transmitting circuit to reduce signal distortion during transmission and improve signal quality.

[0091] The key to this embodiment is that the multi-mode transmission processing circuit can intelligently adjust the signal encoding method and the selection of the processing circuit based on the high m-bit signal sent by the arbitration circuit, thereby optimizing the signal transmission process and ensuring that the signal can be transmitted in the most suitable form and with the highest quality. This dynamic control mechanism is the key to improving the performance of D2D interconnection links. It can automatically select the best signal processing strategy according to the real-time status of the link and the signal transmission requirements, effectively solve the attenuation and interference problems in signal transmission, ensure high-speed, low-latency signal transmission, and meet the application requirements of high data transmission rates between processors and storage devices.

[0092] Optionally, the data packet sending system further includes a link detection unit 40, such as Figure 4 As shown, it is used to: detect the channel status of the n transmission channels, and generate a channel status signal according to the n channel status, wherein the channel status includes an idle state and a busy state, and the channel status signal is an n-bit binary signal; send the channel status signal to the arbitration circuit.

[0093] In the embodiment of the present application, the data packet transmission system also includes a very important component - a link detection unit, which is responsible for monitoring and reporting the real-time status of the transmission channel, thereby providing a decision basis for the arbitration circuit to optimize the signal transmission path and processing method. The specific implementation process is as follows:

[0094] 1. Channel status detection: The link detection unit continuously detects the status of n transmission channels, which are divided into two types: idle state and busy state. The idle state means that the transmission channel is not currently transmitting data and can be used to send new data; the busy state means that the channel is transmitting data and it is not suitable to send new data at this time to avoid data collision and transmission errors.

[0095] 2. Channel status signal generation: The link detection unit generates an n-bit binary signal as a channel status signal based on the real-time status of n channels. In the generated signal, if a transmission channel is idle, the corresponding bit is 0 (or 1, the specific representation method may depend on the specific design); if the channel is busy, the corresponding bit is 1 (or 0). This binary signal form can clearly and quickly reflect the idle or busy status of each channel, which is convenient for the arbitration circuit to make a quick judgment.

[0096] 3. Channel status signal transmission: The channel status signal generated by the link detection unit is sent to the arbitration circuit. After receiving these signals, the arbitration circuit will combine the transmission accuracy evaluation results to determine the signal selection, processing method, and ultimately which transmission channel to choose for data transmission. Through interaction with the arbitration circuit, the link detection unit ensures the rational use of the transmission channel, avoids excessive use of the channel and waste of resources, and improves the overall transmission efficiency of the link.

[0097] The key role of this embodiment is that the link detection unit provides real-time data support for the dynamic resource allocation of the entire system. It can ensure that the data packets are transmitted on the optimal transmission path, avoiding redundant signal transmission and collision risks. At the same time, by dynamically monitoring the channel status, it can also realize resource sharing between transmission channels, reduce the total number of D2D interconnected links, reduce system complexity and cost, and improve the stability and reliability of signal transmission. It is an important component of improving link performance in this application.

[0098] Optionally, the arbitration circuit 38 is also used to: receive the channel status signal sent by the link detection unit; perform AND processing on the channel status signal and the low n bits of the binary signal value to obtain a processing result, and send the processing result to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second coded signal according to the processing result, wherein the processing result is an n-bit binary signal.

[0099] In the embodiment of the present application, the arbitration circuit not only adjusts the signal processing mode based on the quality of the transmission signal, but also further optimizes the selection of the signal transmission path by receiving the channel status signal sent by the link detection unit. The specific implementation process is as follows:

[0100] 1. Receive channel status signal: The arbitration circuit receives the n-bit channel status signal sent by the link detection unit, which details the current idle or busy status of the n transmission channels. A bit value of 0 (or 1, depending on the specific design) represents an idle channel, and a bit value of 1 (or 0) represents a busy channel.

[0101] 2. Signal processing and AND operation: The arbitration circuit performs a logical AND operation on the received channel status signal and the lower n-bit signal in the previously generated m+n-bit binary signal value. The lower n-bit signal is the part converted by the arbitration circuit based on the error count value of the transmission signal, which is used to indicate the selection of the transmission channel. Through the AND operation, the arbitration circuit can determine which channels are suitable choices based on the real-time status of the channels.

[0102] 3. Generate processing result signal: The result of the AND operation is an n-bit binary signal, namely the processing result signal. The bit value of this signal can clearly indicate which transmission channels meet the quality requirements of the current signal transmission and are in an idle state, suitable for signal transmission.

[0103] 4. Sending the processing result to the first multiplexer circuit: The arbitration circuit sends the processing result signal to the first multiplexer circuit. After receiving the signal, the first multiplexer circuit can select the optimal first transmission channel for the second coded signal according to the processing result for signal transmission, thereby ensuring efficient and stable transmission of the signal and avoiding channel conflicts and resource waste.

[0104] The description in this embodiment illustrates the core role of the arbitration circuit in signal transmission path selection. It can comprehensively consider the signal quality and channel status, and intelligently select a channel suitable for signal transmission through logical operations on binary signals. This is the key to improving the performance of D2D interconnection links. Through this mechanism, not only can the efficiency and reliability of signal transmission be improved, but also dynamic sharing and optimization of transmission resources can be achieved, the total number of transmission links in the system can be reduced, power consumption and heat dissipation problems can be reduced, and high-speed, low-latency data transmission between the processor and the storage device can be ensured, meeting the needs of high-computing power applications.

[0105] Optionally, the first multiplexer circuit 36 ​​is further used to: receive the processing result sent by the arbitration circuit; and select the first transmission channel from the n transmission channels according to a high-level signal in the processing result.

[0106] In the embodiment of the present application, the first multi-path selection circuit assumes the important responsibility of intelligently selecting a transmission channel according to the processing result given by the arbitration circuit to ensure that the second coded signal can be transmitted through the optimal path. The specific implementation process is as follows:

[0107] 1. Processing result reception: The first multiplexer circuit receives an n-bit processing result signal from the arbitration circuit. This signal is generated by the arbitration circuit after performing a logical AND operation based on the channel status signal and the lower n-bit signal in the binary signal value. Each bit value in the processing result signal reflects an indication of whether the corresponding transmission channel is selected as the transmission path.

[0108] 2. High-level signal identification: In the received processing result signal, the first multiplexer circuit identifies the high-level signal. The high-level signal indicates those transmission channels that meet the signal transmission quality requirements and are in an idle state. Since the processing result signal is based on a comprehensive evaluation of the real-time channel status and signal quality requirements, the presence of a high-level signal means that the corresponding transmission channel is an ideal choice for the current signal transmission.

[0109] 3. Selection of the first transmission channel: The first multiplexer circuit selects the first transmission channel from the n transmission channels as the actual transmission path of the second coded signal according to the high-level signal identified in the processing result signal. This selection process ensures that the signal can be transmitted in a channel that meets the transmission requirements, avoiding the waste of channel resources, and also prevents the signal from being sent on a busy channel or a channel with poor transmission quality, thereby improving the efficiency and stability of signal transmission.

[0110] This embodiment describes the intelligent decision-making ability of the first multi-path selection circuit in signal transmission control, which can quickly identify and select the first transmission channel according to the dynamic information provided by the arbitration circuit, and provide the optimal transmission path for the second coded signal. This mechanism is the key to improving the performance of D2D interconnection links. It can not only improve the efficiency of signal transmission and reduce delays, but also reduce the bit error rate and improve the accuracy of signal transmission through intelligent selection. It is an important part of realizing high computing power application requirements in this application.

[0111] Optionally, the embodiment of the present application further provides a data packet receiving system, which is arranged at a receiving end, such as Figure 5 As shown, the system includes:

[0112] A second multiplexing circuit 52 is used to receive a second coded signal transmitted by a transmitting end through a first transmission channel in a multimode transmission channel, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer;

[0113] a multi-mode receiving processing circuit 54, connected to the second multiplexing circuit, and configured to perform a second equalization process on the second coded signal to obtain a third coded signal;

[0114] The multi-path cross-decoding circuit 56 is connected to the multi-mode receiving processing circuit and is used to perform cross-decoding processing on the third coded signal to obtain a plurality of second data packets.

[0115] Through this embodiment, a data packet receiving system is provided, comprising: a second multi-way selection circuit, used to receive a second coded signal transmitted by a transmitting end through a first transmission channel in a multi-mode transmission channel, wherein the multi-mode transmission channel comprises n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; a multi-mode receiving and processing circuit, connected to the second multi-way selection circuit, used to perform a second equalization process on the second coded signal to obtain a third coded signal; a multi-way cross-decoding circuit, connected to the multi-mode receiving and processing circuit, used to perform cross-decoding process on the third coded signal to obtain a plurality of second data packets; by adopting the above scheme, by adopting a cross-coding method based on time-sharing polling, the data packets are dispersedly transmitted in multiple links, the problem of linear interference of signals is solved, and the transmission reliability of the link is enhanced; thereby solving the technical problems in the related art of strong interference and other problems existing in the inter-chip D2D interconnection link when the core processor accesses the stored data.

[0116] Optionally, the multi-mode receiving and processing circuit 54 is also used to: receive a binary signal value sent by the arbitration circuit of the sending end, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; determine the signal selection of the second coded signal according to the first sub-signal in the high-m-bit signal in the binary signal value, and determine the second processing circuit corresponding to the second coded signal according to the second sub-signal in the high-m-bit signal, wherein the second processing circuit is used to perform second equalization processing on the second coded signal.

[0117] In the embodiment of the present application, the multi-mode receiving and processing circuit is not only responsible for receiving and processing signals, but also can intelligently adjust the signal receiving and equalization processing mode according to the control information transmitted by the sending end arbitration circuit. The specific implementation process is as follows:

[0118] 1. Receiving control information: The multi-mode receiving processing circuit receives an m+n-bit binary signal value from the transmitting arbitration circuit. This signal value contains important instructions for the signal processing method. Both m and n are positive integers.

[0119] 2. Signal selection determination: From the received m+n-bit binary signal value, the multi-mode receiving processing circuit parses the first sub-signal in the high m-bit signal, which directly indicates the signal selection that the receiving circuit should adopt. Signal selection refers to determining the signal encoding method, for example, choosing between NRZ (Non Return to Zero) and PAM4 (Pulse Amplitude Modulation 4) signal encoding to adapt to the characteristics of the link and improve the accuracy and efficiency of signal reception.

[0120] 3. Processing circuit selection: The multi-mode receiving processing circuit further analyzes the second sub-signal in the high m-bit signal, which is used to indicate the second processing circuit corresponding to the second coded signal. The second processing circuit refers to a circuit used to perform equalization processing on the second coded signal, such as DFE (Decision Feedback Equalizer), FFE (Feed Forward Equalizer) or CTLE+DFE / FFE, etc. Different processing circuits can compensate for various attenuation and interference that the signal may encounter during transmission, thereby restoring the original quality of the signal.

[0121] 4. Second equalization processing: The multi-mode receiving processing circuit performs second equalization processing on the second coded signal according to the selected processing circuit, aiming to further reduce signal distortion and improve the quality and integrity of the received signal. This processing process is a key step in restoring the signal transmission quality and an important guarantee for ensuring accurate data transmission.

[0122] The key role of this embodiment is that the multi-mode receiving and processing circuit can dynamically adjust the signal receiving and processing strategy based on the control information provided by the sending end arbitration circuit to ensure that the signal can be received and interpreted in the best state, avoiding unnecessary delays and errors in the signal processing process, and improving the stability and reliability of signal transmission. It is an important part of optimizing the performance of the signal transmission link in this application. This intelligent control mechanism can flexibly adapt the most optimized signal processing method according to the real-time status of the link, and is one of the key technical points for realizing high-speed, low-latency D2D interconnection links.

[0123] In an optional embodiment, the present application provides an optional D2D interconnection link data transmission method, the process of which is as follows: Figure 6 As shown, the data transmission method of the D2D interconnection link is applied to an optional D2D interconnection link, and the structure of the D2D interconnection link is as follows Figure 7 As shown, the process of the data transmission method of the D2D interconnection link and the structure of the D2D interconnection link are described below in combination with an optional embodiment, specifically:

[0124] 1. The entire D2D link first receives data packets from the protocol layer, and divides and transmits them according to the specified virtual channels, realizing the transition from high-speed data transmission to low-speed data transmission, and solving the problem of tight timing of link transmission.

[0125] 2. Multi-channel cross coding performs signal dispersion and coding processing on low-rate data. Channels are selected according to the time-sharing polling method, and data packets in a virtual channel are dispersed to multiple transmission links in a channel-by-channel and bit-by-bit manner, and then coded. Figure 8 shown.

[0126] 3. The interleaved coded data is processed by the transmitter processing circuit (i.e. the multi-mode transmission processing circuit mentioned above), including signal modulation and signal equalization. The signal modulation and signal equalization are controlled by the arbitration circuit.

[0127] 4. The arbitration circuit receives the source signal and the output signal of the receiving end processing circuit, and compares and analyzes their accuracy to select the appropriate processing circuit and transmission channel.

[0128] 5. Fig. 9 The specific implementation form of the arbitration circuit is given. When the accuracy after comparison is lower than the counting threshold, the error count value needs to be converted into a (3+n)-bit binary signal value, and the signal selection, processing method and transmission channel are realized through the high-order 1bit (i.e. the first sub-signal mentioned above), the middle 2bits (i.e. the second sub-signal mentioned above) and the low-order nbit. When the low-order nbit is ANDed with the link status nbit (i.e. the channel status signal mentioned above), and a certain bit is high, the corresponding transmission channel is selected.

[0129] 6. If Fig.10 As shown in the figure, the multi-mode processing circuit at the transmitting end (i.e., the multi-mode transmitting processing circuit mentioned above) includes source modulation, direct path, pre-emphasis under NRZ signal, and FFE under PAM4 signal. When the high 1 bit is at a high level, the source modulation selects PAM4 as the transmission signal, and vice versa, selects NRZ as the transmission signal. When the middle 2 bits are 00, 10, and 11 respectively, the processing circuit selects direct path, pre-emphasis under NRZ signal, and FFE under PAM4 signal respectively.

[0130] 7. When the D2D interconnection selects the transmission channel, the link detection unit can monitor the status of each transmission channel, that is, idle and busy. As long as the transmission signal in the link is detected, the transmission channel is marked as low level, and the nbit status signal (that is, the above-mentioned channel status signal) is fed back to the arbitration circuit. The AND operation is performed with the converted nbit (that is, the above-mentioned low n-bit signal), and the level corresponding to a certain channel is obtained as a high level to connect the transmission channel. In this way, all transmission channels can be shared, the number of interfaces for D2D interconnection in the processor can be reduced, and the mutual influence between inter-chip interconnections can be effectively reduced.

[0131] 8. The arbitration circuit receives the source signal and the output signal of the receiving end processing circuit, and compares the error between the two. The error signal triggers the addition circuit to automatically add 1 to the count. Then, the count value is compared with the count threshold (i.e., the preset threshold mentioned above). If it is higher than the count threshold, the decimal-to-binary unit is started to convert the counted value into a (3+n)-bit binary signal value to achieve control. If it is lower than the count threshold, the original link state is maintained.

[0132] 9. The multiplexing of the receiving end (i.e. the second multiplexing circuit mentioned above) and the multiplexing of the transmitting end (i.e. the first multiplexing circuit mentioned above) are kept consistent to ensure the homology of the signals.

[0133] 10. Fig.11 As shown, the receiving end multi-mode processing circuit (i.e., the above-mentioned multi-mode receiving processing circuit) receives the signal passing through the transmission channel, and selects the appropriate processing circuit according to the processing mode controlled by the arbitration circuit. When the high 1 bit is at a high level, the PAM4 processing circuit is selected. The processing circuits mainly include DFE and CTLE+DFE, which are controlled by the middle 2 bits "01" and "11". On the contrary, the NRZ processing circuit is selected. The processing circuits include FFE, DFE, CTLE+FFE, CTLE+DFE, etc., which are controlled by the middle 2 bits "00", "01", "10" and "11".

[0134] 11. The deinterleaving decoding circuit at the receiving end is the inverse process of the interleaving coding at the transmitting end. The received signal and the output signal are opposite to the interleaving coding at the transmitting end. Fig.12 First, the decoding process is performed, and the signals in multiple transmission links are transmitted back to the virtual channel in a channel-by-channel and bit-by-bit manner to form corresponding data packets, and then the channel corresponding to the transmitter is selected according to the time-sharing polling method and transmitted back to the protocol layer.

[0135] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0136] In this embodiment, a method for sending a data packet is also provided, which is applied to the above-mentioned data packet sending system. Fig.13 is a flow chart of a method for sending a data packet according to an embodiment of the present application, such as Fig.13 As shown, the method comprises the following steps:

[0137] Step S132, performing cross-coding processing on a plurality of first data packets from a plurality of virtual channels to obtain a first coded signal;

[0138] Step S134, performing a first equalization process on the first coded signal to obtain a second coded signal;

[0139] Step S136, selecting a first transmission channel in a multimode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

[0140] Through the above scheme, a plurality of first data packets from a plurality of virtual channels are first cross-coded to obtain a first coded signal, and then the first coded signal is subjected to a first equalization process to obtain a second coded signal; finally, a first transmission channel is selected in a multi-mode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multi-mode transmission channel comprises n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; by adopting the above scheme, a cross-coding method based on time-sharing polling is adopted to disperse the data packets for transmission in a plurality of links, so as to solve the problem of linear interference of signals and enhance the transmission reliability of the links; thereby solving the technical problems in the related art, such as strong interference and the like existing in the inter-chip D2D interconnection link when the core processor accesses the stored data.

[0141] Optionally, the method also includes: receiving a third coded signal output by the multi-mode receiving processing circuit of the receiving end; comparing and analyzing the second coded signal and the third coded signal to determine the transmission accuracy corresponding to the second coded signal; adjusting the transmission mode of the first coded signal according to the transmission accuracy, wherein the transmission mode includes: signal selection, a first processing circuit, and a transmission channel, and the first processing circuit is used to perform a first equalization processing on the first coded signal.

[0142] Optionally, adjusting the transmission mode of the first coded signal according to the transmission accuracy rate includes: determining whether the transmission accuracy rate is lower than a preset threshold; when the transmission accuracy rate is higher than the preset threshold, not adjusting the transmission mode of the second coded signal; when the transmission accuracy rate is lower than the preset threshold, adjusting the transmission mode of the first coded signal according to an error count value of the second coded signal, wherein the error count value is used to indicate the number of second coded signals with transmission errors.

[0143] Optionally, the adjusting the transmission mode of the first coded signal according to the error count value of the second coded signal includes: converting the error count value into a binary signal value, wherein the binary signal value is an m+n-bit signal value, and m is a positive integer; sending the high m-bit signal in the binary signal value to the multi-mode transmit processing circuit to instruct the multi-mode transmit processing circuit to perform a first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal; and sending the binary signal value to the multi-mode receive processing circuit to instruct the multi-mode receive processing circuit to perform a second equalization processing on the second coded signal according to the binary signal value to obtain the third coded signal.

[0144] Optionally, the method further includes: determining a signal type of the first coded signal according to a first sub-signal in the high-m-bit signal, and determining a first processing circuit corresponding to the first coded signal according to a second sub-signal in the high-m-bit signal.

[0145] Optionally, the method further includes: detecting channel states of the n transmission channels, and generating a channel state signal according to the n channel states, wherein the channel state includes an idle state and a busy state, and the channel state signal is an n-bit binary signal.

[0146] Optionally, the method also includes: performing AND processing on the channel status signal and the low n bits of the binary signal value to obtain a processing result, and sending the processing result to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second encoded signal according to the processing result, wherein the processing result is an n-bit binary signal.

[0147] Optionally, the method further includes: selecting the first transmission channel from the n transmission channels according to the high-level signal in the processing result.

[0148] In this embodiment, a method for receiving a data packet is also provided, which is applied to the above-mentioned data packet receiving system. Fig.14 is a flow chart of a method for receiving a data packet according to an embodiment of the present application, such as Fig.14 As shown, the method comprises the following steps:

[0149] Step S142, receiving a second coded signal transmitted by a transmitting end through a first transmission channel in a multimode transmission channel, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer;

[0150] Step S144, performing a second equalization process on the second coded signal to obtain a third coded signal;

[0151] Step S146, cross-decoding the third coded signal to obtain a plurality of second data packets.

[0152] By adopting the above scheme, the second coded signal transmitted by the transmitting end through the first transmission channel in the multi-mode transmission channel is first received, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; then the second coded signal is subjected to a second equalization process to obtain a third coded signal; finally, the third coded signal is subjected to a cross-decoding process to obtain a plurality of second data packets, thereby completing the transmission of the data packets at the transmitting end and the receiving end; by adopting the above scheme, the data packets are dispersedly transmitted in multiple links by adopting a cross-coding method based on time-sharing polling, so as to solve the problem of linear interference of signals and enhance the transmission reliability of the links; thereby solving the technical problems in the related art such as strong interference in the inter-chip D2D interconnection link when the core processor accesses the stored data.

[0153] Optionally, the method also includes: receiving a binary signal value sent by the arbitration circuit of the sending end, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; determining the signal selection of the second coded signal according to a first sub-signal in the high-m-bit signal in the binary signal value, and determining a second processing circuit corresponding to the second coded signal according to a second sub-signal in the high-m-bit signal, wherein the second processing circuit is used to perform second equalization processing on the second coded signal.

[0154] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0155] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0156] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0157] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0158] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0159] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0160] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0161] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0162] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data packet sending system, characterized in that: Set on the sending end, include: A multi-channel cross-coding circuit, used for performing cross-coding processing on a plurality of first data packets from a plurality of virtual channels to obtain a first coded signal; a multi-mode transmission processing circuit, connected to the multi-path cross-coding circuit, and configured to perform a first equalization process on the first coded signal to obtain a second coded signal; a first multi-channel selection circuit, connected to the multi-mode transmission processing circuit, configured to select a first transmission channel in the multi-mode transmission channel for the second coded signal to transmit the signal, so as to transmit the second coded signal to the receiving end, wherein the multi-mode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; The data packet sending system further includes an arbitration circuit, wherein the arbitration circuit is used to: receiving the second coded signal output by the multi-mode transmission processing circuit, and receiving the third coded signal output by the multi-mode reception processing circuit of the receiving end; Comparing and analyzing the second coded signal and the third coded signal to determine a transmission accuracy rate corresponding to the second coded signal; adjusting a transmission mode of the first coded signal according to the transmission accuracy, wherein the transmission mode includes: signal selection, a first processing circuit, and a transmission channel, wherein the first processing circuit is used to perform a first equalization process on the first coded signal; Wherein, the arbitration circuit is also used for: Determining whether the transmission accuracy is lower than a preset threshold; When the transmission accuracy is higher than the preset threshold, the transmission mode of the second coded signal is not adjusted; When the transmission accuracy is lower than the preset threshold, adjusting the transmission mode of the first coded signal according to the error count value of the second coded signal, wherein the error count value is used to indicate the number of second coded signals with transmission errors; Wherein, the arbitration circuit is also used for: Converting the error count value into a binary signal value, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; The high m-bit signal in the binary signal value is sent to the multi-mode transmission processing circuit to instruct the multi-mode transmission processing circuit to perform a first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal, and the binary signal value is sent to the multi-mode reception processing circuit to instruct the multi-mode reception processing circuit to perform a second equalization processing on the second coded signal according to the binary signal value to obtain the third coded signal.

2. The data packet sending system according to claim 1, characterized in that: The multi-mode transmission processing circuit is further used for: Receiving the high m-bit signal sent by the arbitration circuit; The signal type of the first coded signal is determined according to the first sub-signal in the upper m-bit signal, and the first processing circuit corresponding to the first coded signal is determined according to the second sub-signal in the upper m-bit signal.

3. The data packet sending system according to claim 2, characterized in that: The data packet sending system further includes a link detection unit, which is used to: Detecting the channel states of the n transmission channels, and generating a channel state signal according to the n channel states, wherein the channel state includes an idle state and a busy state, and the channel state signal is an n-bit binary signal; The channel status signal is sent to the arbitration circuit.

4. The data packet transmission system according to claim 3, characterized in that: The arbitration circuit is further used for: receiving the channel status signal sent by the link detection unit; The channel status signal and the lower n bits of the binary signal value are ANDed to obtain a processing result, and the processing result is sent to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second coded signal according to the processing result, wherein the processing result is an n-bit binary signal.

5. The data packet transmission system according to claim 4, characterized in that: The first multiplexer selection circuit is further used for: receiving the processing result sent by the arbitration circuit; The first transmission channel is selected from the n transmission channels according to the high level signal in the processing result.

6. A data packet receiving system, characterized in that: Set at the receiving end, include: A second multiplexing circuit is used to receive a second coded signal transmitted by a transmitting end through a first transmission channel in a multimode transmission channel, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; a multi-mode receiving and processing circuit, connected to the second multi-path selection circuit, for performing a second equalization process on the second coded signal to obtain a third coded signal, and sending the third coded signal to an arbitration circuit, wherein the arbitration circuit is arranged in a data packet sending system, and the arbitration circuit is used to compare and analyze the second coded signal and the third coded signal to determine a transmission accuracy corresponding to the second coded signal; when the transmission accuracy is higher than a preset threshold, the arbitration circuit does not adjust the transmission mode of the second coded signal; when the transmission accuracy is lower than the preset threshold, the arbitration circuit adjusts the transmission mode of the second coded signal according to an error count of the second coded signal; The arbitration circuit is further used to convert the error count value into a binary signal value, and send the high m-bit signal in the binary signal value to the multi-mode transmission processing circuit to instruct the multi-mode transmission processing circuit to perform the first equalization processing on the first coded signal according to the high m-bit signal to obtain the second coded signal, and the binary signal value is a signal value of m+n bits, where m is a positive integer; A multi-channel cross-decoding circuit is connected to the multi-mode receiving and processing circuit and is used to perform cross-decoding processing on the third coded signal to obtain a plurality of second data packets.

7. The data packet receiving system according to claim 6, characterized in that: The multi-mode receiving processing circuit is further used for: Receiving a binary signal value sent by the arbitration circuit of the sending end, wherein the binary signal value is a signal value of m+n bits, and m is a positive integer; The signal selection of the second coded signal is determined according to the first sub-signal in the high m-bit signal in the binary signal value, and the second processing circuit corresponding to the second coded signal is determined according to the second sub-signal in the high m-bit signal, wherein the second processing circuit is used to perform second equalization processing on the second coded signal.

8. A method for sending a data packet, characterized in that: A system for sending a data packet according to any one of claims 1 to 5, include: Performing cross-coding processing on a plurality of first data packets from a plurality of virtual channels to obtain a first coded signal; Performing a first equalization process on the first coded signal to obtain a second coded signal; A first transmission channel is selected in a multimode transmission channel for signal transmission for the second coded signal, so as to transmit the second coded signal to a receiving end, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer.

9. The method for sending a data packet according to claim 8, characterized in that: The method further comprises: The signal type of the first coded signal is determined according to the first sub-signal in the upper m-bit signal, and the first processing circuit corresponding to the first coded signal is determined according to the second sub-signal in the upper m-bit signal.

10. The method for sending a data packet according to claim 8, characterized in that: The method further comprises: The channel states of the n transmission channels are detected, and a channel state signal is generated according to the n channel states, wherein the channel state includes an idle state and a busy state, and the channel state signal is an n-bit binary signal.

11. The method for sending a data packet according to claim 10, characterized in that: The method further comprises: The channel status signal and the lower n bits of the binary signal value are ANDed to obtain a processing result, and the processing result is sent to the first multiplexer circuit to instruct the first multiplexer circuit to select the first transmission channel for signal transmission for the second coded signal according to the processing result, wherein the processing result is an n-bit binary signal.

12. The method for sending a data packet according to claim 11, characterized in that: The method further comprises: The first transmission channel is selected from the n transmission channels according to the high level signal in the processing result.

13. A method for receiving a data packet, characterized in that: A system for receiving data packets according to claim 6 or 7, include: receiving a second coded signal transmitted by a transmitting end through a first transmission channel in a multimode transmission channel, wherein the multimode transmission channel includes n transmission channels, the n transmission channels include the first transmission channel, and n is a positive integer; performing a second equalization process on the second coded signal to obtain a third coded signal; The third coded signal is cross-decoded to obtain a plurality of second data packets.

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