Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a cell structure and a peripheral circuit structure electrically connected to the cell structure. The cell structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit line connected to the channel structure. The peripheral circuit structure includes an active region, a gate structure on the active region, a gate structure crossing the active region, a source / drain region on at least one side of the gate structure and in the active region, an insulating spacer covering the gate structure, a conductive spacer on a sidewall of the insulating spacer and electrically connected to the source / drain region, and a contact electrically connected to the conductive spacer. At least a portion of the topmost surface of the insulating spacer is coplanar with at least a portion of the topmost surface of the conductive spacer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device. Background Art

[0002] In order to meet consumers' demand for high performance and low price of semiconductor memory devices, it is necessary to improve the integration of semiconductor memory devices. The integration of semiconductor memory devices is an important factor in determining their prices. Therefore, there is a particular need for semiconductor memory devices with improved integration.

[0003] In the structure of a transistor that controls the operation of a memory cell, a process of implementing one or more transistors having different gate insulating film thicknesses on one active region is being studied. Summary of the invention

[0004] At least one embodiment is directed to a semiconductor memory device with improved integration.

[0005] The technical purpose of implementing the inventive concept disclosed herein is not limited to the technical purpose mentioned above. Other technical purposes and advantages not mentioned can be understood based on the following description and can be more clearly understood based on various example embodiments. In addition, it will be easily understood that the technical purposes and advantages according to various example embodiments can be achieved using the methods shown in the claims and their combinations.

[0006] According to various example embodiments, a semiconductor memory device is provided, which includes a unit structure and a peripheral circuit structure electrically connected to the unit structure. The unit structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit line connected to the channel structure. The peripheral circuit structure includes an active region; a gate structure on the active region, the gate structure intersecting the active region; a source / drain region on at least one side of the gate structure and in the active region; an insulating spacer covering the gate structure; a conductive spacer on the sidewall of the insulating spacer and electrically connected to the source / drain region; and a contact electrically connected to the conductive spacer. At least a portion of the topmost surface of the insulating spacer is coplanar with at least a portion of the topmost surface of the conductive spacer.

[0007] According to various example embodiments, a semiconductor memory device is provided, which includes: a unit structure; and a peripheral circuit structure electrically connected to the unit structure. The unit structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit line connected to the channel structure. The peripheral circuit structure includes: an active region extending in a first direction; a gate structure extending on the active region and in a second direction, wherein the gate structure intersects the active region; a source / drain region in the active region on at least one side of the gate structure; an insulating spacer covering the upper surface and sidewalls of the gate structure and including an insulating material; and a spacer structure surrounding the sidewalls of the insulating spacer. The spacer structure includes a semiconductor spacer including a semiconductor material and a conductive spacer including a conductive material and electrically connected to the source / drain region and a contact electrically connected to the conductive spacer. The gate structure includes a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in the second direction. In a plan view of the semiconductor memory device, the conductive spacer is on the pair of second sidewalls and does not exist on the pair of first sidewalls.

[0008] According to various example embodiments, a semiconductor memory device is provided, which includes: a unit structure; and a peripheral circuit structure electrically connected to the unit structure. The unit structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit line connected to the channel structure. The peripheral circuit structure includes: an active region extending in a first direction; a gate structure on the active region and extending in a second direction, wherein the gate structure intersects the active region, and the gate structure includes a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in the second direction; a source / drain region on each of the pair of second sidewalls of the gate structure and in the active region; an insulating spacer covering an upper surface of the gate structure, the pair of first sidewalls, and the pair of second sidewalls, and including an insulating material; a spacer structure surrounding an outer sidewall of the insulating spacer, wherein the spacer structure includes: a semiconductor spacer including a semiconductor material and a conductive spacer including a conductive material and electrically connected to the source / drain region; an etching stop film covering a portion of the insulating spacer, the semiconductor spacer, and a portion of the source / drain region; and a contact electrically connected to the conductive spacer. The etching stop film does not overlap with the conductive spacer in a vertical direction. The conductive spacer overlaps with the pair of second sidewalls in a first direction and does not overlap with the pair of first sidewalls in a second direction. The topmost surface of the spacer structure is coplanar with the upper surface of the insulating spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of various example embodiments will become more apparent by describing in detail the embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram for illustrating a semiconductor memory device according to various example embodiments.

[0011] Figure 2 2 is a schematic circuit diagram for illustrating a semiconductor memory device according to various example embodiments.

[0012] Figure 3 are schematic cross-sectional views of semiconductor memory devices according to various example embodiments.

[0013] Figure 4 yes Figure 3 Magnified view of region R in FIG.

[0014] Figure 5 is a plan view for illustrating a peripheral circuit structure of a semiconductor memory device according to various example embodiments.

[0015] Figure 6 It is along Figure 5 A cross-sectional view taken along line AA' in FIG.

[0016] Figure 7 It is along Figure 5 A cross-sectional view taken along line B1-B1' in FIG.

[0017] Figures 8 to 18 is a schematic diagram of a semiconductor memory device according to some other embodiments.

[0018] Figures 19 to 26 are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor memory device according to various example embodiments of the present disclosure.

[0019] Fig. 27 is a schematic block diagram for illustrating an electronic system according to various example embodiments.

[0020] Fig.28 is a schematic perspective view for illustrating an electronic system according to various example embodiments.

[0021] Fig.29 It is along Fig.28 Schematic cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0022] As used herein, the terms "first", "second", etc. are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, within the technical spirit of the present disclosure, the first element or component mentioned below may also be the second element or component.

[0023] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it means that the accuracy of the geometric shape is not required, but the latitude of the shape is within the scope of the present disclosure. In addition, whether a numerical value or shape is modified as "approximately" or "substantially", it will be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0024] It will be understood that elements and / or properties thereof may be stated herein as being "the same" or "equivalent" to other elements, and it will be understood that elements and / or properties thereof described herein as being "equivalent", "identical" or "equivalent" to other elements may be "equivalent", "identical", "equivalent" or "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or properties. Elements and / or properties thereof that are "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or properties thereof will be understood to include elements and / or properties thereof that are equivalent, identical or equivalent to other elements and / or properties thereof within manufacturing tolerances and / or material tolerances. Elements and / or properties thereof that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or properties thereof may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition.

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and repeated descriptions thereof are omitted.

[0026] Figure 1 is a schematic block diagram for illustrating a semiconductor memory device according to some embodiments.

[0027] Reference Figure 1 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30 .

[0028] The memory cell array 20 may include a plurality of memory cell blocks (BLK1 to BLKn). Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through the bit lines BL, the word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0029] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from an external device of the semiconductor memory device 10, and may transmit and receive data DATA to and from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generation circuit for generating various voltages required for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0030] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a storage operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage level of the voltage supplied to the word line WL and the bit line BL.

[0031] The row decoder 33 may select at least one from a plurality of memory cell blocks BLK1 to BLKn in response to an address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected at least one memory cell block BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of the selected at least one memory cell block BLK1 to BLKn.

[0032] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 operates as a write driver to apply a voltage based on the data DATA to be stored in the memory cell array 20 to the bit line BL. On the other hand, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to detect the data DATA stored in the memory cell array 20.

[0033] Figure 2 is a schematic circuit diagram for illustrating a semiconductor memory device according to some embodiments.

[0034] Reference Figure 2 , a memory cell array (eg, Figure 1 20) includes a common source line CSL, a plurality of bit lines BL and a plurality of cell strings CSTR.

[0035] The common source line CSL may extend in the X direction. In some example embodiments, a plurality of common source lines CSL may be arranged in a two-dimensional manner. For example, a plurality of common source lines CSL may be spaced apart from each other and extend in the X direction. The same voltage may be applied to the common source lines CSL. Alternatively, different voltages may be applied to the common source lines CSL individually.

[0036] A plurality of bit lines BL may be arranged in a two-dimensional manner. For example, the bit lines BL may be spaced apart from each other and extend in a Y direction intersecting the X direction. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell string CSTR may be connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0037] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series to each other in the Z direction. As used herein, the X direction, the Y direction, and the Z direction may be substantially perpendicular to each other.

[0038] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL1 to WLn, and a string selection line SSL may be provided between the common source line CSL and the bit line BL. The ground selection line GSL may serve as a gate electrode of the ground selection transistor GST. The word lines WL1 to WLn may be used as gate electrodes of the memory cell transistors MCT, respectively. The string selection line SSL may serve as a gate electrode of the string selection transistor SST.

[0039] In some example embodiments, the erase control transistor ECT may be disposed between a common source line CSL and a ground selection transistor GST. The common source line CSL may be commonly connected to the source of the erase control transistor ECT. In addition, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may serve as a gate electrode of the erase control transistor ECT. The erase control transistor ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

[0040] Figure 3 is a schematic cross-sectional view of a semiconductor memory device according to some embodiments. Figure 4 yes Figure 3 Magnified view of region R in FIG.

[0041] Reference Figure 3 and Figure 4 , a semiconductor memory device according to some embodiments includes a cell structure CELL and a peripheral circuit structure PERI.

[0042] In some example embodiments, the cell structure CELL includes a cell substrate 100 , a mold structure MS, a cell interlayer insulating film 120 , a channel structure CH, a word line cutting structure WLC, a bit line BL, a plurality of cell contacts 153 , and through contacts 155 .

[0043] A semiconductor memory device according to some embodiments may include a cell array region CAR, an extension region EXR, and a pad region PAD. Although the cell array region CAR, the extension region EXR, and the pad region PAD are illustrated as being connected to each other, technical ideas of various example embodiments are not limited thereto.

[0044] including a plurality of storage units (e.g., Figure 1 The memory cell array of 20) may be formed in the cell array region CAR. For example, a channel structure CH, a bit line BL, and gate electrodes ECL, GSL, WL1 to WLn, and SSL, etc., as described later, may be provided in the cell array region CAR.

[0045] The extension region EXR may be disposed around the cell array region CAR. In the extension region EXR, gate electrodes ECL, GSL, WL1 to WLn, and SSL as described later may be stacked in a stepped manner. In addition, in the extension region EXR, a plurality of cell contacts 153 and the like as described below may be disposed.

[0046] The pad area PAD may be disposed inside the cell array area CAR and the extension area EXR, or may be disposed outside the cell array area CAR and the extension area EXR. In the pad area PAD, a through contact 155 or the like to be described later may be disposed.

[0047] The substrate may include a cell array region CAR, an extension region EXR, and a pad region PAD. The substrate may include a unit substrate 100 and an insulating pattern 101. However, various example embodiments are not limited thereto.

[0048] The unit substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the unit substrate 100 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate. In some example embodiments, the unit substrate 100 may include impurities. For example, the unit substrate 100 may include n-type impurities such as phosphorus (P), arsenic (As), etc.

[0049] The insulating pattern 101 may be disposed in the extension region EXR and the pad region PAD. The insulating pattern 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. However, various example embodiments are not limited thereto. Unlike the illustration, the insulating pattern 101 may be disposed in the unit substrate 100.

[0050] The mold structure MS may be disposed on a front surface (e.g., an upper surface) of the unit substrate 100. The mold structure MS may include a plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL alternately stacked on each other while being disposed on the unit substrate 100, and a plurality of mold insulating films 110. Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and each of the mold insulating films 110 may have a layered structure extending in parallel with the upper surface of the unit substrate 100. The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be sequentially stacked on the unit substrate 100 while being spaced apart from each other by each mold insulating film 110.

[0051] The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be stacked in a stepped manner in the extension region EXR. For example, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may extend to have different lengths in the X direction, and thus may be stacked in a stepped manner. In some example embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may extend to have different lengths in the Y direction, and thus may be stacked in a stepped manner. Therefore, a portion of each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may not be covered by other gate electrodes and thus be exposed. The exposed portion of each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may contact each of the plurality of cell contacts 153.

[0052] In some example embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include an erase control line ECL, a ground selection line GSL, and a plurality of word lines WL1 to WLn sequentially stacked on the unit substrate 100. In some further embodiments, the erase control line ECL may be omitted.

[0053] The mold insulating film 110 may be stacked in a stepped manner in the extension region EXR. For example, the mold insulating film 110 may be extended to have different lengths in the X direction and thus may be stacked in a stepped manner. In some example embodiments, the mold insulating film 110 may be extended to have different lengths in the Y direction and thus may be stacked in a stepped manner.

[0054] Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon. However, various example embodiments are not limited thereto. In one example, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include tungsten (W). Unlike the illustration, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may have a multilayer structure. For example, when each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL has a multilayer structure, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a gate electrode barrier film and a gate electrode filling film. The gate electrode barrier film may include, for example, titanium nitride (TiN), and the gate electrode filling film may include tungsten (W). However, various example embodiments are not limited thereto.

[0055] The mold insulating film 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. However, various example embodiments are not limited thereto. In one example, the mold insulating film 110 may include silicon oxide.

[0056] The channel structure CH may be provided in the mold structure MS and in the cell array region CAR. The channel structure CH may extend in a vertical direction (hereinafter referred to as the Z direction) intersecting the upper surface of the cell substrate 100, and may extend through the mold insulating film 110 and the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the channel structure CH may have a column shape (e.g., a cylindrical shape) extending in the Z direction. Therefore, the channel structure CH may intersect each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL.

[0057] The channel structure CH may include a semiconductor pattern 130 and an information storage film 132 .

[0058] The semiconductor pattern 130 may extend in the Z direction and extend through the mold structure MS. Although the semiconductor pattern 130 is shown as having a cup shape, this is only schematic. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a square column shape, and a solid column shape. The semiconductor pattern 130 may include, for example, a semiconductor material, such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, or a carbon nanostructure, etc. However, various example embodiments are not limited thereto.

[0059] The information storage film 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the information storage film 132 may extend along the outer surface of the semiconductor pattern 130. The information storage film 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) material having a dielectric constant higher than that of silicon oxide. The high dielectric constant (high-k) material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or a combination thereof. However, example embodiments are not limited thereto.

[0060] In some example embodiments, the information storage film 132 may be formed as a stack of multiple layers of films. Figure 4 As shown, the information storage film 132 may include a tunnel insulating film 132 a , a charge storage film 132 b , and a blocking insulating film 132 c sequentially stacked on an outer surface of the semiconductor pattern 130 .

[0061] The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than that of silicon oxide, such as aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than that of silicon oxide, such as aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 ).

[0062] In some example embodiments, the channel structure CH may further include a filling pattern 134. The filling pattern 134 may be formed to fill an inner space defined by the cup-shaped semiconductor pattern 130. The filling pattern 134 may include an insulating material, such as silicon oxide. However, various example embodiments are not limited thereto.

[0063] In some example embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to the semiconductor pattern 130. For example, the channel pad 136 may be formed in a cell interlayer insulating film 120 to be described later, and may be connected to the top of the semiconductor pattern 130. The channel pad 136 may include, for example, polysilicon doped with impurities. However, various example embodiments are not limited thereto.

[0064] In some example embodiments, the source layer 102 and the source support layer 104 may be sequentially formed on the unit substrate 100. The source layer 102 and the source support layer 104 may be interposed between the unit substrate 100 and the mold structure MS. For example, the source layer 102 and the source support layer 104 may extend along the upper surface of the unit substrate 100.

[0065] In some example embodiments, the source layer 102 may be formed to be connected to the semiconductor pattern 130 of the channel structure CH. Figure 4 As shown, the source layer 102 may extend through the information storage film 132 and contact the semiconductor pattern 130. The source layer 102 may provide a common source line (eg, Figure 2 The source layer 102 may include, for example, impurity-doped polysilicon or metal. However, various example embodiments are not limited thereto.

[0066] In some example embodiments, the channel structure CH may extend through the source layer 102 and the source supporting layer 104. For example, a bottom of the channel structure CH may extend through the source layer 102 and the source supporting layer 104 and be buried in the unit substrate 100.

[0067] In some example embodiments, the source support layer 104 may serve as a support layer to prevent the mold stack from collapsing during a replacement process for forming the source layer 102 .

[0068] Although not shown, a base insulating film may be interposed between the unit substrate 100 and the source layer 102. The base insulating film may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, various example embodiments are not limited thereto.

[0069] In some example embodiments, the insulating pattern 101 may be formed in the extension region EXR and the pad region PAD. The upper surface of the insulating pattern 101 is shown to be coplanar with the upper surface of the source support layer 104. However, this is only schematic. In another example, the vertical level of the upper surface of the insulating pattern 101 may be higher than the vertical level of the upper surface of the source support layer 104.

[0070] The word line cutting structure WLC may cut the mold structure MS. The mold structure MS may be cut by the word line cutting structure WLC to be divided into parts (eg, Figure 1 For example, although not shown, two adjacent word line cutting structures WLC may define one memory cell block therebetween. A plurality of channel structures CH may be provided in each memory cell block defined by the word line cutting structure WLC.

[0071] In some example embodiments, the word line cutting structure WLC may cut the source layer 102 and the source support layer 104. The lower surface of the word line cutting structure WLC is shown as being coplanar with the lower surface of the source layer 102 only. However, this is only exemplary. In another example, the vertical level of the lower surface of the word line cutting structure WLC may be lower than the vertical level of the lower surface of the source layer 102.

[0072] In some example embodiments, the word line cutting structure WLC may include an insulating material. For example, the insulating material may fill the word line cutting structure WLC. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. However, various example embodiments are not limited thereto.

[0073] Although not shown, a string isolation structure may be provided in the mold structure MS. The string isolation structure may cut the string selection line SSL. The string isolation structure may divide each memory cell block defined by the word line cutting structure WLC into parts constituting a plurality of string regions, respectively. For example, the string isolation structure may define two string regions in one memory cell block.

[0074] The cell interlayer insulating film 120 may be disposed on the mold structure MS. The cell interlayer insulating film 120 may cover the plurality of channel structures CH, the plurality of cell contacts 153, and the through contacts 155. The cell interlayer insulating film 120 may include an oxide-based insulating material. The cell interlayer insulating film 120 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a dielectric constant lower than that of silicon oxide. However, various example embodiments are not limited thereto.

[0075] The bit line BL may be disposed on the substrate and in the cell array region CAR. The bit line BL may be formed on the mold structure MS. The bit line BL may be a bit line of the semiconductor memory device ( Figure 2 The bit line BL may be provided in the cell interlayer insulating film 120. The bit line BL may extend in the Y direction.

[0076] In addition, the bit line BL may be connected to a plurality of channel structures CH. For example, a first bit line contact 151 and a second bit line contact 161 connected to the top of each channel structure CH may be formed in the cell interlayer insulating film 120. The first bit line contact 151 is disposed on the channel structure CH. The first bit line contact 151 may be connected to the channel pad 136. The second bit line contact 161 is disposed on the first bit line contact 151. The second bit line contact 161 may be connected to the bit line BL. The second bit line contact 161 may be disposed between the bit line BL and the first bit line contact 151. The bit line BL may be electrically connected to the channel structure CH through the first bit line contact 151 and the second bit line contact 161.

[0077] The bit line BL may include a conductive material. For example, the bit line BL may include tungsten (W) or copper (Cu). However, various example embodiments are not limited thereto.

[0078] A plurality of cell contacts 153 may be disposed on the substrate and in the extension region EXR. A plurality of cell contacts 153 may be disposed in the extension region EXR, may extend in the Z direction, and may extend through the cell interlayer insulating film 120. Each of the plurality of cell contacts 153 may be connected to one of the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, each of the plurality of cell contacts 153 may land on the topmost gate electrode among the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL. That is, each of the plurality of cell contacts 153 may be electrically connected to the topmost gate electrode among the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL.

[0079] All upper surfaces of the plurality of cell contacts 153 may be coplanar with each other. Also, all lower surfaces of the plurality of cell contacts 153 may not be coplanar with each other. However, technical ideas of the various example embodiments are not limited thereto.

[0080] A plurality of first metal patterns 170 may be disposed on the substrate and in the extension region EXR. A plurality of first metal patterns 170 may be disposed on the mold structure MS. In addition, the plurality of first metal patterns 170 may be connected to the plurality of cell contacts 153, respectively. For example, a first via contact 163 may be formed between each of the plurality of first metal patterns 170 and each of the cell contacts 153. Each of the plurality of first metal patterns 170 and each of the cell contacts 153 may be electrically connected to each other through each first via contact 163.

[0081] Each of the plurality of first metal patterns 170 may include a conductive material. For example, each of the plurality of first metal patterns 170 may include tungsten (W) or copper (Cu). However, various example embodiments are not limited thereto.

[0082] The through contact 155 may be disposed on the substrate and in the pad area PAD. The through contact 155 may be disposed in the pad area PAD and may extend in the Z direction and may extend through the unit interlayer insulating film 120. In addition, the through contact 155 may extend through the insulating pattern 101. The through contact 155 may extend through the insulating pattern 101 and then be connected to the peripheral circuit element PT of the peripheral circuit structure PERI, which will be described later. For example, the through contact 155 may be connected to the wiring pattern 290 of the peripheral circuit structure PERI.

[0083] A plurality of second metal patterns 180 may be disposed on the substrate and in the pad area PAD. A plurality of second metal patterns 180 may be disposed in the unit interlayer insulating film 120. A plurality of second metal patterns 180 may be connected to the through contacts 155. For example, a second via contact 165 may be formed between some of the plurality of second metal patterns 180 and the through contacts 155. Some of the plurality of second metal patterns 180 and the through contacts 155 may be electrically connected to each other through the second via contacts 165.

[0084] Each of the plurality of second metal patterns 180 may include a conductive material. For example, each of the plurality of second metal patterns 180 may include tungsten (W) or copper (Cu). However, various example embodiments are not limited thereto.

[0085] In some example embodiments, the peripheral circuit structure PERI may include a peripheral circuit substrate 200 and a peripheral circuit element PT.

[0086] The peripheral circuit substrate 200 may be disposed below the unit substrate 100. For example, the upper surface of the peripheral circuit substrate 200 may face the lower surface of the unit substrate 100. The peripheral circuit substrate 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the peripheral circuit substrate 200 may be implemented as a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate, etc.

[0087] The peripheral circuit element PT may be formed on the peripheral circuit substrate 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Figure 1 30 in ). For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 37 in), row decoders (e.g., Figure 1 33 in), page buffers (e.g., Figure 1 35) etc. In one example, the peripheral circuit element PT may be a page buffer and may control the operation of the bit line BL. However, technical ideas of various example embodiments are not limited thereto.

[0088] In the following description, the surface of the peripheral circuit substrate 200 on which the peripheral circuit element PT is disposed may be referred to as the front surface of the peripheral circuit substrate 200. Conversely, the surface of the peripheral circuit substrate 200 opposite to the front surface of the peripheral circuit substrate 200 may be referred to as the back surface or rear surface of the peripheral circuit substrate 200.

[0089] The peripheral circuit element PT may include, for example, a transistor. However, various example embodiments are not limited thereto. For example, the peripheral circuit element PT may include not only various active elements such as a transistor, but also various passive elements such as a capacitor, a resistor, and an inductor.

[0090] In some example embodiments, the rear surface of the unit substrate 100 may face the front surface of the peripheral circuit substrate 200. For example, a peripheral circuit interlayer insulating film 210 covering the peripheral circuit element PT may be formed on the front surface of the peripheral circuit substrate 200. The unit substrate 100 and / or the insulating pattern 101 may be stacked on an upper surface of the peripheral circuit interlayer insulating film 210.

[0091] Some of the plurality of second metal patterns 180 may be connected to the peripheral circuit element PT through the through contact 155. For example, a wiring pattern 290 connected to the peripheral circuit element PT may be formed in the peripheral circuit interlayer insulating film 210. The bit line BL, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL, and / or the source layer 102 may be electrically connected to the peripheral circuit element PT through the wiring pattern 290.

[0092] The peripheral circuit elements PT may be isolated from each other by an element isolation film 205. For example, the element isolation film 205 may be provided in the peripheral circuit substrate 200. The element isolation film 205 may be implemented as a shallow trench isolation (STI) film. The element isolation film 205 may define an active region of each peripheral circuit element PT. The element isolation film 205 may include an insulating material. The element isolation film 205 may include, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride. However, example embodiments are not limited thereto.

[0093] Will use Figure 5 and Figure 7 The peripheral circuit element PT is described in more detail. Figure 5 is a plan view for illustrating a peripheral circuit structure of a semiconductor memory device according to some example embodiments. Figure 6 It is along Figure 5 A cross-sectional view taken along line AA' in FIG. Figure 7 It is along Figure 5 A cross-sectional view taken along line B1-B1' in FIG. Figure 5 is a plan view at the same level as the top surface of the gate structure 220 for illustrating a peripheral circuit structure of a semiconductor memory device according to some example embodiments. If not specifically described, the plan view described below is a plan view at the same level as the top surface of the gate structure 220.

[0094] Reference Figures 5 to 7 According to some embodiments, a semiconductor memory device may include a peripheral circuit substrate 200, an element isolation film 205, a peripheral circuit interlayer insulating film 210, an active region ACT, a gate structure 220, an insulating spacer 230, a spacer structure 240, an etching stop film 250, a contact 260 and a source / drain region 270.

[0095] The active area ACT may be disposed on the peripheral circuit substrate 200. The active area ACT may be used as a channel of a transistor. The gate structure 220 may be disposed on the active area ACT. The active area ACT may extend in a first direction D1. The active area ACT may include a long side extending in the first direction D1 and a short side extending in a second direction D2. The first direction D1 and the second direction D2 may be parallel to the upper surface of the peripheral circuit substrate 200. The third direction D3 may intersect the first direction D1 and the second direction D2. The third direction D3 may be a direction perpendicular to the upper surface of the peripheral circuit substrate 200. That is, the third direction D3 may be a vertical direction.

[0096] The gate structure 220 may be disposed on the active area ACT. The gate structure 220 may cross the active area ACT. The gate structure 220 may extend in the second direction D2. The gate structure 220 may include a long side extending in the second direction D2 and a short side extending in the first direction D1.

[0097] In some example embodiments, in a plan view of a semiconductor memory device, the gate structure 220 may include a pair of first sidewalls 220 a and a pair of second sidewalls 220 b .

[0098] The pair of first sidewalls 220a may extend in the first direction D1. The pair of second sidewalls 220b may extend in the second direction D2. Each of the pair of first sidewalls 220a may be a short side of the gate structure 220, and each of the pair of second sidewalls 220b may be a long side of the gate structure 220.

[0099] The gate structure 220 may include a gate insulating pattern 221, a gate pattern 222, and a gate capping pattern 223. The gate insulating pattern 221, the gate pattern 222, and the gate capping pattern 223 may be sequentially stacked in the third direction D3. The gate insulating pattern 221 may be disposed on the active region ACT, the gate pattern 222 may be disposed on the gate insulating pattern 221, and the gate capping pattern 223 may be disposed on the gate pattern 222.

[0100] The gate insulating pattern 221 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant (high-k) material may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or at least one of lead zinc niobate. However, example embodiments are not limited thereto. In one example, the gate insulating pattern 221 may include a silicon oxide film.

[0101] The gate pattern 222 may include a conductive material. For example, the gate pattern 222 may include a polysilicon film doped with impurities, a tungsten (W) film, or a combination thereof. However, various example embodiments are not limited thereto.

[0102] The gate capping pattern 223 may include, for example, a silicon nitride film. However, various example embodiments are not limited thereto.

[0103] The insulating spacer 230 may cover the gate structure 220. The insulating spacer 230 may be disposed on the gate structure 220. The insulating spacer 230 may cover the upper surface of the gate structure 220 and a pair of first sidewalls 220a and a pair of second sidewalls 220b of the gate structure 220. The insulating spacer 230 may include an insulating material. For example, the insulating spacer 230 may include a silicon oxide film. However, various example embodiments are not limited thereto.

[0104] The spacer structure 240 may be disposed on the sidewall of the insulating spacer 230. The spacer structure 240 may surround the outer sidewall of the insulating spacer 230. The topmost surface 240US of the spacer structure 240 may be coplanar with the upper surface 230US of the insulating spacer 230. The topmost surface 240US of the spacer structure 240 may be a portion thereof in contact with the upper surface 230US of the insulating spacer 230. The topmost surface 240US of the spacer structure 240 may mean a portion disposed at the highest vertical level of the spacer structure 240.

[0105] In some example embodiments, the spacer structure 240 may include a conductive spacer 241 and a semiconductor spacer 242 .

[0106] The conductive spacer 241 may be disposed on a pair of second sidewalls 220b of the gate structure 220. The conductive spacer 241 is not disposed on the first pair of sidewalls 220a of the gate structure 220. The conductive spacer 241 may be disposed on the active area ACT. The conductive spacer 241 may be disposed on the source / drain region 270. The conductive spacer 241 may be connected to the source / drain region 270. The conductive spacer 241 may be in contact with the source / drain region 270.

[0107] The conductive spacer 241 may include a conductive material. For example, the conductive spacer 241 may include a metal silicide material. Therefore, the conductive spacer 241 may be electrically connected to the source / drain region 270. In addition, the conductive spacer 241 may be electrically connected to the contact 260. Therefore, even when the contact 260 is not directly connected to the source / drain region 270, the contact 260 may be electrically connected to the source / drain region 270 through the conductive spacer 241. Therefore, a semiconductor memory device with improved integration can be manufactured.

[0108] In some example embodiments, the conductive spacer 241 has a first length L1 in the second direction D2. The active area ACT has a second length L2 in the second direction D2. The gate structure 220 has a third length L3 in the second direction D2. The third length L3 may be a minimum distance between a pair of first sidewalls 220a.

[0109] The first length L1 may be less than the third length L3. That is, in a plan view of the semiconductor memory device, the conductive spacer 241 may completely overlap the gate structure 220 in the first direction D1. However, in a plan view of the semiconductor memory device, a portion of the gate structure 220 does not overlap the conductive spacer 241 in the first direction D1.

[0110] The first length L1 may be the same as the second length L2. That is, in a plan view of the semiconductor memory device, the conductive spacer 241 may completely overlap the active area ACT in the first direction D1. In addition, in a plan view of the semiconductor memory device, the active area ACT may completely overlap the conductive spacer 241 in the first direction D1.

[0111] In some example embodiments, the topmost surface 241US of the conductive spacer 241 may be coplanar with the upper surface 230US of the insulating spacer 230. The topmost surface 241US of the conductive spacer 241 may be a portion thereof in contact with the upper surface 230US of the insulating spacer 230. The topmost surface 241US of the conductive spacer 241 may mean a portion disposed at the highest vertical level of the conductive spacer 241. The topmost surface 241US of the conductive spacer 241 may serve as the topmost surface 240US of the spacer structure 240. In addition, the topmost surface 241US of the conductive spacer 241 may serve as the topmost surface 242US of the semiconductor spacer 242.

[0112] The semiconductor spacer 242 may be disposed on each of the pair of first sidewalls 220a of the gate structure 220 and on a portion of each of the pair of second sidewalls 220b of the gate structure 220. The semiconductor spacer 242 may completely cover each of the pair of first sidewalls 220a of the gate structure 220. The semiconductor spacer 242 may only cover a portion of each of the pair of second sidewalls 220b of the gate structure 220.

[0113] That is, the semiconductor spacer 242 may overlap each of the pair of first sidewalls 220a of the gate structure 220 in the second direction D2. However, a portion of the semiconductor spacer 242 may not overlap each of the pair of first sidewalls 220a of the gate structure 220 in the second direction D2. The semiconductor spacer 242 may overlap a portion of each of the pair of second sidewalls 220b in the first direction D1.

[0114] The semiconductor spacer 242 may include a semiconductor material. For example, the semiconductor spacer 242 may include an undoped polysilicon film.

[0115] In some example embodiments, the topmost surface 242US of the semiconductor spacer 242 may be coplanar with the upper surface 230US of the insulating spacer 230. The topmost surface 242US of the semiconductor spacer 242 may be a portion thereof in contact with the upper surface 230US of the insulating spacer 230. The topmost surface 242US of the semiconductor spacer 242 may mean a portion disposed at the highest vertical level of the semiconductor spacer 242. The topmost surface 242US of the semiconductor spacer 242 may serve as the topmost surface 240US of the spacer structure 240. In addition, the topmost surface 242US of the semiconductor spacer 242 may be coplanar with the topmost surface 241US of the conductive spacer 241.

[0116] In the active area ACT, a source / drain region 270 may be provided. The source / drain region 270 may be provided on at least one side of the gate structure 220. The source / drain region 270 may be provided on each of two opposite sides of the gate structure 220. The source / drain region 270 may be a region doped with impurities. For example, when the gate structure 220 belongs to a PMOS transistor, the source / drain region 270 may be doped with p-type impurities. In another example, when the gate structure 220 belongs to an NMOS transistor, the source / drain region 270 may be doped with n-type impurities.

[0117] The source / drain region 270 may be electrically connected to the conductive spacer 241. In some example embodiments, the source / drain region 270 may be in direct contact with the conductive spacer 241. Therefore, even when the contact 260 is not directly connected to the source / drain region 270, the source / drain region 270 and the contact 260 may be electrically connected to each other through the conductive spacer 241. Therefore, the area size of the source / drain region 270 may be reduced. In other words, a semiconductor memory device with improved integration may be manufactured.

[0118] The etching stop film 250 may extend along a portion of the upper surface of the source / drain region 270, a side profile of the semiconductor spacer 242, a portion of the upper surface of the element isolation film 205, and a portion of the upper surface 230US of the insulating spacer 230. The etching stop film 250 is not disposed on the conductive spacer 241. In addition, the etching stop film 250 is not disposed on a portion of the upper surface 230US of the insulating spacer 230.

[0119] exist Figure 7 , the length of the portion of the upper surface 230US of the insulating spacer 230 that is not covered by the etching stop film 250 in the second direction D2 may be equal to the first length L1. This may be due to the characteristics of the method for manufacturing a semiconductor memory device according to some embodiments of the various example embodiments. In the process of forming the conductive spacer 241, a mask film ( Fig.24MASK). The portion of the etching stop film 250 overlapping with the mask film in the third direction D3 may not be removed, while the portion of the etching stop film 250 not overlapping with the mask film in the third direction D3 may be removed. The conductive spacer 241 may be formed in an area not covered by the mask film. Therefore, the first length L1 of the conductive spacer 241 in the second direction D2 may be equal to the length of the portion of the upper surface 230 of the insulating spacer 230 not covered by the etching stop film 250 in the second direction D2.

[0120] The etching stop film 250 may be made of a material having an etching selectivity with respect to the material of the peripheral circuit interlayer insulating film 210. For example, the etching stop film 250 may include a silicon nitride film. However, technical ideas of various example embodiments are not limited thereto.

[0121] The peripheral circuit interlayer insulating film 210 may cover the gate structure 220 , the source / drain regions 270 , the etch stop film 250 , and the conductive spacer 241 .

[0122] The contact 260 may be disposed in the peripheral circuit interlayer insulating film 210. The contact 260 may be disposed on the conductive spacer 241. The contact 260 may be electrically connected to the conductive spacer 241. The contact 260 may completely overlap the conductive spacer 241 in the third direction D3. The contact 260 may not be in direct contact with the source / drain region 270. However, the contact 260 may be electrically connected to the source / drain region 270 through the conductive spacer 241.

[0123] In some example embodiments, the vertical level of the bottommost surface of the contact 260 may be higher than the vertical level of the upper surface of the source / drain region 270. The bottommost surface of the contact 260 may be a portion thereof closest to the upper surface of the peripheral circuit substrate 200 in the third direction D3. The bottommost surface of the contact 260 is in direct contact with the conductive spacer 241. The bottommost surface of the contact 260 may not be in contact with the source / drain region 270.

[0124] The contact 260 may include a conductive material. For example, the contact 260 may include copper (Cu) or tungsten (W). However, the technical ideas of the various example embodiments are not limited thereto.

[0125] In the following, reference will be made to Figures 8 to 18 Semiconductor memory devices according to some further embodiments of various example embodiments are described. Figures 8 to 18 is a diagram of a semiconductor memory device according to some other embodiments. Figures 1 to 7 Description of Explanations Repetitive contents are briefly explained or omitted.

[0126] First, refer to Figure 8In the semiconductor memory device according to some embodiments, at least a portion of the contact 260 may directly contact the source / drain region 270. At least a portion of the contact 260 may not overlap the conductive spacer 241 in the third direction D3. At least a portion of the contact 260 may extend through the etch stop film 250 to be connected to the source / drain region 270. The vertical level of the bottommost surface of the contact 260 may be the same as the vertical level of the upper surface of the source / drain region 270.

[0127] Reference Fig. 9 In the semiconductor memory device according to some embodiments, the contact 260 may not be connected to the conductive spacer 241. The contact 260 may extend through the etch stop film 250 to be connected to the source / drain region 270. The contact 260 may not overlap the conductive spacer 241 in the third direction D3.

[0128] Reference Fig.10 In some example embodiments, the upper surface 230US of the insulating spacer 230 may protrude toward the peripheral circuit substrate 200. In the process of forming the spacer structure 240, the insulating spacer 230 may be overetched. Therefore, the upper surface 230US of the insulating spacer 230 may be a curved surface. In this regard, the vertical level of the upper surface 230US of the insulating spacer 230 may be lower than the vertical level of the topmost surface 240US of the spacer structure 240.

[0129] Reference Fig.11 , the semiconductor memory device according to some embodiments may further include a silicide film 275. The silicide film 275 may be disposed on the source / drain region 270, or the silicide film 275 may be disposed in the source / drain region 270. At least a portion of the silicide film 275 may be interposed between the conductive spacer 241 and the source / drain region 270. The remaining portion of the silicide film 275 may be disposed in a region that does not overlap with the conductive spacer 241 in the third direction D3.

[0130] In some example embodiments, the etching stop film 250 may be removed before forming the conductive spacer 241. At this time, the etching stop film 250 may be removed to expose a portion of the source / drain region 270. Thereafter, a silicidation (self-aligned silicide) process may be performed. The silicidation process may be performed to form the conductive spacer 241 and the silicide film 275. That is, the silicide film 275 may not overlap with the etching stop film 250 in the third direction D3.

[0131] Reference Fig.12 and Fig.13 , the first length L1 of the conductive spacer 241 in the second direction D2 may be greater than the second length L2 of the active area ACT in the second direction D2. For reference, Fig.13 It can be along Fig.12 A cross-sectional view taken along line B2-B2'.

[0132] The area where the etch stop film 250 is removed may vary according to the structure of the mask film used in forming the conductive spacer 241. When the length of the opening of the mask film in the second direction D2 is greater than the second length L2, the first length L1 of the conductive spacer 241 in the second direction D2 may be greater than the second length L2 of the active area ACT in the second direction D2.

[0133] A first length L1 of the conductive spacer 241 in the second direction D2 may be less than a third length L3 of the gate structure 220 in the second direction D2. That is, at least a portion of the gate structure 220 does not overlap the conductive spacer 241 in the first direction D1.

[0134] In some example embodiments, at least a portion of the upper surface of the element isolation film 205 may not overlap with the etch stop film 250 in the third direction D3. Fig.13 In the embodiment, a space between two opposite ends of the etch stop film 250 on the upper surface 230US of the insulating spacer 230 may be equal to the first length L1.

[0135] Reference Fig.14 and Fig.15 , the first length L1 of the conductive spacer 241 in the second direction D2 may be greater than the second length L2 of the active area ACT in the second direction D2. The first length L1 of the conductive spacer 241 in the second direction D2 may be greater than the third length L3 of the gate structure 220 in the second direction D2. For reference, Fig.15 It can be along Fig.14 A cross-sectional view taken along line B3-B3'.

[0136] The semiconductor spacer 242 may have a bar shape in a plan view. The conductive spacer 241 may have a bar shape in a plan view. The semiconductor spacer 242 may extend in a first direction D1, and the conductive spacer 241 may extend in a second direction D2.

[0137] In some example embodiments, the gate structure 220 may completely overlap the conductive spacer 241 in the first direction D1.

[0138] In some example embodiments, at least a portion of the upper surface of the element isolation film 205 may not overlap with the etch stop film 250 in the third direction D3. Fig.13 In the embodiment, a space between two opposite ends of the etch stop film 250 on the upper surface 230US of the insulating spacer 230 may be equal to the first length L1.

[0139] Reference Fig.16 and Fig.17 , the first length L1 of the conductive spacer 241 in the second direction D2 may be less than the second length L2 of the active area ACT in the second direction D2. For reference, Fig.17 It can be along Fig.16 A cross-sectional view taken along line B4-B4'.

[0140] The area where the etching stop film 250 is removed may vary according to the structure of the mask film used in the process of forming the conductive spacer 241. When the length of the opening of the mask film in the second direction D2 is less than the second length L2, the first length L1 of the conductive spacer 241 in the second direction D2 may be less than the second length L2 of the active area ACT in the second direction D2.

[0141] In some example embodiments, a portion of the etch stop film 250 may not overlap the upper surface of the element isolation film 205 in the third direction D3 .

[0142] Reference Fig.18 , in the semiconductor memory device according to some embodiments, the front surface of the unit substrate 100 faces the front surface of the peripheral circuit substrate 200 .

[0143] For example, a semiconductor memory device according to some embodiments may have a C2C (chip-to-chip) structure. The C2C structure may be manufactured by forming an upper chip including a cell structure CELL on a first wafer (e.g., a unit substrate 100) and then forming a lower chip including a peripheral circuit structure PERI on a second wafer (e.g., a peripheral circuit substrate 200) different from the first wafer and then connecting the upper chip and the lower chip to each other in a bonding scheme.

[0144] In one example, the bonding scheme may refer to a scheme in which the bit line BL, a plurality of first metal patterns 170 and a second metal pattern 180, which are the top metal layer of the upper chip, and the first to third bonding metals 292, 293, and 294, which are the top metal layer of the lower chip, are electrically connected to each other. For example, when the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and each of the first to third bonding metals 292, 293, and 294 are made of copper (Cu), the bonding scheme may be a Cu-Cu bonding scheme. However, this is just an example. In another example, the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and each of the first to third bonding metals 292, 293, and 294 may be made of each of various other metals such as aluminum (Al) or tungsten (W).

[0145] When the bit line BL and the first bonding metal 292 are bonded to each other, the plurality of first metal patterns 170 and the second bonding metal 293 are bonded to each other, and the second metal pattern 180 and the third bonding metal 294 are bonded to each other, the cell structure CELL and the peripheral circuit structure PERI can be electrically connected to each other. For example, the bit line BL and the wiring pattern 290 can be electrically connected to each other through the first bonding metal 292 and the via contact 291. The plurality of first metal patterns 170 and the wiring pattern 290 can be electrically connected to each other through the second bonding metal 293 and another via contact 291. The second metal pattern 180 and the wiring pattern 290 can be electrically connected to each other through the third bonding metal 294 and another via contact 291. Therefore, each of the gate electrodes ECL, GSL, WL1 to WLn and SSL and / or the source layer 102 can be electrically connected to the peripheral circuit element PT.

[0146] In the following, reference will be made to Figures 19 to 26 Methods for manufacturing a semiconductor memory device according to some various example embodiments are described. Figures 19 to 26 are diagrams of intermediate structures corresponding to intermediate steps of a method for fabricating a semiconductor memory device according to various example embodiments.

[0147] First, refer to Fig.19 , a peripheral circuit substrate 200 may be provided. A gate structure 220 may be formed on the peripheral circuit substrate 200. The gate structure 220 may include a gate insulation pattern 221, a gate pattern 222, and a gate cap pattern 223. The gate insulation pattern 221, the gate pattern 222, and the gate cap pattern 223 may be sequentially stacked in the third direction D3. On each of two opposite sides of the gate structure 220, a source / drain region 270 may be formed in the peripheral circuit substrate 200. An active region ACT may be formed between the source / drain regions 270.

[0148] The insulating spacer 230 may be formed on the gate structure 220. The insulating spacer 230 may cover the sidewall and the upper surface of the gate structure 220. That is, the vertical level of the upper surface of the gate structure 220 is lower than the vertical level of the upper surface 230 of the insulating spacer 230.

[0149] Reference Fig. 20 , a pre-spacer structure 240P may be formed on the peripheral circuit substrate 200. The pre-spacer structure 240P may cover the insulating spacer 230 and the source / drain region 270. The pre-spacer structure 240P may include a semiconductor material. For example, the pre-spacer structure 240P may include an undoped polysilicon film.

[0150] Reference Fig.21, the pre-spacer structure 240P may be etched to expose the source / drain regions 270 and the insulating spacers 230. Specifically, a portion of the pre-spacer structure 240P may be removed using an etch-back process.

[0151] Reference Fig. 22 , an etch stop film 250 may be formed on the peripheral circuit substrate 200. The etch stop film 250 may be formed along the upper surface of the peripheral circuit substrate 200, the upper surface of the source / drain region 270, the outline of the pre-spacer structure 240P, and the upper surface 230US of the insulating spacer 230.

[0152] Reference Fig.23 , a peripheral circuit interlayer insulating film 210 may be formed on the peripheral circuit substrate 200. The peripheral circuit interlayer insulating film 210 may cover the etching stop film 250. Although not shown, first, the peripheral circuit interlayer insulating film 210 may completely cover the etching stop film 250. Subsequently, a portion of the peripheral circuit interlayer insulating film 210 may be removed to expose a portion of the etching stop film 250 on the insulating spacer 230.

[0153] Reference Fig.24 , a mask film MASK may be formed on the peripheral circuit interlayer insulating film 210. The mask film MASK may define therein an opening exposing at least a portion of the etch stop film 250. The size of the opening may be the same as the size of the conductive spacer 241 to be formed later.

[0154] The mask film MASK may include at least one of a photoresist film, an ACL (amorphous carbon layer), a SOH (spin-on hard mask), a SOC (spin-on carbon), and a silicon nitride film.

[0155] Using the mask film MASK as an etching mask, a portion of the peripheral circuit interlayer insulating film 210 and a portion of the etching stop film 250 may be removed. The portion of the peripheral circuit interlayer insulating film 210 not covered by the mask film MASK and the portion of the etching stop film 250 not covered by the mask film MASK may be removed. Thus, a portion of the pre-spacer structure 240P may be exposed.

[0156] Subsequently, a conductive spacer 241 may be formed. The conductive spacer 241 may be formed in a silicidation (self-aligned silicide) process. The conductive spacer 241 may be formed by performing a silicidation process on an exposed portion of the pre-spacer structure 240P.

[0157] Reference Fig.25 , a silicon oxide film may be additionally deposited to cover the entirety of each of the conductive spacer 241 and the insulating spacer 230. In other words, the peripheral circuit interlayer insulating film 210 may completely cover the conductive spacer 241 and the insulating spacer 230.

[0158] Reference Fig.26 , a contact 260 may be formed. The contact 260 may be formed on the conductive spacer 241. The contact 260 and the source / drain region 270 may be electrically connected to each other through the conductive spacer 241.

[0159] In the following, reference will be made to Figures 1 to 7 and Figure 27 to Figure 29 An electronic system including a semiconductor memory device according to exemplary embodiments is described.

[0160] Fig. 27 is a schematic block diagram for illustrating an electronic system according to some embodiments. Fig.28 is a schematic perspective view for illustrating an electronic system according to some embodiments. Fig.29 It is along Fig.28 Schematic cross-sectional view taken along line II'.

[0161] Reference Fig. 27 , an electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be implemented as a solid state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0162] The semiconductor memory device 1100 may be implemented as, for example, a NAND flash memory device, and may include, for example, Figures 1 to 5 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0163] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (eg, Figure 1 , a row decoder 33 in the page buffer 1120 (eg, Figure 1 , and logic circuits 1130 (eg, Figure 1 The control logic in 37).

[0164] The second structure 1100S may include the Figure 2The common source line CSL, multiple bit lines BL and multiple cell strings CSTR. The cell string CSTR can be connected to the decoder circuit 1110 through the word line WL, at least one string selection line SSL and at least one ground selection line GSL. In addition, the cell string CSTR can be connected to the page buffer 1120 through the bit line BL.

[0165] In some example embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S.

[0166] In some example embodiments, the bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from the first structure 1100F to the second structure 1100S. The page buffer 1120 may be as described above with reference to Figures 1 to 5 Describe the peripheral circuit components PT.

[0167] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Figure 1 The input / output pads 1101 of the control logic 37 in the first structure 1100F) communicate with the controller 1200. The input / output pads 1101 may be electrically connected to the logic circuit 1130 through input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0168] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100. In this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0169] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on predefined firmware, and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. Through the NAND interface 1221, a control command for controlling the semiconductor memory device 1100, data to be written into the memory cell transistor MCT of the semiconductor memory device 1100, and data to be read from the memory cell transistor MCT of the semiconductor memory device 1100 may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0170] Reference Figure 27 to Figure 29 , an electronic system according to some embodiments may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and at least one DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main substrate 2001.

[0171] The main substrate 2001 may include a connector 2006, which includes a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host using one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), M-Phy for UFS (Universal Flash Memory), etc. However, the example embodiments are not limited thereto. In some example embodiments, the electronic system 2000 may operate using power supplied from an external host via the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0172] The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operating speed of the electronic system 2000 .

[0173] The DRAM 2004 may function as a buffer memory for reducing the difference between the operating speed of the semiconductor package 2003 as a data storage space and the operating speed of the external host. The DRAM 2004 included in the electronic system 2000 may operate as a high-speed cache memory and may provide a space for temporarily storing data therein in the control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0174] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be implemented as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100 to each other, and a mold layer 2500 disposed on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0175] The package substrate 2100 may be implemented as a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig. 27 The input / output pad 1101 in.

[0176] In some example embodiments, the connection structure 2400 may be implemented as a bonding wire that electrically connects the input / output pad 2210 and the on-package pad 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire scheme, and may be electrically connected to the on-package pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through electrode (through silicon via: TSV) instead of the connection structure 2400 using a bonding wire scheme.

[0177] In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in one package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring formed in the interposer substrate.

[0178] In some example embodiments, the package substrate 2100 may be implemented as a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body 2120, a package lower pad 2125 disposed on a lower surface of the package substrate body 2120 or exposed through its lower surface, and an internal line 2135 disposed in the package substrate body 2120 to electrically connect the upper pad 2130 and the lower pad 2125 to each other. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to a conductive connector 2800 such as Fig. 27 The electronic system 2000 is shown with a wiring pattern 2005 of a main substrate 2001 .

[0179] Reference Fig.28 and Fig.29 In the electronic system according to some embodiments, each semiconductor chip 2200 may include the above-mentioned Figures 1 to 7 For example, each semiconductor chip 2200 may include a peripheral circuit structure PERI and a cell structure CELL stacked on the peripheral circuit structure PERI. In one example, the peripheral circuit structure PERI may include a peripheral circuit substrate 200 and a peripheral circuit PT, as described above using Figures 5 to 7 In addition, in one example, the cell structure CELL may include the above-mentioned Figure 3 and Figure 4 The unit substrate 100, the mold structure MS, the channel structure CH, the word line cutting structure WLC and the bit line BL.

[0180] Although various example embodiments have been described with reference to the accompanying drawings, the various example embodiments are not limited to the above embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that various example embodiments can be practiced in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor memory device, comprising: Unit structure; and a peripheral circuit structure electrically connected to the cell structure, The unit structure comprises a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and The bit line, connected to the channel structure, The peripheral circuit structure includes Active area, a gate structure on the active area, the gate structure intersecting the active area, a source / drain region on at least one side of the gate structure and in the active region, an insulating spacer covering the gate structure, a conductive spacer on a sidewall of the insulating spacer and electrically connected to the source / drain region, and a contact electrically connected to the conductive spacer, and Wherein, at least a portion of a topmost surface of the insulating spacer is coplanar with at least a portion of a topmost surface of the conductive spacer.

2. The semiconductor memory device according to claim 1, wherein: An upper surface of the insulating spacer protrudes toward the active region.

3. The semiconductor memory device according to claim 1, wherein: The contact completely overlaps the conductive spacer in the vertical direction.

4. The semiconductor memory device according to claim 1, wherein: At least a portion of the contact does not overlap the conductive spacer in the vertical direction. 5 . The semiconductor memory device according to claim 1 , further comprising a silicide film interposed between the source / drain regions and the conductive spacer.

6. The semiconductor memory device according to claim 5, wherein: The silicide film is not in contact with the contact. 7 . The semiconductor memory device according to claim 1 , further comprising an etch stop film covering at least a portion of the source / drain region.

8. The semiconductor memory device according to claim 7, wherein: The etch stop film covers a portion of an upper surface of the insulating spacer.

9. A semiconductor memory device comprising: Unit structure; and a peripheral circuit structure electrically connected to the cell structure, The unit structure comprises a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and connected to the bit line of the channel structure, Wherein, the peripheral circuit structure includes an active region extending in a first direction, a gate structure on the active region and extending in a second direction, wherein the gate structure intersects the active region, a source / drain region on at least one side of the gate structure and in the active region, an insulating spacer covering the upper surface and sidewalls of the gate structure and comprising an insulating material, and a spacer structure surrounding the sidewalls of the insulating spacer, The spacer structure comprises Semiconductor spacers, including semiconductor materials, a conductive spacer comprising a conductive material and electrically connected to the source / drain region, and a contact electrically connected to the conductive spacer, wherein the gate structure comprises a pair of first side walls extending in the first direction and a pair of second side walls extending in the second direction, and In a plan view of the semiconductor memory device, the conductive spacer is on the pair of second side walls and does not exist on the pair of first side walls.

10. The semiconductor memory device according to claim 9, wherein: A length of the conductive spacer in the second direction is smaller than a length of the gate structure in the second direction.

11. The semiconductor memory device according to claim 9, wherein: A length of the conductive spacer in the second direction is equal to a length of the gate structure in the second direction.

12. The semiconductor memory device according to claim 9, wherein: In a plan view of the semiconductor memory device, at least a portion of the semiconductor spacer overlaps the gate structure in the first direction.

13. The semiconductor memory device according to claim 9, wherein: A topmost surface of the spacer structure is coplanar with an upper surface of the insulating spacer.

14. The semiconductor memory device according to claim 9, wherein: An upper surface of the insulating spacer protrudes toward the active region.

15. The semiconductor memory device according to claim 9, further comprising an etching stopper film covering an upper surface of the semiconductor spacer, and in, The etch stop film does not overlap the conductive spacer in the vertical direction.

16. The semiconductor memory device according to claim 15, wherein: At least a portion of the etch stop film overlaps the insulating spacer in the vertical direction.

17. The semiconductor memory device according to claim 9, wherein: The vertical level of the bottommost surface of the contact is greater than the vertical level of the upper surface of the source / drain region.

18. A semiconductor memory device comprising: Unit structure; and a peripheral circuit structure electrically connected to the cell structure, The unit structure comprises a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and The bit line, connected to the channel structure, The peripheral circuit structure includes an active region extending in a first direction, a gate structure on the active region and extending in a second direction, wherein the gate structure intersects the active region and includes a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in the second direction, a source / drain region on each of the pair of second sidewalls of the gate structure and in the active region, an insulating spacer covering the upper surface of the gate structure, the pair of first sidewalls and the pair of second sidewalls and comprising an insulating material, a spacer structure surrounding an outer side wall of the insulating spacer, The spacer structure comprises A semiconductor spacer comprising a semiconductor material, a conductive spacer comprising a conductive material and electrically connected to the source / drain region, an etch stop film covering a portion of the insulating spacer, the semiconductor spacer, and a portion of the source / drain region, and a contact electrically connected to the conductive spacer, wherein the etching stop film does not overlap with the conductive spacer in the vertical direction, wherein the conductive spacer overlaps with the pair of second side walls in the first direction and does not overlap with the pair of first side walls in the second direction, and Wherein, the topmost surface of the spacer structure is coplanar with the upper surface of the insulating spacer.

19. The semiconductor memory device according to claim 18, wherein: A length of the conductive spacer in the second direction is smaller than a length of the gate structure in the second direction.

20. The semiconductor memory device according to claim 18, wherein The contact completely overlaps the conductive spacer in the vertical direction.

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