Semiconductor memory device

Abstract

The embodiment of the invention provides a semiconductor memory device which can be manufactured well. A semiconductor memory device according to an embodiment of the present invention includes: a plurality of conductive layers stacked in a stacking direction; a semiconductor pillar facing the plurality of conductive layers; a gate insulating film provided between the plurality of conductive layers and the semiconductor pillar, the gate insulating film including a charge storage film; a semiconductor component connected to the semiconductor pillar; a contact electrode connected to the semiconductor component; a first insulating member that breaks a portion of the conductive layer in the first direction; and a second insulating member provided inside the first insulating member. The contact electrode is provided with: a first conductive region provided on the opposite side of the semiconductor pillar in the lamination direction with respect to the contact electrode-side surface of the semiconductor component in the lamination direction; and a second conductive region provided between the semiconductor member and the second insulating member on the semiconductor pillar side in the lamination direction with respect to the surface of the semiconductor member, the second conductive region being in contact with the second insulating member.

Description

[0001] [Reference to related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2023-142611 (filing date: September 1, 2023). The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device is known, which includes a plurality of conductive layers stacked in a stacking direction, a semiconductor pillar extending in the stacking direction and facing the plurality of conductive layers, and a gate insulating film disposed between the plurality of conductive layers and the semiconductor pillar. The gate insulating film includes, for example, an insulating charge storage film such as silicon nitride (SiN), a conductive charge storage film such as a floating gate, and the like. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor memory device that can be preferably manufactured.

[0006] A semiconductor storage device in one embodiment comprises: a plurality of conductive layers stacked in a stacking direction; a first semiconductor column extending in the stacking direction and opposite to the plurality of conductive layers; a first gate insulating film arranged between the plurality of conductive layers and the first semiconductor column and including a first charge storage film; a first semiconductor component connected to one end of the first semiconductor column in the stacking direction; a first contact electrode extending in the stacking direction and connected to the first semiconductor component; a first insulating component arranged at a position overlapping with a portion of the first semiconductor column and the first gate insulating film as viewed in the stacking direction, and separating a portion of the conductive layers on the first contact electrode side arranged in the stacking direction in the plurality of conductive layers in a first direction intersecting the stacking direction; and a second insulating component arranged at least at a first position in the stacking direction corresponding to the first semiconductor component inside the first insulating component. The first contact electrode comprises: a first conductive region, which is arranged on the side opposite to the first semiconductor column in the stacking direction relative to the surface on the first contact electrode side of the first semiconductor component in the stacking direction; and a second conductive region, which is arranged on the side of the first semiconductor column in the stacking direction relative to the surface of the first semiconductor component between the first semiconductor component and the second insulating component and is connected to the second insulating component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic circuit diagram showing the structure of the semiconductor memory device according to the first embodiment.

[0008] Figure 2It is a schematic top view showing a partial structure of the semiconductor memory device.

[0009] Figure 3 It is a schematic top view showing a partial structure of the semiconductor memory device.

[0010] Figure 4 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device.

[0011] Figure 5 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device.

[0012] Figure 6 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device.

[0013] Figure 7 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device.

[0014] Figure 8 is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device.

[0015] Fig. 9 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0016] Fig.10 It is a schematic cross-sectional view for explaining the manufacturing method.

[0017] Fig.11 It is a schematic cross-sectional view for explaining the manufacturing method.

[0018] Fig.12 It is a schematic cross-sectional view for explaining the manufacturing method.

[0019] Fig.13 It is a schematic cross-sectional view for explaining the manufacturing method.

[0020] Fig.14 It is a schematic cross-sectional view for explaining the manufacturing method.

[0021] Fig.15 It is a schematic cross-sectional view for explaining the manufacturing method.

[0022] Fig.16 It is a schematic cross-sectional view for explaining the manufacturing method.

[0023] Fig.17 It is a schematic cross-sectional view for explaining the manufacturing method.

[0024] Fig.18 It is a schematic cross-sectional view for explaining the manufacturing method.

[0025] Fig.19 It is a schematic cross-sectional view for explaining the manufacturing method.

[0026] Fig. 20 It is a schematic cross-sectional view for explaining the manufacturing method.

[0027] Fig.21 It is a schematic cross-sectional view for explaining the manufacturing method.

[0028] Fig. 22 It is a schematic cross-sectional view for explaining the manufacturing method.

[0029] Fig.23 It is a schematic cross-sectional view for explaining the manufacturing method.

[0030] Fig.24 It is a schematic cross-sectional view for explaining the manufacturing method.

[0031] Fig.25 It is a schematic cross-sectional view for explaining the manufacturing method.

[0032] Fig.26 It is a schematic cross-sectional view for explaining the manufacturing method.

[0033] Fig. 27 It is a schematic cross-sectional view for explaining the manufacturing method.

[0034] Fig.28 It is a schematic cross-sectional view for explaining the manufacturing method.

[0035] Fig.29 It is a schematic cross-sectional view for explaining the manufacturing method.

[0036] Fig.30 It is a schematic cross-sectional view for explaining the manufacturing method.

[0037] Fig.31 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a second embodiment.

[0038] Fig.32 is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device.

[0039] Fig.33 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0040] Fig.34 It is a schematic cross-sectional view for explaining the manufacturing method.

[0041] Fig.35 It is a schematic cross-sectional view for explaining the manufacturing method.

[0042] Fig.36 It is a schematic cross-sectional view for explaining the manufacturing method.

[0043] Fig.37 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0044] Fig.38 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0045] Fig.39 is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device.

[0046] Fig.40 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the fourth embodiment.

[0047] Fig.41 It is a schematic cross-sectional view for explaining the manufacturing method.

[0048] Fig.42 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment.

[0049] Fig.43 is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device.

[0050] Fig.44 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a sixth embodiment.

[0051] Fig.45 This is a schematic cross-sectional view showing a partial structure of a semiconductor storage device according to a seventh embodiment.

[0052] Fig.46 is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device.

[0053] Fig.47 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the seventh embodiment.

[0054] Fig.48 It is a schematic cross-sectional view for explaining the manufacturing method.

[0055] Fig.49 It is a schematic cross-sectional view for explaining the manufacturing method.

[0056] Fig.50 It is a schematic cross-sectional view for explaining the manufacturing method.

[0057] Fig.51 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment.

[0058] Fig.52 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION

[0059] Next, the semiconductor memory device of the embodiment is described in detail with reference to the drawings. In addition, the following embodiment is only an example and is not intended to limit the present invention. In addition, the following drawings are schematic diagrams, and sometimes a part of the structure is omitted for the convenience of explanation. In addition, sometimes the same symbols are attached to the parts common to multiple embodiments and the description is omitted.

[0060] In addition, when the term "semiconductor storage device" is used in this specification, it may refer to a storage crystal grain, or a memory chip, a memory card, an SSD (Solid State Drive) or other memory system including a controller crystal grain. Furthermore, it may refer to a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0061] In addition, in this specification, when it is said that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the off state.

[0062] In addition, in this specification, when it is said that the first structure is "connected" "between" the second structure and the third structure, it may mean that the first structure, the second structure and the third structure are connected in series, and the second structure is connected to the third structure via the first structure.

[0063] In addition, in this specification, the direction intersecting the surface of the substrate is sometimes referred to as the stacking direction. In addition, the direction along a specific surface intersecting the stacking direction is sometimes referred to as the first direction, and the direction intersecting the first direction along the surface is sometimes referred to as the second direction. The stacking direction may or may not coincide with the Z direction. In addition, the first direction and the second direction may or may not correspond to any one of the X direction and the Y direction.

[0064] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when the lower surface or lower end of a certain structure is mentioned, it means the surface or end of the substrate side of the structure, and when the upper surface or upper end is mentioned, it means the surface or end of the structure on the opposite side of the substrate. In addition, the surface intersecting the X direction or the Y direction is called the side surface, etc.

[0065] In addition, in this specification, when referring to the "width", "length" or "thickness" in a specific direction of a structure, component, etc., it sometimes means the width, length or thickness in a cross section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0066] [First embodiment]

[0067] [Circuit configuration]

[0068] Figure 1 FIG. 1 is a schematic circuit diagram showing the structure of a semiconductor memory device according to the first embodiment. Figure 1 As shown, the semiconductor memory device of this embodiment includes a memory cell array MCA and a peripheral circuit PC.

[0069] The memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string groups SU. Each of these plurality of string groups SU includes a plurality of memory strings MS. One end of each of these plurality of memory strings MS is connected to a peripheral circuit PC via a bit line BL. In addition, the other ends of each of these plurality of memory strings MS are connected to a peripheral circuit PC via a common source line SL.

[0070] The memory string MS includes drain side selection transistors STDT and STD, a plurality of memory cells MC (memory transistors), and source side selection transistors STS and STSB. The drain side selection transistors STDT and STD are connected in series between the plurality of memory cells MC, the source side selection transistors STS and STSB, the bit line BL, and the source line SL. Hereinafter, the drain side selection transistors STDT and STD and the source side selection transistors STS and STSB are sometimes simply referred to as selection transistors (STDT, STD, STS, STSB).

[0071] The memory cell MC is a field effect transistor. The memory cell MC includes a portion of a semiconductor column, a gate insulating film, and a gate electrode. A portion of the semiconductor column functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multi-bit data. In addition, word lines WL are respectively connected to the gate electrodes of a plurality of memory cells MC corresponding to a memory string MS. These word lines WL are respectively connected in common to all memory strings MS in a memory block BLK.

[0072] The selection transistors (STDT, STD, STS, STSB) are field effect transistors. The selection transistors (STDT, STD, STS, STSB) include a portion of a semiconductor column, a gate insulating film, and a gate electrode. A portion of the semiconductor column functions as a channel region. The gate electrodes of the selection transistors (STDT, STD, STS, STSB) are respectively connected to selection gate lines (SGDT, SGD, SGS, SGSB). One drain-side selection gate line SGDT is commonly connected to all memory strings MS in one memory block BLK. One drain-side selection gate line SGD is commonly connected to all memory strings MS in one string group SU. One source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. One source-side selection gate line SGSB is commonly connected to all memory strings MS in one memory block BLK.

[0073] The peripheral circuit PC includes, for example: a voltage generating circuit that generates an action voltage; a voltage transmission circuit that transmits the generated action voltage to the selected bit line BL, word line WL, source line SL, selection gate line (SGDT, SGD, SGS, SGSB), etc.; a sensing amplifier module that is connected to the bit line BL; and a sequencer that controls these.

[0074] [structure]

[0075] Next, refer to Figure 2 to Figure 8 The structure of the semiconductor memory device according to the first embodiment will be described.

[0076] Figure 2 It is a schematic top view showing a partial structure of the semiconductor memory device. Figure 3 is a schematic top view showing a part of the structure of the semiconductor memory device. Figure 2 The portion shown in A is enlarged. Figure 3 A portion of represents an XY cross section at a height position corresponding to the conductive layer 110 (WL) described below. Figure 3A portion of is a plane in which the bit line BL and the insulating layers 102, 103, and 104 described below are omitted. Figure 3 A portion of FIG. 1 is shown as a bit line BL. Figure 4 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device. Figure 4 Indicates that Figure 3 The structure shown is a cross section cut along line BB′ and observed in the direction of the arrow. Figure 5 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device, and Figure 4 The portion shown in C is enlarged. Figure 5 , but when observing a cross section other than the YZ cross section along the central axis of the semiconductor pillar 120 (for example, the XZ cross section), the same Figure 5 Same structure.

[0077] Figure 6 and Figure 7 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device. Figure 8 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device. Figure 6 Representation and Figure 4 In addition, Figure 6 Indicates that Figure 8 The structure shown is a cross section cut along line DD' and observed along the arrow direction. Figure 7 Indicates that Figure 8 The structure shown is a cross section cut along line EE' and observed in the direction of the arrow. Figure 8 Representation and Figure 6 and Figure 7 The XY cross section at the height position corresponding to the chain line F is shown. The chain line F indicates the height position Z1 corresponding to the semiconductor component 126 described below.

[0078] in addition, Figure 2 to Figure 8 This is a schematic diagram, and sometimes part of the structure is omitted. For example, Figure 4 The following insulating member 151 is omitted ( Figure 6 , Figure 8 ).

[0079] The semiconductor memory device of the first embodiment is, for example, Figure 2 As shown, a semiconductor substrate 100 is provided. In the example shown in the figure, four memory cell array regions R arranged in the X direction and the Y direction are provided on the semiconductor substrate 100. MCA In addition, in the four memory cell array regions R MCA A plurality of finger structures FS are arranged along the Y direction. In addition, a peripheral region R is provided at the end of the semiconductor substrate 100 in the Y direction.P .

[0080] [Finger structure FS]

[0081] Finger-like structures FS, for example Figure 3 As shown, there are a plurality of string groups SU arranged in the Y direction. An inter-finger structure ST is provided between two finger structures FS adjacent to each other in the Y direction. An insulating member SHE is provided between two string groups SU adjacent to each other in the Y direction.

[0082] In this embodiment, one finger structure FS serves as one memory block BLK ( Figure 1 ) to function. In addition, each finger structure FS has 5 string groups SU. Among them, multiple finger structures FS can also function as one memory block BLK. In addition, the finger structure FS can have 2 to 4 string groups SU, or can have more than 6 string groups SU.

[0083] Finger-like structures FS, for example Figure 4 As shown, it includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120. In addition, the upper ends of the semiconductor pillars 120 are connected to the semiconductor component 126, the upper surface of the semiconductor component 126 is connected to the contact electrode Ch, the upper end of the contact electrode Ch is connected to the contact electrode Vy, and the upper end of the contact electrode Vy is connected to the bit line BL.

[0084] [Conductive layer 110]

[0085] The conductive layer 110 extends in the X direction. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction. In addition, an insulating layer 102 such as silicon oxide (SiO2), an insulating layer 103 such as silicon nitride (SiN), and an insulating layer 104 such as silicon oxide (SiO2) are provided above the plurality of conductive layers 110 arranged in the Z direction.

[0086] A conductive layer 112 is provided below the conductive layer 110. The conductive layer 112 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). In addition, a conductive layer such as a metal such as tungsten (W), a tungsten silicide, or other conductive layers may be provided on the lower surface of the conductive layer 112. In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 112 and the conductive layer 110.

[0087] The conductive layer 112 serves as the source line SL ( Figure 1 ) function. For example, for the memory cell array area R MCA ( Figure 2 ) is provided with a source line SL in common for all the finger structures FS included therein.

[0088] In addition, one or more conductive layers 110 located at the bottom of the plurality of conductive layers 110 serve as source side selection gate lines SGSB and a plurality of source side selection transistors STSB ( Figure 1 ) functions as a gate electrode. In the following description, the conductive layer 110 is sometimes referred to as the conductive layer 110 (SGSB). The conductive layer 110 (SGSB) is electrically independent for each finger structure FS. The conductive layer 110 (SGSB) includes a plurality of through holes corresponding to the plurality of semiconductor pillars 120. The inner peripheral surfaces of the plurality of through holes respectively extend all around and surround the outer peripheral surfaces of the corresponding semiconductor pillars 120, and face the outer peripheral surfaces of the corresponding semiconductor pillars 120.

[0089] In addition, one or more conductive layers 110 located above the source side selection gate line SGS and a plurality of source side selection transistors STS ( Figure 1 ) functions as a gate electrode. In the following description, the conductive layer 110 is sometimes referred to as the conductive layer 110 (SGS). The conductive layer 110 (SGS) is electrically independent for each finger structure FS. The conductive layer 110 (SGS) has a plurality of through holes corresponding to the plurality of semiconductor pillars 120. The inner peripheral surfaces of these plurality of through holes respectively extend all around and surround the outer peripheral surfaces of the corresponding semiconductor pillars 120, and face the outer peripheral surfaces of the corresponding semiconductor pillars 120.

[0090] In addition, a plurality of conductive layers 110 located above the word lines WL and a plurality of memory cells MC connected thereto ( Figure 1 ) functions as a gate electrode. In the following description, the conductive layer 110 is sometimes referred to as the conductive layer 110 (WL). The conductive layer 110 (WL) is electrically independent for each finger structure FS. The conductive layer 110 (WL) includes a plurality of through holes corresponding to the plurality of semiconductor pillars 120. The inner peripheral surfaces of the plurality of through holes respectively extend all around and surround the outer peripheral surfaces of the corresponding semiconductor pillars 120, and face the outer peripheral surfaces of the corresponding semiconductor pillars 120.

[0091] In addition, one or more conductive layers 110 located above the drain side selection gate line SGD and a plurality of drain side selection transistors STD ( Figure 1 ) functions as a gate electrode. In the following description, this conductive layer 110 is sometimes referred to as a conductive layer 110 (SGD). Figure 3The conductive layer 110 (SGDT) described below has the same shape as the conductive layer 110 (SGDT). Figure 3 As shown, an insulating member SHE is provided between two conductive layers 110 (SGD) adjacent to each other in the Y direction. The conductive layers 110 (SGD) are electrically independent for each string group SU.

[0092] In addition, if Figure 3 As shown, the length Y of the conductive layer 110 (SGD) in the Y direction SGD , which is smaller than the length Y of the conductive layer 110 (WL) in the Y direction WL .For example Figure 3 In the example, five conductive layers 110 (SGD) arranged in the Y direction and four insulating members SHE arranged in the Y direction are provided corresponding to one conductive layer 110 (WL). Therefore, in the example shown in the figure, the length Y of the conductive layer 110 (SGD) in the Y direction is SGD , which is smaller than the length Y of the conductive layer 110 (WL) in the Y direction WL However, among the five conductive layers 110 (SGD) corresponding to one finger structure FS and arranged along the Y direction, the lengths of the first and fifth conductive layers 110 (SGD) in the Y direction from one side in the Y direction may be greater than the lengths Y of the other three conductive layers 110 (SGD) in the Y direction. SGD , or the length Y of the conductive layer 110 (WL) in the Y direction WL More than 1 / 5 of.

[0093] In addition, the conductive layer 110 (SGD) includes a plurality of through holes 113 corresponding to the plurality of semiconductor pillars 120, and a plurality of recesses 114 corresponding to the plurality of semiconductor pillars 120. The inner peripheral surfaces of the plurality of through holes 113 surround the outer peripheral surfaces of the corresponding semiconductor pillars 120 over the entire circumference, and face the outer peripheral surfaces of the corresponding semiconductor pillars 120. The plurality of recesses 114 are connected to the side surfaces 115 of the conductive layer 110 (SGD) in the Y direction, and face a portion of the outer peripheral surfaces of the corresponding semiconductor pillars 120.

[0094] In addition, one or more conductive layers 110 located above the drain side selection gate line SGDT and a plurality of drain side selection transistors STDT ( Figure 1 ) functions as a gate electrode. In the following description, the conductive layer 110 is sometimes referred to as a conductive layer 110 (SGDT). The conductive layer 110 (SGDT) is basically configured in the same manner as the conductive layer 110 (SGD). Among them, a plurality of conductive layers 110 (SGDT) included in one finger structure FS are electrically connected to each other via wiring or the like.

[0095] [Semiconductor column 120]

[0096] The semiconductor pillar 120 is, for example, Figure 3 As shown, the finger structure FS is arranged in a specific pattern along the X direction and the Y direction. For example, the finger structure FS includes 20 semiconductor column columns SC arranged from one side of the Y direction to the other side of the Y direction. These 20 semiconductor column columns SC each include a plurality of semiconductor columns 120 arranged along the X direction. These 20 semiconductor column columns SC are arranged at a pitch P. SC That is, when focusing on two semiconductor column rows SC adjacent to each other in the Y direction, the center position Y in the Y direction of one semiconductor column row SC is SC The center position Y in the Y direction of another semiconductor column row SC SC , in the Y direction, leaving a distance P SC Equal distance.

[0097] In addition, the spacing P SC It can be specified in various ways.

[0098] For example, SEM, TEM and other methods can be used to observe Figure 3 The XY cross section corresponding to the conductive layer 110 (WL) is shown as an example. In this XY cross section, the center position Y in the Y direction of 20 semiconductor column rows SC corresponding to the finger structure FS of interest is measured. SC , determination of these 20 central positions Y SC The corresponding 19 distances, the average or median value of these 19 distances is set as the spacing P SC In addition, for example, the center position Y in the Y direction of the four semiconductor column arrays SC corresponding to the string group SU of interest may be measured in the XY cross section. SC , determination of these 4 central positions Y SC The corresponding three distances, the average or median of these three distances is set as the spacing P SC .

[0099] In addition, the center position Y of the semiconductor column array SC in the Y direction is SC It can be determined by various methods. For example, it can be observed by SEM, TEM and other methods. Figure 3 The XY cross section shown in the example, in which the center position in the Y direction of at least one semiconductor column 120 included in the semiconductor column column array SC of interest is measured, and any center position, an average value of multiple center positions, or a median value of multiple center positions is set as the center position Y in the Y direction of the semiconductor column column SC. SCThe center position of the semiconductor pillar 120 in the Y direction may be the position in the Y direction of the center point of the circumscribed circle of the semiconductor pillar 120 in the XY cross section, or may be the position in the Y direction of the center of gravity on the image of the semiconductor pillar 120 .

[0100] Hereinafter, the semiconductor pillar 120 corresponding to the 4nth (n is an integer of 1 to 4)th and 4n+1th semiconductor pillar columns SC from one side in the Y direction may be referred to as the semiconductor pillar 120. O In addition, the semiconductor pillars 120 corresponding to the 1st to 3rd, 4n+2nd, 4n+3rd, and 20th semiconductor pillar columns SC counted from one side in the Y direction are sometimes referred to as semiconductor pillars 120. I .

[0101] The semiconductor pillar 120 includes, for example, polysilicon (Si). Figure 4 The structure shown in the figure has a substantially cylindrical shape, and an insulating layer 127 such as silicon oxide (SiO2) is provided in the center portion.

[0102] The semiconductor pillar 120 includes a region 121 arranged at the lower end, a region 122 opposite to one or more conductive layers 110 (SGSB) and one or more conductive layers 110 (SGS), a region 123 opposite to multiple conductive layers 110 (WL), a region 124 opposite to one or more conductive layers 110 (SGD), and a region 125 opposite to one or more conductive layers 110 (SGDT).

[0103] The region 121 contains N-type impurities such as phosphorus (P). The region 121 has a substantially cylindrical shape. The region 121 is connected to the conductive layer 112 .

[0104] The region 122 functions as a channel region of the source side selection transistors STSB and STS. The lower end of the region 122 may also contain N-type impurities such as phosphorus (P). In addition, the other parts of the region 122 may not contain N-type impurities such as phosphorus (P). The region 122 has a substantially cylindrical shape.

[0105] The region 123 functions as a channel region of the memory cell MC. The region 123 does not need to contain N-type impurities such as phosphorus (P). The region 123 has a substantially cylindrical shape.

[0106] In addition, the semiconductor column 120 I The regions 121, 122, and 123 are arranged at positions not overlapping with the insulating member SHE when viewed from the Z direction. O The regions 121 , 122 , and 123 each include a portion provided at a position overlapping with the insulating member SHE when viewed from the Z direction.

[0107] The region 124 functions as a channel region of the drain-side selection transistor STD. The region 124 does not need to contain N-type impurities such as phosphorus (P).

[0108] Here, Figure 3 In the example, the semiconductor column 120 I Separated from the insulating member SHE. In addition, the semiconductor pillar 120 I The region 124 has a substantially cylindrical shape. The semiconductor pillar 120 I The outer peripheral surface of the region 124 faces the inner peripheral surface of the through hole 113 provided in the conductive layer 110 (SGD).

[0109] also, Figure 3 In the example, the semiconductor column 120 O The semiconductor pillar 120 is connected to the insulating member SHE. O The region 124 may have a substantially cylindrical shape, or may have an arc shape when viewed from the Z direction. O A portion of the outer peripheral surface of the region 124 is opposite to the recess 114 provided in the conductive layer 110 (SGD). O The other areas of the outer peripheral surface of the region 124 are in contact with the insulating member SHE.

[0110] Area 125( Figure 4 ) functions as a channel region of the drain side selection transistor STDT. The upper end of the region 125 may also contain N-type impurities such as phosphorus (P). In addition, the other parts of the region 125 may not contain N-type impurities such as phosphorus (P). The semiconductor pillar 120 I The region 125 has a substantially cylindrical shape. The semiconductor pillar 120 O The region 125 may have a substantially cylindrical shape, or may have an arc shape when viewed from the Z direction.

[0111] [Semiconductor component 126]

[0112] Semiconductor component 126 ( Figure 4 ) contains N-type impurities such as phosphorus (P). Figure 8 As shown, the semiconductor column 120 I The semiconductor component 126 (hereinafter, sometimes referred to as “semiconductor component 126”) connected to the I ”) is formed into a substantially cylindrical shape. On the other hand, the semiconductor column 120 O The semiconductor component 126 (hereinafter, sometimes referred to as “semiconductor component 126”) connected to the O ”) is formed into a cylindrical shape with a portion missing. That is, the semiconductor component 126 OA portion of the outer peripheral surface is aligned with the semiconductor component 126 I On the other hand, the semiconductor component 126 is formed into a circle of the same size as the circumscribed circle. O The portion of the outer peripheral surface of the semiconductor component 126 on the insulating component SHE side in the Y direction is a recessed portion 126A. O The length Y in the Y direction 126 , smaller than semiconductor components 126 O The length X in the X direction 126 .

[0113] Figure 6 Three points p1 to p3 on the concave portion 126A are shown as an example. Points p1 and p2 are separated in the Z direction. The position of point p3 in the Z direction is set between the position of point p1 in the Z direction and the position of point p2 in the Z direction. Point p3 is set on the side opposite to the insulating member SHE in the Y direction with respect to points p1 and p2.

[0114] Figure 8 Three points p4 to p6 on the concave portion 126A are shown as an example. Points p4 and p5 are separated in the X direction. The position of point p6 in the X direction is set between the position of point p4 in the X direction and the position of point p5 in the X direction. Point p6 is set on the side opposite to the insulating member SHE in the Y direction with respect to points p4 and p5.

[0115] [Gate insulating film 130]

[0116] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surfaces of the semiconductor pillar 120 and the semiconductor component 126. The gate insulating film 130 may be, for example, Figure 5 As shown, it includes a tunnel insulating film 131, a charge storage film 132, and a blocking insulating film 133 stacked between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 is, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor column 120 except for a portion of the region. For example Figure 4 As shown, the tunnel insulating film 131, the charge storage film 132, and the blocking insulating film 133 are not provided at the contact portion between the semiconductor pillar 120 and the conductive layer 112. O A tunnel insulating film 131 , a charge storage film 132 , and a blocking insulating film 133 are provided on the contact surface with the insulating member SHE.

[0117] in addition, Figure 5The gate insulating film 130 is shown as an example including the charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may include a floating gate made of, for example, polysilicon containing N-type or P-type impurities.

[0118] [Contact electrode Ch]

[0119] The contact electrode Ch extends in the Z direction through a portion of the insulating layer 104, the insulating layer 103, and a portion of the insulating layer 102. The contact electrode Ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Figure 3 As shown, the semiconductor pillars 120 are arranged in a specific pattern along the X direction and the Y direction.

[0120] like Figure 3 and Figure 4 As shown, the semiconductor component 126 I The contact electrode Ch (hereinafter sometimes referred to as “contact electrode Ch”) connected to I ”) is formed into a substantially cylindrical shape. The contact electrode Ch I The lower end of the semiconductor component 126 extends over the entire surface. I The upper surface of .

[0121] like Figure 6 and Figure 7 As shown, the semiconductor component 126 O The contact electrode Ch (hereinafter sometimes referred to as “contact electrode Ch”) connected to O ”), having a conductive region R disposed above the upper surface of the semiconductor component 126 Ch1 , and a conductive region R disposed below the upper surface of the semiconductor component 126 Ch2 .

[0122] Conductive area R Ch1 It is formed in a substantially cylindrical shape extending in the Z direction. Ch1 The lower end portion of the semiconductor component 126 O The upper surface of .

[0123] Conductive area R Ch2 The semiconductor component 126 is provided O Between the insulating member 151 described below or the insulating member 152 described below. Conductive region R Ch2 The lower end of the conductive region R is disposed below the upper surface of the semiconductor component 126 and above the lower surface of the semiconductor component 126 (the upper end of the insulating layer 127). Ch2 The lower end and the side surface on one side in the Y direction are in contact with the insulating members 151 and 152 and are covered by the insulating members 151 and 152. The conductive region R Ch2The side surface on the other side in the Y direction is in contact with the recessed portion 126A of the semiconductor component 126 and is covered by the recessed portion 126A.

[0124] like Figure 6 and Figure 7 As shown in FIG. 1 , an insulating film 157 made of silicon oxide (SiO 2 ) or the like is provided on the outer peripheral surface of the contact electrode Ch. The insulating film 157 has a substantially cylindrical shape and extends in the Z direction along the outer peripheral surface of the contact electrode Ch.

[0125] [Insulation parts SHE]

[0126] Insulation components SHE such as Figure 3 and Figure 4 The diagram shows that the SHE extends in the X direction and the Z direction. The insulating member SHE includes silicon oxide (SiO 2 ), for example.

[0127] The length Y of the insulating member SHE in the Y direction SHE ( Figure 8 ), which is smaller than the length Y in the Y direction of the conductive layer 110 (SGD) and the conductive layer 110 (SGDT). SGD ( Figure 3 ). In addition, the length Y of the insulating member SHE in the Y direction is SHE ( Figure 8 ), which is smaller than the pitch P in the Y direction of the plurality of semiconductor column columns SC. SC ( Figure 3 The insulating member SHE is disposed between the semiconductor columns 120 included in two semiconductor column columns SC adjacent to each other in the Y direction. O However, no through hole or recess corresponding to the semiconductor pillar 120 is provided in the semiconductor pillar itself.

[0128] In addition, if Figure 6 and Figure 7 As shown, the lower end of the insulating member SHE is located above the lower surface of the conductive layer 110 (WL) located at the uppermost layer. In addition, the lower end of the insulating member SHE is located below the lower surface of the conductive layer 110 (SGD) located at the lowermost layer. In addition, the upper end of the insulating member SHE is in contact with the lower surface of the insulating layer 103.

[0129] The insulating member SHE includes a region R1 disposed below a height position Z3 described below, and a region R2 disposed above the height position Z3. In the example shown in the figure, the height position Z3 is disposed below the lower surface of the semiconductor member 126 (the upper end of the insulating layer 127). The height position Z3 corresponds to the height position of the lower end of the insulating members 151 and 152 described below.

[0130] Region R1 is referenced from Fig. 20 and Fig.21The material of the insulating layer SHEB is filled without gaps. That is, no gaps, conductive parts or other insulating parts are provided inside the region R1. In addition, the length of the region R1 in the Z direction (the length from the lower end of the insulating parts 151 and 152 to the lower end of the insulating part SHE) is greater than the length Y of the insulating part SHE in the Y direction. SHE ( Figure 8 ) half.

[0131] In the insulating layer SHEB ( Fig. 20 , Fig.21 ) is formed from a portion of the material, and a region R3 that does not include a portion of the material formed from the insulating layer SHEB is provided. The region R3 is provided at a height position Z1 corresponding to the semiconductor component 126 and its vicinity. Figure 6 to Figure 8 Insulation components 151, 152 are shown.

[0132] [Insulating components 151, 152]

[0133] Figure 8 2 semiconductor column rows SC1 and SC2 are shown adjacent to each other in the Y direction. Figure 3 Two of the plurality of semiconductor column arrays SC described above. Figure 8 The insulating member SHE provided between the two semiconductor column arrays SC1 and SC2, the insulating members 151 arranged along the X direction corresponding to the semiconductor columns 120 included in the semiconductor column array SC1, and the insulating members 152 arranged along the X direction corresponding to the semiconductor columns 120 included in the semiconductor column array SC2 are shown. The insulating members 151 and 152 are provided at the height position Z1 corresponding to the semiconductor component 126 and its vicinity.

[0134] Figure 6 In the cross section shown, the insulating member 151 is surrounded by the insulating member SHE, the contact electrode Ch, and the semiconductor member 126. The insulating member 151 includes, for example, silicon oxide (SiO2). The insulating member 151 is connected to the insulating film 157. The insulating member 151 includes insulating portions 153 and 154.

[0135] The upper end, the lower end, the side surface opposite to the semiconductor column array SC1 in the Y direction, and a portion of the side surface on the semiconductor column array SC1 side in the Y direction (a portion corresponding to a height region from the lower end of the insulating portion 153 to the lower surface of the insulating portion 154) of the insulating portion 153 of the insulating member 151 are in contact with the insulating member SHE and are formed along the insulating member SHE. In addition, a portion of the side surface on the semiconductor column array SC1 side in the Y direction of the insulating portion 153 (a portion corresponding to a height region from the lower end of the contact electrode Ch to the upper end of the insulating portion 153) is in contact with the contact electrode Ch and is formed along the contact electrode Ch.

[0136] Furthermore, a gap V1 is provided at a height position Z1 inside the insulating portion 153 . Figure 6 In the example of FIG. 1 , the height position Z2 corresponding to the lower end of the gap V1 and the height position Z4 corresponding to the upper end of the gap V1 are set above the lower surface of the semiconductor component 126 and below the upper surface of the semiconductor component 126. However, the height position Z2 may be set below the lower surface of the semiconductor component 126. In addition, the height position Z4 may be set above the upper surface of the semiconductor component 126.

[0137] The gap V1 is separated from the contact electrode Ch by a part of the insulating portion 153. The part of the insulating portion 153 disposed above the height position Z4 and the part disposed below the height position Z2 are described by referring to the following. Fig.28 and Fig.29 The material of a part of the insulating component 151A described above is filled without gaps. That is, no gaps, conductive components or other insulating components are provided in these parts. Similarly, the ends of one side and the other side of the insulating portion 153 in the X direction are also filled without gaps by the material of a part of the insulating component 151A described below. That is, no gaps, conductive components or other insulating components are provided in these parts either.

[0138] Figure 6In the example shown in the figure, the height position Z5 corresponding to the upper end of the insulating portion 153 is set above the upper surface of the semiconductor component 126 and below the upper end of the insulating component SHE. However, the height position Z5 may be set below the upper surface of the semiconductor component 126. In addition, the height position Z3 corresponding to the lower end of the insulating portion 153 is set below the lower surface of the semiconductor component 126 and above the lower end of the insulating component SHE. In the example shown in the figure, the height position Z3 is set above the upper surface of the conductive layer 110 located at the top. However, the height position Z3 may be set above the lower surface of the semiconductor component 126 or below the upper surface of the conductive layer 110 located at the top. In addition, in the example shown in the figure, the length from the lower end of the insulating portion 153 to the lower end of the insulating component SHE is greater than the length from the upper end of the insulating portion 153 to the upper end of the insulating component SHE.

[0139] The insulating portion 154 of the insulating member 151 is provided in the conductive region R in contact with the electrode Ch as viewed from the Z direction. Ch2 The upper surface of the insulating portion 154 overlaps the conductive region R of the contact electrode Ch. Ch2 The lower surface of the contact electrode Ch is connected to the conductive region R Ch2 The side surface of the insulating portion 154 in the Y direction is in contact with the semiconductor component 126 and is formed along the semiconductor component 126. The lower surface of the insulating portion 154 is in contact with the insulating member SHE and is formed along the insulating member SHE.

[0140] Figure 6 In the example, the upper surface and the lower surface of the insulating portion 154 are provided between the upper surface and the lower surface of the semiconductor component 126 .

[0141] The length of the insulating component 151 in the Y direction is the maximum in the height range corresponding to the insulating portion 154 (hereinafter referred to as the "first height range"). In addition, the length of the insulating component 151 in the Y direction is smaller than the length of the insulating component 151 in the Y direction in the first height range in the height range corresponding to the upper surface of the insulating portion 154 to the upper end of the insulating component 151 (hereinafter referred to as the "second height range"). For example, the length of the insulating component 151 in the Y direction at the height position Z4 is smaller than the length of the insulating component 151 in the Y direction at the height position Z1. In addition, the length of the insulating component 151 in the Y direction is smaller than the length of the insulating component 151 in the Y direction in the first height range in the height range corresponding to the lower surface of the insulating portion 154 to the lower end of the insulating component 151 (hereinafter referred to as the "third height range"). For example, the length of the insulating component 151 in the Y direction at the height position Z2 is smaller than the length of the insulating component 151 in the Y direction at the height position Z1.

[0142] In the first height range, the length of the insulating component 151 in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed part of the recess 126A. In addition, the length of the insulating component 151 in the Y direction decreases as it moves away from the height position. For example, in the first and second height ranges, the length of the insulating component 151 in the Y direction decreases from the height position toward the top. In addition, in the first and third height ranges, the length of the insulating component 151 in the Y direction decreases from the height position toward the bottom.

[0143] In addition, if Figure 8 As shown, the insulating member 151 expands in the Y direction along the recess 126A. That is, the length of the insulating member 151 in the Y direction is the largest at the position in the X direction corresponding to the most depressed part of the recess 126A. The position in the X direction corresponds to the center position in the X direction of the semiconductor component 126, for example. In addition, the length of the insulating member 151 in the Y direction decreases as it moves away from the position in the X direction. In addition, the two ends of the insulating portion 153 in the X direction are arranged at positions that do not overlap with the contact electrode Ch when viewed from the Z direction.

[0144] Figure 6 In the cross section shown, the cross-sectional area of ​​the insulating member 151 is smaller than the cross-sectional area of ​​the insulating member SHE.

[0145] Figure 7 In the cross section shown, the insulating member 152 is surrounded by the insulating member SHE, the contact electrode Ch, and the semiconductor member 126. The insulating member 152 includes, for example, silicon oxide (SiO2). The insulating member 152 is connected to the insulating film 157. The insulating member 152 includes insulating portions 155 and 156.

[0146] The upper end, the lower end, the side surface opposite to the semiconductor column array SC2 in the Y direction, and a portion of the side surface on the semiconductor column array SC2 side in the Y direction (a portion corresponding to a height region from the lower end of the insulating portion 155 to the lower surface of the insulating portion 156) of the insulating portion 155 of the insulating member 152 are in contact with the insulating member SHE and are formed along the insulating member SHE. In addition, a portion of the side surface on the semiconductor column array SC2 side in the Y direction of the insulating portion 155 (a portion corresponding to a height region from the lower end of the contact electrode Ch to the upper end of the insulating portion 155) is in contact with the contact electrode Ch and is formed along the contact electrode Ch.

[0147] Furthermore, a gap V2 is provided at a height position Z1 inside the insulating portion 155 . Figure 7In the example of FIG. 1 , the height position Z12 corresponding to the lower end of the gap V2 and the height position Z14 corresponding to the upper end of the gap V2 are set above the lower surface of the semiconductor component 126 and below the upper surface of the semiconductor component 126. The height position Z12 may be set below the lower surface of the semiconductor component 126. In addition, the height position Z14 may be set above the upper surface of the semiconductor component 126.

[0148] The gap V2 is separated from the contact electrode Ch by a part of the insulating portion 155. The part of the insulating portion 155 disposed above the height position Z14 and the part disposed below the height position Z12 are described by referring to the following. Fig.28 and Fig.29 The material of a part of the insulating component 151A described above is filled without gaps. That is, no gaps, conductive components or other insulating components are provided in these parts. Similarly, the ends of one side and the other side of the insulating portion 155 in the X direction are also filled without gaps by the material of a part of the insulating component 151A described below. That is, no gaps, conductive components or other insulating components are provided in these parts either.

[0149] Figure 7 In the example shown in the figure, the height position Z15 corresponding to the upper end of the insulating portion 155 is set above the upper surface of the semiconductor component 126 and below the upper end of the insulating component SHE. However, the height position Z15 may be set below the upper surface of the semiconductor component 126. In addition, the height position Z13 corresponding to the lower end of the insulating portion 155 is set below the lower surface of the semiconductor component 126 and above the lower end of the insulating component SHE. In the example shown in the figure, the height position Z13 is set above the upper surface of the conductive layer 110 located at the top. However, the height position Z13 may be set above the lower surface of the semiconductor component 126 or below the upper surface of the conductive layer 110 located at the top. In addition, in the example shown in the figure, the length from the lower end of the insulating portion 155 to the lower end of the insulating component SHE is greater than the length from the upper end of the insulating portion 155 to the upper end of the insulating component SHE.

[0150] The insulating portion 156 of the insulating member 152 is provided in the conductive region R in contact with the electrode Ch as viewed from the Z direction. Ch2 The upper surface of the insulating portion 156 overlaps the conductive region R of the contact electrode Ch. Ch2 The lower surface of the contact electrode Ch is connected to the conductive region R Ch2 The side surface of the insulating portion 156 in the Y direction is in contact with the semiconductor component 126 and is formed along the semiconductor component 126. The lower surface of the insulating portion 156 is in contact with the insulating component SHE and is formed along the insulating component SHE.

[0151] Figure 7 In the example, the upper surface and the lower surface of the insulating portion 156 are provided between the upper surface and the lower surface of the semiconductor component 126 .

[0152] Figure 7 In the cross section shown, the cross-sectional area of ​​the insulating member 152 is smaller than the cross-sectional area of ​​the insulating member SHE.

[0153] The length of the insulating component 152 in the Y direction is the maximum in the height range corresponding to the insulating portion 156 (hereinafter referred to as the "4th height range"). In addition, the length of the insulating component 152 in the Y direction is smaller than the length of the insulating component 152 in the Y direction in the 4th height range in the height range corresponding to the upper surface of the insulating portion 156 to the upper end of the insulating component 152 (hereinafter referred to as the "5th height range"). For example, the length of the insulating component 152 in the Y direction at the height position Z14 is smaller than the length of the insulating component 152 in the Y direction at the height position Z1. In addition, the length of the insulating component 152 in the Y direction is smaller than the length of the insulating component 152 in the Y direction in the 4th height range in the height range corresponding to the lower surface of the insulating portion 156 to the lower end of the insulating component 152 (hereinafter referred to as the "6th height range"). For example, the length of the insulating component 152 in the Y direction at the height position Z12 is smaller than the length of the insulating component 152 in the Y direction at the height position Z1.

[0154] In the fourth height range, the length of the insulating member 152 in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed portion of the recess 126A. In addition, the length of the insulating member 152 in the Y direction decreases as it moves away from the height position. For example, in the fourth and fifth height ranges, the length of the insulating member 152 in the Y direction decreases from the height position toward the upper side. In addition, in the fourth and sixth height ranges, the length of the insulating member 152 in the Y direction decreases from the height position toward the lower side.

[0155] In addition, if Figure 8 As shown in FIG. 1 , the insulating member 152 is widened in the Y direction along the recess 126A. That is, the length of the insulating member 152 in the Y direction is the largest at a position in the X direction corresponding to the most depressed portion of the recess 126A. The position in the X direction corresponds to, for example, the center position in the X direction of the semiconductor component 126. In addition, the length of the insulating member 152 in the Y direction decreases as it moves away from the position in the X direction. In addition, the two ends of the insulating member 152 in the X direction are arranged at positions that do not overlap with the contact electrode Ch when viewed from the Z direction.

[0156] Figure 8In the cross section shown, the insulating portions 153 of the plurality of insulating parts 151 and the insulating portions 155 of the plurality of insulating parts 152 are alternately arranged along the X direction near the center position of the insulating part SHE in the Y direction. In the example shown in the figure, a part of the plurality of insulating parts 151 is connected to any one of the plurality of insulating parts 152. The gap V1 in the insulating part 151 and the gap V2 in the insulating part 152 are separated by the connecting part of the insulating parts 151 and 152. In addition, a part of the plurality of insulating parts 151 is separated from any one of the plurality of insulating parts 152. The gap V1 in the insulating part 151 and the gap V2 in the insulating part 152 are separated by a part of the insulating parts 151 and 152 and a part of the insulating part SHE.

[0157] In addition, as described below, in reference Figure 20 to Figure 27 After forming the insulating member SHE in the process described above, Figure 28 to Figure 30 The insulating members 151 and 152 are formed in the process described below. Therefore, the insulating members 151 and 152 have an etching rate different from that of the insulating member SHE.

[0158] [Inter-finger structure ST]

[0159] Interdigital structure ST, for example Figure 3 and Figure 4 As shown, it includes a conductive layer 141 extending in the X direction and the Z direction, and an insulating layer 142 such as silicon oxide (SiO2) provided on the side of the conductive layer 141 in the Y direction. The lower end of the conductive layer 141 is connected to the conductive layer 112. In addition, the upper end of the conductive layer 141 is located above the upper surface of the semiconductor component 126 and below the lower surface of the insulating layer 103. The conductive layer 141 may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 141 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 141, for example, serves as a source line SL ( Figure 1 ) part of the function.

[0160] [Bit line BL]

[0161] The bit line BL Figure 3 As shown, the bit lines BL extend in the Y direction and are arranged in the X direction. The pitch of the bit lines BL in the X direction is half of the pitch of the semiconductor pillars 120 in the semiconductor pillar array SC in the X direction. The bit lines BL may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The contact electrode Vy is disposed at a position where the bit line BL overlaps with the contact electrode Ch when viewed from the Z direction.

[0162] [Manufacturing method]

[0163] Next, refer to Figures 9 to 30 A method for manufacturing the semiconductor memory device according to the first embodiment will be described. Figures 9 to 30 It is a schematic cross-sectional view for explaining the manufacturing method. Figures 9 to 17 Representation and Figure 4 The corresponding cross section. Fig.18 , Fig. 20 , Fig.24 , Fig.26 and Fig.28 Representation and Figure 8 The corresponding cross section. Fig.19 , Figure 21 to Figure 23 , Fig.25 , Fig. 27 , Fig.29 and Fig.30 Representation and Figure 6 The corresponding cross section.

[0164] When manufacturing the memory grain MD of this embodiment, for example Fig. 9 As shown, an insulating layer 101 is formed on a semiconductor substrate (not shown). Next, a semiconductor layer 112A such as silicon, a sacrificial layer 112B such as silicon oxide, a sacrificial layer 112C such as silicon, a sacrificial layer 112D such as silicon oxide, and a semiconductor layer 112E such as silicon are formed on the insulating layer 101. In addition, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed. In addition, a portion of the insulating layer 102 is formed. This process is performed by a method such as CVD (Chemical Vapor Deposition).

[0165] Next, for example Fig.10 As shown, a memory hole MH is formed at a position corresponding to the semiconductor pillar 120. The memory hole MH extends in the Z direction, penetrates the insulating layer 102, the insulating layer 101, the sacrificial layer 110A, the semiconductor layer 112E, the sacrificial layer 112D, the sacrificial layer 112C, and the sacrificial layer 112B, and exposes the upper surface of the semiconductor layer 112A. For example, this process is performed by a method such as RIE (Reactive Ion Etching).

[0166] Next, for example Fig.11 As shown, a gate insulating film 130, a semiconductor pillar 120, an insulating layer 127, and a semiconductor component 126 are formed inside the memory hole MH. This process is performed by, for example, CVD or the like.

[0167] Next, for example Fig.12As shown in FIG. 1 , a portion of the insulating layer 102 is formed by a method such as CVD. In addition, a groove STA is formed at a position corresponding to the inter-finger structure ST. The groove STA extends in the Z direction and the X direction, and separates the insulating layer 102, the insulating layer 101 and the sacrificial layer 110A, the semiconductor layer 112E and the sacrificial layer 112D in the Y direction, so that the upper surface of the sacrificial layer 112C is exposed. For example, this process is performed by a method such as RIE.

[0168] Next, for example Fig.13 As shown, the sacrificial layer 112B, the sacrificial layer 112C, the sacrificial layer 112D, and a portion of the gate insulating film 130 are removed to form the conductive layer 112. For example, the sacrificial layer 112B, the sacrificial layer 112C, the sacrificial layer 112D, and a portion of the gate insulating film 130 are removed by wet etching or the like. For example, the conductive layer 112 is formed by epitaxial growth or the like.

[0169] Next, for example Fig.14 As shown in FIG. 1 , the sacrificial layer 110A is removed through the groove STA to form a plurality of spaces 110B. Thus, a hollow structure is formed, which includes a plurality of insulating layers 101 and 102 arranged in the Z direction, and a structure (semiconductor pillar 120, gate insulating film 130, semiconductor component 126, and insulating layer 127) in the memory hole MH supporting them. This process is performed, for example, by wet etching or the like.

[0170] Next, for example Fig.15 As shown in FIG. 1 , a conductive layer 110 is formed in the space 110B. This process is performed by, for example, CVD or the like.

[0171] Next, for example Fig.16 As shown in FIG. 1 , the inter-finger structure ST is formed in the groove STA. This process is performed by, for example, CVD or RIE.

[0172] Next, for example Fig.17 As shown, a portion of the insulating layer 102 is formed by a method such as CVD.

[0173] Next, for example Fig.18 and Fig.19 As shown, a groove SHEA is formed at a position corresponding to the insulating member SHE. The groove SHEA extends in the Z direction and the X direction, and separates the insulating layer 102, the conductive layer 110 (SGDT), the conductive layer 110 (SGD), and the insulating layer 101 provided therebetween in the Y direction. This process is performed, for example, by a method such as RIE.

[0174] In this process, the semiconductor pillar 120 is removed. O Thus, the semiconductor column 120 OAreas 124 and 125 ( Figure 4 ) Sometimes, as in reference Figure 3 As described above, the shape is an arc when viewed from the Z direction.

[0175] In addition, the semiconductor component 126 is removed in this process. O Here, Fig.18 and Fig.19 In the example of FIG. 1 , the semiconductor component 126 is removed faster than the insulating layers 102 and 127. O Therefore, a recess 126A is formed on the exposed surface of the semiconductor component 126 toward the groove SHEA. O Sometimes as reference Figure 8 As described above, the shape is a partially missing columnar shape when viewed from the Z direction.

[0176] Next, for example Fig. 20 and Fig.21 As shown in FIG. 1 , an insulating layer SHEB is formed on the upper surface of the insulating layer 102 and inside the groove SHEA. This process is performed by, for example, CVD or the like.

[0177] In this process, the insulating layer SHEB is formed on the inner side surface and bottom surface of the groove SHEA in the Y direction and the upper surface of the insulating layer 102. Inside the groove SHEA, the insulating layer SHEB grows mainly from the inner side surface of the groove SHEA in the Y direction.

[0178] Here, in the region of the groove SHEA below the lower surface of the semiconductor component 126 (the upper end of the insulating layer 127), the inner side surface in the Y direction is formed substantially linearly. Thus, the region of the groove SHEA below the specific height position is filled without gaps mainly by the insulating layer SHEB grown from the inner side surface of the groove SHEA in the Y direction. Thus, no gap or the like is formed in the region of the groove SHEA below the specific height position.

[0179] On the other hand, in the height region of the groove SHEA corresponding to the semiconductor component 126, the inner side surface on one side in the Y direction is realized by the recess 126A. Therefore, at the height position of the groove SHEA corresponding to the semiconductor component 126 and the vicinity thereof, the insulating layer SHEB grows from the recess 126A. As a result, at the height position of the groove SHEA corresponding to the semiconductor component 126 and the vicinity thereof, a plurality of voids V1A ( Fig. 20 , Fig.21 ), and a plurality of gaps V2A ( Fig. 20 ).

[0180] In addition, the length of the gaps V1A and V2A in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed part of the recessed portion 126A. In addition, the length of the gaps V1A and V2A in the Y direction decreases as they are farther away from the height position. For example, the length of the gaps V1A and V2A in the Y direction gradually decreases from the height position upward. In addition, the length of the gaps V1A and V2A in the Y direction gradually decreases from the height position downward.

[0181] The length of the gaps V1A and V2A in the Y direction is the largest at the position in the X direction corresponding to the most depressed part of the recess 126A. The position in the X direction corresponds to, for example, the center position in the X direction of the semiconductor component 126. The length of the gaps V1A and V2A in the Y direction decreases as they are farther from the position in the X direction.

[0182] Next, for example Fig. 22 As shown, a portion of the insulating layer SHEB is removed. In this process, a portion of the insulating layer SHEB formed on the upper surface of the insulating layer 102 is removed. In the example shown in the figure, the upper end of the gap V1A is located below the upper surface of the insulating layer 102, and the gap V1A is not connected to the outside. For example, this process is performed by a method such as RIE. In addition, this process can also be omitted.

[0183] Next, for example Fig.23 As shown, the insulating layers 103 and 104 are formed by a method such as CVD.

[0184] Next, for example Fig.24 and Fig.25 As shown, a contact hole ChA is formed at a position corresponding to the contact electrode Ch. The contact hole ChA extends in the Z direction, penetrates the insulating layers 102, 103, 104 and a portion of the insulating layer SHEB to expose the upper surface of the semiconductor component 126 and a portion of the recess 126A. This process is performed by, for example, RIE or the like.

[0185] in addition, Fig.24 and Fig.25 In the example, the plurality of contact holes ChA communicate with the plurality of voids V1A.

[0186] Next, for example Fig.26 and Fig. 27 As shown, the insulating layer such as silicon oxide is removed by wet etching or the like. Fig.24 and Fig.25 In the above-described process, the residue generated when the contact hole ChA is formed is removed, and the surface of the semiconductor component 126 is cleaned. Alternatively, this process may be omitted.

[0187] Fig.26 and Fig. 27In the example of FIG. 1 , a portion of the insulating layer SHEB is removed, and the gap V1A is extended to the same level as the reference Figure 6 The insulating member SHE is formed. Fig.26 In the example, a plurality of contact holes ChA are connected to a plurality of voids V2A, and a portion of voids V1A is connected to voids V2A. Thus, a path is formed from one contact hole ChA to another contact hole ChA via voids V1A and V2A. Fig.26 In the example, the gaps V1A and a portion of the gaps V2A arranged along the X direction are separated from each other in the Y direction by the insulating layer SHEB. In these portions, sometimes due to the influence of the gaps extending along the Y direction in the insulating layer SHEB, a path is formed from one contact hole ChA through the gaps V1A and V2A to reach another contact hole ChA.

[0188] also, Fig.26 and Fig. 27 In the example, a portion of the insulating layer SHEB is etched and removed isotropically. As a result, the length of the gaps V1A and V2A in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed portion of the recess 126A. In addition, the length of the gaps V1A and V2A in the Y direction is smaller as it is farther away from the height position. Similarly, the length of the gaps V1A and V2A in the Y direction is the largest at the position in the X direction corresponding to the most depressed portion of the recess 126A. In addition, the length of the gaps V1A and V2A in the Y direction is smaller as it is farther away from the position in the X direction.

[0189] Here, when focusing on the voids V1A that are connected to the voids V2A among the plurality of voids V1A, the ends of these voids V1A in the X direction are connected to the ends of the voids V2A in the X direction. The lengths of the voids V1A and V2A in the Y direction decrease as they are farther away from the position in the X direction corresponding to the most depressed part of the recess 126A, and the lengths of the connecting portions of the voids V1A and V2A in the Y direction are relatively small. The lengths of the connecting portions of the voids V1A and V2A in the Y direction are at least smaller than the maximum lengths of the voids V1A and V2A in the Y direction.

[0190] Next, for example Fig.28 and Fig.29 As shown in FIG. 1 , an insulating member 151A is formed inside the contact hole ChA and the voids V1A and V2A. This process is performed by, for example, CVD or the like.

[0191] Here, as reference Fig.26As described above, the length of the connection portion of the voids V1A and V2A in the Y direction is relatively small. Therefore, when the insulating member 151A is formed, the connection portion of the voids V1A and V2A is filled and blocked by the insulating member 151A without any gap at a relatively early stage, and the voids V1A and the voids V2A are disconnected. Thus, the plurality of voids V1 and the plurality of voids V2 are separated.

[0192] In addition, as referenced Fig. 27 As described above, the Y-direction length of the gaps V1A and V2A decreases as they are farther away from the height position in the Z-direction corresponding to the most depressed portion of the recess 126A. Therefore, when the insulating member 151A is formed, the relatively lower portions of the gaps V1A and V2A are filled with no gaps by the insulating member 151A at a relatively early stage.

[0193] When the path from the contact hole ChA to the void V1A is blocked before the void V1A is completely filled by the insulating member 151A, the void V1 is formed inside the void V1A as shown in the figure. Similarly, when the path from the contact hole ChA to the void V2A is blocked before the void V2A is completely filled by the insulating member 151A, the void V2 is formed inside the void V2A as shown in the figure.

[0194] in addition, Fig.28 and Fig.29 In the example of , substantially all regions of the gaps V1A and V2A (regions other than the gaps V1 and V2) are buried by the insulating member 151A. In addition, the region of the contact hole ChA disposed below the upper surface of the semiconductor component 126 (hereinafter referred to as the "lower region") is buried by the insulating member 151A. On the other hand, the region of the contact hole ChA disposed above the upper surface of the semiconductor component 126 (hereinafter referred to as the "upper region") is buried by the insulating member 151A.

[0195] Next, for example Fig.30 As shown in FIG. 1 , a portion of the insulating member 151A is removed to expose the semiconductor member 126 inside the contact hole ChA. In this step, a portion of the insulating member 151A is removed by, for example, RIE or the like. In addition, a residue generated when a portion of the insulating member 151A is removed using dilute hydrofluoric acid (DHF) or the like, and the surface of the semiconductor member 126 is cleaned.

[0196] in addition, Fig.30 In the example of FIG. 1 , a portion of the insulating member 151A formed on the upper surface of the insulating layer 104 is removed. In addition, a portion of the insulating member 151A provided on the inner peripheral surface of the contact hole ChA remains as the insulating film 157 .

[0197] In the present embodiment, the portion of the insulating member 151A provided in the gap V1A serves as the insulating portion 153 ( Figure 8 ). In addition, the portion of the insulating member 151A provided in the gap V2A becomes the insulating portion 155 ( Figure 8 ). In addition, the portion of the insulating member 151A provided in the region below the contact hole ChA becomes the insulating portion 154 ( Figure 8 ), or the insulating portion 156 of the insulating member 152 ( Figure 8 ).

[0198] Thereafter, a contact electrode Ch is formed inside the contact hole ChA by using a method such as CVD to form a reference electrode. Figure 6 and Figure 7 At this time, the portion formed in the upper region of the contact hole ChA becomes a reference Figure 6 The conductive region R described in the above Ch1 The portion formed in the lower region of the contact hole ChA becomes a reference Figure 6 The conductive region R described in the above Ch2 In addition, a reference is formed by forming a contact electrode Vy and a bit line BL. Figure 4 The structure described.

[0199] [Effects of the First Embodiment]

[0200] Reference Fig. 20 and Fig.21 In the example described, a plurality of voids V1A corresponding to the semiconductor components 126 in the semiconductor column array SC1 and a plurality of voids V2A corresponding to the semiconductor components 126 in the semiconductor column array SC2 are formed inside the insulating layer SHEB. Figure 24 to Figure 27 In the described process, the contact hole ChA is connected. Fig.26 For example, the gap V1A and the gap V2A may communicate with each other.

[0201] Here, for example, when referring to Fig.26 and Fig. 27 When the contact electrode Ch is formed in the contact hole ChA soon after the described process, there is a concern that the plurality of contact electrodes Ch may be short-circuited via the gaps V1A and V2A. Even when the gaps V1A and V2A are not directly connected, it is undesirable for the contact electrodes Ch to be formed close to each other in the gaps V1A and V2A connected via a seam in terms of withstand voltage.

[0202] In addition, from the viewpoint of withstand voltage, it is preferable to ensure that the distance between the contact electrode Ch and the drain side selection gate line SGDT is greater than a certain distance. In particular, when the lower ends of the gaps V1A and V2A are arranged below the upper surface of the uppermost conductive layer 110, the contact electrode Ch is close to the uppermost conductive layer 110.

[0203] Therefore, when manufacturing the semiconductor memory device according to the first embodiment, as shown in FIG. Figure 28 to Figure 30 As described above, the insulating members 151 and 152 are formed inside the gaps V1A and V2A.

[0204] Here, as described above, the length of the connection portion of the voids V1A and V2A in the Y direction is relatively small. Therefore, according to this method, the connection portion of the voids V1A and V2A can be filled and blocked by the insulating member 151A, and the voids V1A and V2A can be disconnected to suppress the occurrence of a short circuit between the contact electrodes Ch. Similarly, even when the voids V1A and V2A are not connected, the insulating member 151A blocks the path extending in the Y direction between the voids V1A and V2A through the slit, thereby improving the withstand voltage between the contact electrodes Ch.

[0205] In addition, the length of the gaps V1A and V2A in the Y direction decreases as they are farther away from the height position in the Z direction corresponding to the most depressed portion of the recess 126A. Therefore, according to this method, by filling the relatively lower portion of the gaps V1A and V2A (for example, the portion formed by widening the gaps V1A and V2A in the Y direction and lower than the height position corresponding to the semiconductor component 126 and its vicinity) with the insulating member 151A, the distance between the lower end of the contact electrode Ch and the conductive layer 110 is suppressed from becoming less than a fixed distance, and the distance between the contact electrode Ch and the drain-side selection gate line SGDT is ensured to be greater than a fixed distance.

[0206] In particular, in the present embodiment, the gaps V1 and V2 are separated from the contact electrode Ch by a part of the insulating portion 153 and 155. According to this configuration, the conductive member constituting the contact electrode Ch is not formed inside the gaps V1 and V2, so that the withstand voltage between the contact electrodes Ch can be better ensured, and the withstand voltage between the contact electrode Ch and the drain side selection gate line SGDT can also be better ensured.

[0207] [Second embodiment]

[0208] In the first embodiment, referring to Fig.30 In the described process, the insulating member 151A ( Fig.29 ) remains in the lower region of the contact hole ChA and becomes the insulating portion 154 ( Figure 8 ), or the insulating portion 156 of the insulating member 152 ( Figure 8 However, this configuration is merely an example, and the insulating member 151A ( Fig.29 ) may not remain in the area below the contact hole ChA. This example will be described below as a second embodiment.

[0209] Fig.31 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a second embodiment. Fig.32 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.31 Yes Fig.32 The structure shown is a schematic cross-sectional view cut along line DD' and observed along the arrow direction. Fig.32 Representation and Fig.31 The XY cross section at the height position corresponding to the chain line F is shown. Hereinafter, the same reference numerals are attached to the same parts as those in the first embodiment, and the description thereof will be omitted.

[0210] The semiconductor memory device of the second embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. In the second embodiment, the contact electrode Ch O The conductive area R Ch2 The lower surface of the insulating member SHE is in contact with the insulating member SHE. In addition, the semiconductor memory device according to the second embodiment includes insulating members 251 and 252 instead of the insulating members 151 and 152.

[0211] The insulating member 251 is basically configured in the same manner as the insulating member 151. However, the insulating member 251 is configured in the same manner as the insulating portion 153, and does not have a portion corresponding to the insulating portion 154. The insulating member 251 is surrounded by the insulating member SHE and the contact electrode Ch.

[0212] The length of the insulating component 251 in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed part of the recess 126A. In addition, the length of the insulating component 251 in the Y direction decreases as it moves away from the height position. For example, the length of the insulating component 251 in the Y direction gradually decreases from the height position upward. For example, the length of the insulating component 251 in the Y direction at the height position Z4 is smaller than the length of the insulating component 251 in the Y direction at the height position Z1. In addition, the length of the insulating component 251 gradually decreases from the height position downward. For example, the length of the insulating component 251 in the Y direction at the height position Z2 is smaller than the length of the insulating component 251 in the Y direction at the height position Z1.

[0213] In addition, if Fig.32 As shown, the insulating member 251 expands in the Y direction along the recess 126A when viewed from the Z direction.

[0214] The insulating member 252 is basically configured in the same manner as the insulating member 152. However, the insulating member 252 is configured in the same manner as the insulating portion 155, and does not have a portion corresponding to the insulating portion 156. The insulating member 252 is surrounded by the insulating member SHE and the contact electrode Ch.

[0215] Although not shown in the figure, the length of the insulating member 252 in the Y direction is the largest at the height position in the Z direction corresponding to the most depressed part of the recess 126A. In addition, the length of the insulating member 252 in the Y direction decreases as it moves away from the height position. For example, the length of the insulating member 252 in the Y direction gradually decreases upward from the height position. For example, the height position Z14 (see Figure 7 ) in the Y direction, is smaller than the height position Z1 of the insulating member 251 (refer to Figure 7 ) in the Y direction. In addition, the length of the insulating member 252 in the Y direction gradually decreases from this height position downward. For example, the height position Z12 of the insulating member 251 (refer to Figure 7 ) in the Y direction, is smaller than the height position Z1 of the insulating member 251 (refer to Figure 7 ) in the Y direction.

[0216] In addition, if Fig.32 As shown, the insulating member 252 expands in the Y direction along the recess 126A when viewed from the Z direction.

[0217] Next, refer to Figure 33 to Figure 36 A method for manufacturing the semiconductor memory device according to the second embodiment will be described. Figure 33 to Figure 36 It is a schematic cross-sectional view for explaining the manufacturing method. Figure 33 to Figure 36 Representation and Fig.31 The corresponding cross section.

[0218] When manufacturing the semiconductor memory device of the second embodiment, the method for manufacturing the semiconductor memory device of the first embodiment is performed with reference to Fig.23 The process described above is completed.

[0219] Next, if Fig.33 As shown in FIG. 1 , a contact hole ChA is formed at a position corresponding to the contact electrode Ch. Fig.24 and Fig.25 This process is performed in the same manner as the described process.

[0220] Next, if Fig.34 As shown, the insulating layer such as silicon oxide is removed by wet etching or the like. Fig.26 and Fig. 27 This process is performed in the same manner as the described process.

[0221] Next, if Fig.35 As shown in FIG. 1 , an insulating member 151A is formed inside the contact hole ChA and the gaps V1A and V2A. Fig.28 and Fig.29 This process is performed in the same manner as the described process.

[0222] Next, for example Fig.36 As shown in FIG. 1 , a portion of the insulating member 151A is removed to expose the semiconductor member 126 inside the contact hole ChA. Fig.30 This process is performed in the same manner as the described process.

[0223] However, in this embodiment, the insulating member 151A provided in the contact hole ChA ( Fig.26 ), the insulating member SHE is exposed at the bottom surface of the contact hole ChA. Thus, the insulating members 251 and 252 are formed.

[0224] Thereafter, the steps after forming the contact electrode Ch in the method for manufacturing the semiconductor memory device according to the first embodiment are performed.

[0225] The semiconductor memory device according to the second embodiment can also achieve the same effects as those of the semiconductor memory device according to the first embodiment.

[0226] [Third Embodiment]

[0227] In the second embodiment, referring to Fig.36 In the described process, a part of the insulating member 151A remains on the inner peripheral surface of the contact hole ChA to form the insulating film 157. However, this configuration is only an example, and the insulating member 151A ( Fig.35 ) may not remain on the inner peripheral surface of the contact hole ChA. This example will be described below as a third embodiment.

[0228] Fig.37 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to Embodiment 3. Hereinafter, the same reference numerals are attached to the same parts as those of Embodiment 2, and the description thereof will be omitted.

[0229] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to the third embodiment does not include the insulating film 157 .

[0230] The semiconductor memory device of the third embodiment is manufactured in the same manner as the semiconductor memory device of the second embodiment. Fig.36In a corresponding step, a portion of the insulating member 151A provided on the inner peripheral surface of the contact hole ChA is removed.

[0231] The semiconductor memory device according to the third embodiment can also achieve the same effects as those of the semiconductor memory device according to the second embodiment.

[0232] In addition, the semiconductor memory device of the first embodiment may not include the insulating film 157 similarly to the semiconductor memory device of the third embodiment.

[0233] [Fourth embodiment]

[0234] In the third embodiment, Fig.36 In the corresponding process, the gap V1 is not connected to the contact hole ChA. Fig.36 In a corresponding step, the void V1 and the contact hole ChA may also communicate with each other. This example will be described below as a fourth embodiment.

[0235] Fig.38 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment. Fig.39 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.38 Yes Fig.39 The structure shown is a schematic cross-sectional view cut along line DD' and observed along the arrow direction. Fig.39 Representation and Fig.38 The XY cross section at the height position corresponding to the chain line F is shown. Hereinafter, the same reference numerals are attached to the same parts as those in the third embodiment, and the description thereof will be omitted.

[0236] The semiconductor memory device of the fourth embodiment is basically configured in the same manner as the semiconductor memory device of the third embodiment. However, the semiconductor memory device of the fourth embodiment includes a conductive member ChB instead of the voids V1 and V2. That is, the conductive member ChB is embedded in the voids V1 and V2.

[0237] The conductive component ChB includes the same material as the contact electrode Ch. For example, the conductive component ChB may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive component ChB is disposed inside the insulating components 251 and 252 and is connected to the corresponding contact electrodes Ch, respectively. For example, the barrier conductive film in the conductive component ChB is connected to the barrier conductive film in the contact electrode Ch. Similarly, the metal film in the conductive component ChB is connected to the metal film in the contact electrode Ch.

[0238] Next, refer to Fig.40 and Fig.41 A method for manufacturing the semiconductor memory device according to the fourth embodiment will be described. Fig.40 and Fig.41 It is a schematic cross-sectional view for explaining the manufacturing method. Fig.40 and Fig.41 Representation and Fig.38 The corresponding cross section.

[0239] The semiconductor memory device of the fourth embodiment is manufactured in the same manner as the semiconductor memory device of the third embodiment. Fig.35 In the corresponding process, Fig.40 As shown in FIG. 1 , the gap V1 extends to the vicinity of the contact hole ChA. Fig.36 In the corresponding process, Fig.41 As shown, the insulating member 151A provided on the inner peripheral surface of the contact hole ChA is partially removed, and the void V1 communicates with the contact hole ChA. When the contact electrode Ch is formed, the metal or the like constituting the contact electrode Ch enters the interior of the voids V1 and V2.

[0240] In the fourth embodiment, referring to Fig.41 In the described process, the gap V1 is connected to the contact hole ChA. Therefore, when the contact electrode Ch is formed, the metal and the like constituting the contact electrode Ch enter the gaps V1 and V2. Fig.28 As described above, if the insulating member 151A fills at least a portion of the path between the two contact holes ChA connected via the gaps V1A and V2A to block the path, thereby disconnecting the two contact holes ChA, even if the metal constituting the contact electrode Ch enters the gaps V1 and V2, it is possible to suppress the occurrence of a short circuit between the contact electrodes Ch. In addition, by filling the relatively lower portion of the gaps V1A and V2A (for example, the portion below the height position corresponding to the semiconductor component 126 and the vicinity thereof formed by widening the gaps V1A and V2A in the Y direction) with the insulating member 151A, the distance between the contact electrode Ch and the drain side selection gate line SGDT can be ensured compared to the case where the insulating member 151A is not formed.

[0241] In addition, the semiconductor memory devices of the first and second embodiments may include a conductive member ChB instead of the gaps V1 and V2 , similar to the semiconductor memory device of the fourth embodiment.

[0242] [Fifth embodiment]

[0243] In the first embodiment, the gaps V1 and V2 are provided inside the insulating members 151 and 152, respectively. However, the gaps V1 and V2 may not be provided inside the insulating members 151 and 152. This example will be described below as a fifth embodiment.

[0244] Fig.42 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment. Fig.43 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.42 Yes Fig.43 The structure shown is a schematic cross-sectional view cut along line DD' and observed along the arrow direction. Fig.43 Representation and Fig.42 The XY cross section at the height position corresponding to the chain line F is shown. Hereinafter, the same reference numerals are attached to the same parts as those in the first embodiment, and the description thereof will be omitted.

[0245] The semiconductor memory device of the fifth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment, except that the semiconductor memory device of the fifth embodiment includes insulating members 551 and 552 instead of insulating members 151 and 152 .

[0246] The insulating member 551 is basically configured in the same manner as the insulating member 151. However, the insulating member 551 includes an insulating portion 553 instead of the insulating portion 153. The insulating portion 553 is basically configured in the same manner as the insulating portion 153. Here, the void V1 is not provided inside the insulating portion 553.

[0247] The insulating member 552 is basically configured in the same manner as the insulating member 152. However, the insulating member 552 includes an insulating portion 555 instead of the insulating portion 155. The insulating portion 555 is basically configured in the same manner as the insulating portion 155. Here, the void V2 is not provided inside the insulating portion 555.

[0248] The semiconductor memory device of the fifth embodiment is manufactured in the same manner as the semiconductor memory device of the first embodiment. Fig.28 and Fig.29 In the described process, the interior of the voids V1A and V2A is completely filled with the insulating member 151A, and the voids V1 and V2 are not formed inside the insulating members 551 and 552 .

[0249] The semiconductor memory device according to the fifth embodiment can also achieve the same effects as those of the semiconductor memory device according to the first embodiment.

[0250] In addition, similar to the insulating members 551 and 552 of the fifth embodiment, the gaps V1 and V2 may not be provided inside the insulating members 251 and 252 of the second and third embodiments.

[0251] [Sixth embodiment]

[0252] As described above, the semiconductor memory device of the first embodiment may not have the insulating film 157, similarly to the semiconductor memory device of the third embodiment. In addition, as exemplified as the fifth embodiment, in the semiconductor memory device of the first embodiment, the gaps V1 and V2 may not be provided inside the insulating members 151 and 152. This example will be described below as the sixth embodiment.

[0253] Fig.44 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to Embodiment 6. Hereinafter, the same reference numerals are attached to the same parts as those in Embodiment 5, and the description thereof will be omitted.

[0254] The semiconductor memory device of the sixth embodiment is basically configured in the same manner as the semiconductor memory device of the fifth embodiment. However, the semiconductor memory device of the sixth embodiment does not necessarily have to include the insulating film 157 .

[0255] The semiconductor memory device of the sixth embodiment is manufactured in the same manner as the semiconductor memory device of the fifth embodiment. Fig.30 In a corresponding step, a portion of the insulating member 151A provided on the inner peripheral surface of the contact hole ChA is removed.

[0256] The semiconductor memory device according to the sixth embodiment can also achieve the same effects as those of the semiconductor memory device according to the first embodiment.

[0257] [Seventh embodiment]

[0258] In the first embodiment, the insulating components 151 and 152 include silicon oxide. However, the insulating components 151 and 152 may be formed of materials including other elements in addition to silicon (Si) and oxygen (O), such as silicon oxynitride (SiON) and carbon-containing silicon oxide (SiOC). In addition, they may be formed of materials including elements other than silicon and oxygen, such as silicon nitride (SiN). In particular, silicon oxynitride, carbon-containing silicon oxide, silicon nitride, etc. have higher tolerance to dilute hydrofluoric acid (DHF) than silicon oxide. Therefore, in reference to Fig.30 In the described process, it is possible to suppress excessive removal of the insulating member 151A.

[0259] In addition, the insulating members 151 and 152 may also include a plurality of materials. For example, they may include an insulating region including one of silicon oxide, silicon oxynitride, carbon-containing silicon oxide, silicon nitride, or other materials, and an insulating region including another of these materials. This example will be described below as the seventh embodiment.

[0260] Fig.45 This is a schematic cross-sectional view showing a partial structure of a semiconductor storage device according to a seventh embodiment. Fig.46 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.45 Yes Fig.46 The structure shown is a schematic cross-sectional view cut along line DD' and observed along the arrow direction. Fig.46 Representation and Fig.45 The XY cross section at the height position corresponding to the chain line F is shown. Hereinafter, the same reference numerals are attached to the same parts as those in the second embodiment, and the description thereof will be omitted.

[0261] The semiconductor memory device of the seventh embodiment is basically configured in the same manner as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of the seventh embodiment includes insulating members 751 and 752 instead of the insulating members 251 and 252. In addition, the semiconductor memory device of the seventh embodiment includes an insulating film 760 instead of the insulating film 157.

[0262] The insulating member 751 includes an insulating region 754 and an insulating region 755 provided inside the insulating region 754. The insulating region 754 is configured in a manner substantially similar to that of the insulating member 251. However, the insulating region 754 is not in contact with the contact electrode Ch. The insulating region 754 includes silicon oxide. The insulating region 755 is in contact with the contact electrode Ch. A gap V1 is provided inside the insulating region 755. The insulating region 755 includes a material having a higher tolerance to dilute hydrofluoric acid than silicon oxide, such as silicon oxynitride, carbon-containing silicon oxide, or silicon nitride.

[0263] The insulating member 752 includes an insulating region 757 and an insulating region 758 disposed inside the insulating region 757. The insulating region 757 is configured in substantially the same manner as the insulating member 252. The insulating region 757 is not in contact with the contact electrode Ch. The insulating region 757 includes silicon oxide. The insulating region 758 is in contact with the contact electrode Ch. A gap V2 is provided inside the insulating region 758. The insulating region 758 includes a material having a higher tolerance to dilute hydrofluoric acid than silicon oxide, such as silicon oxynitride, carbon-containing silicon oxide, or silicon nitride.

[0264] The insulating film 760 is basically configured in the same manner as the insulating film 157. However, the insulating film 760 includes an insulating region 761 extending in the Z direction along the outer peripheral surface of the contact electrode Ch, and an insulating region 762 extending in the Z direction along the outer peripheral surface of the insulating region 761. The lower end of the insulating region 761 is connected to the insulating region 755 or the insulating region 758. The insulating region 761 contains a material having a higher tolerance to dilute hydrofluoric acid than silicon oxide, such as silicon nitride oxide, carbon-containing silicon oxide, or silicon nitride. The lower end of the insulating region 762 is connected to the insulating region 754 or the insulating region 757. The insulating region 762 contains silicon oxide.

[0265] Next, refer to Figures 47 to 50 A method for manufacturing the semiconductor storage device according to the seventh embodiment will be described. Figures 47 to 50 It is a schematic cross-sectional view for explaining the manufacturing method. Figures 47 to 50 Representation and Fig.45 The corresponding cross section.

[0266] The semiconductor memory device of the seventh embodiment is manufactured basically in the same manner as the semiconductor memory device of the first embodiment.

[0267] However, when manufacturing the semiconductor storage device of the seventh embodiment, referring to Fig.28 and Fig.29 In the described process, Fig.47 As shown, an insulating member 754A is formed inside the contact hole ChA and the voids V1A and V2A. This process is performed by, for example, CVD or the like.

[0268] Next, if Fig.48 As shown in FIG. 1 , a portion of the insulating member 754A is removed to expose the semiconductor component 126 inside the contact hole ChA. In this step, a portion of the insulating member 754A is removed by a method such as RIE.

[0269] in addition, Fig.48 In the example of FIG. 1 , the portion of the insulating member 754A formed on the upper surface of the insulating layer 104 is removed. In addition, the portion of the insulating member 754A provided on the inner peripheral surface of the contact hole ChA remains and becomes the insulating region 762 of the insulating film 760. In addition, none of the voids V1A, V2A, the region below the contact hole ChA, and the region above the contact hole ChA is filled with the insulating member 754A.

[0270] Next, if Fig.49 As shown in FIG. 1 , an insulating member 755A is formed inside the contact hole ChA and the voids V1A and V2A. This process is performed, for example, by a method such as CVD. In this process, substantially all regions in the voids V1A and V2A (regions excluding the voids V1 and V2) are filled with the insulating member 755A. On the other hand, the region above the contact hole ChA is not filled with the insulating member 755A.

[0271] Next, for example Fig.50 As shown in FIG. 1 , a portion of the insulating member 755A is removed to expose the semiconductor member 126 inside the contact hole ChA. In this step, a portion of the insulating member 755A is removed by, for example, RIE or the like. After a portion of the insulating member 755A is removed, a dilute hydrofluoric acid (DHF) or the like is used to remove residues generated when the insulating member 754A and a portion of the insulating member 755A are removed, and the surface of the semiconductor member 126 is cleaned.

[0272] in addition, Fig.50 In the example of FIG. 7 , the portion of the insulating member 755A formed on the upper surface of the insulating layer 104 is removed. In addition, the portion of the insulating member 755A provided in the region below the contact hole ChA is removed, and the insulating member SHE is exposed at the bottom surface of the contact hole ChA. On the other hand, the portion of the insulating member 755A provided on the inner peripheral surface of the contact hole ChA remains and becomes the insulating region 761 of the insulating film 760.

[0273] In this embodiment, the portions of the insulating members 754A and 755A provided in the gap V1A become the insulating regions 754 and 755 of the insulating member 751. In addition, the portions of the insulating members 754A and 755A provided in the gap V2A become the insulating member 752 ( Fig.46 )'s insulating regions 757, 758.

[0274] The semiconductor memory device according to the seventh embodiment can also achieve the same effects as those of the semiconductor memory device according to the first embodiment.

[0275] In the semiconductor memory device of the seventh embodiment, the insulating members 751 and 752 include insulating regions 754 and 757 containing silicon oxide, respectively. This can effectively suppress the occurrence of short circuits between the contact electrodes Ch. In addition, the withstand voltage of the contact electrodes Ch and the drain-side selection gate line SGDT can be effectively ensured.

[0276] In the semiconductor memory device of the seventh embodiment, the insulating members 751 and 752 include insulating regions 755 and 758, respectively, and the insulating regions 755 and 758 are made of a material having a higher resistance to dilute hydrofluoric acid than silicon oxide. Fig.50 In the described process, it is possible to preferably suppress excessive removal of the insulating member 754A.

[0277] In addition, the insulating members 751 and 752 of the seventh embodiment may be combined with the insulating members 151 and 152 ( Figure 6 , Figure 7 and Figure 8 ) are the same as those of the semiconductor memory device of the fourth embodiment, and include the insulating portions 154 and 156. In addition, the semiconductor memory device of the seventh embodiment may not include a part or all of the insulating film 760. In addition, the semiconductor memory device of the seventh embodiment may also include the conductive component ChB ( Fig.38 , Fig.39 ) instead of the gaps V1 and V2. In addition, the insulating components 551 and 552 ( Fig.42 , Fig.43) is the same as that in the seventh embodiment, the gaps V1 and V2 are not provided inside the insulating parts 751 and 752.

[0278] [Other embodiments]

[0279] The semiconductor memory devices according to the first to seventh embodiments have been described above. However, these configurations are merely examples, and the specific configurations may be adjusted as appropriate.

[0280] Fig.51 and Fig.52 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment.

[0281] For example, refer to Fig.28 and Fig.29 In the described process, the voids V1 and V2 may be formed in one of the voids V1A and V2A, but not in the other. Figure 24 to Figure 27 In the described process, one of the voids V1A and V2A may be connected to the contact hole ChA, while the other may not be connected to the contact hole ChA.

[0282] In addition, for example, Fig.30 In the described process, after removing a part of the insulating member 151A to expose the semiconductor member 126 inside the contact hole ChA, the residue is removed using dilute hydrofluoric acid or the like. At this time, a part of the insulating member 151A is further removed. However, as described above, if at least a part of the path between the two contact holes ChA connected via the gaps V1A and V2A is blocked by the insulating member 151A, even if the metal or the like constituting the contact electrode Ch enters at least a part of the inside of the gaps V1A and V2A without passing through the insulating member 151A, it is possible to suppress the occurrence of a short circuit between the contact electrodes Ch.

[0283] For example, Fig.51 The example in which the insulating member 151A in the void V1A is removed by treatment with dilute hydrofluoric acid or the like, and the insulating member 151A in the void V2A remains as the insulating member 252 is shown. In addition, in the example shown in the figure, the conductive member ChB is formed in the void V1A, but at least a portion of the void V1A may remain as the void V1A without providing the conductive member. In addition, the inside of the void V2A may be completely filled with the insulating member 151A, and the void V2A may not be provided inside the insulating member 252.

[0284] In addition, for example, Fig.52The figure shows that the insulating member 151A is removed from both the void V1A and the void V2A except for the connecting portion of the voids V1A and V2A by the treatment with dilute hydrofluoric acid or the like, while the insulating member 151A remains in the connecting portion of the voids V1A and V2A. In the example shown in the figure, the conductive member ChB is formed in the void V1A and the void V2A, but the conductive member may not be provided in at least a portion of the voids V1A and V2A and the voids V1A and V2A may remain as they are.

[0285] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the same scope as the invention described in the claims.

[0286] [Explanation of Symbols]

[0287] 101: Insulation layer

[0288] 110: Conductive layer

[0289] 120: Semiconductor column

[0290] 126:Semiconductor components

[0291] 127: Insulation layer

[0292] 130: Gate insulating film

[0293] 131: Tunnel insulating film

[0294] 132: Charge storage film

[0295] 133: Barrier insulation film

[0296] 151,152: Insulation parts

[0297] Ch, Vy: contact electrode

[0298] SGD, SGDT: drain side select gate line

[0299] SHE: Insulation parts

[0300] WL: Word line.

Claims

1. A semiconductor storage device comprising: A plurality of conductive layers are stacked in a stacking direction; A first semiconductor column extending in the stacking direction and facing the plurality of conductive layers; A first gate insulating film, disposed between the plurality of conductive layers and the first semiconductor pillar, comprising a first charge storage film; a first semiconductor component connected to one end of the first semiconductor column in the stacking direction; a first contact electrode extending in the stacking direction and connected to the first semiconductor component; a first insulating member, arranged at a position overlapping with the first semiconductor pillar and a portion of the first gate insulating film when viewed from the stacking direction, and separating a portion of the conductive layers arranged on the first contact electrode side in the stacking direction from among the plurality of conductive layers in a first direction intersecting the stacking direction; and a second insulating member provided at least at a first position in the stacking direction corresponding to the first semiconductor member inside the first insulating member; and The first contact electrode comprises: a first conductive region provided on a side opposite to the first semiconductor pillar in the stacking direction with respect to a surface of the first semiconductor component on the first contact electrode side in the stacking direction; and The second conductive region is provided between the first semiconductor component and the second insulating component, on the first semiconductor pillar side in the stacking direction with respect to the surface of the first semiconductor component, and is in contact with the second insulating component. 2 . The semiconductor memory device according to claim 1 , wherein the second insulating member has an etching rate different from that of the first insulating member.

3. The semiconductor memory device according to claim 1, wherein a surface of the first semiconductor component on the second insulating component side in the first direction includes a recessed portion recessed toward the first semiconductor component side in the first direction, The second insulating member is provided at a second position on the first semiconductor column side in the stacking direction relative to the first position. The length of the second insulating member at the second position in the first direction is smaller than the length of the second insulating member at the first position in the first direction. The second insulating member is formed so as to fill the interior of the first insulating member at least at the second position among the first position and the second position.

4. The semiconductor memory device according to claim 3, wherein a gap is provided inside the second insulating member at the first position, The gap is separated from the first contact electrode via a portion of the second insulating member.

5. The semiconductor memory device according to claim 3, wherein a conductive member is provided inside the second insulating member at the first position, The conductive member is connected to the first contact electrode.

6. The semiconductor memory device according to claim 3, wherein the recess comprises: In point 1 and point 2, the positions of the stacking directions are different from each other; and At point 3, the position in the stacking direction is set between the position in the stacking direction of point 1 and the position in the stacking direction of point 2; The third point is provided on the opposite side of the second insulating member in the first direction with respect to the first point and the second point. 7 . The semiconductor memory device according to claim 3 , wherein the second position is provided on the first contact electrode side in the stacking direction with respect to the plurality of conductive layers.

8. The semiconductor storage device according to claim 1, further comprising an insulating film provided on an outer peripheral surface of the first contact electrode, The insulating film is connected to the second insulating member. 9 . The semiconductor memory device according to claim 1 , wherein the second insulating member includes silicon (Si) and oxygen (O), nitrogen (N) or carbon (C).

10. The semiconductor memory device according to claim 1, wherein the second insulating member comprises: The first insulating area; and a second insulating region, arranged inside the first insulating region; The second insulating region includes nitrogen (N) or carbon (C), The first insulating region includes nitrogen (N) or carbon (C).

11. The semiconductor memory device according to claim 1, wherein the second insulating member further comprises: a second position provided on the first semiconductor pillar side in the stacking direction relative to the first position; and a third position provided on the first contact electrode side in the stacking direction relative to the first position; The length of the second insulating member at the second position in the first direction is smaller than the length of the second insulating member at the first position in the first direction. A length of the second insulating member at the third position in the first direction is smaller than a length of the second insulating member at the first position in the first direction.

12. The semiconductor memory device according to claim 1, wherein a length of the first semiconductor component in the first direction is smaller than a length of the first semiconductor component in a second direction intersecting the stacking direction and the first direction.

13. The semiconductor memory device according to claim 1, further comprising: a second semiconductor column extending in the stacking direction, facing the plurality of conductive layers, and having a position in the first direction and a position in a second direction intersecting the stacking direction and the first direction different from those of the first semiconductor column; A second gate insulating film, disposed between the plurality of conductive layers and the second semiconductor pillar, comprising a second charge storage film; a second semiconductor component connected to one end of the second semiconductor column in the stacking direction; and a second contact electrode extending in the stacking direction, connected to the second semiconductor component, and comprising a third conductive region and a fourth conductive region, the third conductive region being provided on the side opposite to the second semiconductor column in the stacking direction with respect to the surface of the second semiconductor component on the second contact electrode side in the stacking direction, and the fourth conductive region being provided between the second semiconductor component and the second insulating component, on the second semiconductor column side in the stacking direction with respect to the surface of the second semiconductor component, and in contact with the second insulating component; The second insulating member is provided to block at least a portion of a path extending in the second direction inside the first insulating member in the stacking direction between the second conductive region of the first contact electrode and the fourth conductive region of the second contact electrode.

14. The semiconductor memory device according to claim 1, wherein an end portion of the second conductive region on the first semiconductor pillar side in the stacking direction is covered by the first insulating member or the second insulating member.

15. A semiconductor storage device comprising: A plurality of conductive layers are stacked in a stacking direction; A semiconductor column extending in the stacking direction and facing the plurality of conductive layers; a gate insulating film disposed between the plurality of conductive layers and the semiconductor pillar, comprising a charge storage film; A semiconductor component connected to one end of the semiconductor column in the stacking direction; A contact electrode extending in the stacking direction and connected to the semiconductor component; a first insulating member, arranged at a position overlapping with the semiconductor pillar and a portion of the gate insulating film when viewed from the stacking direction, and separating a portion of the conductive layers arranged on the contact electrode side in the stacking direction from among the plurality of conductive layers in a first direction intersecting the stacking direction; and The second insulating component is arranged at least at the first position in the stacking direction corresponding to the semiconductor component inside the first insulating component, and one end and the other end in the stacking direction, and the side surface on the opposite side of the semiconductor component in the first direction are separated from one end and the other end of the first insulating component in the stacking direction, and are formed along the first insulating component. 16 . The semiconductor memory device according to claim 15 , wherein the second insulating member has an etching rate different from that of the first insulating member.

17. The semiconductor storage device according to claim 15, wherein the surface of the semiconductor component on the second insulating component side in the first direction has a recessed portion recessed toward the semiconductor component side in the first direction, and the second insulating component is provided at a second position on the semiconductor column side in the stacking direction relative to the first position, The length of the second insulating member at the second position in the first direction is smaller than the length of the second insulating member at the first position in the first direction. The second insulating member is formed so as to fill the interior of the first insulating member at least at the second position among the first position and the second position.

18. A semiconductor storage device comprising: A plurality of conductive layers are stacked in a stacking direction; A first semiconductor column extending in the stacking direction and facing the plurality of conductive layers; a second semiconductor column extending in the stacking direction, facing the plurality of conductive layers, and having a position in a first direction intersecting the stacking direction and a position in a second direction intersecting the stacking direction and the first direction different from those of the first semiconductor column; A first gate insulating film, disposed between the plurality of conductive layers and the first semiconductor pillar, comprising a first charge storage film; A second gate insulating film, disposed between the plurality of conductive layers and the second semiconductor pillar, comprising a second charge storage film; a first semiconductor component connected to one end of the first semiconductor column in the stacking direction; A second semiconductor component connected to one end of the second semiconductor column in the stacking direction; a first contact electrode extending in the stacking direction and connected to the first semiconductor component; a second contact electrode extending in the stacking direction and connected to the second semiconductor component; a first insulating member, which is disposed between the first semiconductor column and the second semiconductor column in a manner overlapping with a portion of the first semiconductor column and the second semiconductor column when viewed from the stacking direction, extends in the second direction, and separates a portion of the conductive layers arranged on the first contact electrode side in the stacking direction from among the plurality of conductive layers in the first direction; and a second insulating member provided at least at a first position in the stacking direction corresponding to the first semiconductor member and the second semiconductor member inside the first insulating member; The second insulating member is configured as follows: Between a first region opposing the side surface of the first insulating component on the first direction of the first contact electrode and a second region opposing the side surface of the first insulating component on the first direction of the second contact electrode, at least a portion of a path formed by the interior of the first insulating component in the stacking direction extending along the second direction is blocked. 19 . The semiconductor memory device according to claim 18 , wherein the second insulating member has an etching rate different from that of the first insulating member.

20. The semiconductor memory device according to claim 18, wherein a space or a conductive member is provided inside the first region and the second region. The space or the conductive member in the first region is separated from the space or the conductive member in the second region via the second insulating member.

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