A low-cost full-vertical gallium nitride schottky barrier diode and a preparation method thereof

Abstract

The application discloses a low-cost full-vertical gallium nitride Schottky barrier diode and a preparation method thereof. The diode comprises a transmission layer, a drift layer located at the lower surface of the transmission layer, a positive electrode located at the middle of the lower surface of the drift layer, a negative electrode located at the middle of the upper surface of the transmission layer, a first dielectric layer located at the lower surface of the remaining drift layer and the sidewall and part of the lower surface of the positive electrode, a second dielectric layer located at the upper surface of the remaining transmission layer and the sidewall and part of the upper surface of the negative electrode, a positive electrode thickening layer located at the lower surface of the first dielectric layer and the lower surface of the remaining negative electrode, a conductive substrate located at the lower surface of the positive electrode thickening layer, an additional positive electrode located at the middle of the lower surface of the conductive substrate, and a negative electrode thickening layer located at the upper surface of part of the second dielectric layer and the upper surface of the remaining negative electrode. The application realizes a full-vertical device structure with full longitudinal conduction, improves the forward current density of the device, and reduces the on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a low-cost fully vertical gallium nitride Schottky barrier diode and its fabrication method. Background Technology

[0002] Compared to traditional silicon (Si) and gallium arsenide (GaAs) materials, gallium nitride (GaN) boasts a bandgap of up to 3.4 eV. This characteristic endows GaN devices with higher voltage withstand capability, enabling stable operation under higher voltage and power conditions. Furthermore, GaN devices exhibit low on-resistance and high switching frequency characteristics, allowing for energy transfer with lower current losses, thereby significantly improving system efficiency and enabling smaller packages and higher system integration. Currently, GaN devices are widely used in several key areas, particularly in power management, high-frequency communication, and high-power conversion, demonstrating enormous potential. With technological advancements and reduced manufacturing costs, they are expected to play an even greater role in high-end applications such as data centers, communication base stations, lidar, power modules, renewable energy, defense, and aerospace.

[0003] Compared to traditional quasi-vertical planar GaN Schottky barrier diodes, vertical GaN Schottky barrier diodes exhibit extremely low on-resistance due to their highly concentrated current paths, contributing to efficient power conversion. While GaN epitaxy on homolithic substrates can effectively reduce high-density defects caused by lattice mismatch, the extremely high cost of GaN homolithic substrates hinders large-scale commercial application. Therefore, researching and developing low-cost, fully vertical GaN Schottky barrier diodes has become a key research focus both domestically and internationally, and achieving low-cost, high-current-density, fully vertical GaN Schottky barrier diodes is a pressing issue that needs to be addressed. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a low-cost, fully vertical gallium nitride Schottky barrier diode and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of the present invention provide a low-cost, fully vertical gallium nitride Schottky barrier diode, the diode comprising:

[0006] Transport layer;

[0007] A drift layer is located on the lower surface of the transport layer;

[0008] The anode is located in the middle of the lower surface of the drift layer and forms a Schottky contact with the drift layer;

[0009] The cathode is located in the middle of the upper surface of the transport layer and forms an ohmic contact with the transport layer;

[0010] A first dielectric layer is located on the lower surface of the remaining drift layer, as well as on the sidewall and part of the lower surface of the anode;

[0011] The second dielectric layer is located on the upper surface of the remaining transport layer, as well as the sidewall and part of the upper surface of the cathode.

[0012] The anode thickening layer is located on the lower surface of the first dielectric layer and on the lower surface of the remaining cathode.

[0013] A conductive substrate is located on the lower surface of the thickened anode layer.

[0014] An additional anode is located in the middle of the lower surface of the conductive substrate;

[0015] A cathode thickening layer is located on the upper surface of a portion of the second dielectric layer and on the upper surface of the remaining cathode.

[0016] In one embodiment of the present invention, the thickness of the anode thickening layer is 0.5 μm to 10 μm.

[0017] In one embodiment of the present invention, the conductive substrate is a low-resistivity Si conductive substrate, a metal conductive substrate, or a tungsten-copper alloy conductive substrate.

[0018] In one embodiment of the present invention, the thickness of the cathode thickening layer is 0.5 μm to 10 μm.

[0019] In one embodiment of the present invention, the thickness of the additional anode is 1 μm to 5 μm.

[0020] Secondly, embodiments of the present invention provide a method for fabricating a low-cost, fully vertical gallium nitride Schottky barrier diode, the method comprising:

[0021] Obtain an epitaxial wafer; the epitaxial wafer comprises a substrate layer, a nucleation layer, a transport layer and a drift layer stacked sequentially from bottom to top;

[0022] An anode is formed in the middle of the upper surface of the drift layer, and the anode forms a Schottky contact with the drift layer;

[0023] A first dielectric layer is formed on the upper surface of the remaining drift layer, as well as on the sidewall and part of the upper surface of the anode;

[0024] An anode thickening layer is formed on the upper surface of the first dielectric layer and on the upper surface of the remaining anode;

[0025] Obtain a conductive substrate and permanently bond the conductive substrate to the upper surface of the anode thickened layer;

[0026] An additional anode is formed in the middle of the upper surface of the conductive substrate;

[0027] The entire device structure is flipped over, and the substrate layer and the nucleation layer are etched away;

[0028] A cathode is formed in the middle of the upper surface of the transport layer, and the cathode forms an ohmic contact with the transport layer;

[0029] A second dielectric layer is formed on the upper surface of the remaining transport layer and on the upper surface of a portion of the cathode;

[0030] A cathode thickening layer is formed on the upper surface of the remaining cathode and on a portion of the upper surface of the second dielectric layer.

[0031] In one embodiment of the present invention, an anode thickening layer is formed on the upper surface of the first dielectric layer and on the upper surface of the remaining anode, comprising:

[0032] An electroplating process is used to form an anode thickening layer with a thickness of 0.5 μm to 10 μm on the upper surface of the first dielectric layer and on the upper surface of the remaining anode.

[0033] In one embodiment of the present invention, the obtained conductive substrate is a low-resistivity Si conductive substrate, a metal conductive substrate, or a tungsten-copper alloy conductive substrate.

[0034] In one embodiment of the present invention, before permanently bonding the conductive substrate to the upper surface of the anode thickened layer, the following steps are included:

[0035] Metal is electroplated onto the upper surface of the conductive substrate using an electroplating process.

[0036] In one embodiment of the present invention, a cathode thickening layer is formed on the upper surface of the remaining cathode and on the upper surface of a portion of the second dielectric layer, comprising:

[0037] An electroplating process is used to form a cathode thickening layer with a thickness of 0.5 μm to 10 μm on the upper surface of the remaining cathode and on a portion of the upper surface of the second dielectric layer.

[0038] The beneficial effects of this invention are:

[0039] This invention proposes a low-cost, fully vertical gallium nitride Schottky barrier diode. Innovatively, the cathode is positioned on the upper surface of the transport layer, and the anode on the lower surface of the drift layer, with the anode directly below the cathode. A low-cost conductive substrate is introduced, and an additional anode is added to the bottom of the conductive substrate, achieving a fully vertically conductive device structure. This effectively avoids the current pooling effect problem present in traditional heterogeneous substrate quasi-vertical planar gallium nitride Schottky barrier diodes. Furthermore, compared to traditional heterogeneous substrate quasi-vertical planar gallium nitride Schottky barrier diodes, it removes a thicker substrate. The relatively weakly conductive substrate layer is addressed by introducing a conductive substrate, which solves the support problem after substrate peeling. Furthermore, the conductive substrate acts as a good conductive layer, compensating for the high on-resistance easily generated when the cathode is directly fabricated on the bottom of the substrate. This results in a device with high forward current density and low on-resistance, as well as excellent switching speed and breakdown voltage, achieving superior electrical characteristics. Because the device can handle larger forward current densities in high-power applications, the thermal effect is reduced, further improving the stability and reliability of the device under high-power operating conditions. In summary, the embodiments of this invention effectively solve the current-edge-collecting effect of traditional heterogeneous substrate quasi-vertical planar gallium nitride Schottky barrier diodes. With its advantages of high current and low cost, it can promote the broad application prospects of low-cost, fully vertical gallium nitride Schottky barrier diodes in high-tech fields, such as data centers, communication base stations, lidar, power modules, and other electronic devices.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a low-cost, fully vertical gallium nitride Schottky barrier diode provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of a low-cost, fully vertical gallium nitride Schottky barrier diode fabrication method provided in an embodiment of the present invention;

[0043] Figures 3a to 3j This is a schematic diagram of the fabrication process of the low-cost fully vertical gallium nitride Schottky barrier diode provided in this embodiment of the invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] 1-Substrate layer; 2-Nucleation layer; 3-Transport layer; 4-Drift layer; 5-Anode; 6-First dielectric layer; 7-Anode thickening layer; 8-Conductive substrate; 9-Additional anode; 10-Cathode; 11-Second dielectric layer; 12-Cathode thickening layer. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0047] Firstly, please see Figure 1 This invention provides a low-cost, fully vertical gallium nitride Schottky barrier diode, specifically comprising the following steps:

[0048] Transport layer 3;

[0049] Drift layer 4 is located on the lower surface of transport layer 3;

[0050] The anode 5 is located in the middle of the lower surface of the drift layer 4 and forms a Schottky contact with the drift layer 4;

[0051] The negative electrode 10 is located in the middle of the upper surface of the transport layer 3 and forms an ohmic contact with the transport layer 3;

[0052] The first dielectric layer 6 is located on the lower surface of the remaining drift layer 4, as well as the sidewall and part of the lower surface of the anode 5;

[0053] The second dielectric layer 11 is located on the upper surface of the remaining transport layer 3, as well as the sidewall and part of the upper surface of the cathode 10.

[0054] The anode thickening layer 7 is located on the lower surface of the first dielectric layer 6 and the lower surface of the remaining cathode 10;

[0055] The conductive substrate 8 is located on the lower surface of the anode thickened layer 7;

[0056] An additional anode 9 is located in the middle of the lower surface of the conductive substrate 8;

[0057] The cathode thickening layer 12 is located on the upper surface of a portion of the second dielectric layer 11 and on the upper surface of the remaining cathode 10.

[0058] In this embodiment of the invention, transport layer 3 is n-type heavily doped GaN with a thickness of 0.5 μm to 5 μm and a silicon doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 Drift layer 4 is an n-type lightly doped GaN drift layer with a thickness of 0.1 μm to 10 μm and a silicon doping concentration of 1 × 10⁻⁶. 15 cm -3 ~5×10 17 cm -3 The materials of the first dielectric layer 6 and the second dielectric layer 10 are one or more of Al2O3, SiO2, and SiN.

[0059] In this embodiment of the invention, Ni / Au (50nm / 150nm) metal, Pt / Au (50nm / 150nm) metal, W / Au (50nm / 150nm) metal, or Mo / Au (50nm / 150nm) metal are selected as the anode 5 of this gallium nitride Schottky barrier diode. This is because: metals Ni, Pt, W, and Mo have excellent adhesion and can form high-quality Schottky contacts on the surface of GaN material; at the same time, the introduction of the Au layer not only effectively improves the conductivity of the diode, but also prevents the oxidation of the underlying metal (Ni, Pt, W, Mo) due to the chemical inertness of Au, thus enhancing the reliability of the device.

[0060] In this embodiment of the invention, Ti / Al / Ni / Au (20nm / 140nm / 50nm / 40nm) metal is selected as the cathode 10 of this gallium nitride Schottky barrier diode. This is because: choosing Ti, a metal with a lower work function, as the contact layer is beneficial for forming an ideal ohmic contact at the Au half-contact interface, thus reducing the contact resistance; Al, by promoting the solid-state reaction between N atoms and Ti atoms, optimizes the interface bonding effect; Ni acts as a barrier layer to prevent interpenetration between different metal layers; and Au is used to protect the underlying metal from oxidation, thereby enhancing the reliability of the device.

[0061] In this embodiment of the invention, the thickness of the conductive substrate 8 is 50 μm to 150 μm; the material of the conductive substrate 8 is a low-resistivity Si conductive substrate, a metal conductive substrate, or a tungsten-copper alloy conductive substrate. The low-resistivity Si conductive substrate has low resistivity, which can reduce energy loss and improve conductivity; the metal conductive substrate has excellent conductivity; the tungsten-copper alloy conductive substrate combines the high thermal stability of tungsten metal with the excellent electrical and thermal conductivity of copper metal, ensuring low cost and high performance of the device and improving the device's heat dissipation capacity.

[0062] In this embodiment of the invention, if the conductive substrate 8 is a low-resistivity Si conductive substrate, the material of the anode thickening layer 7 is selected from a metal that can form good ohmic contact with Si. If the conductive substrate 8 is a metal conductive substrate or a tungsten-copper alloy conductive substrate, the material of the anode thickening layer 7 is not limited. The anode thickening layer 7 is used to thicken the anode 5, and the thickness of the anode thickening layer 7 is 0.5 μm to 10 μm. At the same time, the material of the cathode thickening layer 12 is not limited, for example, it can be Ti / Au metal, used to thicken the cathode 10, and the thickness of the cathode thickening layer 12 is 0.5 μm to 10 μm.

[0063] In this embodiment of the invention, if the conductive substrate 8 is a low-resistivity Si conductive substrate, the material of the additional anode 9 is selected as a metal that can form good ohmic contact with Si. If the conductive substrate 8 is a metal conductive substrate or a tungsten-copper alloy conductive substrate, the material of the additional anode 9 is not limited, and the thickness is 1μm to 5μm. A bias voltage is applied to a low-cost, fully vertical gallium nitride Schottky barrier diode through the additional anode 9 and the thickened cathode layer 12.

[0064] In summary, the low-cost, fully vertical gallium nitride Schottky barrier diode proposed in this invention innovatively places the cathode 10 on the upper surface of the transport layer 3 and the anode 5 on the lower surface of the drift layer 4, with the anode 5 directly below the cathode 10. It also introduces a low-cost conductive substrate 8 and adds an additional anode 9 at the bottom of the conductive substrate, achieving a fully vertically conductive device structure. This effectively avoids the current pooling effect problem present in traditional heterogeneous substrate quasi-vertical planar gallium nitride barrier diodes. Furthermore, compared to traditional heterogeneous substrate quasi-vertical planar gallium nitride barrier diodes... The diode, with its relatively thick and weakly conductive substrate layer stripped away, overcomes the support problem after substrate stripping by introducing a conductive substrate 8. Furthermore, the conductive substrate 8 acts as a good conductive layer, compensating for the high on-resistance easily generated when the cathode is directly fabricated on the bottom of the substrate. This results in a device with high forward current density and low on-resistance, as well as excellent switching speed and breakdown voltage, achieving superior electrical characteristics. Because the device can handle larger forward current densities in high-power applications, the thermal effect is reduced, further improving the stability and reliability of the device under high-power operating conditions. In summary, the embodiments of this invention effectively solve the current-following effect of traditional heterogeneous substrate quasi-vertical planar gallium nitride Schottky barrier diodes. With its advantages of high current and low cost, it can promote the broad application prospects of low-cost, fully vertical gallium nitride Schottky barrier diodes in high-tech fields, such as data centers, communication base stations, lidar, power modules, and other electronic devices.

[0065] Secondly, please see Figure 2 This invention provides a low-cost method for fabricating a fully vertical gallium nitride Schottky barrier diode, the method comprising:

[0066] S10. Obtain an epitaxial wafer; wherein the epitaxial wafer comprises a substrate layer 1, a nucleation layer 2, a transport layer 3 and a drift layer 4 stacked sequentially from bottom to top.

[0067] The embodiments of the present invention obtain as follows Figure 3aThe epitaxial wafer shown comprises, from bottom to top, a substrate layer 1, a nucleation layer 2, a transport layer 3, and a drift layer 4. The substrate layer 1 is made of Si or sapphire, a mature and low-cost manufacturing technology; the nucleation layer 2 is made of one or more of AlN, AlGaN, and GaN, with a thickness of 30 nm to 90 nm; the transport layer 3 is n-type heavily doped GaN, with a thickness of 0.5 μm to 5 μm and a silicon doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 Drift layer 4 is an n-type lightly doped GaN drift layer with a thickness of 0.1 μm to 10 μm and a silicon doping concentration of 1 × 10⁻⁶. 15 cm -3 ~5×10 17 cm -3 The epitaxial wafer can be obtained by epitaxial growth using MOCVD (Metal-organic Chemical Vapor Deposition) technology, or it can be an existing epitaxial wafer with this structure obtained directly.

[0068] Next, the epitaxial wafer undergoes organic cleaning to remove the surface oxide layer. Specifically: First, the epitaxial wafer is immersed in an acetone solution and ultrasonically cleaned for 5 minutes to remove organic contaminants from its surface. Then, it is immersed in an isopropanol solution and ultrasonically cleaned for 5 minutes to effectively remove residual acetone. Next, the epitaxial wafer is rinsed in deionized water to remove any remaining isopropanol. Finally, the surface is dried with high-purity nitrogen to ensure no liquid residue remains. Then, the surface oxide layer is removed by immersing the epitaxial wafer in a 1:7 BOE (Buffered Oxide Etch) solution for 30 seconds, followed by rinsing with copious amounts of deionized water. Finally, the surface is dried with high-purity nitrogen, completing the entire epitaxial wafer cleaning process. Epitaxial wafer cleaning is a necessary process before device fabrication, reducing the interference of oxidation and contamination on subsequent device processes and its impact on device performance.

[0069] S20. An anode 5 is formed in the middle of the upper surface of the drift layer 4, and the anode 5 forms a Schottky contact with the drift layer 4.

[0070] In this embodiment of the invention, the upper surface of the drift layer 4 is subjected to homogenization, baking, exposure, and development. A positive electrode region is defined in the middle of the upper surface of the drift layer 4. Electron beam evaporation is used to grow Ni / Au (50nm / 150nm), Pt / Au (50nm / 150nm), W / Au (50nm / 150nm), or Mo / Au (50nm / 150nm) metal layers in the positive electrode region. Afterwards, organic cleaning is performed to remove residual adhesive and excess metal, thus forming the positive electrode 5. Figure 3b As shown, the anode 5 forms a Schottky contact with the drift layer 4. To reduce the influence of the Au half-contact interface state and suppress reverse leakage, the epitaxial wafer with the anode 5 formed is annealed at 450°C for 5 minutes under a nitrogen atmosphere.

[0071] S30. A first dielectric layer 6 is formed on the upper surface of the remaining drift layer 4, as well as on the sidewall and part of the upper surface of the anode 5.

[0072] In this embodiment of the invention, a 20 nm thick layer of Al2O3, SiO2, or SiN dielectric material is deposited on the upper surface of the drift layer 4 and the sidewalls and upper surface of the anode 5 using PECVD (Plasma Enhanced Chemical Vapor Deposition) technology. This passivates the surface of the device structure obtained in S20, reducing the impact of surface states on device performance and effectively preventing contamination of the epitaxial wafer surface by external impurities. After the first dielectric layer 6 is deposited, the anode region is dry-etched using RIE (Reactive Ion Etching) technology to etch away part of the first dielectric layer 6, thereby creating necessary anode contact holes on the upper surface of the first dielectric layer 6. Figure 3c As shown.

[0073] S40. An anode thickening layer 7 is formed on the upper surface of the first dielectric layer 6 and on the upper surface of the remaining anode 5.

[0074] In this embodiment of the invention, the device structure obtained in S30 is sequentially immersed in acetone and isopropanol solutions, ultrasonically cleaned for 5 minutes each, then rinsed with deionized water and dried with high-purity nitrogen. After cleaning, an anode thickening layer 7 with a thickness of 0.5 μm to 10 μm is formed on the upper surface of the first dielectric layer 6 and the upper surface of the remaining anode 5 using an electroplating process. In the electroplating bath, by controlling process parameters such as current density, temperature, and solution composition, precise control of the metal layer thickness and uniformity is achieved, thickening the anode in the anode region to the required thickness. Annealing is then used to eliminate defects during the deposition process, increasing the crystallinity of the metal layer, resulting in an anode thickening layer 7 with a thickness of 0.5 μm to 10 μm. Figure 3dAs shown. If the conductive substrate 8 is a low-resistivity Si conductive substrate, the material of the anode thickening layer 7 is selected from metals that can form good ohmic contact with Si, such as Ti or W metals. If the conductive substrate 8 is a metal conductive substrate or a tungsten-copper alloy conductive substrate, the material of the anode thickening layer 7 is not limited.

[0075] S50. Obtain the conductive substrate 8 and permanently bond the conductive substrate 8 to the upper surface of the anode thickening layer 7.

[0076] In this embodiment of the invention, a conductive substrate 8 is first obtained. The conductive substrate 8 can be a low-resistivity Si conductive substrate, a metal conductive substrate, or a tungsten-copper alloy conductive substrate. Next, using an electroplating process, the same metal as the anode thickening layer 7 is electroplated onto the conductive substrate 8. Then, using a bonding technique, the surface of the conductive substrate 8, on which the metal is electroplated, is permanently bonded to the upper surface of the anode thickening layer 7. The resulting device structure is as follows: Figure 3e As shown. More specifically: The obtained conductive substrate 8 is cleaned, and after cleaning, the same metal as the anode thickening layer 7 is electroplated on the surface of the conductive substrate 8 using an electroplating process. This metal ensures a good bonding effect between the conductive substrate 8 and the anode thickening layer 7. Using bonding technology, the anode thickening layer 7 and the surface of the conductive substrate 8 with electroplated metal are heated to a temperature higher than their recrystallization temperature, causing localized plastic deformation of the metal. By applying external pressure, the metal achieves bonding between the metal contact interfaces through diffusion and bonding.

[0077] S60. An additional anode 9 is formed in the middle of the upper surface of the conductive substrate 8.

[0078] In this embodiment of the invention, the surface of the conductive substrate 8 is cleaned, and the substrate is then subjected to homogenization, baking, exposure, and development. An additional anode region is defined in the middle of the surface of the conductive substrate 8. Metal is deposited in the additional anode region using electron beam evaporation technology, followed by organic cleaning to remove residual adhesive and excess metal. If the conductive substrate 8 is a low-resistivity Si conductive substrate, the material of the additional anode 9 is selected from metals that can form good ohmic contact with Si, such as Ti / Au or W / Au. Ti and W metals can form good ohmic contact with the Si surface, and Au prevents oxidation of the bottom (Ti / W) metal due to its stability. If the conductive substrate 8 is a metal conductive substrate or a tungsten-copper alloy conductive substrate, the material of the additional anode 9 is not limited, and an additional anode 9 with a thickness of 1μm to 5μm is formed. Figure 3f As shown.

[0079] S70. Flip the entire device structure and etch away the substrate layer 1 and the nucleation layer 2.

[0080] In this embodiment of the invention, the entire device structure obtained in S60 is first flipped. Next, substrate 1 is etched: when substrate 1 is a Si substrate, a mechanical polishing process is used to quickly reduce most of the thickness of substrate 1, followed by deep silicon etching to completely remove the substrate. When substrate 1 is a sapphire substrate, laser lift-off technology is used to remove the substrate. Finally, the nucleation layer 2 is precisely etched using ICP (Inductively Coupled Plasma) technology. A mixed gas of Cl2 and BCl3 is used as the etching medium during the etching process to ensure etching selectivity and precise material removal. Finally, high-purity nitrogen is used to... Figure 3g The device structure with substrate layer 1 and nucleation layer 2 removed is dried to ensure that there is no residual liquid or contaminants on the surface.

[0081] S80. A cathode 10 is formed in the middle of the upper surface of the transport layer 3, and the cathode 10 forms an ohmic contact with the transport layer 3.

[0082] In this embodiment of the invention, the upper surface of the transport layer 3 is subjected to homogenization, baking, exposure, and development. A cathode region is defined in the middle of the upper surface of the transport layer 3. Then, Ti / Al / Ni / Au (20nm / 140nm / 50nm / 40nm) metal is grown in the cathode region using electron beam evaporation technology. Afterwards, residual adhesive and excess metal are removed by organic cleaning to form the cathode 10. Figure 3h As shown, the cathode 10 forms an ohmic contact with the transport layer 3. To reduce the influence of the Au half-contact interface state and suppress reverse leakage, the device structure with the cathode 10 formed is annealed at 850°C for 5 minutes in a nitrogen atmosphere to form a good ohmic contact.

[0083] S90. A second dielectric layer 11 is formed on the upper surface of the remaining transport layer 3 and on the upper surface of part of the cathode 10.

[0084] In this embodiment of the invention, a 20nm thick Al2O3, SiO2, or SiN dielectric material is deposited on the upper surface of the transport layer 3 and the sidewalls and upper surface of the cathode 10 using PECVD technology. This passivates the surfaces of the transport layer 3 and the cathode 10, reducing the impact of surface states on device performance and effectively preventing contamination of the transport layer 3 surface by external impurities. After the second dielectric layer 11 is deposited, the cathode region is dry-etched using RIE technology to create necessary electrode contact holes in the second dielectric layer 11. Figure 3i As shown.

[0085] S100, A cathode thickening layer 12 is formed on the upper surface of the remaining cathode 10 and on the upper surface of a portion of the second dielectric layer 11.

[0086] In this embodiment of the invention, the device structure obtained in S90 is sequentially immersed in acetone and isopropanol solutions, ultrasonically cleaned for 5 minutes each, then rinsed with deionized water and dried with high-purity nitrogen. After cleaning, an electroplating process is used to form a cathode thickening layer 12 with a thickness of 0.5 μm to 10 μm on the upper surface of the remaining cathode 10 and part of the upper surface of the second dielectric layer 11. In the electroplating bath, by controlling process parameters such as current density, temperature, and solution composition, precise control of the metal layer thickness and uniformity is achieved, thickening the metal electrode area to the required thickness. Annealing is used to eliminate defects in the deposition process and increase the crystallinity of the metal layer, resulting in a cathode thickening layer 12 with a thickness of 0.5 μm to 10 μm. Figure 3j As shown.

[0087] The low-cost fully vertical gallium nitride Schottky barrier diode fabrication method provided in this invention, based on the innovative device structure design of the first aspect, allows the use of epitaxial wafers grown on traditional silicon or sapphire substrates and gallium nitride nucleation technology during fabrication, avoiding the use of high-cost homogeneous gallium nitride substrates. This not only effectively reduces device fabrication costs, but also solves the current pooling effect of traditional heterogeneous substrate quasi-vertical planar gallium nitride Schottky barrier diodes, which is beneficial for industrial applications.

[0088] As for the method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple, and relevant details can be found in the description of the structural embodiment of the first aspect.

[0089] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0090] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0091] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a low-cost, all-vertical gallium nitride Schottky barrier diode, comprising: The preparation method comprises: ​ obtaining an epitaxial wafer; the epitaxial wafer comprises, from bottom to top, a substrate layer (1), a nucleation layer (2), a transport layer (3) and a drift layer (4); forming a positive electrode (5) on the middle of the upper surface of the drift layer (4), the positive electrode (5) forming a Schottky contact with the drift layer (4); forming a first dielectric layer (6) on the upper surface of the remaining drift layer (4), and the sidewall and part of the upper surface of the positive electrode (5); forming a positive electrode thickening layer (7) on the upper surface of the first dielectric layer (6), and the upper surface of the remaining positive electrode (5); obtaining a conductive substrate (8), and permanently bonding the conductive substrate (8) to the upper surface of the positive electrode thickening layer (7); forming an additional positive electrode (9) on the middle of the upper surface of the conductive substrate (8); turning over the entire device structure, and etching away the substrate layer (1) and the nucleation layer (2); forming a negative electrode (10) on the middle of the upper surface of the transport layer (3), the negative electrode (10) forming an ohmic contact with the transport layer (3); forming a second dielectric layer (11) on the upper surface of the remaining transport layer (3), and part of the upper surface of the negative electrode (10); forming a negative electrode thickening layer (12) on the upper surface of the remaining negative electrode (10), and part of the upper surface of the second dielectric layer (11).

2. The method of claim 1, wherein the method is a low-cost fabrication method of a full- vertical gallium nitride Schottky barrier diode, characterized by: forming a positive electrode thickening layer (7) on the upper surface of the first dielectric layer (6), and the upper surface of the remaining positive electrode (5) comprises: using an electroplating process to form a positive electrode thickening layer (7) with a thickness of 0.5 μm to 10 μm on the upper surface of the first dielectric layer (6), and the upper surface of the remaining positive electrode (5).

3. The method of claim 1, wherein the method further comprises: The obtained conductive substrate (8) is a low-resistance Si conductive substrate, a metal conductive substrate or a tungsten-copper alloy conductive substrate.

4. The method of claim 1, wherein the method further comprises: Before permanently bonding the conductive substrate (8) to the upper surface of the positive electrode thickening layer (7), it comprises: using an electroplating process to electroplate metal on the upper surface of the conductive substrate (8).

5. The method of claim 1, wherein the method further comprises: forming a negative electrode thickening layer (12) on the upper surface of the remaining negative electrode (10), and part of the upper surface of the second dielectric layer (11) comprises: using an electroplating process to form a negative electrode thickening layer (12) with a thickness of 0.5 μm to 10 μm on the upper surface of the remaining negative electrode (10), and part of the upper surface of the second dielectric layer (11).

6. A low-cost, all-vertical gallium nitride Schottky barrier diode, characterized by, The low-cost full-vertical gallium nitride Schottky barrier diode is prepared by the preparation method of any one of claims 1 to 5; the diode comprises: a transport layer (3); a drift layer (4) located on the lower surface of the transport layer (3); a positive electrode (5) located on the middle of the lower surface of the drift layer (4), and forming a Schottky contact with the drift layer (4); a negative electrode (10) located on the middle of the upper surface of the transport layer (3), and forming an ohmic contact with the transport layer (3); a first dielectric layer (6) located on the lower surface of the remaining drift layer (4), and the sidewall and part of the lower surface of the positive electrode (5); A second dielectric layer (11) is located on the upper surface of the remaining transmission layer (3) and the sidewall and part of the upper surface of the negative electrode (10); A positive electrode thickening layer (7) is located on the lower surface of the first dielectric layer (6) and the lower surface of the remaining negative electrode (10); A conductive substrate (8) is located on the lower surface of the positive electrode thickening layer (7); An additional positive electrode (9) is located in the middle of the lower surface of the conductive substrate (8); A negative electrode thickening layer (12) is located on part of the upper surface of the second dielectric layer (11) and the upper surface of the remaining negative electrode (10).

7. The low-cost, all-vertical gallium nitride Schottky barrier diode of claim 6, wherein the gallium nitride-based layer is a gallium nitride-based layer having a bandgap of 3.4 eV or greater. The thickness of the positive electrode thickening layer (7) is 0.5 μm to 10 μm.

8. The low-cost, all-vertical gallium nitride Schottky barrier diode of claim 6, wherein: The conductive substrate (8) is a low-resistance Si conductive substrate, a metal conductive substrate, or a tungsten-copper alloy conductive substrate.

9. The low-cost, all-vertical gallium nitride Schottky barrier diode of claim 6, wherein, The thickness of the negative electrode thickening layer (12) is 0.5 μm to 10 μm.

10. The low-cost, all-vertical gallium nitride Schottky barrier diode of claim 6, wherein, The thickness of the additional positive electrode (9) is 1 μm to 5 μm.

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