Transistor and display panel

Abstract

The present application discloses a transistor and a display panel. The transistor comprises a gate, an active layer, a first electrode, and a second electrode. By forming a Schottky contact between the first electrode of the transistor and a first sub-area within a first overlapping area, a Schottky barrier can be introduced at the contact surface of the first sub-area, and carriers must overcome the Schottky barrier when entering the first sub-area from the first electrode, so that the flow of the carriers within the first sub-area can be controlled, thereby reducing the saturation voltage, and thus reducing the power consumption of a driving circuit or a display panel to which the transistor is applied. In addition, by forming an ohmic contact between the first electrode of the transistor and a second sub-area within the first overlapping area, a low resistance at the contact surface of the second sub-area can be ensured, so that it can be ensured that the carriers can more easily enter the second sub-area from the first electrode, thereby increasing the on-state current of the transistor.

Description

Transistor and display panel TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a transistor and a display panel. BACKGROUND

[0002] A transistor is a device for controlling current.

[0003] Current transistors generally include a gate, a gate insulating layer, an active layer, a source and a drain, the active layer is electrically connected to the source and the drain, respectively, and the carrier concentration in the active layer can be regulated by adjusting the gate voltage, so that the output current between the source and the drain can be controlled. In a source-gate transistor, a Schottky barrier is introduced in the active layer, which can reduce the saturation voltage to achieve the effect of reducing power consumption.

[0004] However, in the above-mentioned source-gate transistor, the Schottky barrier will hinder the flow of carriers, thereby easily leading to a low on-state current of the transistor.

[0005] SUMMARY

[0006] Embodiments of the present application provide a transistor and a display panel. The technical solutions are as follows:

[0007] According to an aspect of the present application, a transistor is provided, which is distributed on a substrate, and the transistor includes a gate, an active layer, a first electrode and a second electrode.

[0008] The active layer includes a first overlap region and a second overlap region, and a channel region between the first overlap region and the second overlap region.

[0009] A normal projection of the gate on the substrate and a normal projection of the channel region on the substrate overlap, and the gate is insulated from the active layer.

[0010] The first electrode overlaps the first overlap region, and the first overlap region includes a first sub-region and a second sub-region, a Schottky contact can be formed between the first electrode and the first sub-region, and an Ohmic contact can be formed between the first electrode and the second sub-region.

[0011] The second electrode overlaps the second overlap region to form an Ohmic contact.

[0012] Optionally, the first sub-region is closer to the channel region than the second sub-region.

[0013] Optionally, the first overlap region further includes a third sub-region, the third sub-region is between the first sub-region and the channel region, and the first electrode overlaps the third sub-region to form an Ohmic contact.

[0014] Optionally, in the first overlap region, an area of a normal projection of a region forming ohmic contact with the first electrode on the substrate is greater than an area of a normal projection of a region forming Schottky contact with the first electrode on the substrate.

[0015] Optionally, a contact area of the first electrode with the first overlap region is greater than an area of a normal projection of a portion of the first electrode in contact with the first overlap region on the substrate.

[0016] Optionally, the transistor further comprises: a conductive structure embedded in the first overlap region, and the conductive structure is in contact with the first electrode.

[0017] Optionally, a material of the conductive structure comprises at least one of a metal nanowire, a carbon nanotube and graphene.

[0018] Optionally, the first overlap region, the channel region and the second overlap region are arranged in sequence along a first direction.

[0019] The active layer comprises: a first portion, and a second portion and a third portion connected to the first portion; the first portion is located on a side of the gate electrode away from the substrate; the second portion and the third portion are arranged on two sides of the gate electrode respectively in a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

[0020] The first electrode comprises: a fourth portion, and a fifth portion and a sixth portion connected to the fourth portion; the fourth portion is located on a side of the first portion away from the substrate and overlaps the first portion; the fifth portion is distributed on a side of the second portion away from the gate electrode in the second direction and overlaps the second portion; the sixth portion is distributed on a side of the third portion away from the gate electrode in the second direction and overlaps the third portion.

[0021] Optionally, the second portion and the third portion away from the first portion are flush with the fifth portion and the sixth portion away from the fourth portion, and flush with the gate electrode away from the first portion.

[0022] Optionally, in a direction perpendicular to the substrate, a thickness of the gate electrode ranges from 50 nanometers to 5 microns.

[0023] Optionally, the gate electrode is a columnar structure extending in a direction perpendicular to the substrate.

[0024] The active layer covers the gate electrode, wherein the first overlap region is distributed around the gate electrode, and the second overlap region is located on a side of the gate electrode away from the substrate.

[0025] The first electrode is sleeved outside the first overlap region, and the second electrode is located on a side of the second overlap region away from the substrate.

[0026] Optionally, the gate electrode has a circular, rectangular or polygonal shape in a cross section parallel to the substrate.

[0027] Optionally, the first overlap region and the second overlap region are doped with the same element material, wherein a doping concentration of the first overlap region in a region forming a Schottky contact with the first electrode is less than a doping concentration of the second overlap region in a region forming an Ohmic contact with the second electrode.

[0028] In another aspect, a transistor is provided, the transistor being distributed on a substrate, the transistor comprising: a gate electrode, an active layer, a first electrode and a second electrode;

[0029] The active layer comprises: a first overlap region and a second overlap region, and a channel region between the first overlap region and the second overlap region;

[0030] A normal projection of the gate electrode on the substrate overlaps a normal projection of the channel region on the substrate, and the gate electrode is insulated from the active layer;

[0031] The first electrode overlaps the first overlap region to form at least a Schottky contact, and the second electrode overlaps the second overlap region to form an Ohmic contact;

[0032] The contact area between the first electrode and the first overlap region is greater than the area of the normal projection of the part of the first electrode in contact with the first overlap region on the substrate.

[0033] In another aspect, a display panel is provided, the display panel comprising: a display structure and a driving circuit electrically connected to the display structure, the driving circuit comprising any of the above-mentioned transistors.

[0034] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0035] The first sub-region can introduce a Schottky barrier at the contact surface by forming a Schottky contact between the first electrode and the first sub-region in the first overlap region, and the carrier needs to overcome the Schottky barrier when entering the first sub-region from the first electrode, so that the first sub-region can control the flow of the carrier, thereby reducing the saturation voltage, and thus the power consumption of a driving circuit or a display panel using the transistor can be reduced. And the second sub-region can ensure that the resistance of the contact surface is small by forming an ohmic contact between the first electrode and the second sub-region in the first overlap region, so that the carrier can more easily enter the second sub-region from the first electrode, thereby improving the on-state current of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] FIG. 1 is a structural schematic diagram of a transistor provided by the related art;

[0038] FIG. 2 is a structural schematic diagram of a transistor provided by an embodiment of the present application;

[0039] FIG. 3 is a structural schematic diagram of another transistor provided by an embodiment of the present application;

[0040] FIG. 4 is a structural schematic diagram of another transistor provided by an embodiment of the present application;

[0041] FIG. 5 is a schematic diagram of a cross-sectional structure of the transistor provided by FIG. 2;

[0042] FIG. 6 is a structural schematic diagram of another transistor provided by an embodiment of the present application;

[0043] FIG. 7 is a schematic diagram of a cross-sectional structure of the transistor provided by FIG. 6;

[0044] FIG. 8 is a structural schematic diagram of another transistor provided by an embodiment of the present application;

[0045] FIG. 9 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0046] FIG. 10 is an equivalent circuit diagram of a driving circuit provided by an embodiment of the present application.

[0047] The specific embodiments of the present application have been shown by the above drawings, and will be described in more detail hereinafter. These drawings and detailed description are not intended to limit the scope of the present application in any way, but to illustrate the present application by referring to specific embodiments for the person skilled in the art. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in more detail below with reference to the drawings.

[0049] Please refer to FIG. 1, which is a structural schematic diagram of a transistor provided by the related art, the transistor 10 includes a gate 11, a gate insulating layer 12, an active layer 13, a source 14 and a drain 15. The transistor 10 shown in FIG. 1 is a source-gated transistor (SGT), compared with a field effect transistor, the source-gated transistor introduces a Schottky barrier, has lower saturation voltage, higher output impedance, lower carrier concentration, higher internal field and reduces short channel effect.

[0050] Among them, the source 14 and the first region 131 of the active layer 13 form a Schottky contact, and the drain 15 and the second region 132 of the active layer 13 form an Ohmic contact, that is, there is a Schottky barrier in the first region 131, which needs to be overcome when the carrier enters the active layer 13 from the source 14. Therefore, the Schottky barrier can control the flow of carriers, specifically, the region where the Schottky barrier is located will form a space charge region, under a small drain voltage, the space charge region corresponding to the Schottky barrier can extend to the entire channel, produce channel pinch-off, and cause current saturation, so as to reduce the saturation voltage of the transistor 10. Current saturation refers to the state that when the drain voltage reaches a certain value (saturation voltage), the current of the transistor no longer increases and remains at a stable value.

[0051] However, the Schottky barrier will also hinder the flow of carriers, thereby easily leading to low on-state current of the transistor 10. When the transistor 10 is used in the driving circuit of the display panel, the low on-state current of the transistor 10 also easily leads to insufficient brightness of the display panel.

[0052] The embodiments of the present application provide a transistor, please refer to FIG. 2, which is a structural schematic diagram of a transistor provided by the embodiments of the present application, the transistor 20 is distributed on a substrate A1, the substrate A1 is used to carry each film layer in the transistor 20, so as to facilitate the manufacture of the transistor 20. The substrate A1 can be a rigid substrate, for example, a glass substrate, the substrate A1 can also be a flexible substrate, for example, a polyimide (PI) substrate.

[0053] The transistor 20 includes a gate 21, an active layer 22, a first pole 23, and a second pole 24. Here, one of the first pole 23 and the second pole 24 is a source, and the other is a drain. For example, in the transistor 20 shown in FIG. 2, the first pole 23 can be a source, and the second pole 24 can be a drain. The source can serve as an input terminal of the transistor 20 to receive an external electrical signal or voltage, and the drain can serve as an output terminal of the transistor 20 to collect electrical charges flowing from the source and form an output current. For example, the materials of the first pole 23 and the second pole 24 can include metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof, or the first pole 23 and the second pole 24 can also be a titanium / aluminum / titanium (Ti / Al / Ti) multilayer structure including a titanium film layer, an aluminum film layer, and a titanium film layer stacked in sequence. In addition, the first pole 23 and the second pole 24 shown in FIG. 2 are in a same layer structure, but the embodiments of the present application are not limited thereto.

[0054] The active layer 22 includes a first overlap region 221 and a second overlap region 222, and a channel region 223 between the first overlap region 221 and the second overlap region 222. Here, the active layer 22 can serve as a main region for generation and flow of carriers (electrons or holes), wherein at least part of the first overlap region 221 is used for overlap with the first pole 23, at least part of the second overlap region 222 is used for overlap with the second pole 24, and the channel region 223 is used for forming a conductive channel. For example, the material of the active layer 22 can include low temperature poly-silicon (LTPS), amorphous silicon, oxide, etc. For example, the material of the active layer 22 can be indium gallium zinc oxide (InGaZnO4). a (Ga2O3) b (ZnO) c wherein a, b, and c are real numbers satisfying conditions of a≥0, b≥0, and c>0.

[0055] The normal projection of the gate 21 on the substrate 30 overlaps the normal projection of the channel region 223 on the substrate 30, and the gate 21 is insulated from the active layer 22. Here, by setting the gate 21 to at least overlap the channel region 223, it is ensured that the gate 21 can be used to control the formation or disappearance of a conductive channel of the channel region 223. The threshold voltage is the critical voltage of the on state and the off state of the transistor 20, when the voltage between the gate 21 and the source is greater than the threshold voltage, the channel region 223 will form a conductive channel, current can pass through, and the transistor 20 is in the on state. When the voltage between the gate 21 and the source is less than the threshold voltage, the conductive channel of the channel region 223 disappears, and the current cannot pass through, and the transistor 20 is in the off state. Therefore, by controlling the voltage of the gate 21 to control the formation or disappearance of the conductive channel, the transistor 20 can have a switching characteristic, so that the transistor 20 can be used in the driving circuit in the display panel. The material of the gate 21 can include, for example, metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. The gate 21 is insulated from the active layer 22, that is, an insulating layer 25 can be provided between the gate 21 and the active layer 22.

[0056] The first electrode 23 is in contact with the first contact region 221, and the first contact region 221 includes a first sub-region 221a and a second sub-region 221b. A Schottky contact can be formed between the first electrode 23 and the first sub-region 221a, and an Ohmic contact can be formed between the first electrode 23 and the second sub-region 221b.

[0057] The second electrode 24 is in contact with the second contact region 222 to form an Ohmic contact.

[0058] Here, the Ohmic contact refers to the case where the resistance of the contact surface between the metal (the first electrode 23 or the second electrode 24) and the semiconductor (the active layer 22) is very small, the current-voltage relationship is linear, and no obvious additional impedance is generated. In the Ohmic contact, there is no obvious potential barrier between the metal and the semiconductor, and the charge carriers can freely pass through the metal and the semiconductor, so that the formation of the Ohmic contact can improve the on-state current of the transistor 20. The Schottky contact refers to the case where when the metal and the semiconductor material are in contact, the energy band of the semiconductor is bent at the interface to form a potential barrier, which is called the Schottky barrier. This potential barrier can control the flow of charge carriers, thereby realizing the rectification and modulation of current, so that the formation of the Schottky contact can reduce the saturation voltage of the transistor 20. By setting the Schottky contact between the first electrode 23 and the active layer 22 and the Ohmic contact, it can be ensured that the transistor 20 has a lower saturation voltage and a higher on-state current.

[0059] In summary, the transistor provided by the embodiments of the present application forms a Schottky contact between the first electrode and the first sub-region in the first overlap region, so that the first sub-region can introduce a Schottky barrier at the contact surface, and the carrier needs to overcome the Schottky barrier when entering the first sub-region from the first electrode, thus the first sub-region can control the flow of the carrier, reduce the saturation voltage, and thus the power consumption of the driving circuit or display panel using the transistor can be reduced. Moreover, the transistor forms an Ohmic contact between the first electrode and the second sub-region in the first overlap region, so that the second sub-region can ensure that the resistance of the contact surface is small, thus the carrier can more easily enter the second sub-region from the first electrode, and thus the on-state current of the transistor can be improved.

[0060] In the present application, a way to improve the on-state current is to regulate the energy band distribution of the active layer, and the way to regulate the energy band distribution of the active layer is described as follows:

[0061] Referring to FIG. 2, the embodiments of the present application can regulate the energy band distribution of the active layer by a regionally doped way, specifically, the doping degree of each region in the active layer 22 can be changed to form an Ohmic contact or a Schottky contact. The doping process can be ion implantation, and the doping concentration and depth can be controlled by the implantation energy, angle and dose, thus the doping process is more accurate than the traditional diffusion doping process. The doped material can include elements such as phosphorus (P), boron (B), and arsenic (As).

[0062] Optionally, the first overlap region 221 and the second overlap region 222 are doped with the same element material, and the doping concentration of the region where the first overlap region 221 forms a Schottky contact with the first electrode 23 is less than the doping concentration of the region where the second overlap region 222 forms an Ohmic contact with the second electrode 24.

[0063] For the transistor 20 shown in FIG. 2, the first sub-region 221a in the first overlap region 221 is lightly doped, and since the doping concentration of the first sub-region 221a is low, the Fermi level difference between the first electrode 23 and the first sub-region 221a is large, forming a clear barrier, i.e., a Schottky barrier, so that a Schottky contact can be formed. The second overlap region 222 is heavily doped, and since the doping concentration of the second overlap region 222 is high, the space charge region in the second overlap region 222 is narrow, and the carrier can easily tunnel through the space charge region, i.e., an Ohmic contact is formed. Similarly, the second sub-region 221b in the first overlap region 221 is also heavily doped, and thus an Ohmic contact can be formed between the first electrode 23 and the second sub-region 221b.

[0064] For example, the first overlap region 221 and the second overlap region 222 are both doped with boron by ion implantation, wherein the first sub-region 221a has a doping concentration ranging from 0 to 10 14 atoms per square centimeter (atoms / cm 2 ), the ion implantation energy ranges from 0 to 40 kilovolts (kV), and the second sub-region 221b and the second overlap region 222 have a doping concentration greater than 10 14 atoms per square centimeter and an ion implantation energy greater than 40 kV.

[0065] In addition, the channel region 223 can be undoped, or the channel region 223 can be doped to change the ease of formation of a conductive channel, i.e., to achieve the effect of regulating the threshold voltage. For example, the channel region 223 can be lightly doped.

[0066] Optionally, referring to FIG. 2, the first sub-region 221a is closer to the channel region 223 than the second sub-region 221b. Therefore, for the carriers flowing out of the first electrode 23, a part of the carriers flow to the channel region 223 through the first sub-region 221a, and another part of the carriers flow to the first sub-region 221a through the second sub-region 221b and then flow to the channel region 223. In this way, it can be ensured that the carriers flowing out of the first electrode 23 are all controlled by the Schottky barrier, so that the saturation voltage of the transistor 20 can be ensured to be low, and thus the power consumption of a drive circuit or a display panel using the transistor 20 can be reduced.

[0067] Another transistor is provided in an embodiment of the present application. Referring to FIG. 3, FIG. 3 is a structural schematic diagram of another transistor provided in an embodiment of the present application. The transistor 20 includes a gate electrode 21, an active layer 22, a first electrode 23, a second electrode 24, and an insulating layer 25.

[0068] The first overlap region 221 further includes a third sub-region 221c located between the first sub-region 221a and the channel region 223, and the first electrode 23 is in ohmic contact with the third sub-region 221c. In this way, based on the embodiment shown in FIG. 2, the embodiment shown in FIG. 3 adds the third sub-region 221c that can form ohmic contact. Therefore, for the carriers flowing out of the first electrode 23, a part of the carriers directly flow to the channel region 223 from the third sub-region 221c, and the part of the carriers are not hindered and pinched off by the Schottky barrier, and can provide additional current, so that the on-state current of the transistor 20 can be further improved.

[0069] The third sub-region 221c, the channel region 223 and the second overlap region 222 can also constitute an active layer of a transistor in the related art. Therefore, the transistor 20 shown in FIG. 3 is equivalent to a transistor in the related art connected in parallel, and the saturation voltage of the transistor 20 is increased. By adjusting the area ratio of the third sub-region 221c in the first overlap region 221, the demand for saturation voltage and on-state current can be balanced to some extent. For example, when the required saturation current is low, the area ratio of the third sub-region 221c can be reduced, or the third sub-region 221c can not be provided. When the required on-state current is high, the area ratio of the third sub-region 221c can be increased.

[0070] The substrate A1 can also be provided with a functional film layer A2. The functional film layer A2 can have an insulating and barrier effect, and can increase the bonding force between the film layer on the substrate A1, such as the gate 21, and the substrate A1, thereby preventing the gate 21 from peeling off. The functional film layer A2 can include a buffer layer (buffer). When the substrate A1 includes polyimide, the functional film layer A2 can also include a barrier layer (barrier). For example, the material of the functional film layer A2 can include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, zirconium oxide, etc. The functional film layer A2 can have a single-layer structure or a laminated structure. For example, the laminated structure can be silicon nitride / silicon oxide (SiN / SiO2), or silicon oxide / silicon nitride / silicon oxide (SiO2 / SiN / SiO2). X X / SiO2).

[0071] In the transistor 20 shown in FIGS. 2 and 3, the gate 21 is located between the substrate A1 and the active layer 22, i.e., the transistor 20 is a bottom-gate type. In addition, the gate 21 can also be located on the side of the active layer 22 away from the substrate A1, i.e., the transistor 20 is a top-gate type. The gate 21 and the active layer 22 are insulated, i.e., an insulating layer 25 can be provided between the gate 21 and the active layer 22 to avoid short circuit or leakage between the gate 21 and the active layer 22, thereby ensuring the running stability of the transistor 20.

[0072] ​The insulating layer 25 can include a gate insulating layer (GI) 251 and an interlayer dielectric (ILD) 252 stacked in a direction away from the substrate A1. The gate insulating layer 251 can be used to insulate the gate 21 and the active layer 22, and can include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, zirconium oxide, etc. The interlayer dielectric layer 252 can be used to insulate the active layer 22 and the first electrode 23, and can include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, zirconium oxide, etc. For example, the interlayer dielectric layer 252 can be a stacked structure of a first sub-layer 252a (silicon nitride) and a second sub-layer 252b (silicon oxide).

[0073] Optionally, in the first overlap region 221, the area of the orthographic projection of the region forming ohmic contact with the first electrode 23 on the substrate A1 is greater than the area of the orthographic projection of the region forming Schottky contact with the first electrode 23 on the substrate A1. The greater the area of the orthographic projection of the region forming ohmic contact on the substrate A1, the easier the current carriers of the first electrode 23 flow into the active layer 23, and the greater the on-state current of the transistor 20, so that the degree of improvement of the on-state current of the transistor 20 can be ensured.

[0074] For the transistor 20 shown in FIG. 2, that is, the contact area of the second sub-region 221b and the first electrode 23 is greater than the contact area of the first sub-region 221a and the first electrode 23. For example, the area ratio of the orthographic projection of the second sub-region 221b and the first sub-region 221a on the substrate A1 can be 2:1. For the transistor 20 shown in FIG. 3, that is, the sum of the contact areas of the second sub-region 221b and the third sub-region 221c and the first electrode 23 is greater than the contact area of the first sub-region 221a and the first electrode 23.

[0075] In this application, the area of the orthographic projection of the region forming ohmic contact with the first electrode 23 on the substrate A1 can also be less than or equal to the area of the orthographic projection of the region forming Schottky contact with the first electrode 23 on the substrate A1. For example, in the transistor 20 shown in FIG. 2, the area ratio of the orthographic projection of the second sub-region 221b and the first sub-region 221a on the substrate A1 can also be 1:1 or 1:2, etc. Compared with the related art, the on-state current can also be increased to a certain extent.

[0076] In this application, another way to improve the on-state current is to control the contact area of the first electrode and the active layer.

[0077] Please refer to FIG. 4, which is a structural schematic diagram of another transistor provided by an embodiment of the present application. The contact area of the first electrode 23 and the first overlap region 221 is greater than the area of the orthogonal projection of the part of the first electrode 23 in contact with the first overlap region 221 on the substrate A1. In the related art, the contact area of the first electrode and the active layer is the area of the orthogonal projection of the part of the active layer in contact with the first electrode on the substrate. Therefore, compared with the related art, the transistor 20 provided by the embodiment of the present application can effectively increase the contact area of the first electrode 23 and the first overlap region 221, so that more carriers can pass through the channel region 223 under the same gate voltage, thereby further improving the on-state current of the transistor 20.

[0078] The present application can increase the contact area of the first electrode and the active layer through various exemplary embodiments, which are described below by way of three exemplary embodiments:

[0079] The first exemplary embodiment is described with reference to FIG. 4. The transistor 20 further includes a conductive structure 26 embedded in the first overlap region 221, and the conductive structure 26 is in contact with the first electrode 23. On the one hand, the conductive structure 26 is not completely covered by the active layer 22, that is, a part of the conductive structure 26 is exposed outside the material of the active layer 22 and is in contact with the first electrode 23, so that the conductive structure 26 can increase the contact area of the first electrode 23 and the first overlap region 221, thereby increasing the on-state current of the transistor 20. On the other hand, the conductive structure 26 has good conductivity, so that the carriers of the first electrode 23 can flow to the channel region 223 through the conductive structure 26, thereby increasing the on-state current of the transistor 20.

[0080] Optionally, the material of the conductive structure 26 includes at least one of a metal nanowire, a carbon nanotube, and graphene. The metal nanowire, the carbon nanotube, and the graphene all have high conductivity and specific surface area, which can reduce the difficulty of the carriers flowing from the first electrode 23 to the second electrode 24 and increase the size of the channel available for the carriers to pass through, thereby improving the on-state current of the transistor 20. Exemplarily, the metal nanowire can include silver nanowire or copper nanowire.

[0081] In addition, in the present application, the area of the orthogonal projection of the first electrode 23 on the substrate A1 can be greater than the area of the orthogonal projection of the second electrode 24 on the substrate A1. Specifically, a larger opening can be provided for the first electrode 23 on the insulating layer 25 to increase the area of the first electrode 23. Here, the first electrode 23 serves as an input terminal, and by increasing the area of the first electrode 23, the contact area of the first electrode 23 and the active layer 22 can also be increased to allow more carriers to flow in from the first electrode 23.

[0082] Referring to FIG. 2 and FIG. 5, the first overlap region 221, the channel region 223 and the second overlap region 222 are arranged in the first direction X in sequence.

[0083] The active layer 22 includes a first portion C1, and a second portion C2 and a third portion C3 connected to the first portion C1. The first portion C1 is located on a side of the gate 21 away from the substrate A1. The second portion C2 and the third portion C3 are arranged on two opposite sides of the gate 21 in the second direction Y, respectively. The second direction Y is parallel to the substrate A1 and perpendicular to the first direction X. Since the gate 21 has a certain thickness, the active layer 22 can cover the upper surface and the side surface of the gate 21, so as to increase the area of the active layer 22. Moreover, the greater the thickness of the gate 21, the greater the area of the active layer 22.

[0084] The first electrode 23 includes a fourth portion D1, and a fifth portion D2 and a sixth portion D3 connected to the fourth portion D1. The fourth portion D1 is located on a side of the first portion C1 away from the substrate A1, and overlaps the first portion C1. The fifth portion D2 is arranged on a side of the second portion C2 away from the gate 21 in the second direction Y, and overlaps the second portion C2. The sixth portion D3 is arranged on a side of the third portion C3 away from the gate 21 in the second direction Y, and overlaps the third portion C3.

[0085] Since the area of the active layer 22 is increased, the first electrode 23 covers the first portion C1, the second portion C2 and the third portion C3 of the active layer 22, so as to increase the contact area between the first electrode 23 and the active layer 22. Therefore, the embodiment of the present application can increase the contact area between the first electrode 23 and the active layer 22 by increasing the thickness of the gate 21, and the thickness of the gate 21 is positively correlated with the contact area, so as to control the on-state current of the transistor 20.

[0086] Optionally, the side of the second portion C2 and the third portion C3 away from the first portion C1 is flush with the side of the fifth portion D2 and the sixth portion D3 away from the fourth portion D1, and is flush with the side of the gate 21 away from the first portion C1. That is, at least in the region corresponding to the overlap between the active layer 22 and the first electrode 23, the sides of the gate 21, the active layer 22 and the first electrode 23 close to the substrate A1 are flush, so as to ensure that the active layer 22 covers the gate 21, and the first electrode 23 covers the active layer 22, thereby ensuring that the contact area between the first electrode 23 and the active layer 22 is increased, and the on-state current of the transistor 20 is improved.

[0087] Optionally, the thickness of the gate 21 in the direction perpendicular to the substrate A1 ranges from 50 nanometers to 5 micrometers. The thickness of the gate 21 in this range can effectively increase the contact area of the first electrode 23 and the active layer 22, thereby increasing the on-state current of the transistor 20.

[0088] It should be noted that the first sub-region 221a corresponds to the structure of the first electrode 23 at the overlapping position, and the structure of the second sub-region 221b corresponding to the first electrode 23 at the overlapping position can also be referred to Figure 5, and the embodiments of the present application will not be described here.

[0089] A third exemplary embodiment is described with reference to Figure 6 and Figure 7. Figure 6 is a schematic structural diagram of another transistor provided by the embodiments of the present application, and Figure 7 is a schematic cross-sectional structural diagram of the transistor provided by Figure 6 (Figure 7 can be a schematic cross-sectional structural diagram of the transistor provided by Figure 6 at B2-B2). The transistor 20 shown in Figure 6 and Figure 7 can be a vertical transistor. The gate 21 is a columnar structure extending in the direction perpendicular to the substrate A1, and the side surface of the columnar structure has a large area.

[0090] The active layer 22 covers the gate 21, wherein the first overlapping region 221 is distributed around the gate 21, and the second overlapping region 222 is located on the side of the gate 21 away from the substrate A1. That is, the first overlapping region 221 is annular and surrounds the side surface of the gate 21. Therefore, compared with the related art in which the active layer is located on one side of the gate, the annular first overlapping region 221 in the transistor 20 provided by the embodiments of the present application can effectively increase the area of the first overlapping region 221.

[0091] The first electrode 23 is sleeved outside the first overlapping region 221, and the second electrode 24 is located on the side of the second overlapping region 222 away from the substrate A1. That is, the first electrode 23 is also annular and surrounds the outside of the first overlapping region 221. Such an annular first electrode 23 facilitates contact with the first overlapping region 221, can increase the contact area of the first electrode 23 and the active layer 22, and thereby increase the on-state current of the transistor 20.

[0092] Optionally, the cross-sectional shape of the gate 21 in the direction parallel to the substrate A1 is circular, rectangular or polygonal. These shapes can effectively increase the contact area of the first electrode 23 and the active layer 22 and facilitate manufacturing. In addition, the cross-sectional shape of the gate 21 provided by the present application is not limited to this, and the gate 21 can also be other shapes with a high surface area to increase the contact area of the first electrode 23 and the active layer 22.

[0093] In summary, the embodiment of the present application provides a transistor. By forming a Schottky contact between the first electrode and the first sub-region in the first overlap region in the transistor, the first sub-region can introduce a Schottky barrier at the contact surface, and the carrier needs to overcome the Schottky barrier when entering the first sub-region from the first electrode, so that the first sub-region can control the flow of the carrier, reduce the saturation voltage, and thus reduce the power consumption of the driving circuit or display panel using the transistor. And by forming an ohmic contact between the first electrode and the second sub-region in the first overlap region in the transistor, the second sub-region can ensure that the resistance of the contact surface is small, so that the carrier can more easily enter the second sub-region from the first electrode, thereby improving the on-state current of the transistor.

[0094] In another aspect, the embodiment of the present application also provides another kind of transistor. Please refer to FIG. 8, which is a structural schematic diagram of another kind of transistor provided by the embodiment of the present application. The transistor 20 is distributed on the substrate A1, and the transistor 20 includes a gate 21, an active layer 22, a first electrode 23 and a second electrode 24.

[0095] The active layer 22 includes a first overlap region 221 and a second overlap region 222, and a channel region 223 between the first overlap region 221 and the second overlap region 222.

[0096] The orthogonal projection of the gate 21 on the substrate 30 and the orthogonal projection of the channel region 223 on the substrate 30 overlap, and the gate 21 is insulated from the active layer 22.

[0097] The first electrode 23 is overlapped with the first overlap region 221 to form at least a Schottky contact, and the second electrode 24 is overlapped with the second overlap region 222 to form an ohmic contact.

[0098] The contact area of the first electrode 23 and the first overlap region 221 is greater than the area of the orthogonal projection of the part of the first electrode 23 in contact with the first overlap region 221 on the substrate A1.

[0099] The transistor 20 shown in FIG. 8 only increases the contact area of the first electrode 23 and the active layer 22, and does not change the band distribution of the first overlap region 221, so as to also improve the on-state current of the transistor 20.

[0100] The present application can improve the contact area of the first electrode and the active layer through various exemplary embodiments, which will be described below by taking three exemplary embodiments as examples:

[0101] In the first exemplary embodiment, please refer to FIG. 8, the transistor 20 further includes a conductive structure 26, which is embedded in the first overlap region 221, and the conductive structure 26 is in contact with the first electrode 23.

[0102] Optionally, the material of the conductive structure 26 comprises at least one of a metal nanowire, a carbon nanotube, and graphene.

[0103] In a second exemplary embodiment, the first overlap region, the channel region, and the second overlap region are arranged in sequence along a first direction.

[0104] The active layer comprises a first portion, and a second portion and a third portion connected to the first portion; the first portion is located on a side of the gate away from the substrate; the second portion and the third portion are arranged on two sides of the gate respectively in a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

[0105] The first electrode comprises a fourth portion, and a fifth portion and a sixth portion connected to the fourth portion; the fourth portion is located on a side of the first portion away from the substrate and overlaps the first portion; the fifth portion is distributed on a side of the second portion away from the gate in the second direction and overlaps the second portion; the sixth portion is distributed on a side of the third portion away from the gate in the second direction and overlaps the third portion.

[0106] Optionally, the sides of the second portion and the third portion away from the first portion are flush with the sides of the fifth portion and the sixth portion away from the fourth portion, and flush with the side of the gate away from the first portion.

[0107] Optionally, in a direction perpendicular to the substrate, the thickness of the gate ranges from 50 nanometers to 5 micrometers.

[0108] In addition, the structure of the transistor provided by the second exemplary embodiment can also refer to the embodiment shown in FIG. 5, and details are not described herein.

[0109] In a third exemplary embodiment, the gate is a columnar structure extending in a direction perpendicular to the substrate.

[0110] The active layer covers the gate, wherein the first overlap region is distributed around the gate, and the second overlap region is located on a side of the gate away from the substrate.

[0111] The first electrode is sleeved outside the first overlap region, and the second electrode is located on a side of the second overlap region away from the substrate.

[0112] Optionally, the gate has a circular, rectangular, or polygonal cross-sectional shape in a direction parallel to the substrate.

[0113] In addition, the structure of the transistor provided by the third exemplary embodiment can also refer to the embodiment shown in FIG. 6, and details are not described herein.

[0114] In summary, the embodiment of the present application provides a transistor. By forming a Schottky contact between the first electrode and the first sub-region in the first overlap region, the first sub-region can introduce a Schottky barrier at the contact surface, and the carrier needs to overcome the Schottky barrier when entering the first sub-region from the first electrode, so that the first sub-region can control the flow of the carrier, reduce the saturation voltage, and thus reduce the power consumption of the driving circuit or display panel using the transistor. And by forming an ohmic contact between the first electrode and the second sub-region in the first overlap region, the second sub-region can ensure that the resistance of the contact surface is small, so that the carrier can more easily enter the second sub-region from the first electrode, thereby improving the on-state current of the transistor.

[0115] In another aspect, the embodiment of the present application provides a display panel. Please refer to FIG. 9, which is a structural schematic diagram of a display panel provided by an embodiment of the present application. The display panel 30 includes a display structure and a driving circuit electrically connected with the display structure, and the driving circuit includes the transistor provided by any of the above-mentioned embodiments.

[0116] The display panel 30 includes a display area 30a and a non-display area 30b. The display area 30a is provided with a plurality of pixel units 31 arranged in an array, and FIG. 9 only shows one pixel unit 31 as an example. Each pixel unit 31 is composed of a display structure and a driving circuit. Since the display structure is electrically connected with the driving circuit, the driving circuit can be used for driving, so as to realize the display function. Therefore, the display area 30a can be used for displaying images and texts. The non-display area 30b is provided with a control circuit, a carrier element and an auxiliary structure. For example, the control circuit can include a gate on array (GOA), which can output a gate scanning driving signal to the pixel driving circuit in the display area 30a. The carrier element can include structures such as a flexible circuit board and a chip. The auxiliary structure can include structures such as a packaging barrier dam and a crack barrier dam. The non-display area 30b shown in FIG. 9 surrounds the display area 30a, and in addition, at least one non-display area 30b can be arranged in the display area 30a. For example, the display panel 30 can be provided with an aperture area such as a camera hole, and the position corresponding to the aperture area can also be provided with a non-display area 30b. In addition, the shapes of the display area 30a and the non-display area 30b can include rectangles, circles, ellipses or spline curves. Both the display area 30a and the non-display area 30b can have the ability of bending, folding or curling.

[0117] Exemplarily, the display structure can be a light emitting element such as an organic light emitting diode (OLED). Since the OLED light emitting element can be a current driven device, the driving current of the driving circuit will directly affect the luminous brightness of the OLED light emitting element, and thus can affect the display effect of the display panel. An exemplary driving circuit is shown in FIG. 10, which is an equivalent circuit diagram of a driving circuit provided by an embodiment of the present application. The driving circuit includes seven transistors (T1, T2, T3, T4, T5, T6, T7) and a storage capacitor (Cst), i.e., the driving circuit is a 7T1C structure. The transistors shown in FIG. 10 can be P-type metal oxide semiconductor (PMOS) transistors, but the embodiments of the present application are not limited thereto, and can also be N-type metal oxide semiconductor (NMOS) transistors or complementary metal oxide semiconductor (CMOS) transistors.

[0118] wherein VSS is a first power signal, R1 is a first reset control signal, R2 is a second reset control signal, EM is a light emitting control signal, G1 is a first gate signal, G2 is a second gate signal, V d is a data signal, VDD is a second power signal, and N1 is a first node.

[0119] The seven transistors of the driving circuit are switching transistors (T1, T2, T4-T7) and a driving transistor (T3). Exemplarily, the driving transistor can be any of the transistors provided by the above embodiments. On the one hand, the on-state current of the transistors provided by the above embodiments is high, which can ensure that the driving circuit can normally drive the display structure, so that the pixel unit 31 can emit light with the required brightness, avoiding the problem of insufficient brightness of the display panel 30. On the other hand, the saturation voltage of the transistors provided by the above embodiments is low, which can reduce the power consumption of the driving circuit or the display panel to which the driving circuit is applied, and thus can reduce the power consumption of the display panel 30.

[0120] In summary, the display panel provided by the embodiments of the present application forms a Schottky contact between the first electrode in the transistor and the first sub-region in the first overlap region, so that the first sub-region can introduce a Schottky barrier at the contact surface, and the carrier needs to overcome the Schottky barrier when entering the first sub-region from the first electrode, so that the first sub-region can control the flow of the carrier, reduce the saturation voltage, and thus reduce the power consumption of the transistor. And the first electrode in the transistor and the second sub-region in the first overlap region form an ohmic contact, so that the second sub-region can ensure that the resistance of the contact surface is small, so that the carrier can more easily enter the second sub-region from the first electrode, thereby improving the on-state current of the transistor, and thus avoiding the problem of insufficient brightness of the display panel caused by the small on-state current of the transistor.

[0121] The term "at least one of A and B" in the present application is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, at least one of A and B can mean that A exists alone, A and B exist together, and B exists alone. Similarly, "at least one of A, B and C" means that there can be seven relationships, which can mean that A exists alone, B exists alone, C exists alone, A and B exist together, A and C exist together, C and B exist together, and A, B and C exist together.

[0122] It should be noted that in the drawings, the sizes of the layers and regions can be exaggerated for clarity. Also, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can be present. Further, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers or elements can be present. In addition, it can be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers or elements can be present. Similar reference numerals can designate similar elements throughout the specification.

[0123] In the present application, the terms "first", "second", "third", "fourth", "fifth" and "sixth" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "a plurality of" means two or more, unless otherwise explicitly limited.

[0124] The above only describes optional embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A transistor, comprising: The transistor is distributed on a substrate, and comprises a gate, an active layer, a first electrode and a second electrode; The active layer comprises a first overlap region and a second overlap region, and a channel region between the first overlap region and the second overlap region; A normal projection of the gate on the substrate and a normal projection of the channel region on the substrate overlap each other, and the gate is insulated from the active layer; The first electrode overlaps the first overlap region, and the first overlap region comprises a first sub-region and a second sub-region, a Schottky contact can be formed between the first electrode and the first sub-region, and an Ohmic contact can be formed between the first electrode and the second sub-region; The second electrode overlaps the second overlap region to form an Ohmic contact.

2. The transistor of claim 1, wherein The first sub-region is closer to the channel region than the second sub-region.

3. The transistor of claim 2, wherein The first overlap region further comprises a third sub-region, the third sub-region is between the first sub-region and the channel region, and the first electrode overlaps the third sub-region to form an Ohmic contact.

4. The transistor according to any one of claims 1 to 3, wherein In the first overlap region, an area of a normal projection of a region forming an Ohmic contact with the first electrode on the substrate is greater than an area of a normal projection of a region forming a Schottky contact with the first electrode on the substrate.

5. The transistor according to any one of claims 1 to 3, wherein A contact area of the first electrode and the first overlap region is greater than an area of a normal projection of a part of the first electrode contacting the first overlap region on the substrate.

6. The transistor of claim 5, wherein The transistor further comprises a conductive structure, the conductive structure is embedded in the first overlap region, and the conductive structure is in contact with the first electrode.

7. The transistor of claim 6, wherein A material of the conductive structure comprises at least one of a metal nanowire, a carbon nanotube and graphene.

8. The transistor of claim 5, wherein The first overlap region, the channel region and the second overlap region are arranged in a first direction in sequence; The active layer comprises a first part, and a second part and a third part connected to the first part; the first part is located on a side of the gate away from the substrate; the second part and the third part are arranged on two sides of the gate respectively in a second direction; the second direction is parallel to the substrate and perpendicular to the first direction; The first electrode comprises a fourth part, and a fifth part and a sixth part connected to the fourth part; the fourth part is located on a side of the first part away from the substrate and overlaps the first part; the fifth part is distributed on a side of the second part away from the gate in the second direction and overlaps the second part; the sixth part is distributed on a side of the third part away from the gate in the second direction and overlaps the third part.

9. The transistor of claim 8, wherein Sides of the second part and the third part away from the first part are flush with sides of the fifth part and the sixth part away from the fourth part, and are flush with a side of the gate away from the first part.

10. The transistor of claim 8, wherein In a direction perpendicular to the substrate, a thickness of the gate ranges from 50 nanometers to 5 micrometers.

11. The transistor of claim 5, wherein The gate is a columnar structure extending in a direction perpendicular to the substrate. The active layer covers the gate, wherein the first overlap region is distributed around the gate, and the second overlap region is located on a side of the gate away from the substrate; The first electrode is sleeved outside the first overlap region, and the second electrode is located on a side of the second overlap region away from the substrate.

12. The transistor of claim 11, wherein The gate has a cross-sectional shape parallel to the substrate, which is circular, rectangular or polygonal.

13. The transistor of any of claims 1-3, 6-12, wherein, The first overlap region and the second overlap region are doped with the same element material, wherein the doping concentration of the region where the first overlap region forms a Schottky contact with the first electrode is less than the doping concentration of the region where the second overlap region forms an ohmic contact with the second electrode.

14. A transistor, comprising: The transistor is distributed on a substrate, and the transistor comprises a gate, an active layer, a first electrode and a second electrode. The active layer comprises a first overlap region and a second overlap region, and a channel region between the first overlap region and the second overlap region; The gate has a cross-sectional shape parallel to the substrate, which is circular, rectangular or polygonal. The first electrode and the first overlap region form at least a Schottky contact, and the second electrode and the second overlap region form an ohmic contact; The contact area between the first electrode and the first overlap region is greater than the area of the projection of the part of the first electrode in contact with the first overlap region on the substrate.

15. A display panel, characterized by The display panel comprises a display structure and a driving circuit electrically connected to the display structure, and the driving circuit comprises the transistor according to any one of claims 1 to 14.

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