SIC groove type device with embedded junction barrier Schottky diode

Abstract

The invention discloses a SiC trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an embedded junction Schottky barrier diode (JBSD), which is provided with a P shielding (PS) region surrounding the bottom of a source-body Schottky contact (SBSC) trench, so as to reduce the electric field intensity and switching loss of a gate oxide layer. And the source metal is directly connected with the PS region and the JBSD region. A sidewall P (SP) region is formed along a partial region of the sidewall of the SBSC trench to improve tradeoff between drain-source drain current of the SiC trench MOSFET and forward voltage of the JBSD. The device further comprises an N shielding region formed below each gate trench so as to reduce the electric field intensity and the specific on-resistance of the gate oxide layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to a silicon carbide (SiC) trench metal oxide semiconductor field effect transistor (MOSFET) having an embedded junction barrier Schottky diode (JBSD) formed along the sidewall of a source-body-Schottky contact (SBSC) trench, which inactivates the parasitic body diode to reduce the loss of the turn-off switch without reducing the channel density. A sidewall P (SP) region is formed along the SBSC trench to adjust the JBSD region to improve the trade-off between drain-source leakage current and JBSD forward voltage. The device further includes a current diffusion region located below the body region and surrounding the gate trench to obtain a lower specific on-resistance. Background Art

[0002] Due to the physical properties of SiC, SiC-MOSFETs have higher breakdown voltage, lower on-resistance and faster switching speed than Si-MOSFETs. However, due to the poor interface state between SiC and the gate oxide layer, SiC-MOSFETs require a higher gate-source voltage Vgs to fully open the device channel. Therefore, compared with Si-MOSFETs, SiC-MOSFETs have a higher gate oxide layer electric field strength. For example, for Si devices, Vgs = 10V can fully open the device channel, but for SiC devices, Vgs = 18V can fully open the device channel. The higher the Vgs, the higher the gate oxide layer electric field strength will be, which will lead to device reliability issues.

[0003] FIG1 is a cross-sectional view of a semiconductor device disclosed in the prior art (US2022 / 0190117 A1), which has a p+ shielding region 52 located below the trench gate region 60 for reducing the electric field strength of the gate oxide layer, and an embedded Schottky barrier diode (SBD) for reducing switching losses. A metal layer 81 is deposited in the source contact trench to form an SBD having an n-type layer 20 along the sidewalls and bottom of the second trench. However, the SBD formed at the bottom of the second trench as shown in FIG1 will suffer from a severe barrier lowering effect, resulting in a high drain-source leakage current and thus early breakdown of the device.

[0004] Therefore, in the field of design and manufacturing of SiC semiconductor devices, there is still a need to provide a new unit structure, device structure and manufacturing method to solve the difficulties and limitations involved above, so that SiC trench devices have lower gate oxide layer electric field strength, obtain lower on-resistance and lower switching loss. Summary of the invention

[0005] The present invention discloses a novel SiC trench MOSFET having an embedded junction barrier Schottky diode (JBSD), wherein the JBSD comprises two P-type-N-type (PN) junction diodes and a Schottky barrier diode (SBD) formed along a source-body-Schottky contact (SBSC) trench. The device having the JBSD structure solves the high leakage current problem existing in high-voltage SiC-SBD devices.

[0006] The SBSC trench passes through a source region with a first conductivity type and a body region with a second conductivity type, and extends into the epitaxial layer; a P shielding (PS) region with a second conductivity type, which is used to reduce the electric field strength of the gate oxide layer, surrounds the bottom of the SBSC trench and is separated from the gate trench; since the trench depth of the SBSC trench is greater than the trench depth of the gate trench, the PS region can effectively reduce the electric field strength of the gate oxide layer without the need to set an additional PS region under the gate trench (as shown in FIG. 1). A sidewall P (SP) region with a second conductivity type is selectively formed along a portion of the sidewall of the SBSC trench, which connects the PS region to the body contact region, so as to improve the drain-source leakage current I by adjusting the overlap area between the SP region and the SBSC trench. dsl and JBSD's forward voltage V f a body contact region with a second conductivity type is formed in the body region to form an ohmic contact with the source metal; at least one conductive material used as the source metal is filled into the SBSC trench to form an ohmic contact with the source region and the body contact region and a Schottky contact with the epitaxial layer; a JBSD is formed between the source region and the bottom of the buried PS region, which includes two PN junction diodes and one SBD; a first PN junction diode is formed between the body combination region (including the body region and the body contact region) and the epitaxial layer, and a second PN junction diode is formed between the PS region and the epitaxial layer; an SBD is formed between the body contact region and the PS region by establishing a Schottky contact with the epitaxial layer.

[0007] According to one aspect of the present invention, a SiC power device comprising a plurality of units is disclosed, wherein each unit is located in an active region, and further comprises: an epitaxial layer having a first conductivity type, which is located on a substrate; at least one gate trench, which is surrounded by a source region having the first conductivity type, the source region being located in a body region having a second conductivity type and being located on an upper portion of the epitaxial layer; a gate, which is located in the gate trench and is surrounded by a first insulating layer located at the bottom of the gate trench and a gate oxide layer located at a sidewall of the gate trench, and the thickness of the first insulating layer is greater than that of the gate oxide layer; an N shielding (NS) region having a first conductivity type, which is located directly below the gate and is used to protect the gate oxide layer; an SP region is formed along a first sidewall of the SBSC trench, and an SBD is formed along a second sidewall of the SBSC trench, wherein the second sidewall is opposite to the first sidewall.

[0008] According to another aspect of the present invention, the SP regions and the SBD regions are alternately formed along both sidewalls of the SBSC trench.

[0009] According to another aspect of the present invention, in some preferred embodiments, the substrate has a first conductivity type, and the epitaxial layer is a single epitaxial layer with a uniform doping concentration.

[0010] According to another aspect of the present invention, in some preferred embodiments, the substrate has a first conductivity type, and the epitaxial layer is a multi-step epitaxial (MSE) layer with different doping concentrations, and its doping concentration decreases stepwise along the side wall of the trench and from the substrate to the upper surface of the epitaxial layer, wherein each MSE layer has a uniform doping concentration.

[0011] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the SiC power device further includes a buffer layer located between the substrate and the epitaxial layer, having a first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is R>Rb.

[0012] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, and further includes a buffer layer having a first conductivity type located between the substrate and the epitaxial layer, and a plurality of heavily doped regions having the first conductivity type located in the substrate to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

[0013] According to another aspect of the present invention, a SiC power device is disclosed, which further includes a current diffusion region having a first conductivity type and at least surrounding a sidewall of a gate trench located in an active area, wherein the doping concentration of the current diffusion region is higher than the doping concentration of the epitaxial layer.

[0014] According to another aspect of the present invention, a SiC power device is also disclosed, which is formed in an epitaxial layer with a first conductivity type, the epitaxial layer is located on a substrate with the first conductivity type, and further includes: a plurality of gate trenches, which are surrounded by a source region with the first conductivity type, the source region is located in a body region with a second conductivity type and located on the upper part of the epitaxial layer, each gate trench is filled with a gate and a shielding gate, wherein the shielding gate is insulated from the epitaxial layer by a first insulating layer, the gate is insulated from the epitaxial layer by a gate oxide layer, the shielding gate is insulated from the gate by an inter-polysilicon oxide (IPO) layer, the gate oxide layer is formed along the upper sidewall of the gate trench and its thickness is less than the first insulating layer. An NS region with the first conductivity type for protecting the gate oxide layer is formed directly below the gate.

[0015] According to another aspect of the present invention, in some preferred embodiments, in each gate trench, the shielding gate is located in the lower part of the trench, and the gate is located in the upper part of the trench. In other preferred embodiments, in each gate trench, the shielding gate is located in the middle of the trench, and the gate is a pair of split gates, which are formed around the upper sides of the shielding gate. The second insulating layer is formed simultaneously with the gate oxide layer, and the second insulating layer covers the upper part of the shielding gate.

[0016] According to another aspect of the present invention, the SBSC trench includes a first type SBSC trench and a second type SBSC trench; the first type SBSC trench is formed on the second type SBSC trench, and its trench width is greater than that of the second type SBSC trench; the PS region surrounds the sidewall and bottom of the second type SBSC trench. Since the space between the second type SBSC trench and the gate trench opposite to it becomes larger, the pinch-off effect between the second type SBSC trench and the gate trench is weakened, thereby reducing the on-resistance.

[0017] The above and other objects and advantages of the present invention will undoubtedly be apparent to those skilled in the art by reading the following detailed description of the preferred embodiments with reference to the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The advantages of these and other embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, in which:

[0019] FIG. 1 is a cross-sectional view of a semiconductor device disclosed in the prior art (US 2022 / 0190117 A1).

[0020] Figure 2A FIG. 4 is a top view of a preferred trench semiconductor power device having strip-shaped cells according to the present invention.

[0021] Figure 2B According to the present invention Figure 2A A cross-sectional view of a preferred A1-A1' section.

[0022] Figure 2C According to the present invention Figure 2B Equivalent circuit diagram of trench MOSFET with embedded JBSD shown in FIG.

[0023] Figure 2D According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0024] Figure 3A According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0025] Figure 3B According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0026] Figure 4A According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0027] Figure 4B According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0028] Figure 5A According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0029] Figure 5B According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0030] Figure 6 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0031] Fig. 7A According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0032] Figure 7B According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0033] Figure 8 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0034] Fig. 9 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0035] Fig.10 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0036] Fig.11 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0037] Fig. 12A FIG. 4 is a top view of another preferred trench semiconductor power device having strip-shaped cells according to the present invention.

[0038] Fig. 12B According to the present invention Fig. 12A A cross-sectional view of a preferred A2-A2' section.

[0039] Fig. 12C According to the present invention Fig. 12A A cross-sectional view of a preferred B2-B2' section.

[0040] Fig.13 According to the present invention Fig. 12A A cross-sectional view of another preferred A2-A2' section.

[0041] Fig.14 According to the present invention Fig. 12A A cross-sectional view of another preferred A2-A2' section.

[0042] Fig.15 According to the present invention Fig. 12A Another preferred cross-sectional view of the A2-A2' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0043] Fig.16 According to the present invention Fig. 12A Another preferred cross-sectional view of the A2-A2' section is shown, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0044] Fig.17 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0045] Fig.18 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0046] Fig.19 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0047] Fig. 20 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0048] Fig.21 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section.

[0049] Fig. 22 According to the present invention Figure 2A A cross-sectional view of another preferred A1-A1' section. DETAILED DESCRIPTION

[0050] The present invention is described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. The present invention may be embodied in different ways, but should not be limited to the embodiments described herein. For example, the description here refers more to N-channel semiconductor integrated circuits, but it is clear that other devices are also possible. The following is a detailed description of preferred embodiments of practicing the present invention by reference to the various drawings. Some directional terms, such as "top", "bottom", "front", "back", "above", "below", etc., are described with reference to the directions of the various drawings. Since the elements in the embodiments can be placed in many different directions, the directional terms in the present invention are only used for description and cannot be regarded as limiting the present invention. It should be understood that various structural or logical substitutions and modifications in the embodiments should be included in the true spirit and scope of the present invention. Therefore, the following detailed description should not be regarded as limiting the present invention, and the scope of the present invention is defined by the attached claims. It should be understood that the inventive features of the various preferred embodiments described in the present invention can be combined with each other, except where otherwise specified.

[0051] Figure 2A 1 is a top view of a preferred SiC power device with a strip-shaped cell according to the present invention. The gate trench 203 is separated from the source-body-Schottky contact (SBSC) trench 204, wherein the gate trench 203 is strip-shaped and the SBSC trench 204 is surrounded by a P shield (PS) region 218. According to the present invention, a junction barrier Schottky diode (JBSD) region 230 is formed along a first sidewall 2041 of the SBSC trench 204, and a sidewall P (SP) 217 ​​region is formed along a second sidewall 2042 of the SBSC trench 204.

[0052] Figure 2B According to the present invention Figure 2AA cross-sectional view of a preferred A1-A1' section of the illustrated embodiment. The SiC power device includes a trench MOSFET formed in an N-type SiC epitaxial layer 202', the epitaxial layer 202' being located on an N+ type SiC substrate 201', wherein the back side of the N+ type SiC substrate 201' is coated with a Ti / Ni / Ag back metal layer 220' used as a drain metal. In the N-type epitaxial layer 202', a plurality of gate trenches 203' and SBSC trenches 204' extend vertically downward from the upper surface of the N-type epitaxial layer 202', and do not contact the common interface 216' between the N-type epitaxial layer 202' and the N+ substrate 201', wherein the trench depth of the SBSC trenches 204' is greater than that of the gate trenches 203'. In each gate trench 203', a gate 205' (G, as shown) is located at a higher portion of the gate trench 203' and is surrounded by a thick bottom oxide layer located at the bottom of the gate trench 203' and serving as a first insulating layer 206' and a gate oxide layer 209' located at the sidewall of the gate trench 203', wherein the thickness of the gate oxide layer 209' is less than the first insulating layer 206'. Between the gate trench 203' and the SBSC trench 204', a p-body region 210' having an n+ source region 211' is formed, which extends from near the upper surface of the N-type epitaxial layer 202' and surrounds the gate 205' lined with the gate oxide layer 209', and a p+ body contact 215' is formed below the n+ source region 211' and in the p-body region to reduce body contact resistance. A plurality of SBSC trenches 204' are formed passing through the n+ source region 211' and the p-body region 210', and a P shield region 218' (PS, as shown in the figure) is formed around the bottom of the SBSC trench 204' to reduce the electric field strength of the gate oxide layer and to be separated from the gate trench 203'. A dielectric spacer 221' is formed on the epitaxial layer 202', and a source metal 212' is formed on the dielectric spacer 221' and filled into the SBSC trench 204' to contact the n+ source region 211', the p+ body contact region 215' and the P shield region 218', and a Schottky barrier diode region 229' (SBD, as shown in the figure) is formed between the p+ body contact region 215' and the buried P shield region 218' along the first side wall of the SBSC trench 204' by establishing a Schottky contact with the epitaxial layer 202'. According to the present invention, a JBSD region 230' is formed between the n+ source region 211' and the bottom of the P shielding region 218', which includes a first P-type-N-type (PN1, as shown in the figure) junction diode, a second P-type-N-type (PN2, as shown in the figure) junction diode and an SBD, wherein the PN1 junction diode is formed between the body combination region 213' composed of the p+ body contact region 215' and the p body region 210' and the N-type epitaxial layer 202', and the PN2 junction diode is formed between the PS region 218' and the N-type epitaxial layer 202'.A sidewall P region 217 ′ (SP, as shown) is formed along the second sidewall 2042 ′ of the SBSC trench 204 ′, vertically connecting the P shield region 218 ′ to the p+ body contact region 215 ′.

[0053] Figure 2C According to the present invention Figure 2B FIG. 4 is an equivalent circuit diagram of a trench MOSFET with an embedded JBSD, wherein the JBSD includes a PN1, a PN2 and a SBD.

[0054] Figure 2D According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 2B The invention has a similar structure, except that in the structure of the present invention, it also includes an N shielding region 215"' (NS, as shown in the figure) for gate oxide layer protection, and the N shielding region 215"' is located directly below the gate 205"' (G, as shown in the figure) in the N-type epitaxial layer 202"', and its doping concentration is higher than the doping concentration of the N-type epitaxial layer 202"'.

[0055] Figure 3A According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 2B The invention described has a similar structure, except that in the structure of the present invention, it further includes a second P shielding region 328 (PS2, as shown in the figure), which surrounds a side wall 3032 of the gate trench 303 opposite to the JBSD region 330, is adjacent to the p body region 310, and further extends along a portion of the bottom area of ​​the gate trench 303.

[0056] Figure 3B According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 3A The invention described has a similar structure, except that in the structure of the present invention, it also includes a current diffusion layer 327' (Ncs, as shown in the figure) with a first conductivity type, which is located at the higher part of the N-type epitaxial layer 302', below the p-body region 310', and surrounding a side wall 3031' of the gate trench 303', so as to further avoid the formation of a pinch-off current path between the P-shielding region 318' (PS1, as shown in the figure) and the gate trench 303', wherein the doping concentration of the Ncs region 327' is higher than the doping concentration of the N-type epitaxial layer 302', thereby further reducing the on-resistance.

[0057] Figure 4A According to the present invention Figure 2AAnother preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device is an insulated gate bipolar transistor (IGBT) device, which is Figure 2D The invention described has a similar structure, except for a different substrate and an additional N buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 401, which further includes an N buffer layer 422 (NB, as shown in the figure) with a resistivity of Rb located between the P+ substrate 401 and the N-type epitaxial layer 402, wherein the N-type epitaxial layer 402 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, wherein the relationship between R and Rb is R>Rb.

[0058] Figure 4B According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 4A The invention has a similar structure, except that the IGBT device of the present invention further includes a plurality of heavily doped N+ regions 440' located on the P+ substrate 401' to form a plurality of P+ regions and N+ regions located on the substrate and arranged alternately.

[0059] Figure 5A According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 2B The invention has a similar structure, except that in the structure of the present invention, it also includes a current diffusion layer 527 (Ncs, as shown in the figure) with a first conductivity type located at the upper part of the N-type epitaxial layer 502, below the p-body region 510, and surrounding the upper part of the sidewall of the gate trench 503, so as to further avoid the formation of a pinch-off current path between the PS region 518 and the gate trench 503, wherein the doping concentration of the Ncs region 527 is higher than the doping concentration of the N-type epitaxial layer 502, thereby further reducing the on-resistance. In addition, in the present invention, each gate trench 503 includes a shielding gate 507 (SG, as shown in the figure) located at the lower part of the trench, and a single gate 505 (G, as shown in the figure) located at the upper part of the trench and above the shielding gate 507. The shielding gate 507 is insulated from the adjacent epitaxial layer by the first insulating layer 506, and the gate 505 is insulated from the adjacent epitaxial layer by the gate oxide layer 509, wherein the gate oxide layer 509 surrounds the gate 505 and its thickness is less than the first insulating layer 506, and the first insulating layer 506 has a uniform thickness along the sidewall of the trench. At the same time, the shielding gate 507 is insulated from the gate 505 by the IPO layer 508.

[0060] Figure 5B According to the present invention Figure 2AAnother cross-sectional view of a preferred A1-A1' cross-section of the illustrated embodiment. The SiC SGT device is similar to Figure 5A the invention described above, except that in the structure of the present invention, it further includes an N shielding region 515' (NS, as shown in the figure) for protecting the gate oxide layer. The N shielding region 515' is located below the gate trench 503' in the N-type epitaxial layer 502', and its doping concentration is higher than that of the N-type epitaxial layer 502'.

[0061] Figure 6 It is according to the present invention Figure 2A Another cross-sectional view of a preferred A1-A1' cross-section of the illustrated embodiment. The SiC SGT device is similar to Figure 3B the invention described above, except for the different gate trench structures. In the present invention, each gate trench 603 includes a shielding gate 607 (SG, as shown in the figure) located in the lower part of the trench, and a single gate 605 (G, as shown in the figure) located above the shielding gate 607 in the upper part of the trench. The shielding gate 607 is insulated from the adjacent epitaxial layer by a first insulating layer 606, and the gate 605 is insulated from the adjacent epitaxial layer by a gate oxide layer 609. The gate oxide layer 609 surrounds the gate 605 and its thickness is less than that of the first insulating layer 606. The first insulating layer 606 has a uniform thickness along the sidewall of the trench. At the same time, the shielding gate 607 and the gate 605 are insulated from each other by an IPO layer 608.

[0062] Fig. 7A It is according to the present invention Figure 2A Another cross-sectional view of a preferred A1-A1' cross-section of the illustrated embodiment, and reveals the variation of the doping concentration of the N-type epitaxial layer in the vertical direction. The SiC SGT device is similar to Figure 5A the invention described above, except for the different epitaxial layer structures. In the present invention, the N-type epitaxial layer includes two stepped epitaxial layers with different doping concentrations: a bottom first epitaxial layer 724 (N1, as shown in the figure) with a doping concentration of D1 and a top second epitaxial layer 734 (N2, as shown in the figure) located above the bottom first epitaxial layer 724 with a doping concentration of D2. The relationship between D1 and D2 is D2 < D1 to improve the breakdown voltage and reduce the specific on-resistance.

[0063] Figure 7B It is according to the present invention Figure 2A Another cross-sectional view of a preferred A1-A1' cross-section of the illustrated embodiment, and reveals the variation of the doping concentration of the N-type epitaxial layer in the vertical direction. The SiC SGT device is similar to Figure 5A the invention described above, except for the different epitaxial layer structures. In the present invention, a source body (SB) region T SB(Between line A-A and line B-B), formed at the upper part of the epitaxial layer, an oxide charge balance (OCB) region T OCB (Between line B-B and line D-D), formed in the mesa region between two adjacent gate trenches 703', below the body region 710' and above the bottom of the shielding gate 707', a buffer region T B , formed between the bottom of the N+ substrate 701' and the shielding gate 707' (between line D-D and line E-E), located within the OCB region T OCB The epitaxial layer within is two multi-step epitaxial (MSE) layers with different doping concentrations: including a bottom first epitaxial layer 724' (N with a doping concentration of D1 above the buffer epitaxial layer 722' (NB, as shown, between line D-D and line E-E)) S1 , as shown, between line C-C and line D-D), and a top second epitaxial layer 734' (N with a doping concentration of D2 above the bottom first epitaxial layer 724') S2 , as shown, between line B-B and line C-C), where the relationship between D1 and D2 is D2 < D1. In addition, the doping concentration of the epitaxial layer in the SB region T SB is the same as that of the top second epitaxial layer 734' of the MSE layer in the OCB region T OCB , and the doping concentration DB of the buffer epitaxial layer 722' is lower than that of each MSE layer in the OCB region T OCB .

[0064] Figure 8 is another preferred cross-sectional view of the A1-A1' cross-section of the embodiment shown in accordance with the present invention Figure 2A The SiC SGT device is an IGBT device, which has a similar structure to Figure 5B the invention described above, except for a different substrate and an additional N buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 801, which further includes an N buffer layer 822 (NB, as shown) with a resistivity of Rb between the P+ substrate 801 and the N-type epitaxial layer 802. The N-type epitaxial layer 802 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, where the relationship between R and Rb is R > Rb

[0065] Fig. 9 is another preferred cross-sectional view of the A1-A1' cross-section of the embodiment shown in accordance with the present invention, and reveals the variation of the doping concentration of the N-type epitaxial layer in the vertical direction. The SiC SGT device described above is the same as Figure 2A Fig. 7A ​The invention has a similar structure, except for a different gate trench structure and an additional N shielding region. In each gate trench 903, a shielding gate 907 (SG, as shown in the figure) is located in the middle of the trench, and a pair of split gates 905 (G, as shown in the figure) are formed around the upper sides of the shielding gate 907. A second insulating layer 919 for isolating the shielding gate 907 and the gate 905 covers the upper part of the shielding gate 907, wherein the second insulating layer 919 and the gate oxide layer 909 are formed simultaneously during the device manufacturing process. In addition, the present invention also includes an N shielding region 915 (NS, as shown in the figure) for gate oxide protection, which is located directly below the gate trench 903 in the bottom first N-type epitaxial layer 924.

[0066] Fig.10 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown in the figure reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 7B The invention has a similar structure, except for a different gate trench structure and an additional N shielding region. In each gate trench 1003, a shielding gate 1007 (SG, as shown in the figure) is located in the middle of the trench, and a pair of split gates 1005 (G, as shown in the figure) are formed around the upper sides of the shielding gate 1007. A second insulating layer 1019 for isolating the shielding gate 1007 from the gate 1005 covers the upper part of the shielding gate 1007, wherein the second insulating layer 1019 and the gate oxide layer 1009 are formed simultaneously during the device manufacturing process. In addition, the present invention also includes an N shielding region 1015 (NS, as shown in the figure) for gate oxide protection, which is located directly below the gate trench 1003 in the N-type buffer layer 1022.

[0067] Fig.11 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC SGT device and Figure 8 The invention has a similar structure except for a different gate trench structure. In each gate trench 1103, a shielding gate 1107 (SG, as shown in the figure) is located in the middle of the trench, and a pair of split gates 1105 (G, as shown in the figure) are formed around the upper sides of the shielding gate 1107. A second insulating layer 1119 for isolating the shielding gate 1107 from the gate 1105 covers the upper part of the shielding gate 1107, wherein the second insulating layer 1119 and the gate oxide layer 1109 are formed simultaneously during the device manufacturing process.

[0068] Fig. 12A1 is a top view of another preferred SiC power device with a strip-shaped unit according to the present invention. The gate trench 1203 is separated from the SBSC trench 1204, wherein the gate trench 1203 is strip-shaped and the SBSC trench 1204 is surrounded by a P shield (PS) region 1218. According to the present invention, the sidewall P (SP) region 1217 and the junction barrier Schottky diode (JBSD) region 1230 are alternately formed along the two side walls of the SBSC trench 1204.

[0069] Fig. 12B According to the present invention Fig. 12A A cross-sectional view of a preferred A2-A2' section of the embodiment shown. The SiC power device and Figure 2D The invention described has a similar structure, except that Figure 2D The side wall P region 217"' (SP, such as Figure 2D ) is replaced by the SBD region 1229' in the present invention. According to the present invention, the JBSD region 1230' is formed on both sidewalls of the SBSC trench 1204'.

[0070] Fig. 12C According to the present invention Fig. 12A A cross-sectional view of a preferred B2-B2' section of the embodiment shown. The SiC power device and Figure 2D The invention described has a similar structure, except that Figure 2D The SBD region 229'' is replaced by the sidewall P region 1217'' in the present invention. According to the present invention, the sidewall P region 1217'' (SP, as shown in the figure) is formed on both sidewalls of the SBSC trench 1204''.

[0071] Fig.13 According to the present invention Fig. 12A Another preferred cross-sectional view of the A2-A2' section of the embodiment shown. The SiC SGT device and Figure 5B The invention described has a similar structure, except that Figure 5B The sidewall P region 517' (SP, such as Figure 5B ) is replaced by the SBD region 1329 in the present invention. According to the present invention, the JBSD region 1330 is formed on both sidewalls of the SBSC trench 1304.

[0072] Fig.14 According to the present invention Figure 2A Another preferred cross-sectional view of the A2-A2' section of the embodiment shown. The SiC SGT power device is an IGBT device, which is Fig.13The invention described has a similar structure, except for a different substrate and an additional N buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 1401, which further includes an N buffer layer 1422 (NB, as shown in the figure) with a resistivity of Rb located between the P+ substrate 1401 and the N-type epitaxial layer 1402, wherein the N-type epitaxial layer 1402 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, wherein the relationship between R and Rb is R>Rb.

[0073] Fig.15 According to the present invention Fig. 12A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Fig. 9 The invention described has a similar structure, except that Fig. 9 The side wall P region 917 (SP, such as Fig. 9 ) is replaced by the SBD region 1529 in the present invention. According to the present invention, the JBSD region 1530 is formed on both sidewalls of the SBSC trench 1504.

[0074] Fig.16 According to the present invention Fig. 12A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section, and reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Fig.15 The invention described has a similar structure except for a different substrate and an additional N buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 1601, which further includes an N buffer layer 1622 (NB, as shown) located between the P+ substrate 1601 and the bottom first N-type epitaxial layer 1624 (N1, as shown).

[0075] Fig.17 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 2B The invention described has a similar structure, except that in the present invention, the SBSC trench includes a first type SBSC trench 1704 and a second type SBSC trench 1714. The first type SBSC trench 1704 is formed on the second type SBSC trench 1714, and its trench width is greater than that of the second type SBSC trench 1714. A PS region 1718 is formed around the sidewalls and the bottom of the second type SBSC trench 1714.

[0076] Fig.18 According to the present invention Figure 2AAnother preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Figure 3A The invention described has a similar structure, except that in the present invention, the SBSC trench includes a first type SBSC trench 1804 and a second type SBSC trench 1814. The first type SBSC trench 1804 is formed on the second type SBSC trench 1814, and its trench width is greater than the second type SBSC trench 1814. A PS1 region 1818 is formed around the sidewalls and the bottom of the second type SBSC trench 1814.

[0077] Fig.19 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Fig.17 The invention has a similar structure except for a different gate trench structure. In the structure of the present invention, each gate trench 1903 includes a shielding gate 1907 (SG, as shown in the figure) located in the lower part of the trench, and a single gate 1905 (G, as shown in the figure) located in the upper part of the trench and above the shielding gate 1907. The shielding gate 1907 is insulated from the adjacent epitaxial layer by a first insulating layer 1906, and the gate 1905 is insulated from the adjacent epitaxial layer by a gate oxide layer 1909, wherein the gate oxide layer 1909 surrounds the gate 1905 and its thickness is less than the first insulating layer 1906, and the first insulating layer 1906 has a uniform thickness along the sidewall of the trench. At the same time, the shielding gate 1907 and the gate 1905 are insulated by an IPO layer 1908.

[0078] Fig. 20 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Fig.17 The invention has a similar structure, except that in the structure of the present invention, it also includes an N shielding region 2015 (NS, as shown in the figure) for gate oxide layer protection, the N shielding region 2015 is located below the gate 2005 (G, as shown in the figure) in the N-type epitaxial layer 2002, and its doping concentration is higher than the N-type epitaxial layer 2002. In addition, in the structure of the present invention, it also includes a current diffusion layer 2027 (Ncs, as shown in the figure) with a first conductivity type located at a higher part of the N-type epitaxial layer 2002, below the p-body region 2010, at least surrounding the side wall of the gate 2005, so as to further avoid the formation of a pinch-off current path between the P shielding region 2018 (PS, as shown in the figure) and the gate trench 2003, wherein the doping concentration of the Ncs region 2027 is higher than that of the N-type epitaxial layer 2002, thereby further reducing the on-resistance.

[0079] Fig.21 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Fig.18 The invention has a similar structure, except that in the structure of the present invention, it also includes an N shielding region 2115 (NS, as shown in the figure) for gate oxide layer protection, the N shielding region 2115 is located below the gate 2105 (G, as shown in the figure) in the N-type epitaxial layer 2102, and its doping concentration is higher than the N-type epitaxial layer 2102. In addition, in the structure of the present invention, it also includes a current diffusion layer 2127 (Ncs, as shown in the figure) of the first conductivity type, which is located at the higher part of the N-type epitaxial layer 2102, below the p-body region 2110, and surrounds at least one side wall of the gate 2105, so as to further avoid the formation of a pinch-off current path between the P shielding region 2118 (PS1, as shown in the figure) and the gate trench 2103, wherein the doping concentration of the Ncs region 2127 is higher than that of the N-type epitaxial layer 2102, thereby further reducing the on-resistance.

[0080] Fig. 22 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC power device and Fig.19 The invention has a similar structure, except that in the structure of the present invention, it also includes an N shielding region 2215 (NS, as shown in the figure) for gate oxide layer protection, and the N shielding region 2215 is located below the gate trench 2203 in the N-type epitaxial layer 2202, and its doping concentration is higher than the N-type epitaxial layer 2202. In addition, in the structure of the present invention, it also includes a current diffusion layer 2227 (Ncs, as shown in the figure) with a first conductivity type located at a higher part of the N-type epitaxial layer 2202, below the p-body region 2210, and at least surrounding the sidewall of the gate 2205, so as to further avoid the formation of a pinch-off current path between the P shielding region 2218 (PS, as shown in the figure) and the gate trench 2203, wherein the doping concentration of the Ncs region 2227 is higher than that of the N-type epitaxial layer 2202, thereby further reducing the on-resistance.

[0081] Although the present invention has been described in accordance with preferred embodiments, it should be understood that the above disclosure is not to be construed as limiting the present invention. The embodiments described above are generally N-channel devices, and the embodiments may also be applied to P-channel devices by reversing the polarity of the conductivity type. After reading the above disclosure, various substitutions and modifications will undoubtedly be apparent to those skilled in the art. Therefore, the appended claims should be interpreted as covering all substitutions and modifications that fall within the true spirit and scope of the present invention.

Claims

1. A silicon carbide (SiC) power device comprising a plurality of cells, wherein each cell is located in an active region, further comprising: an epitaxial layer of a first conductivity type disposed on the substrate; a gate trench formed in the active region, which is surrounded by a source region having the first conductivity type, the source region being located in a body region having the second conductivity type and located on an upper portion of the epitaxial layer; a source-body-Schottky contact (SBSC) trench extending through the source region and the body region into the epitaxial layer; a P shield (PS) region of the second conductivity type, for reducing the electric field strength of the gate oxide layer, surrounding the bottom of the SBSC trench and separated from the gate trench; a body contact region having the second conductivity type, located in the body region; a body combination region, comprising the body region and the body contact region; a sidewall P (SP) region having the second conductivity type, selectively formed along a portion of the sidewall of the SBSC trench and connecting the PS region to the body contact region; The source metal is filled into the SBSC trench, in contact with the source region, the body contact region and the PS region; and by establishing a Schottky contact with the epitaxial layer, a Schottky barrier diode (SBD) region is formed between the body contact region and the buried PS region. A junction barrier Schottky diode (JBSD) region is formed between the source region and the bottom of the PS region, which includes a first P-type / N-type (PN) junction diode, a second PN junction diode and an SBD, wherein the first PN junction diode is formed between the body combination region and the epitaxial layer, and the second PN junction diode is formed between the buried PS region and the epitaxial layer.

2. The SiC power device according to claim 1, characterized in that: The gate is located in the gate trench and is surrounded by a first insulating layer located at the bottom of the gate trench and a gate oxide layer located at the sidewall of the gate trench, wherein the thickness of the first insulating layer is greater than that of the gate oxide layer.

3. The SiC power device according to claim 1, characterized in that: The gate and the shielding gate are located in the gate trench, the shielding gate is insulated from the epitaxial layer by a first insulating layer, the gate is insulated from the epitaxial layer by a gate oxide layer, the shielding gate is insulated from the gate by an inter-polysilicon oxide layer (IPO), and the thickness of the gate oxide layer is less than that of the first insulating layer.

4. The SiC power device according to claim 3, characterized in that: The shielding gate is located at a lower portion of the gate trench, and the gate is located at an upper portion of the gate trench.

5. The SiC power device according to claim 3, characterized in that: The shielding gate is located in the middle of the trench, and the gate is a pair of split gates formed around two sides of the upper portion of the shielding gate.

6. The SiC power device according to claim 1, characterized in that: The SP region is formed along a first sidewall of the SBSC trench, and the SBD is formed along a second sidewall opposite to the first sidewall of the SBSC trench.

7. The SiC power device according to claim 1, characterized in that: The SP region and the SBD region are alternately formed along both sidewalls of the SBSC trench.

8. The SiC power device according to claim 1, further comprising a current diffusion region having the first conductivity type and surrounding a higher portion of the gate trench sidewall, wherein the doping concentration of the current diffusion region is higher than that of the epitaxial layer.

9. The SiC power device of claim 1, further comprising at least one N shield (NS) region having the first conductivity type, which is located in the epitaxial layer at a deeper position than the gate trench and has a higher doping concentration than the epitaxial layer.

10. The SiC power device according to claim 1, further comprising a second PS region having the second conductivity type, the second PS region surrounding the gate trench sidewall opposite to the JBSD region and adjacent to the body region, and further extending along a portion of the gate trench bottom.

11. The SiC power device according to claim 1, characterized in that: The substrate has the first conductivity type, and the epitaxial layer is a single epitaxial layer with uniform doping concentration.

12. The SiC power device according to claim 3, characterized in that: The substrate has the first conductivity type, and the epitaxial layer is a multi-step epitaxial (MSE) layer with different doping concentrations, and its doping concentration decreases step by step along the side wall of the trench and from the substrate to the upper surface of the epitaxial layer, wherein each of the MSE layers has a uniform doping concentration.

13. The SiC power device according to claim 12, characterized in that: The epitaxial layer includes at least two stepped epitaxial layers with different doping concentrations: a bottom epitaxial layer with a doping concentration of D1 and a top epitaxial layer located above the bottom epitaxial layer with a doping concentration of D2, wherein the relationship between D1 and D2 is D2 <D1。 14. The SiC power device according to claim 1, characterized in that: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and the SiC power device further includes a buffer layer located between the substrate and the epitaxial layer, having the first conductivity type and resistivity Rb, wherein the relationship between R and Rb is R>Rb.

15. The SiC power device according to claim 1, characterized in that: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and further includes a buffer layer located between the substrate and the epitaxial layer, having the first conductivity type and resistivity Rb, wherein the relationship between R and Rb is R>Rb, and a plurality of heavily doped regions located in the substrate and having the first conductivity type to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

16. The SiC power device according to claim 1, characterized in that: The doping concentration of the PS region is higher than that of the SP region.

17. The SiC power device according to claim 2, characterized in that: The trench depth of the SBSC trench is greater than that of the gate trench.

18. The SiC power device according to claim 3, characterized in that: The epitaxial layer further includes an oxide charge balance (OCB) region and a buffer zone; the OCB region having the first conductivity type is formed in a mesa region between two adjacent gate trenches, below the body region and above the bottom of the shielding gate; the buffer zone located in the epitaxial layer and having the first conductivity type is formed between the substrate and the OCB region; the epitaxial layer located in the OCB region has an MSE layer structure, and its doping concentration decreases in a step-by-step manner along the sidewalls of the gate trench and from the bottom of the shielding gate to the body region, wherein each of the MSE layers has a uniform doping concentration; the doping concentration of the epitaxial layer located in the buffer zone is lower than the doping concentration of the MSE layer located in the OCB zone.

19. The SiC device according to claim 1, characterized in that: The source metal is a multi-metal layer including a nickel layer as a first metal layer, a titanium layer as a second metal layer, an aluminum layer as a third metal layer, and a tungsten layer as a fourth metal layer.

20. The SiC device according to claim 1, characterized in that: The SBSC groove includes a first type SBSC groove and a second type SBSC groove; the first type SBSC groove is located above the second type SBSC groove, and its groove width is greater than that of the second type SBSC groove; the PS region surrounds the sidewall and bottom of the second type SBSC groove.

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