A SiC trench device with embedded junction barrier schottky diode

Abstract

A SiC trench MOSFET with embedded junction barrier Schottky diode is disclosed, which has a P shield region around the source-body-Schottky contact trench bottom to reduce the gate oxide electric field strength and switching loss. The source metal is directly connected to the P shield region and the junction barrier Schottky diode region. A sidewall P region is formed along a partial area of the source-body-Schottky contact trench sidewall to improve the trade-off between the drain-source leakage current of the SiC trench MOSFET and the forward voltage of the junction barrier Schottky diode. The device further includes an N shield region formed under each gate trench to reduce the gate oxide electric field strength and the specific on-resistance.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to a SiC (silicon carbide) trench MOSFET (metal oxide semiconductor field effect transistor) having an embedded junction barrier Schottky diode formed along the sidewalls of a source-body-Schottky contact trench. This inactivates the parasitic body diode, thereby reducing turn-off switch losses without compromising channel density. A sidewall P (SP) region is formed along the source-body-Schottky contact trench to modulate the embedded junction barrier Schottky diode region, thereby improving the tradeoff between drain-source leakage current and the forward voltage of the embedded junction barrier Schottky diode. The device further includes a current diffusion region located below the body region and surrounding the gate trench to achieve lower specific on-resistance. Background Art

[0002] Due to the physical properties of SiC, SiC-MOSFETs have higher breakdown voltage, lower on-resistance, and faster switching speeds than Si-MOSFETs. However, due to the poor interface state between SiC and the gate oxide layer, SiC-MOSFETs require a higher gate-source voltage Vgs to fully open the device channel. Therefore, SiC-MOSFETs have a higher gate oxide electric field strength than Si-MOSFETs. For example, for Si devices, Vgs = 10V can fully open the device channel, but for SiC devices, Vgs = 18V can fully open the device channel. The higher the Vgs, the higher the gate oxide electric field strength, which can lead to device reliability issues.

[0003] FIG1 is a cross-sectional view of a semiconductor device disclosed in the prior art (US2022 / 0190117 A1), which has a p+ shielding region 52 located below the trench gate region 60 for reducing the electric field strength of the gate oxide layer, and an embedded Schottky barrier diode for reducing switching losses. A metal layer 81 is deposited in the source contact trench to form an embedded Schottky barrier diode having an n-type layer 20 along the sidewalls and bottom of the second trench. However, the embedded Schottky barrier diode formed at the bottom of the second trench as shown in FIG1 suffers from a severe barrier lowering effect, resulting in a high drain-source leakage current and thus early breakdown of the device.

[0004] Therefore, in the field of SiC semiconductor device design and manufacturing, there is still a need to provide a new unit structure, device structure and manufacturing method to solve the difficulties and limitations mentioned above, so that SiC trench devices have lower gate oxide layer electric field strength, obtain lower on-resistance and lower switching loss. Summary of the Invention

[0005] The present invention discloses a novel SiC trench MOSFET with an embedded junction barrier Schottky diode. The junction barrier Schottky diode comprises two PN junction diodes and a Schottky barrier diode formed along the source-body-Schottky contact trench. Devices with this junction barrier Schottky diode structure address the high leakage current problem commonly seen in high-voltage SiC Schottky barrier diode devices.

[0006] A source-body Schottky contact trench passes through a source region of a first conductivity type and a body region of a second conductivity type, extending into the epitaxial layer. A P shield region of the second conductivity type, used to reduce the electric field strength of the gate oxide layer, surrounds the bottom of the source-body Schottky contact trench and is separated from the gate trench. Because the trench depth of the source-body Schottky contact trench is greater than that of the gate trench, the P shield region can effectively reduce the electric field strength of the gate oxide layer without the need for an additional P shield region below the gate trench (as shown in FIG1 ). A sidewall P region of the second conductivity type is selectively formed along a portion of the sidewall of the source-body Schottky contact trench, connecting the P shield region to the body contact region, thereby improving the drain-source leakage current I by adjusting the overlap area between the sidewall P region and the source-body Schottky contact trench. dsl and the forward voltage of the junction barrier Schottky diode V f a trade-off between the two; forming a body contact region with a second conductivity type in the body region to form an ohmic contact with the source metal; filling at least one conductive material used as the source metal into the source-body-Schottky contact groove to form an ohmic contact with the source region and the body contact region and a Schottky contact with the epitaxial layer; forming a junction barrier Schottky diode between the source region and the bottom of the buried P shielding region, which includes two PN junction diodes and one Schottky barrier diode; a first PN junction diode is formed between the body combination region (including the body region and the body contact region) and the epitaxial layer, and a second PN junction diode is formed between the P shielding region and the epitaxial layer; by establishing a Schottky contact with the epitaxial layer, a Schottky barrier diode is formed between the body contact region and the P shielding region.

[0007] According to one aspect of the present invention, a silicon carbide power device comprising a plurality of units is disclosed, wherein each unit is located in an active region, and further comprises: an epitaxial layer having a first conductivity type, which is located on a substrate; at least one gate trench, which is surrounded by a source region having the first conductivity type, the source region being located in a body region having a second conductivity type and being located on top of the epitaxial layer; a gate, which is located in the gate trench and is surrounded by a first insulating layer located at the bottom of the gate trench and a gate oxide layer located on the sidewalls of the gate trench, and the thickness of the first insulating layer is greater than the gate oxide layer; an N shielding region having the first conductivity type, which is located directly below the gate and is used to protect the gate oxide layer; a sidewall P region is formed along a first sidewall of the source-body-Schottky contact trench, and a Schottky barrier diode is formed along a second sidewall of the source-body-Schottky contact trench, wherein the second sidewall is opposite to the first sidewall.

[0008] According to another aspect of the present invention, the sidewall P regions and the Schottky barrier diode regions are alternately formed along both sidewalls of the source-body-Schottky contact trench.

[0009] According to another aspect of the present invention, in some preferred embodiments, the substrate has a first conductivity type, and the epitaxial layer is a single epitaxial layer with a uniform doping concentration.

[0010] According to another aspect of the present invention, in some preferred embodiments, the substrate has a first conductivity type, and the epitaxial layer is a multi-step epitaxial layer with different doping concentrations, and its doping concentration decreases in a step-by-step manner along the sidewall of the trench and from the substrate to the upper surface of the epitaxial layer, wherein each multi-step epitaxial layer has a uniform doping concentration.

[0011] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the SiC power device further includes a buffer layer located between the substrate and the epitaxial layer, having a first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is R>Rb.

[0012] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, and further includes a buffer layer having a first conductivity type located between the substrate and the epitaxial layer, and a plurality of heavily doped regions having the first conductivity type located in the substrate to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

[0013] According to another aspect of the present invention, a SiC power device is disclosed, further comprising a current diffusion region having a first conductivity type and at least surrounding a sidewall of a gate trench located in an active region, wherein the doping concentration of the current diffusion region is higher than the doping concentration of the epitaxial layer.

[0014] According to another aspect of the present invention, a SiC power device is disclosed. The device is formed in an epitaxial layer having a first conductivity type, the epitaxial layer being located on a substrate having the first conductivity type. The device further comprises: a plurality of gate trenches surrounded by source regions having the first conductivity type, the source regions being located in a body region having a second conductivity type and located above the epitaxial layer; each gate trench is filled with a gate and a shield gate, wherein the shield gate is insulated from the epitaxial layer by a first insulating layer, the gate is insulated from the epitaxial layer by a gate oxide layer, and the shield gate is insulated from the gates by an inter-polysilicon oxide layer; the gate oxide layer is formed along the upper sidewalls of the gate trench and is thinner than the first insulating layer; and an N shield region having the first conductivity type and used to protect the gate oxide layer is formed directly below the gate.

[0015] According to another aspect of the present invention, in some preferred embodiments, within each gate trench, the shield gate is located in the lower portion of the trench, and the gate is located in the upper portion of the trench. In other preferred embodiments, within each gate trench, the shield gate is located in the middle of the trench, and the gate is a pair of split gates formed around both sides of the upper portion of the shield gate. The second insulating layer is formed simultaneously with the gate oxide layer, and the second insulating layer covers the upper portion of the shield gate.

[0016] According to another aspect of the present invention, the source-body Schottky contact trench includes a first-type source-body Schottky contact trench and a second-type source-body Schottky contact trench; the first-type source-body Schottky contact trench is formed above the second-type source-body Schottky contact trench and has a greater trench width than the second-type source-body Schottky contact trench; and a P shielding region surrounds the sidewalls and bottom of the second-type source-body Schottky contact trench. Due to the increased space between the second-type source-body Schottky contact trench and its opposing gate trench, the pinch-off effect between the second-type source-body Schottky contact trench and the gate trench is reduced, thereby reducing on-resistance.

[0017] The above and other objects and advantages of the present invention will undoubtedly be apparent to those skilled in the art by reading the following detailed description of the preferred embodiments with reference to the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] These and other advantages of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] FIG1 is a cross-sectional view of a semiconductor device disclosed in the prior art (US 2022 / 0190117 A1).

[0020] Figure 2A FIG. 4 is a top view of a preferred trench semiconductor power device having strip-shaped cells according to the present invention.

[0021] Figure 2B is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0022] Figure 2C is according to the present invention Figure 2B is an equivalent circuit diagram of a trench MOSFET with embedded junction barrier Schottky diode.

[0023] Figure 2D is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0024] Figure 3A is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0025] Figure 3B is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0026] Figure 4A is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0027] Figure 4B is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0028] Figure 5A is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0029] Figure 5B is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0030] Figure 6 is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle.

[0031] Figure 7A is according to the present invention Figure 2A is a cross-sectional view of another preferred A1-A1' cross-section in the middle, and reveals the variation of N-type epitaxial layer doping concentration along the vertical direction.

[0032] Figure 7B is according to the present invention Figure 2AAnother preferred cross-sectional view of the A1-A1' section is shown, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0033] Figure 8 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0034] Figure 9 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0035] Figure 10 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section is shown, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0036] Figure 11 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0037] Figure 12A FIG. 4 is a top view of another preferred trench semiconductor power device having strip-shaped cells according to the present invention.

[0038] Figure 12B According to the present invention Figure 12A A cross-sectional view of a preferred A2-A2' section.

[0039] Figure 12C According to the present invention Figure 12A A cross-sectional view of a preferred B2-B2' section.

[0040] Figure 13 According to the present invention Figure 12A Another preferred cross-sectional view of the A2-A2' section.

[0041] Figure 14 According to the present invention Figure 12A Another preferred cross-sectional view of the A2-A2' section.

[0042] Figure 15 According to the present invention Figure 12A Another preferred cross-sectional view of the A2-A2' section is shown, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0043] Figure 16 According to the present invention Figure 12AAnother preferred cross-sectional view of the A2-A2' section is shown, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction.

[0044] Figure 17 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0045] Figure 18 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0046] Figure 19 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0047] Figure 20 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0048] Figure 21 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section.

[0049] Figure 22 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section. DETAILED DESCRIPTION

[0050] The present invention is described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. The present invention may be embodied in various ways, but should not be limited to the embodiments described herein. For example, the description herein refers primarily to N-channel semiconductor integrated circuits, but other devices are clearly possible. The following is a detailed description of preferred embodiments of the present invention with reference to the various accompanying drawings. Certain directional terms, such as "top," "bottom," "front," "back," "above," "below," etc., are described with reference to the orientation of the various accompanying drawings. Because the components of the embodiments can be placed in many different orientations, the directional terms in the present invention are for descriptive purposes only and should not be construed as limiting the present invention. It should be understood that various structural or logical substitutions and modifications in the embodiments should be considered within the true spirit and scope of the present invention. Therefore, the following detailed description should not be construed as limiting the present invention, the scope of which is defined by the appended claims. It should be understood that the inventive features of the various preferred embodiments described herein may be combined with each other, unless otherwise specified.

[0051] Figure 2A1 is a top view of a preferred silicon carbide power device with strip-shaped cells according to the present invention. The gate trench 203 is separated from the source-body-Schottky contact trench 204, wherein the gate trench 203 is strip-shaped and the source-body-Schottky contact trench 204 is shielded by a P shielding region 218 (PS, as shown in FIG. Figure 2A According to the present invention, a junction barrier Schottky diode region 230 (JBSD, as shown) is surrounded by Figure 2A As shown) along the first sidewall 2041 of the source-body-Schottky contact trench 204, a sidewall P region 217 (SP, as shown Figure 2A As shown) is formed along the second sidewall 2042 of the source-body-Schottky contact trench 204.

[0052] Figure 2B According to the present invention Figure 2AA cross-sectional view of a preferred A1-A1' section of the illustrated embodiment. The SiC power device includes a trench MOSFET formed within an N-type SiC epitaxial layer 202', which is located on an N+-type SiC substrate 201'. The back surface of the N+-type SiC substrate 201' is coated with a Ti / Ni / Ag back metal layer 220', which serves as a drain metal. Within the N-type epitaxial layer 202', a plurality of gate trenches 203' and source-body Schottky contact trenches 204' extend vertically downward from the top surface of the N-type epitaxial layer 202', without contacting the common interface 216' between the N-type epitaxial layer 202' and the N+-type substrate 201'. The source-body Schottky contact trenches 204' are deeper than the gate trenches 203'. Within each gate trench 203', a gate 205' (G, as shown) is located in the upper portion of the gate trench 203' and is surrounded by a thick bottom oxide layer at the bottom of the gate trench 203', which serves as a first insulating layer 206', and a gate oxide layer 209' located on the sidewalls of the gate trench 203'. The gate oxide layer 209' is thinner than the first insulating layer 206'. A p-body region 210' having an n+ source region 211' is formed between the gate trench 203' and the source-body Schottky contact trench 204'. The p-body region 210' extends from near the upper surface of the N-type epitaxial layer 202' and surrounds the gate 205' lined with the gate oxide layer 209'. A p+ body contact 215' is formed below the n+ source region 211' and within the p-body region to reduce body contact resistance. A plurality of source-body-Schottky contact trenches 204' are formed through the n+ source region 211' and the p-body region 210', and a P shielding region 218' (PS, as shown in the figure) is formed around the bottom of the source-body-Schottky contact trenches 204' to reduce the electric field strength of the gate oxide layer and separate from the gate trench 203'. A dielectric spacer 221' is formed on the epitaxial layer 202', and a source metal 212' is formed on the dielectric spacer 221' and filled into the source-body-Schottky contact trench 204' to contact the n+ source region 211', the p+ body contact region 215' and the P shield region 218'. By establishing a Schottky contact with the epitaxial layer 202', a Schottky barrier diode region 229' (SBD, as shown in the figure) is formed between the p+ body contact region 215' and the buried P shield region 218' and along the first side wall of the source-body-Schottky contact trench 204'.According to the present invention, a junction barrier Schottky diode region 230' (JBSD, as shown) is formed between the n+ source region 211' and the bottom of the P shield region 218'. The JBSD region includes a first P-type-N-type (PN1, as shown) junction diode, a second P-type-N-type (PN2, as shown) junction diode, and a Schottky barrier diode. The PN1 junction diode is formed between the body combination region 213' consisting of the p+ body contact region 215' and the p-body region 210' and the N-type epitaxial layer 202', and the PN2 junction diode is formed between the P shield region 218' and the N-type epitaxial layer 202'. A sidewall P region 217' (SP, as shown) is formed along the second sidewall 2042' of the source-body Schottky contact trench 204', vertically connecting the P shield region 218' to the p+ body contact region 215'.

[0053] Figure 2C According to the present invention Figure 2B FIG. 4 is an equivalent circuit diagram of a trench MOSFET with an embedded junction barrier Schottky diode, wherein the junction barrier Schottky diode includes a PN1, a PN2 and a Schottky barrier diode region.

[0054] Figure 2D According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 2B The invention has a similar structure, except that the structure of the present invention also includes an N shielding region 215"' (NS, as shown in the figure) for gate oxide layer protection. The N shielding region 215"' is located directly below the gate 205"' (G, as shown in the figure) in the N-type epitaxial layer 202"', and its doping concentration is higher than the doping concentration of the N-type epitaxial layer 202"'.

[0055] Figure 3A According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 2B The invention has a similar structure, except that in the structure of the present invention, it further includes a second P shielding region 328 (PS2, as shown in the figure), which surrounds a side wall 3032 of the gate trench 303 opposite to the junction barrier Schottky diode region 330, is adjacent to the p body region 310, and further extends along a portion of the bottom area of ​​the gate trench 303.

[0056] Figure 3B According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 3AThe invention has a similar structure, except that the structure of the present invention further includes a current diffusion layer 327' (Ncs, as shown in the figure) with a first conductivity type, which is located in the upper part of the N-type epitaxial layer 302', below the p-body region 310', and surrounding a side wall 3031' of the gate trench 303', so as to further avoid the formation of a pinch-off current path between the P-shielding region 318' (PS1, as shown in the figure) and the gate trench 303'. The doping concentration of the Ncs region 327' is higher than the doping concentration of the N-type epitaxial layer 302', thereby further reducing the on-resistance.

[0057] Figure 4A According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. The SiC power device is an IGBT (insulated gate bipolar transistor) device. Figure 2D The invention has a similar structure, except for a different substrate and an additional N-buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 401 and further includes an N-buffer layer 422 (NB, as shown) with a resistivity Rb, located between the P+ substrate 401 and an N-type epitaxial layer 402. The N-type epitaxial layer 402 is a single epitaxial layer with a uniform doping concentration and a resistivity R, where R>Rb.

[0058] Figure 4B According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 4A The invention has a similar structure, except that the IGBT device further includes a plurality of heavily doped N+ regions 440' located on the P+ substrate 401' to form a plurality of alternating P+ and N+ regions located on the substrate.

[0059] Figure 5A According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. The SiC power device is an SGT (shielded gate trench) MOSFET. Figure 2BThe aforementioned invention has a similar structure, except that it also includes a current diffusion layer 527 (Ncs, as shown in the figure) of the first conductivity type, located in the upper portion of the N-type epitaxial layer 502, below the p-body region 510, and surrounding the upper portion of the gate trench 503 sidewall. This further prevents the formation of a pinched current path between the P-shield region 518 and the gate trench 503. The doping concentration of the Ncs region 527 is higher than that of the N-type epitaxial layer 502, thereby further reducing the on-resistance. Furthermore, in the present invention, each gate trench 503 includes a shielded gate 507 (SG, as shown in the figure) located in the lower portion of the trench, and a single gate 505 (G, as shown in the figure) located in the upper portion of the trench, above the shielded gate 507. The shielding gate 507 is insulated from the adjacent epitaxial layer by a first insulating layer 506, and the gate 505 is insulated from the adjacent epitaxial layer by a gate oxide layer 509. The gate oxide layer 509 surrounds the gate 505 and is thinner than the first insulating layer 506. The first insulating layer 506 has a uniform thickness along the trench sidewalls. Furthermore, the shielding gate 507 is insulated from the gate 505 by an inter-polysilicon oxide layer 508.

[0060] Figure 5B According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 5A The invention has a similar structure, except that the structure of the present invention further includes an N shielding region 515' (NS, as shown in the figure) for gate oxide layer protection. The N shielding region 515' is located below the gate trench 503' in the N-type epitaxial layer 502', and its doping concentration is higher than the doping concentration of the N-type epitaxial layer 502'.

[0061] Figure 6 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 3B The invention has a similar structure, except for a different gate trench structure. In the present invention, each gate trench 603 includes a shielded gate 607 (SG, as shown in the figure) located in the lower portion of the trench, and a single gate 605 (G, as shown in the figure) located in the upper portion of the trench, above the shielded gate 607. The shielded gate 607 is insulated from the adjacent epitaxial layer by a first insulating layer 606, and the gate 605 is insulated from the adjacent epitaxial layer by a gate oxide layer 609. The gate oxide layer 609 surrounds the gate 605 and is thinner than the first insulating layer 606. The first insulating layer 606 has a uniform thickness along the trench sidewalls. Furthermore, the shielded gate 607 and the gate 605 are insulated by an inter-polysilicon oxide layer 608.

[0062] Figure 7A According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 5A The invention has a similar structure except for the different epitaxial layer structure. In the present invention, the N-type epitaxial layer includes two stepped epitaxial layers with different doping concentrations: a bottom first epitaxial layer 724 (N1, as shown in the figure) with a doping concentration of D1 and a top second epitaxial layer 734 (N2, as shown in the figure) located above the bottom first epitaxial layer 724 with a doping concentration of D2, wherein the relationship between D1 and D2 is D2 <D1,以提高击穿电压、降低比导通电阻。

[0063] Figure 7B According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 5A The invention has a similar structure except for the different epitaxial layer structure. In the present invention, a source body region T SB (between line AA and line BB) is formed on the upper part of the epitaxial layer, an oxide layer charge balance region T OCB (between BB and DD lines), a mesa region formed between two adjacent gate trenches 703', below the body region 710' and above the bottom of the shielding gate 707', a buffer zone T B , formed between the N+ substrate 701' and the bottom of the shielding gate 707' (between the DD line and the EE line), located at T OCB The epitaxial layer inside is composed of two multi-step epitaxial (MSE) layers with different doping concentrations: a bottom first epitaxial layer 724' (N) with a doping concentration of D1 and located on the buffer epitaxial layer 722' (NB, as shown, between the DD line and the EE line) S1 As shown in the figure, between CC line and DD line) and a top second epitaxial layer 734' (N) located on the bottom first epitaxial layer 724' with a doping concentration of D2. S2 , as shown in the figure, between line BB and line CC), where the relationship between D1 and D2 is D2 <D1。此外,位于T SB区 The doping concentration of the epitaxial layer is related to the OCB区 The doping concentration of the second epitaxial layer 734' on the top of the MSE layer is the same, and the doping concentration DB of the buffer epitaxial layer 722' is lower than that of the buffer epitaxial layer 722' located in the OCB region T OCB The doping concentration of each MSE layer.

[0064] Figure 8According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. The SiC SGT device is an IGBT device. Figure 5B The invention has a similar structure, except for a different substrate and an additional N-buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 801 and further includes an N-buffer layer 822 (NB, as shown) with a resistivity Rb, located between the P+ substrate 801 and an N-type epitaxial layer 802. The N-type epitaxial layer 802 is a single epitaxial layer with a uniform doping concentration and a resistivity R, where R>Rb.

[0065] Figure 9 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 7A The invention has a similar structure, except for a different gate trench structure and an additional N-type shielding region. Within each gate trench 903, a shielding gate 907 (SG, as shown) is located in the middle of the trench, and a pair of split gates 905 (G, as shown) are formed around the upper portion of the shielding gate 907. A second insulating layer 919, used to isolate the shielding gate 907 from the gate 905, covers the upper portion of the shielding gate 907. The second insulating layer 919 is formed simultaneously with the gate oxide layer 909 during the device fabrication process. Furthermore, the invention includes an N-type shielding region 915 (NS, as shown) for gate oxide protection, located directly below the gate trench 903 in the bottom first N-type epitaxial layer 924.

[0066] Figure 10 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 7B The invention has a similar structure, except for a different gate trench structure and an additional N-type shielding region. In each gate trench 1003, a shielding gate 1007 (SG, as shown) is located in the middle of the trench, and a pair of split gates 1005 (G, as shown) are formed around the upper portion of the shielding gate 1007. A second insulating layer 1019, which isolates the shielding gate 1007 from the gate 1005, covers the upper portion of the shielding gate 1007. The second insulating layer 1019 is formed simultaneously with the gate oxide layer 1009 during the device fabrication process. Furthermore, the invention includes an N-type shielding region 1015 (NS, as shown) for gate oxide protection, located directly below the gate trench 1003 in the N-type buffer layer 1022.

[0067] Figure 11 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 8 The invention has a similar structure, except for a different gate trench structure. In each gate trench 1103, a shield gate 1107 (SG, as shown) is located in the middle of the trench, and a pair of split gates 1105 (G, as shown) are formed around the top of the shield gate 1107. A second insulating layer 1119, which isolates the shield gate 1107 from the gate 1105, covers the top of the shield gate 1107. The second insulating layer 1119 and the gate oxide layer 1109 are formed simultaneously during the device manufacturing process.

[0068] Figure 12A FIG2 is a top view of another preferred SiC power device with stripe-shaped cells according to the present invention. Gate trench 1203 is separated from source-body Schottky contact trench 1204, wherein gate trench 1203 is stripe-shaped and source-body Schottky contact trench 1204 is surrounded by P shield region 1218. According to the present invention, sidewall P regions 1217 and junction barrier Schottky diode regions 1230 are alternately formed along both sidewalls of source-body Schottky contact trench 1204.

[0069] Figure 12B According to the present invention Figure 12A A cross-sectional view of a preferred A2-A2' section of the embodiment shown. Figure 2D The invention has a similar structure except that Figure 2D The sidewall P region 217"' (SP, such as Figure 2D ) is replaced by a Schottky barrier diode region 1229' in the present invention. According to the present invention, a junction barrier Schottky diode region 1230' is formed on both sidewalls of the source-body-Schottky contact trench 1204'.

[0070] Figure 12C According to the present invention Figure 12A A cross-sectional view of a preferred B2-B2' section of the embodiment shown. The SiC power device and Figure 2D The invention has a similar structure except that Figure 2D The Schottky barrier diode region 229'' is replaced by the sidewall P region 1217'' in the present invention. According to the present invention, the sidewall P region 1217'' is formed on both sidewalls of the source-body-Schottky contact trench 1204''.

[0071] Figure 13 According to the present invention Figure 12AAnother preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section. Figure 5B The invention has a similar structure except that Figure 5B The sidewall P region 517' is replaced by the Schottky barrier diode region 1329 in the present invention. According to the present invention, the junction barrier Schottky diode region 1330 is formed on both sidewalls of the source-body-Schottky contact trench 1304.

[0072] Figure 14 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section. The SiC SGT power device is an IGBT device. Figure 13 The invention has a similar structure, except for a different substrate and an additional N-buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 1401 and further includes an N-buffer layer 1422 (NB, as shown) with a resistivity Rb located between the P+ substrate 1401 and an N-type epitaxial layer 1402. The N-type epitaxial layer 1402 is a single epitaxial layer with a uniform doping concentration and a resistivity R, where R>Rb.

[0073] Figure 15 According to the present invention Figure 12A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 9 The invention has a similar structure except that Figure 9 The sidewall P region 917 is replaced by a Schottky barrier diode region 1529 in the present invention. According to the present invention, a junction barrier Schottky diode region 1530 is formed on both sidewalls of the source-body-Schottky contact trench 1504.

[0074] Figure 16 According to the present invention Figure 12A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A2-A2' section, which reveals the variation of the doping concentration of the N-type epitaxial layer along the vertical direction. Figure 15 The invention has a similar structure, except for a different substrate and an additional N-type buffer layer. In the present invention, the IGBT device is formed on a P+ substrate 1601 and further includes an N-type buffer layer 1622 (NB, as shown) located between the P+ substrate 1601 and a bottom first N-type epitaxial layer 1624 (N1, as shown).

[0075] Figure 17 According to the present invention Figure 2AAnother preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 2B The invention has a similar structure, except that in the present invention, the source-body-Schottky contact trench includes a first-type source-body-Schottky contact trench 1704 and a second-type source-body-Schottky contact trench 1714. The first-type source-body-Schottky contact trench 1704 is formed above the second-type source-body-Schottky contact trench 1714 and has a greater trench width than the second-type source-body-Schottky contact trench 1714. A PS region 1718 is formed around the sidewalls and bottom of the second-type source-body-Schottky contact trench 1714.

[0076] Figure 18 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 3A The invention has a similar structure, except that in the present invention, the source-body-Schottky contact trench includes a first-type source-body-Schottky contact trench 1804 and a second-type source-body-Schottky contact trench 1814. The first-type source-body-Schottky contact trench 1804 is formed above the second-type source-body-Schottky contact trench 1814 and has a greater trench width than the second-type source-body-Schottky contact trench 1814. A PS1 region 1818 is formed around the sidewalls and bottom of the second-type source-body-Schottky contact trench 1814.

[0077] Figure 19 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 17 The invention described above has a similar structure, except for a different gate trench structure. In the structure of the present invention, each gate trench 1903 includes a shielded gate 1907 (SG, as shown in the figure) located in the lower portion of the trench, and a single gate 1905 (G, as shown in the figure) located in the upper portion of the trench, above the shielded gate 1907. Shielded gate 1907 is insulated from the adjacent epitaxial layer by a first insulating layer 1906, while gate 1905 is insulated from the adjacent epitaxial layer by a gate oxide layer 1909. Gate oxide layer 1909 surrounds gate 1905 and is thinner than first insulating layer 1906. First insulating layer 1906 has a uniform thickness along the trench sidewalls. Shielded gate 1907 is also insulated from gate 1905 by an inter-polysilicon oxide layer 1908.

[0078] Figure 20 According to the present invention Figure 2AAnother preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 17 The invention described above has a similar structure, except that the structure of the present invention further includes an N-shielding region 2015 (NS, as shown in the figure) for gate oxide protection. The N-shielding region 2015 is located below the gate 2005 (G, as shown in the figure) in the N-type epitaxial layer 2002 and has a higher doping concentration than the N-type epitaxial layer 2002. Furthermore, the structure of the present invention further includes a current diffusion layer 2027 (Ncs, as shown in the figure) of the first conductivity type, located in the upper portion of the N-type epitaxial layer 2002, below the p-body region 2010, and surrounding at least the sidewalls of the gate 2005. This further prevents the formation of a pinched current path between the P-shielding region 2018 (PS, as shown in the figure) and the gate trench 2003. The doping concentration of the Ncs region 2027 is higher than that of the N-type epitaxial layer 2002, thereby further reducing the on-resistance.

[0079] Figure 21 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 18 The invention described above has a similar structure, except that the structure of the present invention further includes an N-shielding region 2115 (NS, as shown in the figure) for gate oxide protection. The N-shielding region 2115 is located below the gate 2105 (G, as shown in the figure) in the N-type epitaxial layer 2102 and has a higher doping concentration than the N-type epitaxial layer 2102. Furthermore, the structure of the present invention also includes a current diffusion layer 2127 (Ncs, as shown in the figure) of the first conductivity type, located in the upper portion of the N-type epitaxial layer 2102, below the p-body region 2110, and surrounding at least one sidewall of the gate 2105. This further prevents the formation of a pinched current path between the P-shielding region 2118 (PS1, as shown in the figure) and the gate trench 2103. The doping concentration of the Ncs region 2127 is higher than that of the N-type epitaxial layer 2102, thereby further reducing the on-resistance.

[0080] Figure 22 According to the present invention Figure 2A Another preferred cross-sectional view of the embodiment shown is a cross-sectional view of the A1-A1' section. Figure 19The invention described above has a similar structure, except that the structure of the present invention further includes an N-shielding region 2215 (NS, as shown in the figure) for gate oxide protection. The N-shielding region 2215 is located below the gate trench 2203 in the N-type epitaxial layer 2202 and has a higher doping concentration than the N-type epitaxial layer 2202. Furthermore, the structure of the present invention further includes a current diffusion layer 2227 (Ncs, as shown in the figure) of the first conductivity type, located in the upper portion of the N-type epitaxial layer 2202, below the p-body region 2210, and surrounding at least the sidewalls of the gate 2205. This further prevents the formation of a pinched current path between the P-shielding region 2218 (PS, as shown in the figure) and the gate trench 2203. The doping concentration of the Ncs region 2227 is higher than that of the N-type epitaxial layer 2202, thereby further reducing the on-resistance.

[0081] While the present invention has been described in terms of preferred embodiments, it should be understood that the foregoing disclosure is not intended to limit the present invention. While the embodiments described above generally relate to N-channel devices, the embodiments are also applicable to P-channel devices by reversing the polarity of the conductivity type. After reading the foregoing disclosure, various alternatives and modifications will undoubtedly become apparent to those skilled in the art. Therefore, the appended claims should be construed to cover all alternatives and modifications that fall within the true spirit and scope of the present invention.

Claims

1. A silicon carbide power device comprising a plurality of cells, wherein each cell is located in an active region, further comprising: an epitaxial layer of a first conductivity type located on the substrate; a gate trench formed in the active region, surrounded by a source region having the first conductivity type, the source region being located in a body region having the second conductivity type and located on an upper portion of the epitaxial layer; a source-body-Schottky contact trench, passing through the source region and the body region, and extending into the epitaxial layer; a P shielding region of the second conductivity type, for reducing the electric field strength of the gate oxide layer, surrounding the bottom of the source-body-Schottky contact trench and separated from the gate trench; a body contact region having the second conductivity type, located in the body region; a body combination region, comprising the body region and the body contact region; a sidewall P region of the second conductivity type, selectively formed along a portion of the sidewall of the source-body-Schottky contact trench and connecting the P shield region to the body contact region, wherein the doping concentration of the P shield region is higher than that of the sidewall P region; The source metal is filled into the source-body-Schottky contact trench and contacts the source region, the body contact region and the P shield region; and a Schottky barrier diode region is formed between the body contact region and the P shield region by establishing a Schottky contact with the epitaxial layer; A junction barrier Schottky diode region is formed between the source region and the bottom of the P shielding region, which includes a first PN junction diode, a second PN junction diode and the Schottky barrier diode, wherein the first PN junction diode is formed between the body combination region and the epitaxial layer, and the second PN junction diode is formed between the P shielding region and the epitaxial layer.

2. The silicon carbide power device according to claim 1, wherein: The gate trench also includes a gate surrounded by a first insulating layer at the bottom of the gate trench and a gate oxide layer at the sidewall of the gate trench, wherein the thickness of the first insulating layer is greater than that of the gate oxide layer.

3. The silicon carbide power device according to claim 1, wherein: The gate trench also includes a gate and a shielding gate, the shielding gate and the epitaxial layer are insulated by a first insulating layer, the gate and the epitaxial layer are insulated by a gate oxide layer, the shielding gate and the gate are insulated by an inter-polysilicon oxide layer, and the thickness of the gate oxide layer is less than that of the first insulating layer.

4. The silicon carbide power device according to claim 3, wherein: The shielding gate is located at a lower portion of the gate trench, and the gate is located at an upper portion of the gate trench.

5. The silicon carbide power device according to claim 3, wherein: The shielding gate is located in the middle of the gate trench, and the gate is a pair of split gates formed around two sides of the upper portion of the shielding gate.

6. The silicon carbide power device according to claim 1, wherein: The sidewall P region is formed along a first sidewall of the source-body-Schottky contact trench, and the Schottky barrier diode is formed along a second sidewall opposite to the first sidewall of the source-body-Schottky contact trench.

7. The silicon carbide power device according to claim 1, wherein: The sidewall P regions and the Schottky barrier diode regions are alternately formed along two sidewalls of the source-body-Schottky contact trench.

8. The silicon carbide power device according to claim 1, further comprising a current diffusion region having the first conductivity type and surrounding a higher portion of the gate trench sidewall, wherein the doping concentration of the current diffusion region is higher than that of the epitaxial layer.

9. The silicon carbide power device according to claim 1, further comprising at least one N shielding region having the first conductivity type, which is located in the epitaxial layer at a deeper position than the gate trench and has a higher doping concentration than the epitaxial layer.

10. The silicon carbide power device according to claim 1 further comprises a second P shielding region having the second conductivity type, wherein the second P shielding region surrounds the sidewall of the gate trench opposite to the junction barrier Schottky diode region and is adjacent to the body region, and further extends along a portion of the bottom area of ​​the gate trench.

11. The silicon carbide power device according to claim 1, wherein: The substrate has the first conductivity type, and the epitaxial layer is a single epitaxial layer with uniform doping concentration.

12. The silicon carbide power device according to claim 3, wherein: The substrate has the first conductivity type, and the epitaxial layer is a multi-step epitaxial layer with different doping concentrations, the doping concentration of which decreases stepwise along the sidewall of the gate trench and from the substrate to the upper surface of the epitaxial layer, wherein each of the multi-step epitaxial layers has a uniform doping concentration.

13. The silicon carbide power device according to claim 12, wherein: The epitaxial layer includes at least two stepped epitaxial layers with different doping concentrations: a bottom epitaxial layer with a doping concentration of D1 and a top epitaxial layer located above the bottom epitaxial layer with a doping concentration of D2, wherein the relationship between D1 and D2 is D2 <D1。 14. The silicon carbide power device according to claim 1, wherein: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the silicon carbide power device further includes a buffer layer located between the substrate and the epitaxial layer, having the first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is R>Rb.

15. The silicon carbide power device according to claim 1, wherein: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and further includes a buffer layer located between the substrate and the epitaxial layer, having the first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is R>Rb, and a plurality of heavily doped regions located in the substrate and having the first conductivity type to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

16. The silicon carbide power device according to claim 2, wherein: The source-body-Schottky contact trench has a greater trench depth than the gate trench.

17. The silicon carbide power device according to claim 3, wherein: The epitaxial layer further includes an oxide layer charge balance region and a buffer region; the oxide layer charge balance region having the first conductivity type is formed in a mesa region between two adjacent gate trenches, below the body region and above the bottom of the shielding gate; The buffer zone located in the epitaxial layer and having the first conductivity type is formed between the substrate and the oxide layer charge balance region; the epitaxial layer located in the oxide layer charge balance region has a multi-step epitaxial layer structure, and its doping concentration decreases stepwise along the sidewall of the gate trench and from the bottom of the shielding gate to the body region, wherein each of the multi-step epitaxial layers has a uniform doping concentration; the doping concentration of the epitaxial layer located in the buffer zone is lower than the doping concentration of the multi-step epitaxial layer located in the oxide layer charge balance region.

18. The silicon carbide power device according to claim 1, wherein: The source metal is a multi-metal layer including a nickel layer as a first metal layer, a titanium layer as a second metal layer, an aluminum layer as a third metal layer, and a tungsten layer as a fourth metal layer.

19. The silicon carbide power device according to claim 1, wherein: The source-body-Schottky contact trench includes a first-type source-body-Schottky contact trench and a second-type source-body-Schottky contact trench; the first-type source-body-Schottky contact trench is located above the second-type source-body-Schottky contact trench, and its trench width is greater than that of the second-type source-body-Schottky contact trench; The P shielding region surrounds the sidewalls and the bottom of the second-type source-body-Schottky contact trench.

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