Shield gate trench MOSFET device structure
By setting trench structures with different widths in a shielded gate trench MOSFET device, the hole lithography alignment problem is solved and the reliability and electrical performance of the device are improved.
Patent Information
- Application Number
- CN202422751232.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-12
AI Technical Summary
In the prior art, as the pitch of shielded gate trench MOSFET devices shrinks, the requirements for hole photolithography alignment process increase, leading to an increased risk of short circuit between the gate and drain, and a decrease in device reliability.
A shielded gate trench MOSFET device structure is designed. By setting trenches of different widths in the active area and the terminal area, the widths of the second trench and the third trench are larger than the first trench, meeting the requirements of the lithography alignment process, and the cross-arrangement is used to increase the ease of alignment, and to match the gate and source lead-out structures.
The accuracy of lithography alignment is improved, the risk of device failure is reduced, and the effective proportion of the active area is increased, while meeting electrical parameter and reliability requirements, such as the reverse withstand voltage value is not reduced.
Smart Images
Figure CN223452325U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of integrated circuit, concretely relates to a shielded gate trench MOSFET device structure. BACKGROUND
[0002] Shielded gate trench MOSFET (SGT-MOSFET, Shielded-Gate Trench MOSFET) is an advanced discrete device MOSFET structure, with the characteristics of high breakdown voltage, low on-resistance and fast switching speed. The general structure of shielded gate trench MOSFET is to fill polycrystalline silicon in the trench, and the polycrystalline silicon is divided into two parts: the polycrystalline silicon located in the lower part of the trench, which forms the source poly (source poly), that is, the shielded gate polysilicon, which is short-circuited with the source of the device; the polycrystalline silicon located in the upper part of the trench forms the gate poly, and the two layers of polycrystalline silicon are separated by a silicon oxide film.
[0003] With the development of technology, greater current density is needed, that is, smaller internal resistance under unit area, which requires more SGT-MOSFET units in parallel in the same area, and the width of each unit is called pitch, so it is necessary to reduce the pitch of each unit, and the width of the trench (trench) also needs to be reduced, so higher requirements are put forward for hole lithography alignment process, which is also a key factor limiting the reduction of pitch. If the hole alignment deviates, it will cause short circuit between the gate and the drain, and the chip will be scrapped, and the device will be directly invalid due to leakage. UTILITY MODEL CONTENTS
[0004] In view of the deficiencies of the prior art, the utility model discloses a shielded gate trench MOSFET device structure.
[0005] The technical scheme adopted by the utility model is as follows:
[0006] A shielded gate trench MOSFET device structure, comprising at least one group of MOSFET units; the MOSFET unit comprises an active region and a terminal region;
[0007] The active region comprises a first trench, and a shielded gate structure is formed in the first trench; a body region and a source region are formed on the outside of the two sides of the first trench, and the body region and the source region are connected to the source region metal through a source region contact hole;
[0008] The terminal region comprises a second trench and a third trench, a source lead-out structure is formed in the second trench, and the source lead-out structure comprises a source poly; the source poly is connected to the source region metal through a source poly contact hole;
[0009] A gate lead-out structure is formed in the third trench, and the gate lead-out structure includes gate polysilicon; the gate polysilicon is connected to gate region metal through a gate polysilicon contact hole.
[0010] The width of the second trench and the width of the third trench are greater than the width of the first trench, and the width of the second trench meets the requirement of a source polysilicon contact hole photolithography alignment process, and the width of the third trench meets the requirement of a gate polysilicon contact hole photolithography alignment process.
[0011] Further, the width of the second trench ranges from 0.6 um to 1.0 um; the width of the third trench ranges from 0.6 um to 1.0 um; and the width of the first trench ranges from 0.25 um to 0.4 um.
[0012] Further, the second trench and the third trench are arranged in a staggered manner.
[0013] Further, when the shielded gate trench MOSFET device structure includes multiple groups of MOSFET units, the first trench, the second trench, and the third trench in the multiple groups of MOSFET units are parallel to each other; the multiple groups of source region metals of the first trench and the second trench in the multiple groups of MOSFET units are integrated; the gate polysilicon in the MOSFET unit is connected to a gate metal line through a gate polysilicon contact hole; and the gate metal lines of the multiple groups of MOSFET units are connected to the gate region metal.
[0014] Further, the shielded gate structure of the active region includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench; a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; and an IPO oxide layer is formed between the gate polysilicon and the source polysilicon.
[0015] Further, in the source lead-out structure, a field oxide layer is formed between the inner wall of the second trench and the source polysilicon.
[0016] Further, the gate lead-out structure includes gate polysilicon and source polysilicon; a field oxide layer is formed between the gate polysilicon and the inner wall of the third trench; a field oxide layer is formed between the source polysilicon and the inner wall of the third trench; and a field oxide layer is formed between the gate polysilicon and the source polysilicon.
[0017] The above shielded gate trench MOSFET device manufacturing method includes the following steps:
[0018] An epitaxial layer of a second conductive type is grown on a substrate of a first conductive type, and a first trench, a second trench, and a third trench are formed; a field oxide layer is formed at the bottom and the sidewall of the first trench, the second trench, and the third trench;
[0019] Depositing source polysilicon to fill the first trench, the second trench and the third trench, and planarizing to the surface of the epitaxial layer;
[0020] Etching the source polysilicon in the first trench and the third trench by a part of thickness, and etching away the field oxide layer on the sidewall of the corresponding first trench and third trench;
[0021] Forming the field oxide layer again on the sidewall of the first trench and the third trench and the upper part of the source polysilicon;
[0022] After the photolithography and etching process, etching away the oxide layer on the sidewall and the bottom of the first trench, and then generating the gate oxide layer on the sidewall and the bottom of the first trench;
[0023] Depositing gate polysilicon to fill the first trench and the third trench, and planarizing to the surface of the epitaxial layer;
[0024] Doping on the front surface of the first trench to form the body region and the source region, then forming the active region contact hole, the source polysilicon contact hole and the gate polysilicon contact hole respectively, and then forming the source metal and the gate metal.
[0025] Further technical solutions are that the active region contact hole is formed on the side of the first trench through the photolithography and etching of the contact hole; the source polysilicon contact hole is formed above the second trench; and the gate polysilicon contact hole 109 is formed above the third trench.
[0026] Further technical solutions are that the source metal of the first trench and the second trench of the plurality of MOSFET units in the MOSFET device is integrally formed.
[0027] The beneficial effects of the utility model are as follows:
[0028] The utility model provides a kind of terminal structure of shielded gate trench MOSFET, solve the problem that the width of source polysilicon and gate polysilicon is reduced simultaneously due to the width of trench is reduced, and then cause the alignment limit problem of source polysilicon contact hole and gate polysilicon contact hole photolithography process.
[0029] In the technical scheme provided in the utility model, the width of the second trench and the width of the third trench are greater than the width of the first trench. Such setting can make the width of the second trench and the third trench independent of the first trench, make the second trench and the third trench wider, increase the ease of alignment, and cooperate with the gate lead-out structure and the source lead-out structure without affecting the design of making the first trench narrower. Not only solve the limitation of gate polysilicon and source polysilicon hole exposure alignment, but also increase the effective proportion of active region, and meet the electrical parameters and reliability requirements of the device, such as reverse withstand voltage BVDSS (drain-source breakdown voltage). BRIEF DESCRIPTION OF DRAWINGS
[0030] Figure 1 Layout schematic diagram of the shielding gate trench MOSFET device structure in the embodiment of the utility model.
[0031] Figure 2 For Figure 1 The screenshot along the d line.
[0032] Figure 3 For Figure 1 The screenshot along the b line.
[0033] Figure 4 The schematic diagram of the trench forming step in the embodiment of the utility model.
[0034] Figure 5 The schematic diagram of the trench backfilling step in the embodiment of the utility model.
[0035] Figure 6 The schematic diagram of the etching step in the embodiment of the utility model.
[0036] Figure 7 The schematic diagram of the field oxide layer regrowth step in the embodiment of the utility model.
[0037] Figure 8 The schematic diagram of the gate oxide layer growth step in the embodiment of the utility model.
[0038] Figure 9 The schematic diagram of the active region in the gate polysilicon deposition step in the embodiment of the utility model.
[0039] Figure 10 The schematic diagram of the termination region in the gate polysilicon deposition step in the embodiment of the utility model.
[0040] Figure 11 The partial screenshot of the active region in the embodiment of the utility model.
[0041] Figure 12 For Figure 3 The partial screenshot including the source polysilicon contact hole structure.
[0042] Figure 13 For Figure 1 The screenshot along the c line.
[0043] In the figure: 1, first trench; 2, second trench; 3, third trench; 100, substrate; 101, epitaxial layer; 102, trench; 103, field oxide layer; 104, source polysilicon; 105, gate oxide layer; 106, gate polysilicon; 107, source contact hole; 108, source polysilicon contact hole; 109, gate polysilicon contact hole; 110, source region metal; 111, gate region metal; 112, source region; 113, dielectric layer; 114, bulk region. DETAILED DESCRIPTION
[0044] The specific implementation of the present application is described below with reference to the accompanying drawings.
[0045] Figure 1 The layout of the shielding gate trench MOSFET device structure in the embodiment of the present application is shown in the figure. As shown in the figure, the shielding gate trench MOSFET device structure comprises at least one MOSFET unit. The MOSFET unit comprises an active region and a termination region. In the embodiment, the active region refers to the part of the MOS tube comprising the transistor key structure, including but not limited to the source region (source), the body region (body), etc., and the termination region (termination area) generally refers to the part for electrical connection and protection. Figure 1
[0046] Figure 2 The part of the structure along the line a in the figure is shown. Figure 1 The part of the structure along the line a in the figure is shown. Figure 11 The part of the structure along the line a in the figure is shown. Figure 11 The part of the structure along the line a in the figure is shown. Figure 1 The part of the structure along the line a in the figure is shown. Figure 1 The active region comprises a first trench 1, and a shielding gate structure is formed in the first trench 1. The shielding gate structure comprises gate polysilicon 106 and source polysilicon 104. A field oxide layer 103 is formed between the source polysilicon 106 and the inner wall of the first trench 1, and a gate oxide layer 105 is formed between the gate polysilicon 106 and the inner wall of the first trench 1. An IPO oxide layer is formed between the gate polysilicon 106 and the source polysilicon 104. A body region 114 is formed on the outer side of the first trench 1, and a source region 112 is formed on the body region 114 on the outer side of the first trench 1. A dielectric layer 113 is formed on the upper part of the first trench 1 and covers the source region. A source contact hole 107 passes through the dielectric layer, one end of the source contact metal in the source contact hole 107 contacts the source region metal 110, and the other end contacts the source region 112 and the body region 114. In the embodiment, the body region 114 is P-type, and the source region 112 is N-type. Figure 2 Figure 11 The termination region comprises a second trench 2 and a third trench 3. The part of the structure along the line b in the figure is shown.
[0047] The part of the structure along the line b in the figure is shown. Figure 3 The part of the structure along the line b in the figure is shown. Figure 1 The source polysilicon contact hole structure is formed in the second trench 2, and the source polysilicon contact hole structure comprises source polysilicon 104. A field oxide layer 103 is formed between the inner wall of the second trench 2 and the source polysilicon 104. The source polysilicon 104 is connected to the source region metal 110 through a source polysilicon contact hole 108. Figure 12 Figure 3 The part of the structure along the line b in the figure is shown. Figure 3 The part of the structure along the line b in the figure is shown. Figure 12 The part of the structure along the line b in the figure is shown.
[0048] Figure 13 for Figure 1 A screenshot along line c in the figure. Figure 13 As shown, a gate lead structure is formed in the third trench 3, and the gate lead structure includes a gate polysilicon 106. The gate polysilicon 106 is connected to the gate metal 111 through a gate polysilicon contact hole 109. A field oxide layer is formed between the gate polysilicon 106 and the inner wall of the third trench 3, and a field oxide layer 103 is formed between the source polysilicon 104 and the inner wall of the third trench 3. A field oxide layer 103 is formed between the gate polysilicon 106 and the source polysilicon 104.
[0049] Combine Figure 1-3 as well as Figure 11-13 In this embodiment, the widths of the second trench 2 and the third trench 3 are greater than the width of the first trench 1. Furthermore, the widths of the second trench 2 and the third trench 3 at least meet the photolithography alignment requirements for the source polysilicon contact hole 108 in the second trench 2 and the gate polysilicon contact hole 109 in the third trench 3, respectively. This arrangement allows the widths of the second trench 2 and the third trench 3 to be independent of the first trench 1, making them wider and facilitating alignment. Furthermore, this arrangement, in conjunction with the gate and source lead-out structures, does not affect the narrower design of the first trench 1. This not only overcomes the limitations of exposure alignment for the gate and source polysilicon holes, but also ensures that the structure meets the device's electrical requirements and reliability while increasing the active area ratio. For example, the device's reverse withstand voltage (BVDSS) is not reduced.
[0050] Preferably, the width of the second trench 2 is in the range of 0.6 μm to 1.0 μm, the width of the third trench 3 is in the range of 0.6 μm to 1.0 μm, and the width of the first trench 1 is in the range of 0.25 μm to 0.4 μm. Of course, the above-mentioned width ranges of the second trench 2 and the third trench 3 are preferred values. Those skilled in the art can further widen the widths of the second trench 2 and the third trench 3 according to actual needs or process conditions without affecting the electrical characteristics of the device.
[0051] Further, such as Figure 1 As shown, the second trenches 2 and the third trenches 3 are arranged alternately and crosswise, which can further reduce the area of the MOSFET unit.
[0052] Further, such as Figure 1As shown, when the shielded gate trench MOSFET device structure includes multiple groups of MOSFET units, the first trench 1, the second trench 2 and the third trench 3 in the multiple groups of MOSFET units are all parallel to each other, and the source region metal 110 of the first trench 1 and the second trench 2 of the MOSFET device is integral, the gate polysilicon 106 is connected to the gate metal line after passing through the gate polysilicon contact hole 109, and the gate metal lines of the multiple groups of MOSFET units are all connected to the gate region metal 111.
[0053] The manufacturing method of the shielded gate trench MOSFET device structure will be described below. Specifically, it includes the following steps:
[0054] Step 1, forming a trench. Figure 4 It is a schematic diagram of the step of forming a trench in the embodiment of the utility model. As shown in the figure, Figure 4 As shown, the target thickness of the second conductive type epitaxial layer 101 is grown on the first conductive type substrate 100, and the trench 102 of the target depth is formed. The trench 102 includes the first trench 1, the second trench 2 and the third trench 3, and the field oxide layer 103 is formed at the bottom and the sidewall of the trench 102.
[0055] Generally, the first conductive type is N type, and the second conductive type is P type, or the first conductive type can be P type and the second conductive type can be N type. The trench 102 can be formed by trench photolithography, etching and other processes. The field oxide layer 103 can be formed by, but not limited to, thermal oxidation, CVD deposition and other methods. The target thickness and the target depth in this step and the subsequent steps are determined according to the device model and the functional parameters, and can be adjusted according to the known technology by the person skilled in the art. For example, in this step, the thickness of the epitaxial layer 101 of the common 30V SGTMOSFET device is about 2.8um, the resistivity is about 0.07ohm-cm, and the depth of the trench 102 is about 1.3um. The specific values of the target thickness and the target depth in the subsequent steps are not described here.
[0056] Step 2, backfilling the trench, Figure 5 It is a schematic diagram of the step of backfilling the trench in the embodiment of the utility model. As shown in the figure, Figure 5 As shown, the source polysilicon 104 of the target thickness is deposited to backfill the trench 102, and is planarized to the surface of the epitaxial layer 101 by CMP.
[0057] Step 3, etching. Figure 6 It is a schematic diagram of the etching step in the embodiment of the utility model. As shown in the figure, Figure 6As shown in the figure, a pattern to be etched is formed by a photoetch process, and a photoresist is used as a mask layer to etch away the source polysilicon 104 of a target thickness in the first trench 1 and the third trench 3, specifically, the thickness of the etched away source polysilicon 104 is a part of the depth of the first trench 1 and the third trench 3, and the corresponding field oxide layer 103 on the sidewalls of the corresponding first trench 1 and third trench 3 is etched away. Then the photoresist is removed.
[0058] Step 4, growing the field oxide layer again. Figure 7 It is a schematic diagram of the step of growing the field oxide layer again in the embodiment of the utility model. As shown in the figure, Figure 7 A field oxide layer 103 of a target thickness is formed on the sidewalls of the first trench 1 and the third trench 3 and the upper part of the source polysilicon 104. Specifically, the field oxide layer 103 can be formed by, but not limited to, thermal oxidation, CVD deposition and the like.
[0059] Step 5, growing the gate oxide layer. Figure 8 It is a schematic diagram of the step of growing the gate oxide layer in the embodiment of the utility model. As shown in the figure, Figure 8 A field oxide layer 103 on the sidewalls and bottom of the first trench 1 of the active region is etched away by a photoetch process to form a pattern to be etched, a photoresist is used as a mask layer, the photoresist is removed, and then a gate oxide layer 105 is generated on the sidewalls and bottom of the first trench 1 by a thermal oxidation method.
[0060] Step 6, depositing the gate polysilicon. Figure 9 It is a schematic diagram of the active region in the step of depositing the gate polysilicon in the embodiment of the utility model. Figure 10 It is a schematic diagram of the terminal region in the step of depositing the gate polysilicon in the embodiment of the utility model. As shown in the figure, Figure 9 , Figure 10 The gate polysilicon is deposited, the first trench and the third trench are backfilled, and CMP planarization is performed to the surface of the epitaxial layer 101.
[0061] Step 7, ion implantation of impurities is performed on the front surface of the first trench and annealing is performed to form a body region 114, and then photoetch implantation of impurities is performed and annealing is performed to form a source region 112. In the embodiment of the utility model, the body region 114 is P-type, and the source region 112 is N-type, and the type of the implanted impurities can be determined according to the type of the doping.
[0062] Step 8, depositing a dielectric layer, and then performing photoetch and etching of the contact hole to form an active region contact hole 107, a source polysilicon contact hole 108 and a gate polysilicon contact hole 109 respectively;
[0063] Step 9, metal deposition, metal photoetch and etching to form a source region metal 110 and a gate region metal 111. As shown in the figure, Figure 1As shown, the source region metal 110 of the first trench 1 and the second trench 2 of the MOSFET device is integral. The gate polysilicon 106 is connected to the gate metal line after the gate polysilicon contact hole 109, and the gate metal line of each group of MOSFET devices is connected to the gate region metal 111.
[0064] The structure related to steps 7-9 can refer to Figure 10-12 , which shows the active region contact hole 107, the source polysilicon contact hole 108 and the gate polysilicon contact hole 109, and the source region metal 110 and the gate region metal 111. Figure 10-12
[0065] In this embodiment, the specific process parameters of steps 1-9 are adjusted and selected by those skilled in the art according to the general process knowledge of integrated circuits and the device parameter requirements, and the specific process parameters are not the content to be protected by the present application, and will not be described herein.
[0066] The above description is an explanation of the present application, not a limitation of the present application, the scope of the present application is defined in the claims, and the present application can be modified in any form without departing from the basic structure of the present application.
Claims
1. A shielded gate trench MOSFET device structure, characterized in that: The device comprises at least one group of MOSFET units; the MOSFET units include an active region and a terminal region; The active area includes a first trench, and a shield gate structure is formed in the first trench; a body region and a source region are formed on both sides of the first trench, and the body region and the source region are connected to the source region metal through a source region contact hole; The terminal region includes a second trench and a third trench, a source lead-out structure is formed in the second trench, and the source lead-out structure includes source polysilicon; the source polysilicon is connected to the source region metal through a source polysilicon contact hole; forming a gate lead-out structure in the third trench, wherein the gate lead-out structure includes gate polysilicon; the gate polysilicon is connected to the gate metal through a gate polysilicon contact hole; The width of the second trench and the width of the third trench are greater than the width of the first trench, and the width of the second trench meets the requirements of the source polysilicon contact hole lithography alignment process, and the width of the third trench meets the requirements of the gate polysilicon contact hole lithography alignment process.
2. The shielded gate trench MOSFET device structure according to claim 1, wherein: The width of the second groove ranges from 0.6um to 1.0um; the width of the third groove ranges from 0.6um to 1.0um; and the width of the first groove ranges from 0.25um to 0.4um.
3. The shielded gate trench MOSFET device structure according to claim 1, wherein: The second grooves and the third grooves are arranged to cross each other with an interval.
4. The shielded gate trench MOSFET device structure according to claim 1, wherein: When the shielded gate trench MOSFET device structure includes multiple groups of MOSFET units, the first trenches, second trenches and third trenches in the multiple groups of MOSFET units are parallel to each other; the multiple groups of source metals of the first trenches and second trenches of the multiple MOSFET units in the MOSFET device are integrated; the gate polysilicon in the MOSFET unit is connected to the gate metal line through the gate polysilicon contact hole, and the gate metal lines of the multiple groups of MOSFET units are all connected to the gate metal.
5. The shielded gate trench MOSFET device structure according to claim 1, wherein: The shielding gate structure of the active area includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; and an IPO oxide layer is formed between the gate polysilicon and the source polysilicon.
6. The shielded gate trench MOSFET device structure according to claim 1, wherein: In the source lead-out structure, a field oxide layer is formed between the inner wall of the second trench and the source polysilicon.
7. The shielded gate trench MOSFET device structure according to claim 1, wherein: The gate lead-out structure includes gate polysilicon and source polysilicon; the gate polysilicon and the inner wall of the third trench form a field oxide layer, the source polysilicon and the inner wall of the third trench form a field oxide layer, and a field oxide layer is formed between the gate polysilicon and the source polysilicon.