Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device can be an HEMT device, such as a depletion mode HEMT device, and can also be an enhancement mode HEMT device. The semiconductor device comprises a heterojunction, a source electrode, a drain electrode, a grid electrode, a grid field plate, a source field plate, a first dielectric layer and a second dielectric layer, the source electrode, the drain electrode and the grid electrode are all arranged on the heterojunction, and the source electrode, the drain electrode and the grid electrode are in contact with the heterojunction. The gate field plate is arranged on the gate electrode and electrically connected with the gate electrode, and the gate field plate is located between the source electrode and the drain electrode. The source field plate is arranged on the side, close to the drain electrode, of the gate field plate, and the source field plate is electrically connected with the source electrode. The first dielectric layer and the second dielectric layer are arranged between the side wall of the gate field plate and the source field plate, the first dielectric layer is located on the side wall of the gate field plate, and the second dielectric layer is located between the first dielectric layer and the source field plate. As an HEMT device, the semiconductor device can be applied to a radio frequency device and a power device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, a chip and an electronic device. Background Art

[0002] A high electron mobility transistor (HEMT) device is a semiconductor device having a heterojunction, which includes a barrier layer and a channel layer. A two-dimensional electron gas (2DEG) channel is generated at the interface between the barrier layer and the channel layer due to the polarization effect. Under the action of an electric field, the two-dimensional electron gas can be used to efficiently conduct electrons.

[0003] HEMT devices are widely used in the fields of high frequency, high temperature and high power density. How to improve the performance and reliability of the devices has become a problem that needs to be solved urgently in this field. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, a chip and an electronic device, aiming to improve the performance and reliability of the device.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided. The semiconductor device may be a HEMT device, for example, a depletion-mode HEMT device or an enhancement-mode HEMT device, and may be applied to radio frequency devices and power devices.

[0007] The semiconductor device includes a heterojunction, a source, a drain, a gate, a gate field plate, a source field plate, a first dielectric layer and a second dielectric layer, wherein the source, the drain and the gate are all arranged on the heterojunction, and the source, the drain and the gate are respectively in contact with the heterojunction. The gate field plate is arranged on the gate and is electrically connected to the gate, and the gate field plate is located between the source and the drain. The source field plate is arranged on a side of the gate field plate close to the drain, and the source field plate is electrically connected to the source. The first dielectric layer and the second dielectric layer are both arranged between the side wall of the gate field plate and the source field plate, the first dielectric layer is located on the side wall of the gate field plate, and the second dielectric layer is located between the first dielectric layer and the source field plate.

[0008] In the semiconductor device provided by the above-mentioned embodiment of the present application, the source, drain and gate are arranged on the heterojunction and are respectively in contact with the heterojunction. The gate field plate is arranged on the gate and is electrically connected to the gate, and the gate field plate is located between the source and the drain. The source field plate is arranged on the side of the gate field plate close to the drain, and the source field plate is electrically connected to the source.

[0009] By adding a first dielectric layer and a second dielectric layer between the side wall of the gate field plate and the source field plate, the first dielectric layer is located on the side wall of the gate field plate, and the second dielectric layer is located between the first dielectric layer and the source field plate, so that the first dielectric layer and the second dielectric layer are spaced between the side wall of the gate field plate and the source field plate, the number and thickness of the dielectric layers on the side wall of the gate field plate are selectively increased, thereby increasing the distance between the side wall of the gate field plate and the source field plate, which can improve the leakage and stress concentration between the side wall of the gate field plate and the source field plate, and improve the reliability of the device.

[0010] Furthermore, since the first dielectric layer is located on the side wall of the gate field plate, the thickness of the dielectric layer on the side wall of the gate field plate is selectively increased, and the number and thickness of the dielectric layer between the source field plate and the heterojunction will not be increased, that is, the distance between the portion of the source field plate close to the drain and the heterojunction will not be increased, which is beneficial to weakening the electric field line aggregation effect in the device, flattening the electric field of the two-dimensional electron gas channel and evenly distributing it, which is beneficial to reducing the parasitic capacitance between the gate and the drain, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0011] In some embodiments, the first dielectric layer covers the sidewalls of the gate field plate and exposes the surface of the gate field plate away from the heterojunction. The orthographic projection of the first dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction.

[0012] In the above embodiment, the first dielectric layer is a patterned film layer, not a film layer covering the entire surface. The thickness of the dielectric layer covering the side wall of the gate field plate can be selectively increased to increase the distance between the side wall of the gate field plate and the source field plate without increasing the thickness of the dielectric layer in the partial area between the source field plate and the heterojunction.

[0013] In some embodiments, the gate field plate includes a bottom surface close to one side of the heterojunction, and the minimum angle between the side wall and the bottom surface of the gate field plate is an acute angle. The first dielectric layer includes a first surface and a second surface in contact with the second dielectric layer, the first surface is perpendicular to the bottom surface of the gate field plate, the second surface is connected to the first surface, and the second surface is a curved surface.

[0014] In some embodiments, the second dielectric layer covers the first dielectric layer and the top surface of the gate field plate away from the heterojunction. The orthographic projection of the second dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction.

[0015] In the above embodiment, since the first dielectric layer does not cover the top surface of the gate field plate, the second dielectric layer is provided to cover the top surface of the gate field plate to avoid contact between the top surfaces of the source field plate and the gate field plate, thereby achieving insulation between the gate field plate and the source field plate.

[0016] Furthermore, by patterning the second dielectric layer so that it does not cover the source and drain, the thickness of the dielectric layer between the portion of the source field plate and the heterojunction can be reduced, and the distance between the portion of the source field plate close to the drain and the heterojunction can be reduced, which is beneficial to weakening the electric field line aggregation effect in the device, making the electric field of the two-dimensional electron gas channel flat and evenly distributed, which is beneficial to reducing the parasitic capacitance between the gate and the drain, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0017] In some embodiments, the semiconductor device further includes a third dielectric layer and a fourth dielectric layer stacked in sequence, the third dielectric layer and the fourth dielectric layer being located between the heterojunction and the first dielectric layer. The orthographic projection of the fourth dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction.

[0018] The source electrode at least penetrates the third dielectric layer and makes ohmic contact with the heterojunction. The drain electrode at least penetrates the third dielectric layer and makes ohmic contact with the heterojunction. The gate electrode penetrates the third dielectric layer and the fourth dielectric layer and makes Schottky contact with the heterojunction. There is at least a third dielectric layer between the source field plate and the heterojunction.

[0019] In the above embodiment, the semiconductor device includes a third dielectric layer and a fourth dielectric layer located between the heterojunction and the first dielectric layer, and the orthographic projection of the fourth dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction, that is, the fourth dielectric layer does not cover the source electrode and the drain electrode, so that the portion of the source field plate close to the drain electrode and the heterojunction are separated by the third dielectric layer, and not by the fourth dielectric layer, thereby reducing the number of dielectric layers between the portion of the source field plate close to the drain electrode and the heterojunction, which is beneficial to reducing the distance between the portion of the source field plate close to the drain electrode and the heterojunction, thereby improving the high-frequency performance and reliability of the device.

[0020] In some embodiments, the source electrode further penetrates the fourth dielectric layer, and the drain electrode further penetrates the fourth dielectric layer.

[0021] In some embodiments, the fourth dielectric layer includes a first portion and a second portion, the outer boundary of the orthographic projection of the first portion on the heterojunction coincides with the outer boundary of the orthographic projection of the first dielectric layer on the heterojunction, the orthographic projection of the second portion on the heterojunction does not overlap with the orthographic projection of the first dielectric layer on the heterojunction, and the thickness of the first portion is greater than the thickness of the second portion.

[0022] Based on this, the second part of the fourth dielectric layer is between the part of the source field plate close to the drain and the heterojunction, but not the first part. This reduces the thickness of the dielectric layer between the part of the source field plate close to the drain and the heterojunction, which is beneficial to reducing the distance between the part of the source field plate close to the drain and the heterojunction, thereby improving the high-frequency performance and reliability of the device.

[0023] In some embodiments, at least a second dielectric layer, a third dielectric layer and a fourth dielectric layer are disposed between the source field plate and the heterojunction, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is greater than the sum of the thicknesses of the second dielectric layer, the third dielectric layer and the fourth dielectric layer.

[0024] It can be understood that the first dielectric layer and the second dielectric layer are between the sidewall of the gate field plate and the source field plate, and the second dielectric layer, the third dielectric layer and the fourth dielectric layer are between the source field plate and the heterojunction.

[0025] By setting the sum of the thicknesses of the first dielectric layer and the second dielectric layer to be greater than the sum of the thicknesses of the second dielectric layer, the third dielectric layer and the fourth dielectric layer, the minimum distance between the side wall of the gate field plate and the source field plate is made greater than the minimum distance between the source field plate and the heterojunction, which can improve the leakage and stress concentration between the side wall of the gate field plate and the source field plate and improve the reliability of the device, and can also weaken the electric field line aggregation effect in the device, so that the electric field of the two-dimensional electron gas channel is flattened and evenly distributed, which is beneficial to reducing the parasitic capacitance between the gate and the drain, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0026] In some embodiments, the distance between the sidewall of the gate field plate and the source field plate ranges from 50 nm to 500 nm; the distance between the source field plate and the heterojunction ranges from 20 nm to 500 nm.

[0027] In some embodiments, the material of the first dielectric layer is the same as the material of the second dielectric layer.

[0028] In a second aspect, a method for preparing a semiconductor device is provided, the method comprising: forming a source, a drain, a gate and a gate field plate on a heterojunction, the gate field plate being located on the gate and electrically connected to the gate, and the gate field plate being located between the source and the drain. Forming a first dielectric layer, the first dielectric layer being located on the sidewall of the gate field plate. Forming a second dielectric layer on the first dielectric layer. Forming a source field plate, the source field plate being located on the second dielectric layer and on a side of the gate field plate close to the drain, the source field plate being electrically connected to the source.

[0029] The preparation method provided by the above-mentioned embodiment of the present application forms a source, a drain, a gate and a gate field plate on a heterojunction, forms a first dielectric layer on the side wall of the gate field plate, forms a second dielectric layer on the first dielectric layer, and forms a source field plate on the second dielectric layer, so that the first dielectric layer and the second dielectric layer are spaced between the side wall of the gate field plate and the source field plate, and the number and thickness of the dielectric layers on the side wall of the gate field plate are selectively increased, thereby increasing the distance between the side wall of the gate field plate and the source field plate, which can improve the leakage and stress concentration between the side wall of the gate field plate and the source field plate, and improve the reliability of the device.

[0030] Furthermore, the number and thickness of the dielectric layer between the source field plate and the heterojunction will not be increased, that is, the distance between the portion of the source field plate close to the drain and the heterojunction will not be increased, which is beneficial to weakening the electric field line aggregation effect in the device, making the electric field of the two-dimensional electron gas channel flat and evenly distributed, which is beneficial to reducing the parasitic capacitance between the gate and the drain, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0031] In some embodiments, forming a first dielectric layer includes: forming a first dielectric film, the first dielectric film covering the source, the drain and the gate field plate. Etching the first dielectric film, wherein the etching rate of the first dielectric film along the first direction is greater than the etching rate along the second direction, so as to retain a portion of the first dielectric film covering the side wall of the gate field plate, thereby obtaining the first dielectric layer. The first direction is perpendicular to the surface of the heterojunction away from the gate field plate, and the second direction is parallel to the surface of the heterojunction away from the gate field plate.

[0032] Since the sidewall of the gate field plate is an inclined surface, the dielectric material is easily accumulated on the inclined surface during the deposition of the dielectric material, so that the thickness of the portion of the first dielectric film covering the sidewall of the gate field plate is greater than that of other portions.

[0033] By adopting the above preparation method, during the process of etching the first dielectric film, since the etching rate of the first dielectric film along the first direction is greater than the etching rate along the second direction, and the first direction is perpendicular to the surface of the heterojunction away from the gate field plate, the etching rate of the portion of the first dielectric film parallel to the heterojunction surface is faster.

[0034] Furthermore, the sidewall of the gate field plate is an inclined surface that is not parallel to the surface, and the portion of the first dielectric film covering the sidewall of the gate field plate is thicker and has a slower etching rate. As the etching time increases, the portion of the first dielectric film covering the sidewall of the gate field plate is retained to obtain the first dielectric layer.

[0035] In some embodiments, a ratio of an etching rate of the first dielectric film along the first direction to an etching rate of the first dielectric film along the second direction is in a range of 2-4.

[0036] In some embodiments, forming a source, a drain, a gate, and a gate field plate on a heterojunction includes: forming a second dielectric film on the heterojunction. Forming a source and a drain, wherein the source and the drain respectively penetrate the second dielectric film and contact the heterojunction. Forming a third dielectric film, wherein the third dielectric film covers the second dielectric film, the source, and the drain. Forming a gate and a gate field plate, wherein the gate penetrates the third dielectric film and the second dielectric film and contact the heterojunction. In the process of etching the first dielectric film, the third dielectric film is also etched to adjust the thickness of the third dielectric film.

[0037] In some embodiments, the first dielectric layer and the second dielectric layer are not formed simultaneously, and therefore, an interface exists between them.

[0038] In some embodiments, the first dielectric layer and the second dielectric layer are formed respectively in two film forming processes.

[0039] In a third aspect, a chip is provided, which includes a substrate, and the semiconductor device described in any one of the above embodiments, wherein the semiconductor device is arranged on the substrate.

[0040] In a fourth aspect, an electronic device is provided, the electronic device comprising a radio frequency device and an antenna, the radio frequency device comprising the chip as described in the above embodiment, the radio frequency device being configured to amplify and output radio frequency signals, and the antenna being coupled to the radio frequency device, and being configured to receive and radiate radio frequency signals.

[0041] In a fifth aspect, an electronic device is provided. The electronic device includes a power device. The power device includes the chip as described in the above embodiment.

[0042] It can be understood that the beneficial effects that can be achieved by the chips and electronic devices provided in the above embodiments of the present application can refer to the beneficial effects of the semiconductor devices mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0044] Figure 1 A schematic diagram of the structure of a base station provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of an active antenna unit provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of the structure of a charger provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of the structure of a HEMT device provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application;

[0050] Figure 7 for Figure 6 A local enlarged view of the device at position P;

[0051] Figure 8 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application;

[0052] Figures 9 to 11 Schematic diagram of the structures of various HEMT devices provided in the embodiments of the present application;

[0053] Fig.12 A flow chart of preparing a HEMT device provided in an embodiment of the present application;

[0054] FIG. 13A to FIG. 13I A diagram of each step of preparing a HEMT device provided in an embodiment of the present application;

[0055] Figure 14 to Figure 16 A diagram showing the steps for preparing various HEMT devices provided in the embodiments of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0057] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to has a specific orientation, is constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0058] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0059] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0060] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0061] “At least one of A, B or C” includes the following combinations of A, B and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

[0062] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0063] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0064] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0065] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0066] The technical terms involved in some embodiments of the present application are as follows:

[0067] Current collapse effect: When the drain voltage of a GaN HEMT device exceeds a certain value, the current begins to decrease as the drain voltage increases and cannot reach the ideal current value.

[0068] Some embodiments of the present application provide an electronic device, which may be, for example, a charger, a charging small household appliance (such as a soymilk machine, a sweeping robot), an on-board charger (OBC), a drone, an aerospace equipment, a laser radar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network, the fifth generation mobile communication technology) communication device, and other different types of user equipment or terminal equipment, and the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0069] Take the electronic device as a base station as an example. Figure 1 A schematic diagram of the structure of a base station provided in an embodiment of the present application.

[0070] See also Figure 1 The base station 1 includes a baseband processing unit (BBU) 101 and an active antenna unit (AAU) 102. The baseband processing unit 101 is mainly responsible for baseband digital signal processing, for example, it can realize fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT), modulation / demodulation, channel coding / decoding and other processing functions.

[0071] Figure 2 A schematic diagram of the structure of an active antenna unit provided in an embodiment of the present application.

[0072] See also Figure 2, the active antenna unit 102 includes a computing unit 121, a first transmission unit 122 and an antenna unit 123. The computing unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212 and a power supply unit 1213, and the control unit 1210, the second transmission unit 1211, the baseband unit 1212 and the power supply unit 1213 are electrically connected to each other, the control unit 1210 is responsible for the control of the radio frequency signal; the second transmission unit 1211 is responsible for the transmission of the radio frequency signal; the baseband unit 1212 is responsible for the conversion of digital signals and analog signals, and the baseband unit 1212 can be a digital to analog converter (DAC), for example, and the baseband unit 1212 can convert the digital signal output by the baseband processing unit 101 into an analog signal; the power supply unit 1213 is electrically connected to the power supply 124, and is used to supply power to the control unit 1210, the second transmission unit 1211 and the baseband unit 1212 in the computing unit 121.

[0073] The first transmission unit 122 is used for transmitting and amplifying radio frequency signals. The first transmission unit 122 includes a radio frequency unit (RF) 1221 and a power amplifier (PA) 1222. The radio frequency unit 1221 is used to receive an analog signal from the baseband unit 1212 and convert the analog signal into a low-power radio frequency signal. The power amplifier 1222 is used to amplify the low-power radio frequency signal and output it to the antenna unit 123. The power amplifier 1222 is a radio frequency device, which can be a radio frequency chip.

[0074] The antenna unit 123 is coupled to the power amplifier 1222 to receive the power-amplified RF signal from the power amplifier 1222 and radiate the RF signal outward. Exemplarily, the active antenna unit 102 may include multiple RF units 1221 , multiple power amplifiers 1222 , and multiple antenna units 123 .

[0075] Take the charger of electronic equipment as an example. Figure 3 A schematic diagram of the structure of a charger provided in an embodiment of the present application.

[0076] See also Figure 3 The charger 2 may include a transformer 21, a resistor 22, an inductor 23, a capacitor 24 and a circuit board 25. The transformer 21, the resistor 22, the inductor 23 and the capacitor 24 are respectively coupled to the circuit board 25 to achieve interconnection of the devices. The transformer 21 is a power device, which may be a power chip.

[0077] A high electron mobility transistor (HEMT) device is a semiconductor device that can be widely used in radio frequency devices or power devices due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability. That is, HEMT devices can be used in both the power amplifier 1222 and the transformer 21.

[0078] Figure 4 A schematic diagram of the structure of a HEMT device provided in an embodiment of the present application.

[0079] See also Figure 4 The HEMT device 3 includes a substrate 31, an AlN nucleation layer 32, a GaN buffer layer 33, a GaN channel layer 34, an AlGaN barrier layer 35 and a GaN cap layer 36 stacked on the substrate 31 in sequence, and a gate G, a source S and a drain D. The material of the substrate 31 includes a semiconductor material. The GaN channel layer 34 and the AlGaN barrier layer 35 form a heterojunction, the gate G is arranged between the source S and the drain D, the source S and the drain D respectively form a conductive ohmic contact with the heterojunction, and the gate G forms a Schottky contact with the GaN cap layer 36.

[0080] Exemplarily, the material of the substrate 31 includes at least one of silicon carbide (chemical formula: SiC), silicon (chemical formula: Si), sapphire or diamond.

[0081] Exemplarily, the materials of the gate G, the source S, and the drain D may each include at least one of titanium (chemical formula: Ti), aluminum (chemical formula: Al), nickel (chemical formula: Ni), or gold (chemical formula: Au).

[0082] The working principle of the HEMT device 3 is as follows: a two-dimensional electron gas channel is generated at the interface of the GaN channel layer 34 and the AlGaN barrier layer 35 in the heterojunction due to the polarization effect, and the two-dimensional electron gas can be used to efficiently conduct electrons. When the gate G does not receive a voltage signal, that is, when there is no bias voltage, the two-dimensional electron gas is allowed to pass through to achieve conduction between the source S and the drain D, and the HEMT device 3 is in an on state. When the gate G receives a voltage signal, that is, when a bias voltage is applied, the two-dimensional electron gas is in a pinch-off state to achieve cutoff between the source S and the drain D, and the HEMT device 3 is in a closed state. Therefore, in the absence of a bias voltage, the HEMT device 3 is a normally-on device.

[0083] Furthermore, electrons are trapped in a small area at the interface between the GaN channel layer 34 and the AlGaN barrier layer 35 , so that the device has a higher electron mobility, thereby making the two-dimensional electron gas have a higher conductivity.

[0084] The HEMT device 3 is a depletion-mode HEMT device, which can be applied to radio frequency devices.

[0085] Figure 5 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application.

[0086] See also Figure 5 The HEMT device 4 includes a substrate 41, an AlN nucleation layer 42, an AlGaN buffer layer 43, a GaN channel layer 44, an AlGaN barrier layer 45, a GaN cap layer 46, and an AlGaN layer 47 doped with a P-type element, which are sequentially stacked on the substrate 41, and a gate G, a source S, and a drain D. The material of the substrate 41 includes a conductive material. The GaN channel layer 44 and the AlGaN barrier layer 45 form a heterojunction, the gate G is arranged between the source S and the drain D, the source S and the drain D respectively form a conductive ohmic contact with the heterojunction, and the gate G forms a Schottky contact with the gate insulating layer 47.

[0087] The working principle of the HEMT device 4 is as follows: a two-dimensional electron gas channel is generated at the interface of the GaN channel layer 34 and the AlGaN barrier layer 35 in the heterojunction due to the polarization effect, and the two-dimensional electron gas can be used to efficiently conduct electrons. When the gate G does not receive a voltage signal, that is, when there is no bias voltage, the two-dimensional electron gas is in a pinch-off state to achieve cutoff between the source S and the drain D, and the HEMT device 4 is in a closed state. When the gate G receives a voltage signal, that is, when a bias voltage is applied, the two-dimensional electron gas is allowed to pass to achieve conduction between the source S and the drain D, and the HEMT device 4 is in an open state. Therefore, in the absence of a bias voltage, the HEMT device is a normally-off device.

[0088] The HEMT device 4 is an enhancement-mode HEMT device and can be applied to power devices.

[0089] HEMT devices are widely used in the fields of high frequency, high temperature and high power density. In order to improve the performance and reliability of the devices, the embodiment of the present application further provides a HEMT device. Figure 6 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application.

[0090] See also Figure 6 , the HEMT device 5 includes a heterojunction 50 .

[0091] Exemplarily, the HEMT device 5 includes a substrate 51, an AlN nucleation layer 52, an AlGaN buffer layer 53, a GaN channel layer 54 and an AlGaN barrier layer 55 stacked in sequence on the substrate 51, and the GaN channel layer 54 and the AlGaN barrier layer 55 form a heterojunction 50, but the embodiments of the present application are not limited thereto.

[0092] Continue to see Figure 6 The HEMT device 5 further includes a source S, a drain D and a gate G. The source S, the drain D and the gate G are all disposed on the heterojunction 50 and are in contact with the heterojunction 50 respectively.

[0093] Exemplarily, the gate G is disposed between the source S and the drain D. The source S and the drain D respectively form a conductive ohmic contact with the heterojunction 50 , and the gate G forms a Schottky contact with the AlGaN barrier layer 55 .

[0094] Continue to see Figure 6 The HEMT device 5 further includes a gate field plate (Gate Field Plate, GFP) 56 , a first dielectric layer 57 , a second dielectric layer 58 and a source field plate (Source Field Plate, SFP) 59 .

[0095] The gate field plate 56 is disposed on the gate G and electrically connected to the gate G. The gate field plate 56 is located between the source S and the drain D.

[0096] Exemplarily, the gate field plate 56 is located above the gate G and forms an integral structure with the gate G. The cross-section of the integral structure is "hat-shaped", that is, the left and right boundaries of the gate field plate 56 exceed the left and right boundaries of the gate G.

[0097] The gate G has an inverted trapezoidal cross section, the gate field plate 56 has a regular trapezoidal cross section, and the gate field plate 56 has an inclined side wall C.

[0098] Typically, the source field plate 59 is disposed on a side of the gate field plate 56 close to the drain D, and the source field plate 59 is electrically connected to the source S. The source field plate 59 is Z-shaped, and includes a portion close to the source S and a portion close to the drain D. The portion of the source field plate 59 close to the source S is located above the gate field plate 56, and the portion of the source field plate 59 close to the drain D is not located above the gate field plate 56.

[0099] By way of example, the materials of the gate field plate 56 and the source field plate 59 may each include at least one of titanium, aluminum, nickel, or gold.

[0100] The first dielectric layer 57 and the second dielectric layer 58 are both disposed between the side wall C of the gate field plate 56 and the source field plate 59. The first dielectric layer 57 is located on the side wall C of the gate field plate 56, and the second dielectric layer 58 is located between the first dielectric layer 57 and the source field plate 59. That is, the first dielectric layer 57 and the second dielectric layer 58 are spaced between the side wall C of the gate field plate 56 and the source field plate 59, and the first dielectric layer 57 and the second dielectric layer 58 are used for insulation between the gate field plate 56 and the source field plate 59.

[0101] Exemplarily, the first dielectric layer 57 may be located only on the side wall C of the gate field plate 56, and the second dielectric layer 58 may be located not only between the first dielectric layer 57 and the source field plate 59, but also above the source S and the drain D. In this case, the source field plate 59 may pass through the second dielectric layer 58 and be electrically connected to the source S, but the embodiments of the present application are not limited to this.

[0102] Exemplarily, the material of the first dielectric layer 57 is the same as the material of the second dielectric layer 58. For example, both materials include silicon nitride. The material of the first dielectric layer 57 and the material of the second dielectric layer 58 may also be different, which is not limited in the embodiments of the present application.

[0103] It can be understood that by adding field plates (FP), for example, a gate field plate 56 connected to the gate G and a source field plate 59 connected to the source S, and adjusting parameters such as the structure and position relationship of the field plates, the parasitic capacitance and electric field distribution morphology of the device can be adjusted to adjust and slow down the electric field peaks of the gate G and the drain D, thereby suppressing the current collapse effect and reducing the leakage current of the gate G.

[0104] When the HEMT device 5 is applied to a radio frequency device, the performance parameters of the device such as breakdown voltage, on-resistance, output power and operating frequency are optimized by adjusting the structure and position relationship of the gate field plate 56 and the source field plate 59, and balancing the numerical relationship between the various performance parameters so that the device can achieve better performance.

[0105] However, existing HEMT devices have a contradiction between performance and reliability. For example, the vertical distance between the source field plate and the heterojunction in the device is large. When the device is in the on state, the distance between the source field plate and the two-dimensional electron gas channel in the heterojunction is large, resulting in a large parasitic capacitance CGD between the gate and the drain, which in turn leads to a decrease in the high-frequency performance of the device. When the device is in the off state, the electric field line concentration effect occurs near the gate and drain in the two-dimensional electron gas channel, resulting in a decrease in the breakdown voltage of the device, affecting the reliability of the device.

[0106] In addition, the distance between the side wall of the gate field plate and the source field plate in the device is small. When the gate receives a high voltage, a leakage channel is easily generated between the side wall of the gate field plate and the source field plate, resulting in a short circuit between the gate and the source. When the device is in a high-frequency working state, thermal stress is generated between the side wall of the gate field plate and the source field plate. The stress concentration can easily cause the source field plate to break, resulting in failure of the source field plate.

[0107] In the HEMT device 5 in the above embodiment of the present application, the source S, the drain D and the gate G are arranged on the heterojunction 50 and are respectively in contact with the heterojunction 50. The gate field plate 56 is arranged on the gate G and is electrically connected to the gate G. The gate field plate 56 is located between the source S and the drain D. The source field plate 59 is arranged on the side of the gate field plate 56 close to the drain D, and the source field plate 59 is electrically connected to the source S.

[0108] By adding a first dielectric layer 57 and a second dielectric layer 58 between the side wall C of the gate field plate 56 and the source field plate 59, the first dielectric layer 57 is located on the side wall C of the gate field plate 56, and the second dielectric layer 58 is located between the first dielectric layer 57 and the source field plate 59, so that the first dielectric layer 57 and the second dielectric layer 58 are spaced between the side wall C of the gate field plate 56 and the source field plate 59, and the number and thickness of the dielectric layers (the first dielectric layer 57 and the second dielectric layer 58) on the side wall C of the gate field plate 56 are selectively increased, thereby increasing the distance between the side wall C of the gate field plate 56 and the source field plate 59, which can improve the leakage and stress concentration between the side wall C of the gate field plate 56 and the source field plate 59, thereby improving the reliability of the device.

[0109] Furthermore, since the first dielectric layer 57 is located on the side wall C of the gate field plate 56, the thickness of the dielectric layer on the side wall C of the gate field plate 56 is selectively increased, and the number and thickness of the dielectric layers between the portion of the source field plate 59 (the portion close to the drain D) and the heterojunction 50 will not be increased, that is, the distance between the portion of the source field plate 59 close to the drain D and the heterojunction 50 will not be increased, which is beneficial to weakening the electric field line aggregation effect in the device, making the electric field of the two-dimensional electron gas channel flat and evenly distributed, which is beneficial to reducing the parasitic capacitance CGD between the gate G and the drain D, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0110] In some embodiments, see Figure 6 The first dielectric layer 57 covers the sidewall C of the gate field plate 56 , but does not cover the top surface of the gate field plate 56 away from the heterojunction 50 .

[0111] Furthermore, the orthographic projection of the first dielectric layer 57 on the heterojunction 50 does not overlap with the orthographic projection of the source electrode S on the heterojunction 50 and the orthographic projection of the drain electrode D on the heterojunction 50 .

[0112] It can be understood that the first dielectric layer 57 is a patterned film layer, not a film layer that covers the entire surface. The first dielectric layer 57 only selectively covers the side wall C of the gate field plate 56, and does not cover the top surface, source S and drain D of the gate field plate 56, thereby selectively increasing the thickness of the dielectric layer covering the side wall C of the gate field plate 56 to increase the distance between the side wall C of the gate field plate 56 and the source field plate 59.

[0113] Furthermore, since the first dielectric layer 57 only selectively covers the sidewall C of the gate field plate 56 , the thickness of the dielectric layer in the partial region between the source field plate 59 and the heterojunction 50 will not be increased.

[0114] In other embodiments, the first dielectric layer 57 may also be a film layer covering the entire surface. The first dielectric layer 57 may cover the top surface of the gate field plate 56. The orthographic projection of the first dielectric layer 57 on the heterojunction 50 may overlap with the orthographic projection of the source S on the heterojunction 50, and may overlap with the orthographic projection of the drain D on the heterojunction 50.

[0115] However, it should be ensured that the portion of the first dielectric layer 57 covering the side wall C of the gate field plate 56 is thicker than the portion of the side wall C not covering the gate field plate 56, so as to ensure that the setting of the first dielectric layer 57 can selectively increase the distance between the side wall C of the gate field plate 56 and the source field plate 59.

[0116] Figure 7 for Figure 6 A local enlarged view of the device at P.

[0117] See also Figure 6 and Figure 7 The gate field plate 56 includes a bottom surface 561 close to the heterojunction 50 and a top surface 562 away from the heterojunction 50 . The minimum angle α between the side wall C of the gate field plate and the bottom surface 561 is an acute angle.

[0118] The first dielectric layer 57 includes a first surface M1 and a second surface M2 in contact with the second dielectric layer 58, the first surface M1 is perpendicular to the bottom surface 561 of the gate field plate 56, the second surface M2 is connected to the first surface M1, and the second surface M2 is a curved surface, so that the average thickness of the first dielectric layer 57 away from the heterojunction 50 (top) is greater than the average thickness of the first dielectric layer 57 close to the heterojunction 50 (bottom).

[0119] Exemplarily, the difference between the average thickness of the top of the first dielectric layer 57 and the average thickness of the bottom is greater than or equal to 10 nm, for example, the difference is 10 nm, 13 nm, 15 nm, 18 nm or 20 nm.

[0120] In some embodiments, see Figure 7The minimum distance H1 between the portion of the side wall C of the gate field plate 56 close to the top surface 562 and the source field plate 59 is greater than the minimum distance H2 between the portion of the side wall C of the gate field plate 56 close to the bottom surface 561 and the source field plate 59 .

[0121] It can be understood that the first dielectric layer 57 and the second dielectric layer 58 are interposed between the side wall of the gate field plate 56 and the source field plate 59. Since the average thickness of the top of the first dielectric layer 57 is greater than the average thickness of the bottom, the second dielectric layer 58 covers the first dielectric layer 57. Therefore, when the thickness of the second dielectric layer 58 is uniform, the thickness of the dielectric layer between the portion of the side wall C of the gate field plate 56 close to the top surface 562 and the source field plate 59 is greater than the thickness of the dielectric layer between the portion of the side wall C of the gate field plate 56 close to the bottom surface 561 and the source field plate 59, so that the above-mentioned minimum distance H1 is greater than the minimum distance H2.

[0122] Figure 8 A schematic diagram of the structure of another HEMT device provided in an embodiment of the present application.

[0123] See also Figure 8 The second dielectric layer 58 covers the first dielectric layer 57 and the top surface of the gate field plate 56 away from the heterojunction 50. In addition, the orthographic projection of the second dielectric layer 58 on the heterojunction 50 does not overlap with the orthographic projection of the source S on the heterojunction 50, and does not overlap with the orthographic projection of the drain D on the heterojunction 50.

[0124] It is understandable that the second dielectric layer 58 is a patterned film layer, not a film layer that covers the entire surface. The second dielectric layer 58 only selectively covers the first dielectric layer 57 and the top surface of the gate field plate 56 , and does not cover the source S and the drain D.

[0125] Since the first dielectric layer 57 does not cover the top surface of the gate field plate 56 , the second dielectric layer 58 is provided to cover the top surface of the gate field plate 56 to avoid contact between the source field plate 59 and the top surface of the gate field plate 56 , thereby achieving insulation between the gate field plate 56 and the source field plate 59 .

[0126] Furthermore, by patterning the second dielectric layer 58 so that it does not cover the source S and the drain D, the thickness of the dielectric layer between the portion of the source field plate 59 (the portion close to the drain D) and the heterojunction 50 can be reduced, and the distance between the portion of the source field plate 59 close to the drain D and the heterojunction 50 can be reduced, which is beneficial to weakening the electric field line aggregation effect in the device, making the electric field of the two-dimensional electron gas channel flat and evenly distributed, which is beneficial to reducing the parasitic capacitance CGD between the gate G and the drain D, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0127] Figures 9 to 11 Schematic diagram of the structures of various HEMT devices provided in the embodiments of the present application.

[0128] See also Fig. 9 The HEMT device 5 further includes a third dielectric layer 60 and a fourth dielectric layer 61 which are stacked in sequence. The third dielectric layer 60 and the fourth dielectric layer 61 are located between the heterojunction 50 and the first dielectric layer 57 .

[0129] The orthographic projection of the fourth dielectric layer 61 on the heterojunction 50 does not overlap with the orthographic projection of the source electrode S on the heterojunction 50, and does not overlap with the orthographic projection of the drain electrode D on the heterojunction 50. That is, the fourth dielectric layer 61 is a patterned film layer, not a film layer covering the entire surface, and the fourth dielectric layer 61 does not cover the source electrode S and the drain electrode D.

[0130] The source electrode S at least penetrates the third dielectric layer 60 and contacts the heterojunction 50, the drain electrode D at least penetrates the third dielectric layer 60 and contacts the heterojunction 50, and the gate electrode G penetrates the third dielectric layer 60 and the fourth dielectric layer 61 and contacts the heterojunction 50. The source field plate 59 and the heterojunction 50 are at least separated by the third dielectric layer 60.

[0131] Exemplarily, the source electrode S penetrates the third dielectric layer 60 and contacts the heterojunction 50, and the drain electrode D penetrates the third dielectric layer 60 and contacts the heterojunction 50. The second dielectric layer 58 selectively covers only the first dielectric layer 57 and the top surface of the gate field plate 56. In this case, the source field plate 59 and the heterojunction 50 are separated by the third dielectric layer 60.

[0132] Generally, in an existing HEMT device, a plurality of dielectric layers are provided between the source field plate and the heterojunction, resulting in a large distance between the source field plate and the heterojunction.

[0133] In the above-mentioned embodiment of the present application, the HEMT device 5 includes a third dielectric layer 60 and a fourth dielectric layer 61 located between the heterojunction 50 and the first dielectric layer 57. The orthographic projection of the fourth dielectric layer 61 on the heterojunction 50 does not overlap with the orthographic projection of the source S on the heterojunction 50, and does not overlap with the orthographic projection of the drain D on the heterojunction 50, that is, the fourth dielectric layer 61 does not cover the source S and the drain D, so that the portion of the source field plate 59 close to the drain D is separated from the heterojunction 50 by the third dielectric layer 60, and is not separated by the fourth dielectric layer 61, thereby reducing the number of dielectric layers between the portion of the source field plate 59 close to the drain D and the heterojunction 50, which is beneficial to reducing the distance between the portion of the source field plate 59 close to the drain D and the heterojunction 50, thereby improving the high-frequency performance and reliability of the device.

[0134] In some embodiments, see Fig.10 The source S penetrates the third dielectric layer 60 and the fourth dielectric layer 61 and contacts the heterojunction 50 , the drain D penetrates the third dielectric layer 60 and the fourth dielectric layer 61 and contacts the heterojunction 50 , and the gate G penetrates the third dielectric layer 60 and the fourth dielectric layer 61 and contacts the heterojunction 50 .

[0135] Exemplarily, the fourth dielectric layer 61 is a film layer covering the entire surface, and the thickness of the fourth dielectric layer 61 is uneven.

[0136] For example, the fourth dielectric layer 61 includes a first portion 611 and a second portion 612, and the outer boundary of the orthographic projection of the first portion 611 on the heterojunction 50 coincides with the outer boundary of the orthographic projection of the first dielectric layer 57 on the heterojunction 50. The orthographic projection of the second portion 612 on the heterojunction 50 does not overlap with the orthographic projection of the first dielectric layer 57 on the heterojunction 50, and the thickness of the first portion 611 is greater than the thickness of the second portion 612. The portion of the source field plate 59 close to the drain D and the heterojunction 50 are separated by the second portion 612 of the fourth dielectric layer 61, and the first portion 611 is not separated, which reduces the thickness of the dielectric layer between the portion of the source field plate 59 close to the drain D and the heterojunction 50, which is beneficial to reducing the distance between the portion of the source field plate 59 close to the drain D and the heterojunction 50, thereby improving the high-frequency performance and reliability of the device.

[0137] In some embodiments, see Fig.11 At least a second dielectric layer 58 , a third dielectric layer 60 , and a fourth dielectric layer 61 are disposed between the source field plate 59 and the heterojunction 50 , wherein the sum of the thicknesses of the first dielectric layer 57 and the second dielectric layer 58 is greater than the sum of the thicknesses of the second dielectric layer 58 , the third dielectric layer 60 , and the fourth dielectric layer 61 .

[0138] Exemplarily, the source field plate 59 and the heterojunction 50 are separated by a second dielectric layer 58, a third dielectric layer 60, and a fourth dielectric layer 61. The sum of the thicknesses of the first dielectric layer 57 and the second dielectric layer 58 is greater than the sum of the thicknesses of the second dielectric layer 58, the third dielectric layer 60, and the fourth dielectric layer 61. When the thickness of the second dielectric layer 58 is uniform, the thickness of the first dielectric layer 57 is greater than the sum of the thicknesses of the third dielectric layer 60 and the fourth dielectric layer 61.

[0139] Exemplarily, the sum of the thicknesses of the first dielectric layer 57 and the second dielectric layer 58 ranges from 50 nm to 500 nm. For example, the sum of the thicknesses is 50 nm, 100 nm, 200 nm, 240 nm, 250 nm, 275 nm or 500 nm.

[0140] Exemplarily, the sum of the thicknesses of the second dielectric layer 58, the third dielectric layer 60 and the fourth dielectric layer 61 is in the range of 20 nm to 500 nm, for example, the sum of the thicknesses is 20 nm, 120 nm, 160 nm, 260 nm, 300 nm, 400 nm or 500 nm. Furthermore, when the sum of the thicknesses of the first dielectric layer 57 and the second dielectric layer 58 is 500 nm, the sum of the thicknesses of the second dielectric layer 58, the third dielectric layer 60 and the fourth dielectric layer 61 is less than 500 nm.

[0141] It is understandable that the first dielectric layer 57 and the second dielectric layer 58 are between the side wall C of the gate field plate 56 and the source field plate 59 , and the second dielectric layer 58 , the third dielectric layer 60 and the fourth dielectric layer 61 are between the source field plate 59 and the heterojunction 50 .

[0142] By setting the sum of the thicknesses of the first dielectric layer 57 and the second dielectric layer 58 to be greater than the sum of the thicknesses of the second dielectric layer 58, the third dielectric layer 60 and the fourth dielectric layer 61, the minimum distance between the side wall C of the gate field plate 56 and the source field plate 59 is made greater than the minimum distance between the source field plate 59 and the heterojunction 50. This can improve the leakage and stress concentration between the side wall C of the gate field plate 56 and the source field plate 59, thereby improving the reliability of the device, and can also weaken the electric field line aggregation effect in the device, so that the electric field of the two-dimensional electron gas channel is flattened and evenly distributed, which is beneficial to reducing the parasitic capacitance CGD between the gate G and the drain D, and is beneficial to improving the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0143] Exemplarily, the distance between the sidewall C of the gate field plate 56 and the source field plate 59 ranges from 50 nm to 500 nm. For example, the distance may be 50 nm, 100 nm, 200 nm, 240 nm, 250 nm, 275 nm or 500 nm.

[0144] Exemplarily, the distance between the source field plate 59 and the heterojunction 50 ranges from 20 nm to 500 nm, for example, the distance may be 20 nm, 120 nm, 160 nm, 260 nm, 300 nm, 400 nm or 500 nm. Furthermore, when the distance between the side wall C of the gate field plate 56 and the source field plate 59 is 500 nm, the distance between the source field plate 59 and the heterojunction 50 is less than 500 nm.

[0145] The embodiment of the present application also provides a method for preparing a HEMT device. Fig.12 A flow chart of preparing a HEMT device provided in an embodiment of the present application; FIG. 13A to FIG. 13I A diagram of the steps for preparing a HEMT device provided in an embodiment of the present application.

[0146] See also Fig.12 The preparation method of the HEMT device includes the following S10 to S40:

[0147] S10: See FIG. 13A to FIG. 13D A source S, a drain D, a gate G and a gate field plate 56 are formed on the heterojunction 50 . The gate field plate 56 is located on the gate G and is electrically connected to the gate G. The gate field plate 56 is located between the source S and the drain D.

[0148] In some examples, the above S10 includes the following S11 to S14:

[0149] S11: See Fig.13A , a dielectric film K1 is formed on the heterojunction 50 .

[0150] Exemplarily, a metal organic chemical vapor deposition (MOCVD) process is used to sequentially grow an AlN nucleation layer 52, an AlGaN buffer layer 53, a GaN channel layer 54, and an AlGaN barrier layer 55 on a substrate 51 to form a plurality of epitaxial layers on the substrate 51. The GaN channel layer 54 and the AlGaN barrier layer 55 form a heterojunction 50.

[0151] Then, a dielectric film K1 may be formed on the heterojunction 50 by using a film forming process called plasma enhanced chemical vapor deposition (PECVD).

[0152] S12: See Fig. 13B , forming a source S and a drain D, the source S and the drain D respectively penetrate the dielectric film K1 and contact the heterojunction 50.

[0153] For example, a photolithography process may be used to form a via hole on the dielectric film K1 to expose the heterojunction 50. Then, a metal material is deposited to fill the via hole and cover the surface of the dielectric film K1 to form a conductive film layer. Finally, a lift-off process is used to pattern the conductive film layer to form a source electrode S and a drain electrode D.

[0154] The source electrode S and the drain electrode D are annealed by alloy annealing so that they form conductive ohmic contacts with the heterojunction 50 respectively.

[0155] S13: See Fig. 13C , a dielectric film K2 is formed, and the dielectric film K2 covers the dielectric film K1, the source S and the drain D.

[0156] For example, a plasma enhanced chemical vapor deposition film forming process may be used to form the dielectric film K2 . The dielectric film K2 is a film layer covering the entire surface, which covers the dielectric film K1 , the source electrode S and the drain electrode D.

[0157] S14: See Fig.13D , forming a gate G and a gate field plate 56 , wherein the gate G penetrates the dielectric film K2 and the dielectric film K1 and contacts the heterojunction 50 .

[0158] For example, a photolithography process may be used to form a via hole penetrating the dielectric film K2 and the dielectric film K1 to expose the heterojunction 50. Then, a metal material is deposited, the metal material is filled in the via hole, and covers the surface of the dielectric film K2 to form a conductive film layer. Finally, a lift-off process is used to pattern the conductive film layer, retaining the metal material filled in the via hole and located above the via hole, the metal material filled in the via hole forms the gate G, and the metal material located above the via hole forms the gate field plate 56.

[0159] It can be understood that, by adopting the above-mentioned preparation method, the gate G and the gate field plate 56 are integrally arranged.

[0160] S20: See Figure 13E to Figure 13G , forming a first dielectric layer 57 , wherein the first dielectric layer 57 is located on the side wall C of the gate field plate 56 .

[0161] In some examples, the above S20 includes the following S21-S22:

[0162] S21: See Fig.13E , a dielectric film K3 is formed, and the dielectric film K3 covers the source S, the drain D and the gate field plate 56.

[0163] Exemplarily, a plasma enhanced chemical vapor deposition film forming process can be used to form a dielectric film K3. The dielectric film K3 is a film layer covering the entire surface, which covers the dielectric film K2 and the gate field plate 56. Since the dielectric film K2 covers the source S and the drain D, the dielectric film K3 also covers the source S and the drain D.

[0164] Since the side wall C of the gate field plate 56 is an inclined surface, the dielectric material is easily accumulated on the inclined surface during the deposition of the dielectric material, so that the thickness of the portion of the dielectric film K3 covering the side wall C of the gate field plate 56 is greater than that of other portions.

[0165] S22: See Fig.13F and Figure 13G , etching the dielectric film K3, the etching rate of the dielectric film K3 along the first direction Y is greater than the etching rate along the second direction X, wherein the first direction Y is perpendicular to the surface P of the heterojunction 50 away from the gate field plate 56, and the second direction X is parallel to the surface P.

[0166] Exemplarily, a dry etching process is adopted to etch the dielectric film K3 , and the anisotropy of the dry etching process is utilized to achieve different etching rates of the dielectric film K3 along different directions.

[0167] The ratio of the etching rate of the dielectric film K3 along the first direction Y to the etching rate along the second direction X is in the range of 2-4. For example, the etching rate ratio is 2, 2.5, 3, 3.5 or 4.

[0168] Using the above preparation method, during the process of etching the dielectric film K3, since the etching rate of the dielectric film K3 along the first direction Y is greater than the etching rate along the second direction X, and the first direction Y is perpendicular to the surface P, the etching rate of the portion of the dielectric film K3 parallel to the surface P is faster.

[0169] Furthermore, the side wall C of the gate field plate 56 is an inclined surface, which is not parallel to the surface P. The portion of the dielectric film K3 covering the side wall C of the gate field plate 56 is thicker and has a slower etching rate.

[0170] As the etching time increases, until the portion of the dielectric film K3 parallel to the surface P is completely etched, the portion of the dielectric film K3 covering the side wall C of the gate field plate 56 is retained to obtain the first dielectric layer 57 .

[0171] For some examples, see Fig.13F and Figure 13G In the process of etching the dielectric film K3, the dielectric film K2 is also etched.

[0172] It can be understood that the dielectric film K3 is etched until the source S, the drain D and the gate field plate 56 are exposed. Since the etching rate of the metal material is lower than that of the dielectric material, when the source S, the drain D and the gate field plate 56 are over-etched, the dielectric film K2 can be etched to adjust the thickness of the dielectric film K2.

[0173] Exemplarily, the thickness of the dielectric film K1 is 20 nm, the thickness of the dielectric film K2 is 40 nm, and the thickness of the dielectric film K3 is 200 nm.

[0174] Based on this, the ratio of the etching rate of the dielectric film K3 along the first direction Y to the etching rate along the second direction X is 4:1. When the gate field plate 56 is over-etched, the dielectric film K2 is etched until the dielectric film K1 underneath is exposed. At this time, the thickness of the first dielectric layer 57 is 140 nm.

[0175] S30: See Fig.13H , a second dielectric layer 58 is formed on the first dielectric layer 57. The second dielectric layer 58 and the first dielectric layer 57 are formed in different process steps, for example, the second dielectric layer 58 and the first dielectric layer 57 are formed in two different film forming processes, and therefore, an interface exists between the second dielectric layer 58 and the first dielectric layer 57.

[0176] For example, the second dielectric layer 58 may be formed by using a plasma enhanced chemical vapor deposition film forming process.

[0177] S40: See Fig.13I , forming a source field plate 59 , the source field plate 59 is located on the second dielectric layer 58 and on the side of the gate field plate 56 close to the drain D, and the source field plate 59 is electrically connected to the source S.

[0178] For example, when the second dielectric layer 58 covers the source S and the drain D, a photolithography process may be used to form a via hole penetrating the second dielectric layer 58 to expose the source S. Then, a metal material is deposited, filled in the via hole, and covers the surface of the second dielectric layer 58 to form a conductive film layer. Finally, a lift-off process is used to pattern the conductive film layer to form a source field plate 59.

[0179] The preparation method provided by the above-mentioned embodiment of the present application forms a source S, a drain D, a gate G and a gate field plate 56 on the heterojunction 50, forms a first dielectric layer 57 and a second dielectric layer 58 on the side wall C of the gate field plate 56, and forms a source field plate 59 on the second dielectric layer 58, so that the first dielectric layer 57 and the second dielectric layer 58 are spaced between the side wall C of the gate field plate 56 and the source field plate 59, and the number and thickness of the dielectric layers on the side wall C of the gate field plate 56 are selectively increased, thereby increasing the distance between the side wall C of the gate field plate 56 and the source field plate 59, which can improve the leakage and stress concentration between the side wall C of the gate field plate 56 and the source field plate 59, thereby improving the reliability of the device.

[0180] Furthermore, the number and thickness of the dielectric layer between the source field plate 59 (the portion close to the drain D) and the heterojunction 50 will not be increased, that is, the distance between the portion of the source field plate 59 close to the drain D and the heterojunction 50 will not be increased, which is beneficial to weakening the electric field line aggregation effect in the device, making the electric field of the two-dimensional electron gas channel flat and evenly distributed, which is beneficial to reducing the parasitic capacitance CGD between the gate G and the drain D, and is beneficial to increasing the breakdown voltage of the device, thereby improving the high-frequency performance and reliability of the device.

[0181] Figure 14 to Figure 16 A diagram showing the steps for preparing various HEMT devices provided in the embodiments of the present application.

[0182] See also Fig.14 The thickness of the dielectric film K1 is 20 nm, the thickness of the dielectric film K2 is 40 nm, and the thickness of the dielectric film K3 is 200 nm.

[0183] Based on this, the ratio of the etching rate of the dielectric film K3 along the first direction Y to the etching rate along the second direction X is 4:1. The dielectric film K3 is etched until the dielectric film K2 underneath is exposed, the top surface of the gate field plate 56 is just exposed, and the gate field plate 56 is not over-etched. At this time, the thickness of the first dielectric layer 57 is 150nm.

[0184] See also Fig.15 After etching the dielectric film K3 until the dielectric film K2 thereunder is exposed, the dielectric film K2 is further etched until the source electrode S and the drain electrode D are exposed.

[0185] See also Fig.16 The thickness of the dielectric film K1 is 20 nm, the thickness of the dielectric film K2 is 40 nm, and the thickness of the dielectric film K3 is 200 nm.

[0186] Based on this, the ratio of the etching rate of the dielectric film K3 along the first direction Y to the etching rate along the second direction X is 2:1. The dielectric film K3 is etched until the dielectric film K2 underneath is exposed, the top surface of the gate field plate 56 is just exposed, and the gate field plate 56 is not over-etched. At this time, the thickness of the first dielectric layer 57 is 100 nm.

[0187] By adjusting the ratio of the etching rate of the dielectric film K3 along the first direction Y to the etching rate along the second direction X, and the total etching time, the thickness of the dielectric layer after etching can be adjusted, thereby adjusting the distance between the side wall C of the gate field plate 56 and the source field plate 59, and the distance between the source field plate 59 and the heterojunction 50.

[0188] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: Heterojunction; A source electrode, a drain electrode and a gate electrode are arranged on the heterojunction and are in contact with the heterojunction respectively; A gate field plate is disposed on the gate and electrically connected to the gate; the gate field plate is located between the source and the drain; A source field plate, disposed on a side of the gate field plate close to the drain electrode and electrically connected to the source electrode; A first dielectric layer and a second dielectric layer are disposed between the side wall of the gate field plate and the source field plate; The first dielectric layer is located on a side wall of the gate field plate, and the second dielectric layer is located between the first dielectric layer and the source field plate.

2. The semiconductor device according to claim 1, wherein: The first dielectric layer exposes a top surface of the gate field plate away from the heterojunction; The orthographic projection of the first dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction and the orthographic projection of the drain electrode on the heterojunction.

3. The semiconductor device according to claim 1 or 2, characterized in that: The gate field plate comprises a bottom surface close to one side of the heterojunction, and the minimum angle between the side wall of the gate field plate and the bottom surface is an acute angle; The first dielectric layer includes a first surface and a second surface in contact with the second dielectric layer, the first surface is perpendicular to the bottom surface of the gate field plate, the second surface is connected to the first surface, and the second surface is a curved surface.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The second dielectric layer covers the first dielectric layer and the top surface of the gate field plate away from the heterojunction; The orthographic projection of the second dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device further comprises a third dielectric layer and a fourth dielectric layer which are stacked in sequence, wherein the third dielectric layer and the fourth dielectric layer are located between the heterojunction and the first dielectric layer; The orthographic projection of the fourth dielectric layer on the heterojunction does not overlap with the orthographic projection of the source electrode on the heterojunction, and does not overlap with the orthographic projection of the drain electrode on the heterojunction; The source electrode at least penetrates the third dielectric layer and makes ohmic contact with the heterojunction; the drain electrode at least penetrates the third dielectric layer and makes ohmic contact with the heterojunction; the gate electrode penetrates the third dielectric layer and the fourth dielectric layer and makes Schottky contact with the heterojunction; Wherein, at least the third dielectric layer is spaced between the source field plate and the heterojunction.

6. The semiconductor device according to claim 5, characterized in that The source electrode also penetrates the fourth dielectric layer; The drain electrode also penetrates the fourth dielectric layer.

7. The semiconductor device according to claim 6, characterized in that The fourth dielectric layer includes a first portion and a second portion; An outer boundary of an orthographic projection of the first portion on the heterojunction coincides with an outer boundary of an orthographic projection of the first dielectric layer on the heterojunction; The orthographic projection of the second portion on the heterojunction does not overlap with the orthographic projection of the first dielectric layer on the heterojunction; The thickness of the first portion is greater than the thickness of the second portion.

8. The semiconductor device according to any one of claims 5 to 7, characterized in that: At least the second dielectric layer, the third dielectric layer and the fourth dielectric layer are spaced between the source field plate and the heterojunction; The sum of the thicknesses of the first dielectric layer and the second dielectric layer is greater than the sum of the thicknesses of the second dielectric layer, the third dielectric layer, and the fourth dielectric layer.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: A minimum distance between a side wall of the gate field plate and the source field plate is greater than a minimum distance between the source field plate and the heterojunction.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The distance between the side wall of the gate field plate and the source field plate is in the range of 50nm to 500nm; The distance between the source field plate and the heterojunction ranges from 20 nm to 500 nm.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: The material of the first dielectric layer is the same as that of the second dielectric layer.

12. A method for preparing a semiconductor device, characterized in that: include: Forming a source electrode, a drain electrode, a gate electrode and a gate field plate on the heterojunction, wherein the gate field plate is located on the gate electrode and is electrically connected to the gate electrode; The gate field plate is located between the source electrode and the drain electrode; forming a first dielectric layer, wherein the first dielectric layer is located on a side wall of the gate field plate; forming a second dielectric layer on the first dielectric layer; forming a source field plate, wherein the source field plate is located on the second dielectric layer and on a side of the gate field plate close to the drain; The source field plate is electrically connected to the source electrode.

13. The preparation method according to claim 12, characterized in that: The forming of the first dielectric layer comprises: forming a first dielectric film, wherein the first dielectric film covers the source electrode, the drain electrode and the gate field plate; Etching the first dielectric film, wherein the etching rate of the first dielectric film along the first direction is greater than the etching rate along the second direction, so as to retain the portion of the first dielectric film covering the side wall of the gate field plate, to obtain the first dielectric layer; The first direction is perpendicular to the surface of the heterojunction away from the gate field plate; the second direction is parallel to the surface of the heterojunction away from the gate field plate.

14. The preparation method according to claim 13, characterized in that: The ratio of the etching rate of the first dielectric film along the first direction to the etching rate along the second direction is in the range of 2-4.

15. The preparation method according to claim 13 or 14, characterized in that: The forming of a source, a drain, a gate and a gate field plate on the heterojunction comprises: forming a second dielectric film on the heterojunction; forming the source electrode and the drain electrode, wherein the source electrode and the drain electrode respectively penetrate the second dielectric film and contact the heterojunction; forming a third dielectric film, wherein the third dielectric film covers the second dielectric film, the source electrode and the drain electrode; forming the gate and the gate field plate, wherein the gate penetrates the third dielectric film and the second dielectric film and contacts the heterojunction; During the process of etching the first dielectric film, the third dielectric film is also etched.

16. The preparation method according to any one of claims 12 to 15, characterized in that: The first dielectric layer and the second dielectric layer are formed asynchronously.

17. The preparation method according to claim 16, characterized in that: The first dielectric layer and the second dielectric layer are formed respectively in two film forming processes.

18. A chip, characterized in that: include: substrate; The semiconductor device according to any one of claims 1 to 11, arranged on the substrate.

19. An electronic device, characterized in that: include: A radio frequency device, comprising the chip as claimed in claim 18; The radio frequency device is configured to amplify and output a radio frequency signal; The antenna is coupled to the radio frequency device and is configured to receive and radiate the radio frequency signal.

20. An electronic device, characterized in that: include: A power device, comprising the chip as claimed in claim 18; A circuit board, wherein the power device is arranged on the circuit board and is electrically connected to the circuit board.

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