Absorption enhancing structure of back-illuminated image sensor and method for forming metal wires on back surface of peripheral circuit

Abstract

The invention provides a method for forming an absorption enhancement structure and a peripheral circuit back metal wire of a back-illuminated image sensor, which improves the formation process of a mask layer, such as a back etching process, a reflow soldering process and a gradual change light flux photoetching process. The method comprises the following steps of: firstly, simultaneously forming a mask layer with an absorption enhancement structure shape and a peripheral circuit back surface metal wiring pattern on the surface of a substrate, and then etching the substrate by using the mask layer to simultaneously form an absorption enhancement structure which fluctuates along the surface of the substrate and a peripheral circuit back surface metal wiring groove, and filling a conductive layer in the peripheral circuit back metal wiring groove to form back metal wiring. The process difficulty of forming the absorption enhancement structure is reduced, meanwhile, etching of the metal wiring groove in the back face of the peripheral circuit is completed, the process steps are simplified, and the process cost is reduced. The absorption enhancement structure with a more ideal shape is obtained, a better absorption enhancement effect is achieved, the height difference of the back face of a peripheral circuit is reduced, the influence of a subsequent process on the shapes of color filters and lenses at the edge of a pixel array is reduced, and the color cast risk is reduced.

Description

Technical Field

[0001] The invention relates to the field of image sensors, and in particular to a method for forming an absorption enhancement structure of a back-illuminated image sensor and a metal wiring on the back side of a peripheral circuit. Background Art

[0002] An image sensor is a device that converts optical images into electronic signals. It is currently widely used in many fields, including digital cameras, camera phones, digital video cameras, medical imaging devices (such as gastroscopes), and automotive imaging devices.

[0003] For back-illuminated image sensor technology, the existing technology mainly focuses on the active pixel area, metal shielding area, pad area and routing area.

[0004] For the active pixel area, an undulating absorption enhancement structure is often provided on the surface of the substrate. The absorption enhancement structure can reduce the reflectivity of the substrate, increase the effective absorption of light by the substrate, and thus improve the quantum efficiency and other performance of the image sensor. The conventional preparation method of the absorption enhancement structure of the image sensor: the undulating absorption enhancement structure is formed on the surface of the substrate by etching using a photoresist mask or a hard mask patterned for the first time. Due to the limitations of the existing process, the photoresist mask or the hard mask patterned for the first time is generally formed in a shape close to a rectangular parallelepiped (the longitudinal section is a rectangle or a trapezoid close to a rectangle, and the angle between the side wall and the plane where the bottom is located is close to 90°), so the angle between the side wall of the concave part of the formed absorption enhancement structure and the plane where the bottom is located is also close to 90°, and it is impossible to form a shape similar to the expected absorption enhancement structure (the concave part is similar to an inverted pyramid structure, and the angle between the side wall and the plane where the bottom is located is generally 30-60°), which makes it difficult to form the required absorption enhancement structure on the substrate surface (especially when dry etching is used).

[0005] The routing area is usually set outside the pixel array area. The routing needs to be formed on the back of the semiconductor substrate. In order to ensure good conductivity and share the metal layer with the pad area, the thickness of the routing conductive layer is about to approximately It is used to transmit power signals, ground signals or data signals. In the prior art, pads and traces are generally located on the dielectric layer on the back of the semiconductor substrate, and are relatively thick. There is a significant height difference between them and other areas (active pixel area, metal shielding area), which can easily cause the color filter and microlens morphology at the edge of the pixel array to change during the subsequent spin coating process of the color filter layer and the microlens layer, resulting in abnormal pixel response at the edge of the pixel array, and further causing problems such as image color cast. In order to reduce the height difference on the back of the semiconductor substrate, a step-shaped groove can be formed on the back of the semiconductor substrate, and a conductive layer can be filled in the step-shaped groove to form a trace on the back.

[0006] In the prior art, the formation of the absorption enhancement structure and the formation of the peripheral circuit metal wiring grooves belong to different process flows, the preparation process is relatively complex, and the preparation cost is relatively high. Summary of the invention

[0007] The purpose of the present invention is to provide a method for forming an absorption enhancement structure and a peripheral circuit metal wiring of a back-illuminated image sensor, which reduces the process difficulty of forming the absorption enhancement structure while completing the etching of the metal wiring groove on the back of the peripheral circuit, simplifies the process steps, and reduces the process cost. It is not only conducive to obtaining an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, but also conducive to reducing the height difference on the back of the peripheral circuit, reducing the impact of subsequent processes on the color filter and lens morphology at the edge of the pixel array, and reducing the risk of color cast.

[0008] Based on the above considerations, the present invention provides a method for forming an absorption enhancement structure and a metal wiring on the back side of a peripheral circuit of a back-illuminated image sensor, comprising: forming a mask layer above the back side of a substrate, the mask layer having a shape of an absorption enhancement structure and a metal wiring pattern on the back side of a peripheral circuit; etching the substrate using the mask layer to simultaneously form an absorption enhancement structure with undulating surfaces along the substrate and a peripheral circuit back side wiring groove; and filling a conductive layer in the peripheral circuit back side wiring groove to form a back side wiring.

[0009] Furthermore, the step of forming a mask layer includes at least: forming a patterned first mask layer above the back side of the substrate; depositing a second mask layer above and between the first mask layer; the first mask layer and the second mask layer together constitute a third mask layer, and the third mask layer is formed into the pattern shape through a back etching process.

[0010] In some embodiments, the step of forming the fourth mask layer includes: forming a patterned fourth mask layer on the back side of the substrate; and forming the fourth mask layer into the pattern shape through a reflow process.

[0011] In some embodiments, the step of forming the fifth mask layer includes: forming a fifth mask layer above the back side of the substrate; and forming the fifth mask layer into the pattern shape through a gradient light flux photolithography process.

[0012] Furthermore, the absorption enhancement structure includes at least one recessed portion, and the recessed portion is in at least one of a cone, a pyramid, a truncated cone, and a truncated pyramid shape.

[0013] In some embodiments, the acute angle between the side wall of the recessed portion and the plane where the bottom thereof lies is 30°-60°.

[0014] Furthermore, at least one dielectric layer may be deposited on the absorption enhancement structure.

[0015] Furthermore, the dielectric layer includes at least one high-K dielectric material having a dielectric constant K greater than 3.9.

[0016] Furthermore, the first mask layer, the second mask layer, the fourth mask layer, and the fifth mask layer are formed by at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and a spin coating process.

[0017] Furthermore, the first mask layer and the second mask layer respectively include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0018] Furthermore, the fourth mask layer and the fifth mask layer respectively include at least one of silicon oxide, silicon nitride, silicon oxynitride or photoresist.

[0019] Furthermore, the substrate is etched by at least one of a dry etching process and a wet etching process.

[0020] Furthermore, the angle between the side wall of the metal wiring groove on the back side of the peripheral circuit and the plane where the bottom thereof is located is 30°-150°.

[0021] Furthermore, before filling the conductive layer, a dielectric layer is covered on the bottom and sidewalls of the metal wiring trench on the back side of the peripheral circuit.

[0022] The method for forming the absorption enhancement structure of the image sensor and the metal wiring on the back of the peripheral circuit of the present invention improves the formation process of the mask layer, for example, by a back etching process, a reflow process, and a gradient light flux photolithography process, a mask layer with the shape of the absorption enhancement structure is first formed above the substrate surface, and then the mask layer with the shape of the absorption enhancement structure is used to etch the substrate to form an absorption enhancement structure with convex and concave convexities along the substrate surface, thereby reducing the process difficulty of forming the absorption enhancement structure on the substrate surface, facilitating the acquisition of an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, especially improving the near-infrared quantum efficiency. Furthermore, by simultaneously etching the absorption enhancement structure and the metal wiring groove on the back of the peripheral circuit through the mask layer with the shape of the absorption enhancement structure and the metal wiring pattern on the back of the peripheral circuit, not only can the process cost be reduced and the process flow be saved, but it is also conducive to reducing the height difference on the back of the peripheral circuit, reducing the influence of subsequent processes on the color filter and lens morphology at the edge of the pixel array, and reducing the risk of color cast. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0024] Figure 1-Figure 14 A schematic diagram of a process for forming an absorption enhancement structure of an image sensor and a metal wiring on the back side of a peripheral circuit according to embodiments 1, 2 and 3 of the present invention;

[0025] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0026] In order to solve the above-mentioned problems in the prior art, the present invention provides a method for forming an absorption enhancement structure of an image sensor and a metal wiring on the back side of a peripheral circuit. A mask layer having the shape of an absorption enhancement structure and a metal wiring pattern on the back side of a peripheral circuit is formed above the surface of a substrate, and then the mask layer is used to etch the substrate to simultaneously form an absorption enhancement structure and metal wiring grooves on the back side of the peripheral circuit with uneven surfaces along the substrate surface, thereby reducing the process cost of forming the absorption enhancement structure and the metal wiring on the back side of the peripheral circuit on the substrate surface.

[0027] In the following specific description of the preferred embodiments, reference will be made to the attached drawings which constitute a part of the present invention. The attached drawings show by way of example specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0028] The present invention provides a method for forming an absorption enhancement structure of an image sensor and a metal wiring on the back side of a peripheral circuit, comprising: forming a mask layer having an absorption enhancement structure shape and a metal wiring pattern on the back side of a peripheral circuit above a substrate surface; etching the substrate using the mask layer to form an absorption enhancement structure with convex and concave shapes along the substrate surface and a metal wiring groove on the back side of a peripheral circuit; and then filling the groove with a conductive material to form the metal wiring on the back side of the peripheral circuit.

[0029] The method of the present invention is described in detail below with reference to specific embodiments.

[0030] Embodiment 1

[0031] Figure 1-Figure 5 Schematic diagram of a method for forming an absorption enhancement structure of an image sensor and metal wiring on the back side of a peripheral circuit according to a first embodiment of the present invention.

[0032] See also Figure 1 , a semiconductor substrate 100 is provided. Preferably, a trench isolation structure 101 may be formed in the substrate 100 in advance to be used for isolation between pixel units.

[0033] Then, a patterned first mask layer 106 is formed on the surface of the substrate 100. The first mask layer 106 can be made of a conventional hard mask material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and other suitable materials, and is first deposited on the surface of the substrate 100 by at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process or other suitable deposition processes to form a hard mask layer (not shown in the figure), and then a photoresist layer not shown is deposited on the hard mask layer, and then the hard mask layer is patterned by photolithography and etching processes, so as to form a hard mask layer as shown in the figure. Figure 1 The patterned first mask layer 106 is shown. Due to the limitation of the existing process, the patterned first mask layer 106 is generally formed in a shape close to a cuboid (the angle between the side wall and the plane where the bottom thereof is located is close to 90°).

[0034] See also Figure 2 Next, a second mask layer 107 is deposited on and between the patterned first mask layer 106. The second mask layer 107 also uses a hard mask material, for example, at least one selected from silicon oxide, silicon nitride, and silicon oxynitride, and can be the same as or different from the first mask layer 106. The deposition process of the second mask layer 107 can also be selected from at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and a spin coating process, and can be the same as or different from the deposition process of the first mask layer 106. The first mask layer 106 and the second mask layer 107 together constitute the third mask layer 102.

[0035] See also Figure 3-5 Next, the third mask layer 102 is subjected to a maskless etch-back process, so that the shape of the third mask layer 102 changes, gradually forming an absorption enhancement structure shape and a peripheral circuit back metal wiring pattern, and then the third mask layer 102 having the absorption enhancement structure shape and the peripheral circuit back metal wiring pattern is used to etch the substrate 100 to form an absorption enhancement structure 103 with undulating surfaces along the substrate 100 and a peripheral circuit back metal wiring groove 105.

[0036] The back-etching process may only etch away a portion of the second mask layer 107, or may further etch away a portion of the first mask layer 106. Specifically, according to product design requirements, by controlling the back-etching conditions, the shape of the third mask layer 102 after back-etching may be as close as possible to the expected absorption enhancement structure shape. Specifically, the expected absorption enhancement structure 103 includes at least one recessed portion 104. In this embodiment, the recessed portion 104 is conical or pyramidal. Those skilled in the art will appreciate that, according to requirements, the recessed portion 104 may also be configured as follows: Figure 4At least one of the truncated cone, truncated pyramid or other similar inverted pyramid shapes shown. Further preferably, as Figure 4 , 5 As shown by the middle dotted line, the acute angle α between the side wall of the recessed portion 104 and the plane where its bottom is located is 30°-60°, so that the absorption enhancement structure 103 has a better absorption enhancement effect, which can effectively reduce the reflectivity of the substrate 100 and increase the effective absorption of light by the substrate 100. Therefore, the quantum efficiency of the image sensor can be improved, especially the near-infrared quantum efficiency and other performance.

[0037] In addition, the angle between the side wall of the metal wiring groove 105 on the back of the peripheral circuit (not shown in the figure) and the plane where the bottom thereof is located is 30°-150°.

[0038] After forming the third mask layer 102 having the shape of the absorption enhancement structure and the metal wiring pattern of the back side of the peripheral circuit on the surface of the substrate 100 by the back etching process, preferably, the substrate 100 can be etched by at least one of the dry etching process and the wet etching process to form the absorption enhancement structure 103 and the metal wiring groove 105 of the back side of the peripheral circuit along the surface of the substrate 100. Since the third mask layer 102 itself has the shape of the absorption enhancement structure by improving the mask layer formation process, when the substrate 100 is etched by the third mask layer 102 having the shape of the absorption enhancement structure, the process difficulty of forming the absorption enhancement structure on the surface of the substrate is reduced, which is conducive to obtaining an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, especially improving the near-infrared quantum efficiency. Furthermore, the metal wiring groove of the back side of the peripheral circuit is formed while forming the absorption enhancement structure, which simplifies the process flow and reduces the process cost.

[0039] In addition, see Figure 6 At least one dielectric layer is deposited on the absorption enhancement structure 103 and the peripheral circuit back metal routing groove 105. The dielectric layer may include at least one high-K dielectric material with a dielectric constant K greater than 3.9. Then, the peripheral circuit back metal routing groove 105 is filled with a conductive material to form a peripheral circuit back metal routing 108.

[0040] Embodiment 2

[0041] Figure 7-Figure 10 It is a schematic diagram of the process of forming the absorption enhancement structure of an image sensor and the metal wiring on the back side of the peripheral circuit according to the second embodiment of the present invention.

[0042] See also Figure 7 , a semiconductor substrate 200 is provided. Preferably, a trench isolation structure 201 may be pre-formed in the substrate 200 for isolation between pixel units.

[0043] Then, a patterned fourth mask layer 202 is formed on the surface of the substrate 200. The fourth mask layer 202 may be a photoresist, which is first deposited on the surface of the substrate 200 by at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes to form a photoresist layer 202, and then patterned by a photolithography process; the fourth mask layer 202 may also be made of a conventional hard mask material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and other suitable materials, which is first deposited on the surface of the substrate 200 by at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes to form a hard mask layer 202, and then a photoresist layer not shown is deposited on the hard mask layer 202, and then patterned by photolithography and etching processes, thereby forming a hard mask layer 202 as shown in FIG. Figure 6 The patterned fourth mask layer 202 is shown. Due to the limitation of the existing process, the patterned fourth mask layer 202 is generally formed in a shape close to a cuboid (the angle between the side wall and the plane where the bottom thereof is located is close to 90°).

[0044] See also Figure 8 , Fig. 9 Next, the patterned fourth mask layer 202 is subjected to a reflow process so that the shape of the fourth mask layer 202 changes, gradually forming an absorption enhancement structure shape and a peripheral circuit back metal wiring groove pattern, and then the fourth mask layer 202 having the absorption enhancement structure shape and the peripheral circuit back metal wiring groove pattern is used to etch the substrate 200 to form an absorption enhancement structure 203 and a peripheral circuit back metal wiring groove 205 with undulating surfaces along the substrate 200.

[0045] The reflow process can melt the material of the fourth mask layer 202 at a high temperature, so that the melted material in the middle top flows to the bottom of both sides to form a redistribution. Therefore, according to the specific product design needs, the reflow conditions can be controlled to make the shape of the fourth mask layer 202 after reflow as close as possible to the expected absorption enhancement structure shape. Specifically, the expected absorption enhancement structure 203 includes at least one recessed portion 204. In the present embodiment, the recessed portion 204 is conical or pyramidal. In other embodiments not shown, the recessed portion 204 can also be set to at least one of a truncated cone, a truncated pyramid or other similar inverted pyramid shapes. Further preferably, the side wall of the recessed portion 204 is aligned with the plane where its bottom is located (such as Figure 7The acute angle β between the two surfaces (as shown by the dotted line in the middle) is 30°-60°, so that the absorption enhancement structure 203 has a better absorption enhancement effect, which can effectively reduce the reflectivity of the substrate 200 and increase the effective absorption of light by the substrate 200. Therefore, the quantum efficiency of the image sensor can be improved, especially the near-infrared quantum efficiency and other performance.

[0046] In addition, the angle between the side wall of the metal wiring groove 205 on the back of the peripheral circuit and the plane where its bottom is located is 30°-150°.

[0047] After forming the fourth mask layer 202 having the shape of the absorption enhancement structure and the metal wiring pattern of the back side of the peripheral circuit on the surface of the substrate 200 by the reflow process, preferably, the substrate 200 can be etched by at least one of a dry etching process and a wet etching process to form the absorption enhancement structure 203 and the metal wiring groove 205 of the back side of the peripheral circuit along the surface of the substrate 200. Since the fourth mask layer 202 itself has the shape of the absorption enhancement structure by improving the mask layer formation process, when the fourth mask layer 202 having the shape of the absorption enhancement structure and the metal wiring pattern of the back side of the peripheral circuit is used to etch the substrate 200, the process difficulty of simultaneously forming the absorption enhancement structure on the substrate surface is reduced, which is conducive to obtaining an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, especially improving the near-infrared quantum efficiency. Furthermore, the metal wiring groove of the back side of the peripheral circuit is formed while forming the absorption enhancement structure, simplifying the process flow and reducing the process cost.

[0048] In addition, see Fig.10 At least one dielectric layer is deposited on the absorption enhancement structure 203 and the peripheral circuit back metal routing groove 205. The dielectric layer may include at least one high-K dielectric material with a dielectric constant K greater than 3.9. Then, the peripheral circuit back metal routing groove 205 is filled with a conductive material to form a peripheral circuit back metal routing 208.

[0049] Embodiment 3

[0050] Figure 11-Figure 14 Schematic diagram of a method for forming an absorption enhancement structure of an image sensor and metal wiring on the back side of a peripheral circuit according to a third embodiment of the present invention.

[0051] See also Fig.11 , a semiconductor substrate 300 is provided. Preferably, a trench isolation structure 301 may be pre-formed in the substrate 300 for isolation between pixel units.

[0052] Then, a fifth mask layer 302 is deposited on the surface of the substrate 300 by at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process or other suitable deposition processes. The fifth mask layer 302 may be a photoresist or a hard mask material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and other suitable materials.

[0053] See also Fig.12 , Fig.13 Next, the fifth mask layer 302 is patterned by a gradient light flux photolithography process, so that the fifth mask layer 302 forms an absorption enhancement structure shape and a peripheral circuit back metal wiring pattern, and then the fifth mask layer 302 having the absorption enhancement structure shape and the peripheral circuit back metal wiring pattern is used to etch the substrate 300 to form an absorption enhancement structure 303 and a peripheral circuit back metal wiring groove with convex and concave shapes along the surface of the substrate 300. Specifically, if the fifth mask layer 302 is a photoresist, it is directly patterned by the gradient light flux photolithography process; if the fifth mask layer 302 is a hard mask layer, a photoresist layer (not shown) is first deposited on the hard mask layer 302, and then the photoresist layer is patterned by the gradient light flux photolithography process, and then the pattern is transferred to the hard mask layer 302 by an etching process, so that the fifth mask layer 302 forms an absorption enhancement structure shape and a peripheral circuit back metal wiring pattern.

[0054] The gradient light flux lithography process, also known as the gray tone lithography process, modulates the energy density distribution of the processing beam into different shapes through the gray mask, exposes the photoresist, and forms the micro device in one go. There is no need to move the mask or the processing wafer, nor to heat treat the photoresist. It only requires certain coding of the mask and standard lithography equipment, which is easy to be compatible with other IC processes to achieve the production of system chip structures. The gray lithography process uses a gray mask to modulate uniform radiation. A single exposure and development can form micro-optical devices on any surface, and can ensure that the device surface is smooth, eliminating the alignment error in the binary lithography process and the shortcomings of multi-step lithography and multi-layer masks. The performance and quality of the device are only related to the exposure dose, not the processing process, and has strong repeatability.

[0055] Therefore, according to the specific product design needs, a grayscale mask (not shown) can be used to control the gradient light transmittance lithography conditions so that the expected absorption enhancement structure shape and the metal wiring pattern on the back of the peripheral circuit can be directly formed during the patterning of the fifth mask layer 302. Specifically, the expected absorption enhancement structure 303 includes at least one recessed portion 304. In the present embodiment, the recessed portion 304 is conical or pyramidal. In other embodiments not shown, the recessed portion 304 can also be set to at least one of a truncated cone, a truncated pyramid, or other similar inverted pyramid shapes. Further preferably, the side wall of the recessed portion 304 is aligned with the plane where its bottom is located (such as Fig.10 The acute angle γ between the two surfaces (as shown by the dotted line in the middle) is 30°-60°, so that the absorption enhancement structure 303 has a better absorption enhancement effect, which can effectively reduce the reflectivity of the substrate 300 and increase the effective absorption of light by the substrate 300. Therefore, the quantum efficiency of the image sensor can be improved, especially the near-infrared quantum efficiency and other performance. At the same time as the absorption enhancement structure is formed, a metal wiring groove on the back of the peripheral circuit is formed, which simplifies the process flow and reduces the process cost.

[0056] In addition, the angle between the side wall of the metal wiring groove 305 on the back of the peripheral circuit (not shown in the figure) and the plane where the bottom thereof is located is 30°-150°.

[0057] After forming the fifth mask layer 302 having the shape of the absorption enhancement structure and the metal wiring pattern of the back side of the peripheral circuit on the surface of the substrate 300 by the gradual light flux photolithography process, preferably, the substrate 300 can be etched by at least one of the dry etching process and the wet etching process to form the absorption enhancement structure 303 with undulations along the surface of the substrate 300 and the metal wiring groove 305 of the back side of the peripheral circuit. Since the fifth mask layer 302 itself has the shape of the absorption enhancement structure by improving the mask layer formation process, when the fifth mask layer 302 with the absorption enhancement structure is used to etch the substrate 300, the process difficulty of forming the absorption enhancement structure on the substrate surface is reduced, which is conducive to obtaining an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, especially improving the near-infrared quantum efficiency. Furthermore, the metal wiring groove of the back side of the peripheral circuit is formed while forming the absorption enhancement structure, which simplifies the process flow and reduces the process cost.

[0058] In addition, see Fig.14, at least one dielectric layer is deposited above the absorption enhancement structure 303 and the peripheral circuit back metal routing groove 305, and the dielectric layer may include at least one of high-K dielectric materials with a dielectric constant K greater than 3.9. Then the peripheral circuit back metal routing groove 305 is filled with a conductive material to form a peripheral circuit back metal routing 308. In summary, the absorption enhancement structure of the image sensor of the present invention and the method for forming the peripheral circuit back metal routing are formed by improving the formation process of the mask layer, for example, by a back etching process, a reflow process, and a gradient light flux lithography process, first forming a mask layer having an absorption enhancement structure shape and a peripheral circuit back metal routing pattern on the substrate surface, and then etching the substrate with the absorption enhancement structure shape and the peripheral circuit back metal routing pattern to form an absorption enhancement structure with convex and concave convexities along the substrate surface, thereby reducing the process difficulty of forming the absorption enhancement structure on the substrate surface, facilitating obtaining an absorption enhancement structure with a more ideal shape, achieving a better absorption enhancement effect, and improving the quantum efficiency of the image sensor, especially improving the near-infrared quantum efficiency. Furthermore, a metal wiring groove on the back side of the peripheral circuit is formed while forming the absorption enhancement structure, thereby simplifying the process flow and reducing the process cost.

[0059] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The words first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A method for forming an absorption enhancement structure of a back-illuminated image sensor and a metal wiring on the back side of a peripheral circuit, characterized in that: include: forming a mask layer on the back side of the substrate, wherein the mask layer has an absorption enhancement structure shape and a metal wiring pattern on the back side of the peripheral circuit; The substrate is etched using the mask layer to simultaneously form an absorption enhancement structure with bumps along the surface of the substrate and a metal wiring groove on the back side of the peripheral circuit; A conductive layer is filled in the peripheral circuit back metal routing groove to form a back metal routing.

2. The method according to claim 1, characterized in that The step of forming a mask layer comprises: forming a patterned first mask layer over the back side of the substrate; Depositing a second mask layer above and between the first mask layers; The first mask layer and the second mask layer together constitute a third mask layer, and the third mask layer is formed into the pattern shape through an etch-back process.

3. The method according to claim 1, characterized in that The step of forming a mask layer comprises: forming a patterned fourth mask layer over the back side of the substrate; The fourth mask layer is formed into the pattern shape through a reflow process.

4. The method according to claim 1, characterized in that The step of forming a mask layer comprises: forming a fifth mask layer over the back side of the substrate; The fifth mask layer is formed into the pattern shape through a gradient light flux photolithography process.

5. The method according to claim 1, characterized in that The absorption enhancement structure includes at least one recessed portion, and the recessed portion is at least one of a cone, a pyramid, a truncated cone, and a truncated pyramid.

6. The method according to claim 5, characterized in that The acute angle between the side wall of the concave portion and the plane where the bottom thereof is located is 30°-60°.

7. The method according to claim 1, characterized in that Further including: At least one dielectric layer is deposited over the absorption enhancement structure.

8. The method according to claim 7, characterized in that The dielectric layer includes at least one high-K dielectric material having a dielectric constant K greater than 3.

9.

9. The method according to any one of claims 2 to 4, characterized in that: At least one of the first mask layer, the second mask layer, the fourth mask layer or the fifth mask layer is formed by deposition through at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process and a spin coating process.

10. The method according to claim 9, characterized in that The first mask layer and the second mask layer respectively include at least one of silicon oxide, silicon nitride and silicon oxynitride.

11. The method according to claim 9, characterized in that The fourth mask layer and the fifth mask layer respectively include at least one of silicon oxide, silicon nitride, silicon oxynitride or photoresist.

12. The method according to claim 1, characterized in that The substrate is etched by at least one of a dry etching process and a wet etching process.

13. The method according to claim 1, characterized in that The angle between the side wall of the metal wiring groove on the back side of the peripheral circuit and the plane where the bottom is located is 30°-150°.

14. The method according to claim 1, wherein: Before filling the conductive layer, the bottom and sidewalls of the metal wiring trench on the back side of the peripheral circuit are covered with a dielectric layer.

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