Light emitting element and display device including same

Abstract

The invention relates to a light emitting element and a display device including the same. A display device is provided. The display device includes a first semiconductor layer, a first electrode and an active layer disposed on the first semiconductor layer to be spaced apart from each other, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer, the active layer includes a plurality of first portions having a first width in the width direction and a second portion disposed between the plurality of first portions and having a second width smaller than the first width in the width direction.

Description

Technical Field

[0001] The present disclosure relates to a light emitting element and a display device including the same, and more particularly, to a light emitting diode (LED) and a display device using the same. Background Art

[0002] As display devices used for monitors of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0003] The application range of the display device is diversified to personal digital assistants as well as monitors and televisions of computers, and display devices having a large display area and reduced volume and weight are being studied.

[0004] In addition, recently, a display device including a light emitting diode (LED) is receiving attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it is excellent in reliability so that its life is longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast lighting speed, excellent luminous efficiency, and strong impact resistance so that it is excellent in stability and can display an image with high brightness. Summary of the invention

[0005] An object to be achieved by the present disclosure is to provide a light emitting element and a display device including the same, in which a deviation in the inclination angle of a side surface of the light emitting element is reduced.

[0006] Another object to be achieved by the present disclosure is to provide a light emitting element in which brightness deviation is reduced according to a viewing angle and a display device including the same.

[0007] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the present disclosure, a light-emitting element is provided, which includes a first semiconductor layer, a first electrode and an active layer disposed on the first semiconductor layer to be spaced apart from each other, a second semiconductor layer located on the active layer, and a second electrode located on the second semiconductor layer, wherein the active layer includes a plurality of first portions having a first width in a width direction and a second portion disposed between the plurality of first portions and having a second width smaller than the first width in the width direction.

[0009] According to another aspect of the present disclosure, a display device is provided. The display device includes a substrate and a plurality of light-emitting elements disposed on the substrate. Each of the plurality of light-emitting elements includes: a first semiconductor layer, a first electrode and an active layer disposed on the first semiconductor layer, a second semiconductor layer located on the active layer, and a second electrode disposed on the second semiconductor layer to be spaced apart from the first electrode along a longitudinal direction. The active layer includes a first portion having a first width and a second portion having the same width as the first portion and a second width less than the first width.

[0010] Additional details of example implementations are included in the detailed description and the accompanying drawings.

[0011] According to the present disclosure, even if process deviation occurs, the inclination angle of the side surface of the light emitting element can be uniformly formed.

[0012] According to the present disclosure, the occurrence of chromatic aberration due to a change in viewing angle may be reduced.

[0013] According to the present disclosure, the occurrence of mura due to a change in viewing angle may be minimized.

[0014] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic plan view of a light emitting element according to an exemplary embodiment of the present disclosure;

[0017] FIG. 2A to FIG. 2C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the present disclosure;

[0018] Figure 3A and Figure 3B is a process diagram showing a method for manufacturing a light emitting element according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0020] Figure 5A and Figure 5B is a cross-sectional view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0021] Fig. 6A and Figure 6B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0022] Fig. 7A and Figure 7B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0023] Fig. 8A and Figure 8B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0024] Fig.9A and Fig. 9B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure;

[0025] Fig.10 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure; and

[0026] Fig.11 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] By referring to the following and attached Figure 1 With the exemplary embodiments described in detail, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0028] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any singular reference may include plural numbers.

[0029] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0030] When terms such as “on,” “above,” “below,” and “beside” are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms “immediately next to” or “directly.”

[0031] When an element or a layer is referred to as being “on” another element or layer, the other layer or element may be directly interposed on the other element or between them.

[0032] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0033] Like reference numbers generally refer to like elements throughout this specification.

[0034] The sizes and thicknesses of various components shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the sizes and thicknesses of the components shown.

[0035] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may be technically interlocked and operated in various ways, and these embodiments may be performed independently or in association with each other.

[0036] Hereinafter, a light emitting element and a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a schematic plan view of a light emitting element according to an exemplary embodiment of the present disclosure. FIG. 2A to FIG. 2C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the present disclosure. Figure 1 In the figure, for the convenience of illustration, only the first semiconductor layer 131, the active layer 132, the first electrode 134 and the second electrode 135 of the light emitting element ED1 are shown. Figure 2A It is along Figure 1 A cross-sectional view taken along line AA'. Figure 2B It is along Figure 1 A cross-sectional view taken along line BB'. Figure 2C It is along Figure 1 A cross-sectional view taken along line CC'.

[0038] Reference Figures 1 to 2C The plurality of light emitting elements ED1 include a base layer 137 , a first semiconductor layer 131 , an active layer 132 , a second semiconductor layer 133 , a first electrode 134 , and a second electrode 135 .

[0039] The plurality of light emitting elements ED1 may be formed into various structures such as lateral, vertical, and flip-chip. The lateral light emitting element includes a first electrode and a second electrode disposed laterally on both sides of the active layer. The vertical light emitting element includes a first electrode and a second electrode disposed on the upper side and the lower side of the active layer. The flip-chip light emitting element has substantially the same structure as the lateral light emitting element. The lateral light emitting element has a first electrode and a second electrode disposed laterally on the upper side of the active layer, while the flip-chip light emitting element has a first electrode and a second electrode disposed laterally on the lower side of the active layer. Hereinafter, the plurality of light emitting elements ED1 will be described under the assumption that they have a lateral structure, but the type of the plurality of light emitting elements ED1 is not limited thereto.

[0040] The base layer 137 may be formed of an undoped semiconductor material, such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs), but is not limited thereto.

[0041] The first semiconductor layer 131 is disposed above the base layer 137. The first semiconductor layer 131 may be a layer formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 131 may be a layer formed by doping n-type impurities and p-type impurities into materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), and gallium arsenide (GaAs). Here, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto. In the present disclosure, the first semiconductor layer 131 is defined as an n-type semiconductor layer doped with n-type impurities, but is not limited thereto.

[0042] In addition, a portion of the first semiconductor layer 131 may protrude outside the second semiconductor layer 133 and the active layer 132 and may be exposed from the second semiconductor layer 133 and the active layer 132. In this case, a top surface of the first semiconductor layer 131 protruding outside the second semiconductor layer 133 and the active layer 132 may be defined as a first plane F1 of the light emitting element ED1.

[0043] In this case, the first plane F1 may be formed to surround the peripheral region of the active layer 132 and the second semiconductor layer 133. In addition, a side surface of the light emitting element ED1 extending downward from the first plane F1 may be defined as a first side surface S1. FIG. 2A to FIG. 2C As shown, the first side surface S1 may refer to side surfaces of the first semiconductor layer 131 and the base layer 137 and be disposed below the first plane F1.

[0044] The first semiconductor layer 131 may have a constant width in a width direction at a portion other than a corner portion. Figure 1As shown, the corner portions of the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133 may have a round shape. In this regard, when the light emitting element ED1 is driven, in order to suppress current concentration in the corner portions of the light emitting element ED1, some regions of the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133 disposed at the corner portions of the light emitting element ED1 may be removed, but are not limited thereto.

[0045] The active layer 132 and the second semiconductor layer 133 are disposed on the first semiconductor layer 131 .

[0046] The entire active layer 132 and the second semiconductor layer 133 may overlap the first semiconductor layer 131, and the entire second semiconductor layer 133 may overlap the active layer 132. In addition, only a portion of the first semiconductor layer 131 may overlap the active layer 132 and the second semiconductor layer 133.

[0047] In this case, a portion of the first semiconductor layer 131 overlapping the first semiconductor layer 131 and the active layer 132 and the second semiconductor layer 133 disposed on the first semiconductor layer 131 may be referred to as a MESA portion.

[0048] In addition, the side surface of the light emitting element ED1 extending from the first plane F1 to extend upward may be defined as a second side surface S2, and may be composed of a side surface of the first semiconductor layer 131, a side surface of the active layer 132, and a side surface of the second semiconductor layer 133. The second side surface S2 may be disposed to be inclined relative to the first plane F1. In this case, the second side surface S2 may be the same as the side surface of the MESA portion.

[0049] The active layer 132 may be disposed on the first semiconductor layer 131 to be spaced apart from the first electrode 134. The active layer 132 may emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0050] Reference Figure 1 , the active layer 132 may include a plurality of first portions P1 having a first width W1 in a width direction and a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 smaller than the first width W1 in the width direction. A plurality of second portions P2 are disposed, and the plurality of first portions P1 and the plurality of second portions P2 may be disposed alternately. In addition, Figure 1 The number of the first portions P1 and the number of the second portions P2 shown are merely examples and are not limited thereto.

[0051] At least a portion of the second side surface S2 of the second portion P2 may be disposed inside the second side surface S2 of the first portion P1. Figure 1 As shown, the second side surface S2 of the first portion P1 may be disposed to be closer to the first side surface S1 than the second side surface S2 of the second portion P2, and the second side surface S2 of the second portion P2 may be disposed adjacent to the center of the light emitting element ED1. Figure 2B and Figure 2C As shown, a distance W1 between second side surfaces S2 facing the width direction in the plurality of first portions P1 may be longer than a distance W2 between second side surfaces S2 facing the width direction in the second portions P2.

[0052] In addition, if Figure 1 As shown, the active layer 132 may be disposed to be biased toward the B side of the B side and the B' side as the width direction. Figure 2B As shown, a distance d1 between the second side surface S2 disposed toward the B side in the first portion P1 and the first side surface S1 may be smaller than a distance d2 between the second side surface S2 disposed toward the B′ side in the first portion P1 and the first side surface S1 .

[0053] In addition, the distance between the second side surface S2 and the first side surface S1 in the first portion P1 may refer to the shortest distance between the first side surface S1 and the second side surface S2 disposed on the light emitting element ED1. Therefore, the distance d1 between the second side surface S2 disposed on the B side in the first portion P1, which is the shortest distance between the first side surface S1 and the second side surface S2 on one side in the width direction, may be smaller than the distance d2 between the second side surface S2 and the first side surface S1 disposed on the B' side in the first portion P1, which is the shortest distance between the first side surface S1 and the second side surface S2 on the other side.

[0054] In addition, the second side surface S2 of the first portion P1 may include at least one surface having different inclination angles. For example, the inclination angle of the second side surface S2 of the first portion P1 on one side may be greater than the inclination angle of the second side surface S2 of the first portion P1 on the other side, and the inclination angle of the second side surface S2 of the second portion P2 on one side may be the same as the inclination angle of the second side surface S2 of the second portion P2 on the other side. Figure 2B In the embodiment, the inclination angle of the second side surface S2 disposed on the B side is greater than the inclination angle b of the second side surface S2 disposed on the B' side, and Figure 2C In the embodiment, the inclination angle c of the second side surface S2 disposed at the C side may be the same as the inclination angle c of the second side surface S2 disposed at the C′ side.

[0055] In addition, Figure 1 , the width of the first portion P1 and the width of the second portion P2 are shown to be the same, but may not be limited thereto.

[0056] The following will refer to Figure 3A and Figure 3B A more detailed description of the second side surface S2 of the first portion P1 and the second side surface S3 of the second portion P2 will be described.

[0057] The second semiconductor layer 133 is disposed above the active layer 132. The second semiconductor layer 133 may be a layer formed by doping n-type impurities and p-type impurities into a specific material. For example, the second semiconductor layer 133 may be a layer formed by doping n-type impurities and p-type impurities into materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), and gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto. In the present disclosure, the second semiconductor layer 133 is defined as a p-type semiconductor layer doped with p-type impurities, but is not limited thereto.

[0058] The first electrode 134 is disposed on the first plane F1 of the first semiconductor layer 131. The first semiconductor layer 131 may be a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be disposed on the top surface of the first semiconductor layer 131 exposed from the active layer 132 and the second semiconductor layer 133. The first electrode 134 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, etc., but is not limited thereto.

[0059] The second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 may be disposed on the top surface of the second semiconductor layer 133. In this case, the second semiconductor layer 133 may be a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, etc., but is not limited thereto.

[0060] Figure 3A and Figure 3B 2 is a process diagram illustrating a method of manufacturing a light emitting element according to an exemplary embodiment of the present disclosure. Figure 3A is a cross-sectional view showing a state after a MESA etching process. Figure 3B is a cross-sectional view showing an isolation process for separating the light emitting element ED1 from the wafer WA.

[0061] Reference Figure 3A, a base layer 137 , a first semiconductor layer 131 , an active layer 132 and a second semiconductor layer 133 are disposed on the wafer WA.

[0062] Some areas of the active layer 132 and the second semiconductor layer 133 may be patterned by a MESA etching process. Here, the MESA etching process may refer to a process of defining light-emitting areas of the plurality of light-emitting elements ED1. The MESA etching process may refer to a process of leaving the active layer 132 and the second semiconductor layer 133 only in areas corresponding to the light-emitting areas of the plurality of light-emitting elements ED1 on the wafer WA, and etching the active layer 132 and the second semiconductor layer 133 disposed in areas corresponding to non-light-emitting areas of the plurality of light-emitting elements ED1. In this case, some areas of the first semiconductor layer 131 may also be etched in the MESA etching process. Therefore, the thickness of the first semiconductor layer 131 disposed outside the active layer 132 and the second semiconductor layer 133 may be thinner than the first semiconductor layer 131 in an area overlapping the active layer 132 and the second semiconductor layer 133.

[0063] Reference Figure 3A The photoresist PR covers the active layer 132 and the second semiconductor layer 133 so as to perform an isolation process of separating the plurality of light emitting elements ED1 from the wafer WA. When the photoresist PR is used as a mask, the first semiconductor layer 131 and the base layer 137 may be etched in a region not covered by the photoresist PR.

[0064] When there is no process error during the formation of the photoresist, such as Figure 3A As shown, the photoresist is set in the form of a dotted line, and the first semiconductor layer 131 and the base layer 137 can be etched normally. However, when a process error occurs during the formation of the photoresist, the photoresist PR can be set as shown in a solid line by being biased to one side compared to the area shown in the dotted line. Therefore, portions of the active layer 132 and the second semiconductor layer 133 may be exposed from the photoresist PR. In addition, portions of the active layer 132 and the second semiconductor layer 133 that are not covered by the photoresist PR may be affected by the isolation process.

[0065] The side surfaces of the active layer 132 and the second semiconductor layer 133 that are not covered by the photoresist PR may be exposed to the etching process and etched together with the first semiconductor layer 131 and the base layer 137. Figure 3B As shown, the inclination angle b of the second side surface S2 exposed to the outside by the photoresist PR may be greater than the inclination angle a of the second side surface S2 covered by the photoresist PR.

[0066] When light generated from the light emitting element passes through the side surface of the MESA portion of the light emitting element, the traveling direction of the light on the side surface of the MESA portion may change. Therefore, the brightness distribution according to the viewing angle of the light emitting element may vary according to the inclination angle of the region called the MESA portion of the light emitting element (i.e., the side surfaces of the second semiconductor layer and the active layer).

[0067] The MESA portion of the light emitting element may be formed by a MESA etching process, and the inclined surface of the MESA portion of the light emitting element may be formed by the MESA etching process. In addition, various processes for forming the light emitting element are performed even after the MESA etching process. In this case, the MESA portion of the light emitting element may be exposed to various processes performed after the MESA etching process. For example, after the MESA etching process, an isolation process may be performed to separate the light emitting element by etching the wafer and the semiconductor layer disposed on the wafer. In this case, the isolation process may refer to a process for separating the light emitting element from the wafer by etching an area corresponding to the peripheral area of ​​the light emitting element. Therefore, the etching process performed in the isolation process is performed in an area other than the MESA portion. However, when a process deviation occurs, the MESA portion may be exposed to the isolation process. For example, when a photoresist is used as a mask, due to a process error, one side of the MESA portion may be covered by the photoresist, but the other side of the MESA portion may be exposed due to a difference in the area covered by the photoresist. Therefore, the MESA portion exposed due to the process deviation of the photoresist may be etched together with the wafer and the semiconductor layer disposed on the wafer. In this case, the inclination angle of the inclined surface of the MESA portion exposed in the isolation process may be different from the inclination angle of the inclined surface of the MESA portion covered by the photoresist, and the inclination angles of the inclined surfaces of the MESA portion may be deviated.

[0068] In particular, when the light-emitting element is a micro light-emitting diode (micro LED), a deviation in the inclination angle of the inclined surface of the MESA portion may occur even in the case of a micron-level tolerance. For example, when the width of the MESA portion is wide, the MESA portion may be disposed adjacent to the peripheral area of ​​the light-emitting element. Therefore, even in the case of a small error, some areas of the MESA portion may be exposed by the photoresist. Therefore, when the width of the MESA portion increases, the possibility of the MESA portion being exposed to the etching process increases, and the deviation in the inclination angle of the side surface of the MESA portion may become worse. Therefore, when the width of the MESA portion increases, the inclination angle of the inclined surface of the MESA portion of the light-emitting element deviates, and thus the possibility of color difference may increase depending on the viewing angle, and color spots depending on the viewing angle may be visible to the viewer.

[0069] Therefore, in the light emitting element ED1 according to the exemplary embodiment of the present disclosure, the active layer 132 includes a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the plurality of first portions P1 may be disposed adjacent to the peripheral region of the light emitting element ED1, but the second portion P2 may be disposed adjacent to the center of the light emitting element ED1 compared to the plurality of first portions P1. Therefore, the second portion P2 may be less affected by the manufacturing process of the light emitting element ED1, and in particular, the peripheral region of the light emitting element ED1 may be less affected by the process deviation. For example, even if a process error occurs in the isolation process of separating the plurality of light emitting elements ED1 from the wafer WA, the second portion P2 having a narrow width may be covered by the photoresist PR. Therefore, even if the inclination angles of the inclined surfaces of the plurality of first portions P1 deviate in the manufacturing process of the light emitting element ED1, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed, and thus the deviation of the viewing angle of the light emitting element ED1 may be reduced.

[0070] In addition, the light emitting element ED1 according to the exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2. Therefore, the light emitting area of ​​the light emitting element ED1 in the first portion P1 can be increased, and the second portion P2 and the first portion P1 can be alternately arranged to improve the color difference according to the viewing angle of the light emitting element ED1.

[0071] Figure 4 is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure. Figure 5A and Figure 5B is a cross-sectional view of a light emitting element according to another exemplary embodiment of the present disclosure. Figures 4 to 5B The light emitting element ED2 and Figures 1 to 3B The light emitting element ED1 of FIG. 4 is different only in the first semiconductor layer 431 , the active layer 432 , and the second semiconductor layer 433 . However, the other components are substantially the same, and thus a redundant description thereof will be omitted. Figure 4 In the figure, for the convenience of illustration, only the first semiconductor layer 431, the active layer 432, the first electrode 134 and the second electrode 135 of the light emitting element ED2 are shown. Figure 5A It is along Figure 4 A cross-sectional view taken along line D-D', Figure 5B It is along Figure 4 A cross-sectional view taken along line EE'.

[0072] Reference Figures 4 to 5BThe light emitting element ED2 includes a first plane F1 of the light emitting element ED2 protruding out of the second semiconductor layer 433 and the active layer 432, a first side surface S1 extending downward from the first plane F1, and a second side surface S2 extending upward from the first plane F1. The first plane F1 of the light emitting element ED2 may be composed of the top surface of the first semiconductor layer 431, the first side surface S1 may be composed of the side surface of the first semiconductor layer 431, and the second side surface S2 may be composed of the side surface of the first semiconductor layer 431, the side surface of the active layer 432, and the side surface of the second semiconductor layer 433.

[0073] The first semiconductor layer 431, the active layer 432, and the second semiconductor layer 433 may be disposed over the base layer 137, and the active layer 432 includes a plurality of first portions P1 having a first width W1 in a width direction and a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 smaller than the first width W1 in the width direction.

[0074] also, Figures 4 to 5B The light emitting element ED2 shown may be a light emitting element ED2 manufactured under the condition that no process error occurs during the manufacturing process or the process deviation is substantially insignificant. For example, when the MESA portion is designed to be disposed at the center of the width direction of the light emitting element ED2, as shown in FIG. Figure 4 As shown in FIG. 4 , the active layer 432 may be disposed at the center of the width direction of the light emitting element ED2. Figure 5A As shown, a distance d1 between the second side surface S2 disposed toward the D side in the first portion P1 and the first side surface S1 may be the same as a distance d2 between the second side surface S2 disposed toward the D′ side in the first portion P1 and the first side surface S1 .

[0075] In addition, the distance between the second side surface S2 and the first side surface S1 in the first portion P1 may refer to the shortest distance between the first side surface S1 and the second side surface S2 disposed on the light emitting element ED2. Therefore, the distance d1 between the second side surface S2 disposed on the D side in the first portion P1 and the first side surface S1 (the shortest distance in the width direction between the first side surface S1 and the second side surface S2 on one side) may be the same as the distance d2 between the second side surface S2 and the first side surface S1 disposed on the D' side in the first portion P1 (the shortest distance between the first side surface S1 and the second side surface S2 on the other side).

[0076] In addition, the inclination angle between the second side surface S2 and the first plane F1 may be constant. Figure 5A In the embodiment, the inclination angle a of the second side surface S2 disposed on the D side in the first portion P1 may be the same as the inclination angle b of the second side surface S2 disposed on the D' side, and Figure 5BIn the embodiment, the inclination angle c of the second side surface S2 disposed on the E side and the inclination angle c of the second side surface S2 disposed on the E′ side in the second portion P2 may be the same.

[0077] In the light emitting element ED2 according to another exemplary embodiment of the present disclosure, the active layer 632 includes a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the second portion P2 may be less affected by deviations in the manufacturing process of the light emitting element ED2. Therefore, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED2 may be reduced.

[0078] In addition, the light emitting element ED2 according to another exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2. Therefore, the light emitting area of ​​the light emitting element ED2 in the first portion P1 can be increased, and the second portion P2 and the first portion P1 can be alternately arranged to improve the color difference according to the viewing angle of the light emitting element ED2.

[0079] Fig. 6A and Figure 6B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure. FIG. 6A to FIG. 6B The light emitting element ED3 and Figures 1 to 3B The light emitting element ED1 of FIG. 1 is different only in the first semiconductor layers 631 and 631', the active layers 632 and 632', and the second semiconductor layer. However, other components are substantially the same, and thus a redundant description thereof will be omitted. Fig. 6A The light emitting element ED3 is shown when a manufacturing process error occurs. Figure 6B FIG. 2 shows a light emitting element ED3 manufactured under the condition that no process error occurs or the process deviation is substantially insignificant. Fig. 6A and Figure 6B In the figure, for convenience of illustration, only the first semiconductor layers 631 and 631 ′, the active layers 632 and 632 ′, the first electrode 134 and the second electrode 135 of the light emitting element ED3 are shown.

[0080] Reference Fig. 6A , the light emitting element ED3 includes a first semiconductor layer 631, an active layer 632, a second semiconductor layer, a first electrode 134 and a second electrode 135. Figure 6B The light emitting element ED3 includes a first semiconductor layer 631 ′, an active layer 632 ′, a second semiconductor layer, a first electrode 134 and a second electrode 135 .

[0081] The light emitting element ED3 may include a first plane F1 protruding out of the second semiconductor layer and the active layers 632 and 632'. Fig. 6A and Figure 6BThe light emitting element ED3 includes a first side surface S1 extending downward from the first plane F1 and a second side surface S2 extending upward from the first plane F1. The first side surface S1 may be composed of side surfaces of the first semiconductor layers 631 and 631', and the second side surface S2 may be composed of side surfaces of the first semiconductor layers 631 and 631', side surfaces of the active layers 632 and 632', and side surfaces of the second semiconductor layer.

[0082] Reference Fig. 6A and Figure 6B , the first semiconductor layers 631 and 631', the active layers 632 and 632', and the second semiconductor layer may be disposed over the base layer 137, and the active layers 632 and 632' include a plurality of first portions P1 having a first width W1 in a width direction and a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 less than the first width W1 in the width direction.

[0083] The second portion P2 may have a point-symmetrical shape based on the center C of the active layers 632 and 632'. For example, the second portion P2 may include a plurality of recesses formed concavely toward the center of the light emitting element ED3. The plurality of recesses face each other in the width direction and may be arranged in a point-symmetrical shape. For example, referring to Fig. 6A and Figure 6B One recess is disposed adjacent to the first electrode 134 on one side, and the other recess is disposed adjacent to the second electrode 135 on the other side opposite to the one side.

[0084] In this case, in the region outside the recess, the side surface of the second portion P2 may be disposed on the same plane as the side surface of the first portion P1. For example, in the region adjacent to the first electrode 134 and the second electrode 135 of the light emitting element ED3, the side surface of the second portion P2 may be disposed on the same plane as the side surface of the first portion P1. Therefore, the second side surface S2 of the second portion P2 disposed on one side of the light emitting element ED3 may be disposed on the same plane as the second side surface S2 of one of the plurality of first portions P1 disposed on both sides of the second portion P2, and the second side surface S2 of the second portion P2 disposed on the other side may be disposed on the same plane as the second side surface S2 of another of the plurality of first portions P1 disposed on both sides of the second portion P2.

[0085] In addition, refer to Fig. 6A , the active layer 632 may be arranged to be offset in one direction relative to the center of the light emitting element ED3. Fig. 6A As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be smaller than a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1.

[0086] In this case, the inclination angle of the second side surface S2 of the first portion P1 on one side may be greater than the inclination angle of the second side surface S2 of the first portion P1 on the other side, and the inclination angle of the second side surface S2 of the second portion P2 on one side may be the same as the inclination angle of the second side surface S2 of the second portion P2 on the other side.

[0087] Reference Figure 6B , the active layer 632' may be disposed at the center of the light emitting element ED3 in the width direction. That is, in this case, Fig. 6A and Figure 6B As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be the same as a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1 .

[0088] In addition, the inclination angles of the plurality of second side surfaces S2 disposed on the light emitting element ED3 may be constant. The inclination angles of the second side surfaces S2 of the first portion P1 may all be the same, and may also be the same as the inclination angle of the second side surface S2 of the second portion P2.

[0089] In the light emitting element ED3 according to another exemplary embodiment of the present disclosure, the active layers 632 and 632' include a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the second portion P2 may be less affected by a deviation in the manufacturing process of the light emitting element ED3. Therefore, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED3 may be reduced.

[0090] In addition, the light emitting element ED3 according to another exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2. Therefore, the light emitting area of ​​the light emitting element ED3 in the first portion P1 can be increased, and the second portion P2 and the first portion P1 can be alternately arranged to improve the color difference according to the viewing angle of the light emitting element ED3.

[0091] Fig. 7A and Figure 7B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure. FIG. 7A to FIG. 7B The light emitting element ED4 and Figures 1 to 3B The light emitting element ED1 of FIG. 1 is different only in the first semiconductor layers 731 and 731', the active layers 732 and 732', and the second semiconductor layer. However, other components are substantially the same, and thus a redundant description thereof will be omitted. Fig. 7A The light emitting element ED4 is shown when a manufacturing process error occurs. Figure 7BFIG. 4 shows a light emitting element ED4 manufactured under the condition that no process error occurs or the process deviation is substantially insignificant. Fig. 7A and Figure 7B In the figure, for convenience of illustration, only the first semiconductor layers 731 and 731 ′, the active layers 732 and 732 ′, the first electrode 134 and the second electrode 135 of the light emitting element ED4 are shown.

[0092] Reference Fig. 7A , the light emitting element ED4 includes a first semiconductor layer 731, an active layer 732, a second semiconductor layer, a first electrode 134 and a second electrode 135. Figure 7B The light emitting element ED4 includes a first semiconductor layer 731 ′, an active layer 732 ′, a second semiconductor layer, a first electrode 134 and a second electrode 135 .

[0093] The light emitting element ED4 may include a first plane F1 protruding out of the second semiconductor layer and the active layers 732 and 732'. Fig. 7A and Figure 7B The light emitting element ED4 includes a first side surface S1 extending downward from the first plane F1 and a second side surface S2 extending upward from the first plane F1. The first side surface S1 may be composed of side surfaces of the first semiconductor layers 731 and 731', and the second side surface S2 may be composed of side surfaces of the first semiconductor layers 731 and 731', side surfaces of the active layers 732 and 732', and side surfaces of the second semiconductor layer.

[0094] The first semiconductor layers 731 and 731', the active layers 732 and 732', and the second semiconductor layer may be disposed above the base layer 137, and the active layers 732 and 732' may include a plurality of first portions P1 having a first width W1 in a width direction, a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 smaller than the first width W1 in the width direction, and a third portion P3 disposed between the plurality of first portions P1 and having a third width W3 smaller than the second width W2 in the width direction.

[0095] In this case, if Fig. 7A and Figure 7B As shown, the third portion P3 may be disposed adjacent to the first electrode 134 of the first electrode 134 and the second electrode 135, but is not limited thereto and may be disposed adjacent to the second electrode 135 or the center of the light emitting element ED4. Fig. 7A and Figure 7B In the embodiment, the second portion P2 and the third portion P3 are shown to be alternately disposed between the plurality of first portions P1, but are not limited thereto, and the second portion P2 and the third portion P3 may be continuously disposed.

[0096] In addition, refer to Fig. 7A, the active layer 732 may be arranged to be offset in one direction relative to the center of the light emitting element ED4. Fig. 7A As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be smaller than a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1.

[0097] In this case, the inclination angle of the second side surface S2 of the first portion P1 on one side may be greater than the inclination angle of the second side surface S2 of the first portion P1 on the other side, and the inclination angle of the second side surface S2 of the second portion P2 on one side may be the same as the inclination angle of the second side surface S2 of the second portion P2 on the other side.

[0098] Reference Figure 7B , the active layer 732' may be disposed at the center of the light emitting element ED4 in the width direction. That is, in this case, Fig. 7A and Figure 7B As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be the same as a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1 .

[0099] In addition, the inclination angles of the plurality of second side surfaces S2 disposed on the light emitting element ED4 may be constant. The inclination angles of the second side surfaces S2 of the first portion P1 may all be the same, and may also be the same as the inclination angle of the second side surface S2 of the second portion P2.

[0100] In the light emitting element ED4 according to another exemplary embodiment of the present disclosure, the active layers 732 and 732' include a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the second portion P2 may be less affected by a deviation in the manufacturing process of the light emitting element ED4. Therefore, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED4 may be reduced.

[0101] The light emitting element ED4 according to another embodiment of the present disclosure includes a third portion P3, in which the active layers 732 and 732' have a width smaller than that of the second portion P2. Therefore, the third portion P3 may be less affected by the deviation in the manufacturing process of the light emitting element ED4. Therefore, the inclination angle of the MESA portion in the third portion P3 (that is, the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED4 may be reduced.

[0102] In addition, the light emitting element ED4 according to another exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2 and the third portion P3. Therefore, the light emitting area of ​​the light emitting element ED4 in the first portion P1 can be increased, and the second portion P2 and the third portion P3 can be alternately arranged with the first portion P1 to improve the color difference according to the viewing angle of the light emitting element ED4.

[0103] Fig. 8A and Figure 8B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure. FIG. 8A to FIG. 8B The light emitting element ED5 and FIG. 6A to FIG. 6B The light emitting element ED3 of FIG. 8 is different only in the first semiconductor layers 831 and 831', the active layers 832 and 832', and the second semiconductor layer. However, other components are substantially the same, and thus a redundant description thereof will be omitted. Fig. 8A The light emitting element ED5 is shown when a manufacturing process error occurs. Figure 8B FIG. 4 shows a light emitting element ED5 manufactured under the condition that no process error occurs or the process deviation is substantially insignificant. Fig. 8A and Figure 8B In the figure, for convenience of illustration, only the first semiconductor layers 831 and 831 ′, the active layers 832 and 832 ′, the first electrode 134 and the second electrode 135 of the light emitting element ED5 are shown.

[0104] Reference Fig. 8A , the light emitting element ED5 includes a first semiconductor layer 831, an active layer 832, a second semiconductor layer, a first electrode 134 and a second electrode 135. Figure 8B The light emitting element ED5 includes a first semiconductor layer 831 ′, an active layer 832 ′, a second semiconductor layer, a first electrode 134 and a second electrode 135 .

[0105] The light emitting element ED5 may include a first plane F1 protruding out of the second semiconductor layer and the active layers 832 and 832'. Fig. 8A and Figure 8B The light emitting element ED5 includes a first side surface S1 extending downward from the first plane F1 and a second side surface S2 extending upward from the first plane F1. The first side surface S1 may be composed of side surfaces of the first semiconductor layers 831 and 831', and the second side surface S2 may be composed of side surfaces of the first semiconductor layers 831 and 831', side surfaces of the active layers 832 and 832', and side surfaces of the second semiconductor layer.

[0106] The first semiconductor layers 831 and 831', the active layers 832 and 832', and the second semiconductor layer may be disposed over the base layer 137, and the active layers 832 and 832' include a plurality of first portions P1 having a first width W1 in a width direction and a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 less than the first width W1 in the width direction.

[0107] The second portion P2 may include a plurality of recesses formed concavely toward the center of the light emitting element ED5. The plurality of recesses of the second portion P2 may be arranged in a point-symmetrical shape relative to the center C of the second portion P2. In this case, the plurality of recesses may be arranged so that the width of the second portion P2 may gradually change. For example, Fig. 8A and Figure 8B As shown, the planar shape of the plurality of recesses of the second portion P2 may be triangular. For example, in a plan view, the active layer may have a "Z" shape or a sawtooth shape, but the embodiment is not limited thereto. The active layer may have a circular or curved shape, such as an "S" shape. Therefore, the width of the second portion P2 may gradually change in the portion where the plurality of recesses are provided, and may gradually change in the longitudinal direction.

[0108] In addition, refer to Fig. 8A , the active layer 832 may be arranged to be offset in one direction relative to the center of the light emitting element ED5. Fig. 8A As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be smaller than a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1.

[0109] In this case, the inclination angle of the second side surface S2 of the first portion P1 on one side may be greater than the inclination angle of the second side surface S2 of the first portion P1 on the other side, and the inclination angle of the second side surface S2 of the second portion P2 on one side may be the same as the inclination angle of the second side surface S2 of the second portion P2 on the other side.

[0110] Reference Figure 8B , the active layer 832' may be disposed at the center of the light emitting element ED5 in the width direction. That is, in this case, Fig. 8A and Figure 8B As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be the same as a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1 .

[0111] In addition, the inclination angles of the plurality of second side surfaces S2 disposed on the light emitting element ED5 may be constant. The inclination angles of the second side surfaces S2 of the first portion P1 may all be the same, and may also be the same as the inclination angle of the second side surface S2 of the second portion P2.

[0112] In the light emitting element ED5 according to another exemplary embodiment of the present disclosure, the active layers 832 and 832' include a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the second portion P2 may be less affected by deviations in the manufacturing process of the light emitting element ED5. Therefore, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED5 may be reduced.

[0113] In addition, the light emitting element ED5 according to another exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2. Therefore, the light emitting area of ​​the light emitting element ED5 in the first portion P1 can be increased, and the second portion P2 and the first portion P1 can be alternately arranged to improve the color difference according to the viewing angle of the light emitting element ED5.

[0114] In addition, in the light emitting element ED5 according to another exemplary embodiment of the present disclosure, the width of the second portion P2 may be gradually changed in the longitudinal direction. Therefore, the width may be suppressed from suddenly changing in the boundary region between the second portion P2 and the first portion P1, and thus the deviation of the inclination angle of the second side surface S2 may be reduced in the boundary region between the second portion P2 and the first portion P1.

[0115] Fig.9A and Fig. 9B is a schematic plan view of a light emitting element according to another exemplary embodiment of the present disclosure. Fig.9A and Fig. 9B The light emitting element ED6 and Figures 1 to 3B The light emitting element ED1 of FIG. 1 is different only in the first semiconductor layers 931 and 931', the active layers 932 and 932', and the second semiconductor layer. However, other components are substantially the same, and thus a redundant description thereof will be omitted. Fig.9A The light emitting element ED6 is shown when a manufacturing process error occurs. Fig. 9B FIG. 4 shows a light emitting element ED6 manufactured under the condition that no process error occurs or the process deviation is substantially insignificant. Fig.9A and Fig. 9B In the figure, for convenience of illustration, only the first semiconductor layers 931 and 931 ′, the active layers 932 and 932 ′, the first electrode 134 and the second electrode 135 of the light emitting element ED6 are shown.

[0116] Reference Fig.9A, the light emitting element ED6 includes a first semiconductor layer 931, an active layer 932, a second semiconductor layer, a first electrode 134 and a second electrode 135. Fig. 9B The light emitting element ED6 includes a first semiconductor layer 931 ′, an active layer 932 ′, a second semiconductor layer, a first electrode 134 and a second electrode 135 .

[0117] The light emitting element ED6 may include a first plane F1 protruding out of the second semiconductor layer and the active layers 932 and 932'. Fig.9A and Fig. 9B The light emitting element ED6 includes a first side surface S1 extending downward from the first plane F1 and a second side surface S2 extending upward from the first plane F1. The first side surface S1 may be composed of side surfaces of the first semiconductor layers 931 and 931', and the second side surface S2 may be composed of side surfaces of the first semiconductor layers 931 and 931', side surfaces of the active layers 932 and 932', and side surfaces of the second semiconductor layer.

[0118] The first semiconductor layers 931 and 931', the active layers 932 and 932', and the second semiconductor layer may be disposed over the base layer 137, and the active layers 932 and 832' may include a plurality of first portions P1 having a first width W1 in a width direction and a second portion P2 disposed between the plurality of first portions P1 and having a second width W2 less than the first width W1 in the width direction.

[0119] The width of the second portion P2 may vary according to the position. For example, the width of the second portion P2 may gradually increase or decrease in the longitudinal direction. Fig.9A and Fig. 9B , the second width W2 of the second portion P2 may be smallest at the center of the second portion P2, and the second width W2 may increase as the distance from the center of the second portion P2 increases. For example, the active layer may have a symmetrical "bow tie" shape. In addition, according to embodiments, the edges of the symmetrical shape may not be straight, for example, they may be curved, arched, or wavy, etc.

[0120] In addition, refer to Fig.9A , the active layer 932 may be arranged to be offset in one direction relative to the center of the light emitting element ED6. Fig.9A As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be smaller than a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1.

[0121] In this case, the inclination angle of the second side surface S2 of the first portion P1 on one side may be greater than the inclination angle of the second side surface S2 of the first portion P1 on the other side, and the inclination angle of the second side surface S2 of the second portion P2 on one side may be the same as the inclination angle of the second side surface S2 of the second portion P2 on the other side.

[0122] Reference Fig. 9B , the active layer 932' may be disposed at the center of the light emitting element ED6 in the width direction. That is, in this case, Fig. 9B As shown, a distance d1 between the second side surface S2 disposed on one side of the first portion P1 and the first side surface S1 may be the same as a distance d2 between the second side surface S2 disposed on the other side of the first portion P1 and the first side surface S1 .

[0123] In addition, the inclination angles of the plurality of second side surfaces S2 disposed on the light emitting element ED6 may be constant. The inclination angles of the second side surfaces S2 of the first portion P1 may all be the same, and may also be the same as the inclination angle of the second side surface S2 of the second portion P2.

[0124] In the light emitting element ED6 according to another exemplary embodiment of the present disclosure, the active layers 932 and 932' include a plurality of first portions P1 and a second portion P2 having a width smaller than the plurality of first portions P1. Therefore, the second portion P2 may be less affected by deviations in the manufacturing process of the light emitting element ED6. Therefore, the inclination angle of the MESA portion in the second portion P2 (i.e., the inclination angle of the second side surface S2) may be uniformly formed. Thus, the deviation of the viewing angle of the light emitting element ED6 may be reduced.

[0125] In addition, the light emitting element ED6 according to another exemplary embodiment of the present disclosure includes a plurality of first portions P1 having a width wider than the second portion P2. Therefore, the light emitting area of ​​the light emitting element ED6 in the first portion P1 can be increased, and the second portion P2 and the first portion P1 can be alternately arranged to improve the color difference according to the viewing angle of the light emitting element ED6.

[0126] In addition, in the light emitting element ED6 according to another exemplary embodiment of the present disclosure, the width of the second portion P2 may gradually change in the longitudinal direction. For example, in a plan view, the width of the active layer may be the widest at the opposite ends and gradually decrease to the minimum width at the center (for example, a "bow tie" shape or a "butterfly" shape). Fig.9A and Fig. 9BAn active layer having two relatively trapezoidal shapes in a plan view is shown, but the embodiment is not limited thereto. For example, in a plan view, the active layer may have two relatively triangular shapes, or a shape that is wider at opposite ends and narrower at the center (e.g., a pinched elliptical shape, a pinched racetrack shape, a pinched stadium shape). Therefore, the size of the width can be suppressed from suddenly changing in the boundary region between the second portion P2 and the first portion P1, and thus the size of the deviation of the inclination angle of the second side surface S2 can be reduced in the boundary region between the second portion P2 and the first portion P1.

[0127] Fig.10 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure. For convenience of explanation, Fig.10 Only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown among various components of the display device 1000 .

[0128] Reference Fig.10 , the display device 1000 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0129] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals provided from the timing controller TC. Fig.10 , one gate driver GD is illustrated as being spaced apart from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto.

[0130] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals provided from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0131] The timing controller TC sorts the image data input from the outside and supplies the sorted image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. The timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively.

[0132] The display panel PN is configured to display an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the figure, each of the plurality of sub-pixels SP may be connected to a high potential power line, a low potential power line, a reference line, etc.

[0133] A display area AA and a non-display area NA surrounding the display area AA may be defined in the display panel PN.

[0134] The display area AA is an area where an image is displayed on the display device 1000. A plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be provided in the display area AA. The plurality of sub-pixels SP are the minimum units constituting the display area AA, and n sub-pixels SP may form one pixel. A light-emitting element, a thin film transistor for driving the light-emitting element, and the like may be provided in each of the plurality of sub-pixels SP. The plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be a light-emitting diode (LED) or a micro light-emitting diode (micro-LED).

[0135] A plurality of lines that transmit various signals to the plurality of sub-pixels SP are disposed in the display region AA. For example, the plurality of lines may include a plurality of data lines DL that supply a data voltage to each of the plurality of sub-pixels SP, a plurality of scan lines SL that supply a scan signal to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL may extend in one direction in the display region AA and be connected to the plurality of sub-pixels SP, and the plurality of data lines DL may extend in a direction different from the one direction in the display region AA and be connected to the plurality of sub-pixels SP. In addition, a low potential power line, a high potential power line, and the like may be further disposed in the display region AA, but are not limited thereto.

[0136] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. Link lines and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, driver ICs such as a gate driver IC and a data driver IC, etc. may be disposed in the non-display area NA.

[0137] The non-display area NA may be located on the rear surface of the display panel PN (ie, on a surface without the sub-pixel SP), or may be omitted without being limited to that shown in the drawings.

[0138] In addition, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA using a gate-in-panel (GIP) method, and may be installed between a plurality of sub-pixels SP in the display area (AA) using a gate-in-active-area (GIA) method. For example, the data driver DD and the timing controller TC may be formed on a separate flexible film and a printed circuit board PCB, and the data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board PCB to pad electrodes formed in the non-display area NA of the display panel PN.

[0139] When the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, the area of ​​the non-display area NA where the gate driver GD and the pad electrodes are disposed needs to be a certain level or above, so the bezel may increase.

[0140] On the contrary, when the gate driver GD is installed in the display area AA using the GIA method and the flexible film and the printed circuit board are bonded to the rear surface of the display panel PN by forming a side line for connecting the signal line on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN, the non-display area NA in front of the display panel PN can be reduced to a minimum. In other words, when the gate driver GD, the data driver DD and the timing controller TC are connected to the display panel PN in the above manner, a zero frame with substantially no frame can be achieved.

[0141] First, refer to Fig.11 , the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components disposed above the display device 1000, and may be an insulating substrate. A plurality of pixels may be formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass, resin, or the like. In addition, the first substrate 110 may be formed of a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a plastic material having flexibility.

[0142] A plurality of sub-pixels SP may be disposed on the first substrate 110 to form a plurality of rows and columns. Each of the plurality of sub-pixels SP includes a light emitting element ED and a pixel circuit, and thus, may independently emit light.

[0143] A plurality of lines for transmitting various signals to a plurality of sub-pixels SP are provided in the first substrate 110. For example, a plurality of data lines DL extending in the column direction, a plurality of high potential power lines VL1, and a plurality of low potential power lines may be provided on the first substrate 110. For example, a plurality of light emission control signal lines extending in the row direction, a plurality of auxiliary high potential power lines, a plurality of auxiliary low potential power lines, and a plurality of scan lines may be provided on the first substrate 110. In addition, the high potential power line VL1 extending in the column direction may be electrically connected to the auxiliary high potential power line extending in the row direction through a contact hole. In this case, the light emission control signal line may transmit a light emission control signal to the pixel circuits of the plurality of sub-pixels SP, thereby controlling the light emission timing of each of the plurality of sub-pixels SP.

[0144] A pixel circuit for driving the light emitting element ED is provided in each of the plurality of sub-pixels SP on the first substrate 110. The pixel circuit may include a plurality of thin film transistors and a plurality of capacitors. Fig.11 In the figure, for convenience of description, among the components of the pixel circuit, only the driving transistor DT, the first capacitor C1 and the second capacitor C2 are shown. However, the pixel circuit may further include a switching transistor, a sensing transistor, a light emission control transistor, etc., but is not limited thereto.

[0145] Fig.11 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure.

[0146] Reference Fig.11 A light shielding layer BSM, a driving transistor DT, a first capacitor C1, a second capacitor C2, a reflective plate RF, a plurality of light emitting elements ED, a first connection electrode CE1, a second connection electrode CE2, a dam BB, a protective layer 117, an encapsulation layer 160, an adhesive portion 118, an optical film MF, and an insulating layer including a plurality of inorganic insulating layers and a plurality of organic insulating layers may be disposed on the first substrate 110.

[0147] Among the insulating layers disposed on the first substrate 110 , the plurality of inorganic insulating layers include a buffer layer 111 , a gate insulating layer 112 , a first interlayer insulating layer 113 , a second interlayer insulating layer 114 , a first passivation layer 115 a , and a second passivation layer 115 b .

[0148] In addition, among the insulating layers disposed on the first substrate 110 , the plurality of organic insulating layers may include a first planarization layer 116 a , an adhesive layer AD, a second planarization layer 116 b , and a third planarization layer 116 c .

[0149] Reference Fig.11, a light shielding layer BSM is disposed on the first substrate 110. The light shielding layer BSM can minimize leakage current by blocking light incident on the active layer ACT of the plurality of transistors. For example, the light shielding layer BSM may be disposed under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. When light is irradiated to the active layer ACT, leakage current may occur to reduce the reliability of the transistor. Therefore, the light shielding layer BSM that blocks light may be disposed on the first substrate 110 to improve the reliability of the driving transistor DT. The light shielding layer BSM may be formed of an opaque conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0150] The buffer layer 111 is disposed on the light shielding layer BSM. The buffer layer 111 is an inorganic insulating layer that can reduce the penetration of moisture or impurities through the first substrate 110. For example, the buffer layer 111 may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted according to the type of the first substrate 110 or the type of the thin film transistor, but is not limited thereto.

[0151] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111 .

[0152] In addition, despite Fig.11 Although not shown, an additional buffer layer may be disposed between the first substrate 110 and the light shielding layer BSM. The additional buffer layer is an inorganic insulating layer that can reduce the penetration of moisture or impurities through the first substrate 110 in the same manner as the above-mentioned buffer layer 111, and may be configured by a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or a double layer thereof, but is not limited thereto.

[0153] First, the active layer ACT of the driving transistor DT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. In addition, although not shown in the figure, in addition to the driving transistor DT, other transistors such as a switching transistor, a sensing transistor, and a light emitting control transistor may be additionally provided, and the active layers of these transistors may also be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto. In addition, the active layers of the transistors included in the pixel circuit (e.g., the driving transistor DT, the switching transistor, the sensing transistor, and the light emitting control transistor) may be formed of the same material or may be formed of different materials.

[0154] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an inorganic insulating layer for electrically insulating the active layer ACT and the gate electrode GE, and may be configured of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or a double layer thereof, but is not limited thereto.

[0155] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0156] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114 to connect the source electrode SE and the drain electrode DE to the active layer ACT, respectively. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be an inorganic insulating layer to protect the underlying components, and may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0157] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE is connected to the second capacitor C2 and the first electrode 134 of the light emitting element ED, and the drain electrode DE is connected to other components of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0158] A plurality of high potential power lines VL1 are disposed on the second interlayer insulating layer 114. The plurality of high potential power lines VL1 may transmit a high potential power voltage to the light emitting element ED of each of the plurality of sub-pixels SP. The plurality of high potential power lines VL1 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0159] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1th capacitor electrode C1a and a 1-2th capacitor electrode C1b.

[0160] First, the 1-1th capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1th capacitor electrode C1a may be integrated with the gate electrode GE of the driving transistor DT.

[0161] The 1-2nd capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The 1-2nd capacitor electrode C1b is disposed to overlap with the 1-1st capacitor electrode C1a with the first interlayer insulating layer 113 interposed therebetween.

[0162] Therefore, the first capacitor C1 may be connected to the gate electrode GE of the driving transistor DT, and may maintain the voltage of the gate electrode GE of the driving transistor DT for a certain period of time.

[0163] Next, the second capacitor C2 is disposed on the first substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The second capacitor C2 includes a 2-1st capacitor electrode C2a as a lower capacitor electrode, a 2-2nd capacitor electrode C2b as a middle capacitor electrode, and a 2-3rd capacitor electrode C2c as an upper capacitor electrode.

[0164] The 2-1st capacitor electrode C2a is disposed on the first substrate 110. The 2-1st capacitor electrode C2a may be disposed on the same layer as the light shielding layer BSM, and may be formed of the same material.

[0165] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b may be disposed on the same layer as the gate electrode GE, and may be formed of the same material.

[0166] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3rd capacitor electrode C2c may be composed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3rd capacitor electrode C2c may be formed of the same material as the 1-2nd capacitor electrode C1b on the same layer. The first layer C2c1 may be disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113 interposed therebetween.

[0167] The second layer C2c2 of the 2-3rd capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole in the second interlayer insulating layer 114.

[0168] Therefore, the second capacitor C2 is electrically connected between the source electrode SE of the driving transistor DT and the light emitting element ED, so the capacitance inherent in the light emitting element ED may be increased, and light with higher brightness may be emitted from the light emitting element ED.

[0169] The first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an inorganic insulating layer to protect components thereunder and may be formed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0170] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be configured by a single layer or a double layer and may be formed of, for example, a benzocyclobutene or acrylic-based organic insulating layer.

[0171] Reference Fig.11 , a plurality of reflective plates RF are disposed on the first planarization layer 116a. The reflective plate RF is configured to reflect light emitted from a plurality of light emitting elements ED to an upper portion of the first substrate 110, and may have a shape corresponding to each of a plurality of sub-pixels SP. One reflective plate RF may be configured to cover most of the area of ​​one sub-pixel SP. The reflective plate RF may reflect light emitted from the light emitting element ED, and at the same time, may also be used as an electrode to electrically connect the light emitting element ED to the pixel circuit. Therefore, considering the light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may be configured by an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof together with a transparent conductive layer such as indium tin oxide (ITO). However, the structure of the reflective plate RF is not limited thereto.

[0172] The reflection plate RF may include a plurality of first reflection plates RFa and a plurality of second reflection plates RFb disposed in each of the plurality of sub-pixels SP.

[0173] The plurality of first reflective plates RFa may reflect light emitted from the light emitting element ED to the outside of the display device 1000. The plurality of first reflective plates RFa may be disposed in each driving transistor DT in each of the plurality of subpixels SP and may be electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1.

[0174] A plurality of second reflection plates RFb may be disposed to overlap the light emitting element ED. The plurality of second reflection plates RFb may be disposed on each driving transistor DT in each of the plurality of sub-pixels SP and connected to the high potential power line VL1 through the second contact hole CH2. Therefore, the plurality of second reflection plates RFb may reflect light emitted from the light emitting element ED to the outside of the display device 1000 while supplying a high potential power supply voltage to the light emitting element ED.

[0175] Furthermore, all of the plurality of light emitting elements ED may be individually connected to the high potential power line VL1 without the reflection plate RF, but is not limited thereto.

[0176] Reference Fig.11The second passivation layer 115b is disposed on the plurality of reflection plates RF. The second passivation layer 115b is an inorganic insulating layer to protect components below the second passivation layer 115b, and may be configured of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or a double layer thereof, but is not limited thereto.

[0177] The adhesive layer AD is disposed on the second passivation layer 115b. The adhesive layer AD may be formed on the front surface of the first substrate 110 and fix the light emitting element ED disposed on the adhesive layer AD. The adhesive layer AD may be configured by an organic insulating layer. The adhesive layer AD may be formed of a photocurable adhesive material that can be cured by light. For example, the adhesive layer AD may be formed of an acrylic-based material including a photoresist, but is not limited thereto.

[0178] A plurality of light emitting elements ED are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. The light emitting element ED is an element that emits light by current, and may include a first light emitting element that emits red light, a second light emitting element that emits green light, and a third light emitting element that emits blue light, and various colors of light including white are realized by a combination thereof. For example, the light emitting element ED may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0179] The plurality of light emitting elements ED include a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a first electrode 134, and a second electrode 135. Hereinafter, the plurality of light emitting elements ED will be described under the assumption that they have a lateral structure, but the type of the plurality of light emitting elements ED is not limited thereto. Fig.11 In the invention, a plurality of light emitting elements ED are described as applied Figures 1 to 3B The light emitting element ED described in, but not limited to, may be applied Figures 4 to 9B All light emitting elements according to various exemplary embodiments of the present disclosure described in Figures 1 to 3B The plurality of light emitting elements ED are described in detail, so a redundant description thereof will be omitted.

[0180] Next, an encapsulation film 136 is provided surrounding the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation film 136 is formed of an insulating material and may protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. Contact holes may be formed in the encapsulation film 136 to expose the first electrode 134 and the second electrode 135, so that the first connection electrode CE1 and the second connection electrode CE2 may be electrically connected to the first electrode 134 and the second electrode 135.

[0181] In addition, considering the process margin, the encapsulation film 136 may surround only a portion of the light emitting element ED. The encapsulation film 136 may cover all side surfaces of the second semiconductor layer 133 and the active layer 132, and may cover a portion of the side surface of the first semiconductor layer 131. For example, the encapsulation film 136 may cover the side surface of the light emitting element ED provided with the first electrode 134, and expose the side surface of the light emitting element ED provided with the second electrode 135, but is not limited thereto.

[0182] In addition, a portion of the side surface of the first semiconductor layer 131 may be exposed from the encapsulation film 136. The light emitting element ED manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, during the process of separating the light emitting element ED from the wafer, a portion of the encapsulation film 136 may be torn. For example, during the process of separating the light emitting element ED and the wafer, a portion of the encapsulation film 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting element ED is torn off, so a portion of the lower side surface of the first semiconductor layer 131 may be exposed to the outside. However, even if the lower portion of the light emitting element ED is exposed from the encapsulation film 136, a second planarization layer 116b and a third planarization layer 116c covering the side surface of the first semiconductor layer 131 may be formed, and then the first connection electrode CE1 and the second connection electrode CE2 may be formed. Thus, short circuit defects may be reduced.

[0183] Next, a second planarization layer 116 b and a third planarization layer 116 c are provided on the adhesive layer AD and the light emitting element ED.

[0184] The second planarization layer 116b may overlap a portion of the side surface portion of the plurality of light emitting elements ED to fix and protect the plurality of light emitting elements ED. The second planarization layer 116b may be configured by a single layer or a double layer, and may be formed of, for example, a benzocyclobutene or acrylic-based organic insulating layer. The second planarization layer 116b may be formed using a halftone mask. Therefore, the second planarization layer 116b may be formed to have a step.

[0185] Specifically, in the second planarization layer 116b, a portion disposed relatively adjacent to the light emitting element ED may be formed to have a relatively thin thickness, and a portion disposed relatively far from the light emitting element ED may be formed to have a relatively thick thickness. The portion of the second planarization layer 116b disposed adjacent to the light emitting element ED may be disposed to surround the light emitting element ED and to contact the side surface of the light emitting element ED. Therefore, in the process of separating the light emitting element ED from the wafer and transferring the light emitting element ED to the display panel PN, the torn portion of the encapsulation film 136 protecting the side surface of the first semiconductor layer 131 of the light emitting element ED may be covered by the second planarization layer 116b. As a result, future contact and short circuit defects between the first connection electrode CE1 and the second connection electrode CE2 and the first semiconductor layer 131 may be suppressed.

[0186] The third planarization layer 116c may be formed to cover the upper portion of the second planarization layer 116b and the light emitting element ED, and may be formed with a contact hole exposing the first electrode 134 and the second electrode 135 of the light emitting element ED. The first electrode 134 and the second electrode 135 of the light emitting element ED may be exposed from the third planarization layer 116c, and the third planarization layer 116c may be partially disposed in a region between the first electrode 134 and the second electrode 135, so that a short circuit defect may be reduced. The second planarization layer 116b and the third planarization layer 116c may be configured by a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic insulating material.

[0187] In addition, the third planarization layer 116c may cover the light emitting element ED and the region adjacent to the light emitting element ED. The third planarization layer 116c may be disposed in the region of the sub-pixel SP surrounded by the bank BB, and may be disposed in an island shape. Therefore, the bank BB may be disposed on a portion of the top surface of the second planarization layer 116b. For example, the bank BB may be disposed on the third planarization layer 116c to overlap a portion of the third planarization layer 116c.

[0188] The first and second link electrodes CE1 and CE2 are disposed on the third planarization layer 116c.

[0189] The first connection electrode CE1 is an electrode that electrically connects the first electrode 134 of the light emitting element ED and the driving transistor DT. The first connection electrode CE1 may be electrically connected to the first electrode 134 exposed from the third planarization layer 116c, and may be connected to the first reflective plate RFa through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. Therefore, the first electrode 134 and the source electrode SE of the driving transistor DT may be electrically connected through the first connection electrode CE1 and the first reflective plate RFa.

[0190] The second connection electrode CE2 is an electrode that electrically connects the second electrode 135 of the light emitting element ED and the high potential power line VL1. The second connection electrode CE2 may be electrically connected to the second reflective plate RFb through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b while being electrically connected to the second electrode 135 exposed from the third planarization layer 116c. Therefore, the second electrode 135 and the high potential power line VL1 may be electrically connected through the second connection electrode CE2.

[0191] The first and second connection electrodes CE1 and CE2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0192] In addition, in the drawings, the first electrode 134, the first connection electrode CE1, the reflection plate RF and the first reflection plate RFa are shown as being electrically connected to the source electrode SE of the driving transistor DT, but the first electrode 134, the first connection electrode CE1, the reflection plate RF and the first reflection plate RFa may be connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0193] Reference Fig.11 , the embankment BB is disposed on the second planarization layer 116b exposed from the third planarization layer 116c and the first connection electrode CE1 and the second connection electrode CE2. The embankment BB may be disposed at a specific distance to be spaced apart from the light emitting element ED, and may overlap with at least a portion of the reflective plate RF. For example, the embankment BB may cover a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b. In addition, for example, the embankment BB may be disposed on the second planarization layer 116b at a specific distance from the light emitting element ED.

[0194] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and is formed of, for example, a black resin, but is not limited thereto.

[0195] In addition, the thickness of the portion of the dam BB formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b and covering a portion of the first connection electrode CE1 and the second connection electrode CE2 and the thickness of the portion disposed on the second planarization layer 116b may be different. Specifically, in the case of the portion of the dam BB covering a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b, the contact hole is formed from the second passivation layer 115b to the third planarization layer 116c, and thus the dam BB may be disposed below the light emitting element ED, that is, at a position lower than the light emitting element ED. Therefore, the thickness of the portion of the dam BB formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b and covering a portion of the first connection electrode CE1 and the second connection electrode CE2 may be thicker than the thickness of the portion of the dam BB disposed on the second planarization layer 116b.

[0196] In addition, the present disclosure is not limited thereto, and the bank BB is disposed outside the contact holes of the third and second planarization layers 116 c and 116 b to cover portions of the first and second connection electrodes CE1 and CE2 .

[0197] The protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 117 is a layer that protects components below the protective layer 117. The protective layer 117 may be configured by a single layer or a double layer, and may be formed of, for example, benzocyclobutene, light-transmitting epoxy resin, photoresist, or an acrylic-based organic material, but is not limited thereto.

[0198] The encapsulation layer 160 is disposed over the protective layer 117. The encapsulation layer 160 is a layer for minimizing moisture penetration from outside the display device 1000 and encapsulating components surrounded by the encapsulation layer 160. The encapsulation layer 160 may be disposed to surround the front, side, and rear surfaces of the first substrate 110.

[0199] The encapsulation layer 160 may be formed of a material having low moisture permeability and high insulation property. For example, the encapsulation layer 160 may be formed of a material including polyparaxylene, but is not limited thereto.

[0200] Reference Fig.11 , an optical film MF covering an upper portion of the encapsulation layer 160 is disposed in the entire upper region of the first substrate 110. The optical film MF may be disposed on the sealing member 150 and the protective layer 117. The optical film MF may be a functional film that realizes a higher quality image while protecting the display device 1000. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, a polarizer, etc., but is not limited thereto.

[0201] The adhesive portion 118 may be disposed between the protective layer 117 and the optical film MF above the first substrate 110. The adhesive portion 118 may be formed on the front surface of the first substrate 110 to bond the protective layer 117 and the optical film MF. The adhesive portion 118 may be formed of a photocurable adhesive material that can be cured by light. For example, the adhesive portion 118 may be formed of an acrylic-based material including a photoresist, but is not limited thereto.

[0202] In addition, in the present disclosure, the adhesive portion 118 and the optical film MF are defined as separate components, but not limited thereto, the optical film MF and the adhesive portion 118 may be defined as one component.

[0203] Exemplary embodiments of the present disclosure may also be described as follows:

[0204] According to one aspect of the present disclosure, a light-emitting element is provided, which includes a first semiconductor layer, a first electrode and an active layer disposed on the first semiconductor layer to be spaced apart from each other, a second semiconductor layer located on the active layer, and a second electrode located on the second semiconductor layer, wherein the active layer includes a plurality of first portions having a first width in a width direction and a second portion disposed between the plurality of first portions and having a second width smaller than the first width in the width direction.

[0205] Corner portions of the first semiconductor layer, the active layer, and the second semiconductor layer may have a rounded shape.

[0206] The first semiconductor layer may have a constant width in a width direction except for a corner portion.

[0207] The light emitting element may further include a first plane provided with a first electrode, a first side surface extending downward from the first plane, and a second side surface extending upward from the first plane. The distance between the first side surfaces facing the width direction may be constant. The distance between the second side surfaces facing the width direction in the plurality of first portions may be longer than the distance between the second side surfaces facing the width direction in the second portions.

[0208] At least a portion of the second side surface of the second portion may be disposed inside the second side surface of the first portion.

[0209] The shortest distance between the first side surface and the second side surface on one side and the shortest distance between the first side surface and the second side surface on the other side in the width direction may be the same.

[0210] The inclination angle of the second side surface may be constant.

[0211] The shortest distance between the first side surface and the second side surface on one side in the width direction may be smaller than the shortest distance between the first side surface and the second side surface on the other side.

[0212] An inclination angle of the second side surface of the first portion on one side may be greater than an inclination angle of the second side surface of the first portion on the other side.

[0213] The inclination angle of the second side surface of the second portion on one side may be the same as the inclination angle of the second side surface of the second portion on the other side.

[0214] The light emitting element may further include a substrate including a first region and a second region, wherein the second portion is plural in number, and the plurality of first portions and the plurality of second portions may be alternately disposed.

[0215] The second portion may have a point-symmetrical shape with respect to the center of the active layer.

[0216] The second side surface of the second part disposed on one side may be disposed on the same plane as the second side surface of one of the plurality of first parts disposed on both sides of the second part. The second side surface of the second part disposed on the other side may be disposed on the same plane as the second side surface of another of the plurality of first parts disposed on both sides of the second part.

[0217] The active layer may be disposed between the plurality of first portions. The active layer may further include a third portion having a third width smaller than the second width in a width direction.

[0218] The second width may increase as the distance from the center of the second portion increases.

[0219] The light emitting element may further include an encapsulation film covering the top surface and side surfaces of the light emitting element. The encapsulation film may cover all side surfaces of the second semiconductor layer and the active layer, and cover a portion of the side surface of the first semiconductor layer.

[0220] According to another aspect of the present disclosure, a display device is provided. The display device includes a substrate and a plurality of light-emitting elements disposed on the substrate. Each of the plurality of light-emitting elements includes a first electrode and an active layer disposed on a first semiconductor layer, a second semiconductor layer located on the active layer, and a second electrode disposed on the second semiconductor layer to be spaced apart from the first electrode along a longitudinal direction. The active layer includes a first portion having a first width and a second portion having the same width as the first portion and a second width less than the first width.

[0221] The light emitting element may include a first side surface disposed below the first electrode and a second side surface spaced apart from the first side surface and disposed above the first electrode. The second side surface of the first portion may include at least one surface having a different inclination angle, and the second side surface of the second portion may be formed by surfaces having the same inclination angle.

[0222] The active layer may be disposed to be offset toward one side with respect to a width direction of the light emitting element.

[0223] Although the exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be specifically implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0224] CROSS-REFERENCE TO RELATED APPLICATIONS

[0225] This application claims the priority of Korean Patent Application No. 10-2023-0115702 filed on August 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A light-emitting element, comprising: a first semiconductor layer; a first electrode and an active layer, the first electrode and the active layer being disposed on the first semiconductor layer to be spaced apart from each other; a second semiconductor layer, wherein the second semiconductor layer is located on the active layer; as well as a second electrode, the second electrode being located on the second semiconductor layer, Wherein, the active layer comprises: a plurality of first portions having a first width in a width direction; and A second portion is disposed between at least two of the plurality of first portions and has a second width in the width direction that is smaller than the first width.

2. The light-emitting element according to claim 1, wherein A corner portion of the first semiconductor layer, a corner portion of the active layer, and a corner portion of the second semiconductor layer have a round shape, Wherein, the first semiconductor layer has a constant width in the width direction except for the corner portion.

3. The light-emitting element according to claim 2, further comprising: a first plane, on which the first electrode is disposed; a first side surface extending in a downward direction from the first plane; as well as a second side surface extending in an upward direction from the first plane, wherein a distance between the first side surfaces facing each other in the width direction is constant, wherein a distance between the second side surfaces facing each other in the width direction in the plurality of first portions is longer than a distance between the second side surfaces facing each other in the width direction in the second portion.

4. The light-emitting element according to claim 3, wherein At least a portion of the second side surface of the second portion is disposed inside the second side surface of the first portion.

5. The light-emitting element according to claim 3, wherein In the width direction, the shortest distance between the first side surface and the second side surface on one side of the light emitting element is equal to or substantially equal to the shortest distance between the first side surface and the second side surface on the other side of the light emitting element.

6. The light emitting element according to claim 3, wherein In the width direction, a shortest distance between the first side surface and the second side surface on one side of the light emitting element is smaller than a shortest distance between the first side surface and the second side surface on the other side of the light emitting element.

7. The light-emitting element according to claim 6, wherein An inclination angle of the second side surface of at least one of the plurality of first portions on the one side is greater than an inclination angle of the second side surface of at least one of the plurality of first portions on the other side.

8. The light emitting element according to claim 6, wherein An inclination angle of the second side surface of the second portion on the one side is equal to or substantially equal to an inclination angle of the second side surface of the second portion on the other side.

9. The light-emitting element according to claim 6, in, The second portion is one of a plurality of second portions, and The plurality of first portions and the plurality of second portions are alternately arranged.

10. The light emitting element according to claim 6, wherein The second portion has a point-symmetrical shape with respect to a center of the active layer.

11. The light emitting element according to claim 6, wherein The second side surface of the second portion disposed on one side of the light emitting element is disposed on the same plane as the second side surface of one of the plurality of first portions, and The second side surface of the second portion disposed on the other side of the light emitting element is disposed on the same plane as the second side surface of another one of the plurality of first portions.

12. The light emitting element according to claim 6, wherein The active layer includes a third portion disposed between the plurality of first portions, and further includes the third portion having a third width smaller than the second width in the width direction.

13. The light emitting element according to claim 6, wherein The second width increases as the distance from the center of the second portion increases.

14. The light-emitting element according to claim 1, further comprising: a packaging film covering the top surface and the side surfaces of the light emitting element, The encapsulation film covers all side surfaces of the second semiconductor layer and all side surfaces of the active layer, and covers a portion of the side surfaces of the first semiconductor layer.

15. A display device, comprising: substrate; as well as a plurality of light emitting elements, wherein the plurality of light emitting elements are arranged on the substrate, Wherein, each of the plurality of light emitting elements comprises: a first semiconductor layer; A first electrode and an active layer, wherein the first electrode and the active layer are disposed on the first semiconductor layer; a second semiconductor layer, the second semiconductor layer being located on the active layer; and a second electrode, the second electrode being disposed on the second semiconductor layer and being spaced apart from the first electrode; Wherein, the active layer comprises: a first portion having a first width; and A second portion having a width in a longitudinal direction that is the same as a width of the first portion and having a second width in a width direction that is smaller than the first width.

16. The display device according to claim 15, wherein: Each of the plurality of light emitting elements further comprises: a first side surface, the first side surface being disposed below the first electrode; and a second side surface, the second side surface being spaced apart from the first side surface and disposed above the first electrode, wherein the second side surface of the first portion includes at least one surface having a different inclination angle, and Wherein, the second side surfaces of the second parts have the same inclination angle.

17. The display device according to claim 16, wherein: The active layer is disposed closer to the first side of the light emitting element.

18. A light emitting element, comprising: a first semiconductor layer; a first electrode, the first electrode being disposed on the first semiconductor layer; an active layer, the active layer being disposed on the first semiconductor layer, and the active layer being spaced apart from the first electrode; a second semiconductor layer, wherein the second semiconductor layer is disposed on the active layer; as well as a second electrode, the second electrode being disposed on the second semiconductor layer, A first portion of the active layer between the first electrode and the second electrode is wider than a second portion of the active layer between the first electrode and the second electrode.

19. The light emitting element according to claim 18, wherein The width of the active layer varies in a region between the first electrode and the second electrode.

20. The light emitting element according to claim 18, wherein A portion of the first semiconductor layer, the second semiconductor layer, and the active layer form a stacked structure having a mesa shape, and wherein opposite sides of the table shape have the same inclination angle, or Wherein, the opposite sides of the table shape have different inclination angles.

21. The light emitting element according to claim 20, wherein The mesa shape is disposed closer to a first side of the light emitting element than to a second side of the light emitting element.

22. The light emitting element according to claim 18, wherein A third portion of the active layer between the first electrode and the second electrode has a third width, and the third width is smaller than the first width of the first portion and the second width of the second portion.

23. The light emitting element according to claim 18, wherein The active layer includes a first notch portion at a first side of the active layer and a second notch portion at a second side of the active layer, the second side being opposite to the first side, and Wherein, in a plan view, the first notch portion and the second notch portion have point symmetry about a center of the active layer.

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