Display device

Abstract

There is provided a display device including: a pixel electrode on a substrate; a bank layer on the substrate and the pixel electrode and dividing a light emitting region and a non-light emitting region; a light emitting element on the pixel electrode and including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a first via layer on the pixel electrode and around at least a portion of a side surface of the light emitting element; a common electrode on the first via layer, a side surface of the light emitting element protruding from the first via layer, and a top surface of the light emitting element; a first insulating layer on the common electrode; a partition wall unit on the first insulating layer and overlapping the bank; a second insulating layer on the partition wall unit; a reflective layer on the first insulating layer around a side surface of the partition wall unit and a side surface of the light emitting element and between the partition wall unit and the light emitting element; a second via layer between the partition wall units; and a wavelength conversion layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0112629 filed in the Korean Intellectual Property Office on August 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] As multimedia develops, display devices are becoming more and more important. In response to this, various types of display devices such as organic light emitting diode (OLED) displays and liquid crystal displays (LCD) are being used.

[0004] The display device for displaying an image includes a display panel such as a light-emitting display panel or a liquid crystal display panel. Among them, the light-emitting display panel may include a light-emitting element such as a light-emitting diode (LED). For example, the LED includes an organic light-emitting diode (OLED) using an organic material as a light-emitting material, an inorganic light-emitting diode using an inorganic material as a light-emitting material, and the like. Summary of the invention

[0005] Aspects and features of embodiments of the present disclosure provide a display device that can improve light emitting efficiency of a light emitting element.

[0006] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments, a display device includes: a pixel electrode on a substrate; a levee layer on the substrate and the pixel electrode and dividing a light-emitting area and a non-light-emitting area; a light-emitting element on the pixel electrode and including a first semiconductor layer, a second semiconductor layer and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first via layer on the pixel electrode and around at least a portion of a side surface of the light-emitting element; a common electrode on the first via layer, a side surface of the light-emitting element protruding from the first via layer, and a top surface of the light-emitting element; a first insulating layer on the common electrode; a partition wall unit on the first insulating layer and overlapped with the levee layer; a second insulating layer on the partition wall unit; a reflective layer on the second insulating layer around a side surface of the partition wall unit and on the first insulating layer around a side surface of the light-emitting element, and on the first insulating layer between the partition wall unit and the light-emitting element; a second via layer between the partition wall units and having an opening exposing the first insulating layer on the light-emitting element; and a wavelength conversion layer on the second via layer.

[0008] The display device further includes an anti-degradation layer located between the second via layer and the wavelength conversion layer and including a base resin and a scatterer.

[0009] The partition wall unit includes a first partition wall on the first insulating layer and having a first width and a second partition wall on the first partition wall and having a second width, wherein the first width is greater than the second width.

[0010] The reflective layer includes a first reflective layer around a side of the first partition wall, a second reflective layer around a side of the second partition wall, a third reflective layer around a portion of a side of the light emitting element, and a fourth reflective layer located between the first reflective layer and the third reflective layer and between the second via layer and the first insulating layer.

[0011] The third reflective layer contacts the first insulating layer and has a height equal to that of the second via layer.

[0012] The third reflective layer is located on the first insulating layer around at least a portion of a side surface of the second semiconductor layer of the light emitting element.

[0013] The first via layer covers the bank layer and a portion of the pixel electrode on which the light emitting element is not disposed, wherein the second via layer covers the fourth reflective layer between the partition wall units and around the third reflective layer.

[0014] The light emitting element further includes an element insulating layer around the first semiconductor layer, the active layer and the second semiconductor layer, and a connecting electrode located between the first semiconductor layer and the pixel electrode.

[0015] The display device further includes an element reflective layer spaced apart from the common electrode and located around at least a portion of a side surface of the light emitting element on the element insulating layer.

[0016] The display device further includes a capping layer, a coating layer, and a color filter layer sequentially disposed on the wavelength conversion layer and the partition wall unit.

[0017] The display device further includes a touch sensing unit located between the overcoat layer and the color filter layer.

[0018] According to one or more embodiments, a display device includes: a first electrode and a second electrode on a substrate; a levee layer on the substrate, the first electrode and the second electrode and dividing a light-emitting area and a non-light-emitting area; a light-emitting element, including a first contact electrode, a second contact electrode, a first semiconductor layer on the first contact electrode, an active layer, and a second semiconductor layer on the second contact electrode and the active layer; a first via layer on the first electrode and the second electrode and around at least a portion of a side surface of the light-emitting element; a first insulating layer on the first via layer, a side surface of the light-emitting element protruding from the first via layer, and a top surface of the light-emitting element; a partition wall unit on the first insulating layer and overlapped with the levee layer; a second insulating layer on the partition wall unit; a reflective layer on the second insulating layer around the side surface of the partition wall unit and on the first insulating layer around the side surface of the light-emitting element, and on the first insulating layer between the partition wall unit and the light-emitting element; a second via layer between the partition wall units; and a wavelength conversion layer on the second via layer.

[0019] The display device further includes an anti-degradation layer located between the second via layer and the wavelength conversion layer and including a base resin and a scatterer.

[0020] The partition wall unit includes a first partition wall on the first insulating layer and having a first width and a second partition wall on the first partition wall and having a second width, wherein the first width is greater than the second width.

[0021] The reflective layer includes a first reflective layer around a side of the first partition wall, a second reflective layer around a side of the second partition wall, a third reflective layer around a portion of a side of the light emitting element, and a fourth reflective layer located between the first reflective layer and the third reflective layer and between the second via layer and the first insulating layer.

[0022] The third reflective layer contacts the first insulating layer and has a height equal to that of the second via layer.

[0023] The third reflective layer is located on the first insulating layer around at least a portion of a side surface of the second semiconductor layer of the light emitting element.

[0024] The first via layer covers the bank layer and portions of the first electrode and the second electrode on which the light emitting element is not disposed, wherein the second via layer covers the fourth reflective layer between the partition wall units and around the third reflective layer.

[0025] The height of the first partition wall is greater than or equal to the height of the second partition wall.

[0026] The display device further includes a capping layer, a coating layer, and a color filter layer sequentially disposed on the wavelength conversion layer and the partition wall unit.

[0027] The display device according to one or more embodiments of the present disclosure may improve the light emitting efficiency of the light emitting element by surrounding the inner wall of the wavelength conversion layer with the reflective layer.

[0028] However, the effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and various other effects, aspects, and features are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0030] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments.

[0031] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0032] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0033] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0034] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted.

[0035] Figure 8 It shows reference Figure 6 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described.

[0036] Fig. 9 is a plan view illustrating a light emitting region and a region of a reflective layer according to one or more embodiments.

[0037] Fig.10 is a plan view illustrating a light emitting region and a region of a reflective layer according to one or more embodiments.

[0038] Fig.11 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0039] Fig.12 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0040] Fig.13 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0041] Fig.14 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0042] Fig.15 is schematically shown with reference to Fig.14 An enlarged view of the first light emitting region is depicted.

[0043] Fig.16 It shows reference Fig.14 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described.

[0044] Fig.17 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0045] Fig.18 is schematically shown with reference to Fig.17 An enlarged view of the first light emitting region is depicted.

[0046] Fig.19 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0047] Fig. 20 Refer to the detailed Fig.19 An enlarged layout diagram of one example of touch nodes is described.

[0048] Fig.21 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0049] Fig. 22 is schematically shown with reference to Fig.21 An enlarged view of the first light emitting region is depicted.

[0050] Fig.23 It shows reference Fig. 22 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described.

[0051] Figures 24 to 43 is a diagram for illustrating a method of manufacturing a display device according to one or more embodiments.

[0052] Fig.44 is an exemplary diagram schematically illustrating a virtual reality device including a display device according to one or more embodiments.

[0053] Fig.45 is an exemplary diagram schematically illustrating a smart device including a display device according to one or more embodiments.

[0054] Fig.46is a diagram schematically illustrating an example of a vehicle including a display device according to one or more embodiments.

[0055] Fig.47 is an exemplary diagram schematically illustrating a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0056] One or more embodiments will now be described more fully below with reference to the accompanying drawings. However, one or more embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0057] For describing the embodiments of the present disclosure, some of the parts irrelevant to the description may not be provided.

[0058] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0059] In addition, the phrase "in a plan view" refers to the situation where a portion of an object is observed from above, and the phrase "in a schematic cross-sectional view" refers to a schematic cross-section obtained by vertically cutting a portion of an object from the side. The term "superimposed" or "superimposed" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "superimposed" may include stacking, stacking, facing or facing, extending thereon, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-superimposed" may include meanings such as "spaced" or "separated" or "deviation" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is placed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0060] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, where the device shown in the drawings is flipped, a device positioned "below" or "beneath" another device may be placed "above" another device. Thus, the exemplary term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0061] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or may be "electrically connected" or "electrically coupled" to the other element through one or more intervening elements disposed therebetween. It will also be understood that when the terms "comprises," "having," "comprising," and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0062] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate its description and explanation. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and without departing from the teachings herein, the "second element" and the "third element" may be named in a similar manner.

[0063] As used herein, the terms "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0064] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0065] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless explicitly defined in the specification, they will not be interpreted in an idealized or overly formal sense.

[0066] Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0068] Reference Figure 1 The display device 10 is a device for displaying video and / or still images, such as mobile phones, smart phones, tablet personal computers, and portable electronic devices (such as smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation and ultra mobile PCs (UMPCs)) and display screens for various products such as televisions, laptop computers, monitors, billboards, and / or Internet of Things (IOT) devices.

[0069] The display device 10 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a small light-emitting display device using a micron or nanometer light-emitting diode (micron LED or nano LED). Hereinafter, the description focuses on the fact that the display device 10 is a micron light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, an ultra-small light-emitting diode is described here as a micron light-emitting diode.

[0070] The display device 10 includes a display panel 100 , a display driving circuit 250 , and a circuit board 300 .

[0071] The display panel 100 may be formed as a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be formed as a right angle. The planar shape of the display panel 100 is not limited to a rectangle, and may be formed into other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed to be flexible, such as being able to bend, bend, fold, and / or curl.

[0072] The substrate of the display panel 100 may include a main area MA and a sub area SBA.

[0073] The main area MA may include a display area DA configured to display an image and a non-display area NDA which is a peripheral area of ​​the display area DA and is disposed along one or more edges or peripheries of the display area DA. The display area DA may include a plurality of pixels that display an image. For example, a pixel may include a first sub-pixel configured to emit a first light, a second sub-pixel configured to emit a second light, and a third sub-pixel configured to emit a third light.

[0074] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The sub-region SBA is shown as being expanded, but the sub-region SBA may be curved, and in this case, the sub-region SBA may be disposed on the bottom surface of the display panel 100. When the sub-region SBA is curved, the sub-region SBA may overlap the main region MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driving circuit 250 may be disposed in the sub-region SBA.

[0075] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0076] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. As such, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film.

[0077] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments. Figure 2 The sub-area SBA is shown unfolded and not bent. Figure 3 It is shown that the sub-area SBA is bent.

[0078] Reference Figure 2 and Figure 3 , the display panel 100 may include a main area MA and a sub-area SBA.

[0079] The main area MA may include a display area DA configured to display an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

[0080] The non-display area NDA may be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., surrounding the display area DA). The non-display area NDA may be an edge area of ​​the display panel 100.

[0081] The first scan driving unit SDC1 and the second scan driving unit SDC2 may be disposed in the non-display area NDA. The first scan driving unit SDC1 is disposed at one side (e.g., the left side) of the display panel 100, and the second scan driving unit SDC2 is disposed at the other side (e.g., the right side) of the display panel 100. However, this is not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to a scan line.

[0082] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be smaller than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be smaller than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be disposed at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0083] The sub-area SBA may include a connection area CA, a pad (or referred to as a “pad” or “bonding pad”) area PA, and a bending area BA.

[0084] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0085] The pad area PA is an area where the pad PD and the display driving circuit 250 are provided. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0086] The bending area BA is a bent area. When the bending area BA is bent, the pad area PA may be disposed below the connection area CA and below the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0087] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0088] Reference Figure 4 , the first subpixel SPX1 according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL and GBL, the emission line EL and the data line DL. For example, the first subpixel SPX1 may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EL and the data line DL.

[0089] The first subpixel SPX1 according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1 and a first light emitting element LE1. The switching element includes first, second, third, fourth, fifth, and sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0090] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode of the driving transistor DT.

[0091] The first light emitting element LE1 may be a micro light emitting diode.

[0092] The first light emitting element LE1 is configured to emit light according to the driving current Ids. The amount of light emitted from the first light emitting element LE1 may be proportional to the driving current Ids. The anode electrode of the first light emitting element LE1 may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power line VSL to which the second power supply voltage is applied.

[0093] The capacitor C1 may be formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first power line VDL.

[0094] like Figure 4 As shown in , the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may all be formed as p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may be formed of polysilicon.

[0095] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. Because the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, when the scan signal of the gate low voltage and the emission signal are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the light emitting line EL, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0096] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0097] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be formed of a p-type MOSFET, and the first transistor ST1 and the third transistor ST3 may be formed of an n-type MOSFET. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as a p-type MOSFET may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as an n-type MOSFET may be formed of an oxide semiconductor. In this case, the transistor formed of polysilicon and the transistor formed of an oxide semiconductor may be arranged in different layers.

[0098] Because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal with a gate high voltage is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, so when a scan signal with a gate low voltage and an emission signal are respectively applied to the write scan line GWL, the bias scan line GBL, and the light emitting line EL, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be turned on.

[0099] Optionally, Figure 4 The fourth transistor ST4 in the embodiment may be formed by an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an n-type MOSFET, the fourth transistor ST4 may be turned on when a bias scan signal of a gate high voltage is applied to the bias scan line GBL.

[0100] For example, the first transistor ST1 is connected between the second electrode and the gate electrode of the driving transistor DT. The second transistor ST2 is connected between the data line DL and the first electrode of the driving transistor DT. The third transistor ST3 is connected between the gate electrode of the driving transistor DT and the initialization voltage line VIL, the fourth transistor ST4 may be connected between the initialization voltage line VIL and the second electrode of the sixth transistor ST6, the fifth transistor ST5 is connected between the first power line VDL and the first electrode of the driving transistor DT, and the sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the first light emitting element LE1. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 are connected to the light emitting line EL.

[0101] Alternatively, in one or more embodiments, the first transistor ST1 , the second transistor ST2 , the third transistor ST3 , the fourth transistor ST4 , the fifth transistor ST5 , and the sixth transistor ST6 and the driving transistor DT may all be formed as n-type MOSFETs.

[0102] In one or more embodiments, the circuit diagram of the second sub-pixel and the third sub-pixel according to one or more embodiments is combined with Figure 4 and Figure 5 The circuit diagram of the first sub-pixel SPX1 described is substantially the same, and thus a description thereof will be omitted.

[0103] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0104] Reference Figure 6 , the display device 10 may include a substrate 110 , a light emitting element unit LEP, a wavelength control unit 200 , and a color filter layer CFL.

[0105] The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass, quartz, etc. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto, and may include a plastic such as polyimide, and may have a flexible property that allows it to bend, bend, fold, and / or curl. A plurality of light emitting areas EA1, EA2, and EA3 and a non-light emitting area NEA may be defined in the substrate 110.

[0106] The switching elements T1, T2, and T3 may be positioned on the substrate 110. In one or more embodiments, the first switching element T1 may be positioned in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be positioned in the second light emitting area EA2, and the third switching element T3 may be positioned in the third light emitting area EA3. However, it is not limited thereto, and in one or more embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be positioned in the non-light emitting area NEA.

[0107] In one or more embodiments, the first switching element T1, the second switching element T2, and the third switching element T3 may each be a thin film transistor (TFT) including amorphous silicon, polycrystalline silicon, and / or an oxide semiconductor. In one or more embodiments, a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) transmitting signals to each switching element may be further positioned on the substrate 110.

[0108] Each of the switching elements T1 , T2 , and T3 may include a semiconductor layer 65 , a gate electrode 75 , a source electrode 85 a , and a drain electrode 85 b .

[0109] Specifically, the buffer layer 60 may be disposed on the substrate 110. The buffer layer 60 may be disposed to cover the entire surface of the substrate 110. The buffer layer 60 includes silicon nitride, silicon oxide, and / or silicon oxynitride, and may be made of a single layer or a double layer thereof.

[0110] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, and / or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (AB) containing, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and / or magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z In one or more embodiments, the semiconductor layer 65 may include indium gallium zinc oxide (IGZO).

[0111] The gate insulating layer 70 may be disposed on the semiconductor layer 65 and the buffer layer 60. The gate insulating layer 70 may include a silicon compound and / or a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and / or titanium oxide, etc. In one or more embodiments, the gate insulating layer 70 may include silicon oxide.

[0112] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may be disposed to overlap the semiconductor layer 65 in the third direction DR3. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, In 2 O 3 The gate electrode 75 may be made of a metal oxide and / or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni). For example, the gate electrode 75 may be made of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0113] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75 and the gate insulating layer 70. The first interlayer insulating layer 80 may be disposed directly on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed directly on the first interlayer insulating layer 80. The first interlayer insulating layer 80 and the second interlayer insulating layer 82 both include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and / or zinc oxide. However, the present disclosure is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the level difference below. In this embodiment, two interlayer insulating layers, the first interlayer insulating layer 80 and the second interlayer insulating layer 82, are shown and described, but the present disclosure is not limited thereto, and only one interlayer insulating layer may be provided.

[0114] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may contact the semiconductor layer 65 through contact holes passing through the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70, respectively. The source electrode 85a and the drain electrode 85b may include a material such as ITO, IZO, ITZO, In 2 O 3 The source electrode 85a and the drain electrode 85b may be made of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, and / or a metal oxide such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be made of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0115] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3 on the second interlayer insulating layer 82. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In one or more embodiments, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0116] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 is disposed to correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 described later to the switching elements T1, T2, and T3 described above. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole passing through the first planarization layer 120.

[0117] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 may planarize the underlying level difference, and may include the same material as the first planarization layer 120 described above.

[0118] The light emitting element unit LEP may be disposed on the second planarization layer 130. The light emitting element unit LEP may include a plurality of pixel electrodes PE1, PE2 and PE3, a plurality of light emitting elements LE and a common electrode CE. In addition, the light emitting element unit LEP may further include a bank BNL and a first via layer VIA1 that separate each of the light emitting areas EA1, EA2 and EA3.

[0119] The plurality of pixel electrodes PE1, PE2, and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be used as first electrodes of the light emitting element LE, and may be anode electrodes or cathode electrodes. The first pixel electrode PE1 may be positioned in the first light emitting area EA1, the second pixel electrode PE2 may be positioned in the second light emitting area EA2, and the third pixel electrode PE3 may be positioned in the third light emitting area EA3. The light emitting elements LE may be regularly arranged with certain rules (e.g., predetermined rules). For example, the light emitting elements LE may be arranged at regular intervals to be spaced apart from each other.

[0120] Each light emitting element LE may be generally disposed on each pixel electrode PE1, PE2 and PE3. However, the present disclosure is not limited thereto, and some light emitting elements LE may be disposed between each pixel electrode PE1, PE2 and PE3, may be partially disposed on one pixel electrode, or may not be disposed on any pixel electrode.

[0121] In one or more embodiments, the first pixel electrode PE1 may overlap the first light emitting region EA1, the second pixel electrode PE2 may overlap the second light emitting region EA2, and the third pixel electrode PE3 may overlap the third light emitting region EA3.

[0122] Each pixel electrode PE1, PE2 and PE3 may be directly connected to the pixel connection electrode 125 through a contact hole passing through the second planarization layer 130, and may be electrically connected to the respective switching elements T1, T2 and T3 through the pixel connection electrode 125. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and / or a mixture thereof. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a double-layer structure in which a copper layer is stacked on a titanium layer, but the structure is not limited thereto.

[0123] A plurality of light emitting elements LE may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 .

[0124] like Figures 6 to 8 As shown in , the light emitting element LE may be disposed in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE may be a vertical light emitting diode element extending in the third direction DR3. That is, the length of the light emitting element LE in the third direction DR3 may be greater than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the first direction DR1 or the length in the second direction DR2 may be approximately 1 μm to 5 μm, but is not limited thereto. In addition, the length of the light emitting element LE in the third direction DR3 may be approximately 7 μm to 10 μm. However, the present disclosure is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may be equal to or less than the length in the horizontal direction.

[0125] The light emitting element LE may be a micro light emitting diode element.

[0126] The bank BNL may be formed on the second planarization layer 130 to separate the pixel electrodes PE1, PE2, and PE3 to define a light emitting region. The bank BNL may be arranged to cover edges of the pixel electrodes PE1, PE2, and PE3. The bank BNL may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0127] The first via layer VIA1 may be disposed on the bank BNL and the pixel electrodes PE1, PE2, and PE3. The first via layer VIA1 covers the bank BNL and the pixel electrodes PE1, PE2, and PE3, and may planarize a step at the bottom to allow formation of a common electrode CE as described later.

[0128] The common electrode CE may be disposed on the first via layer VIA1 and the plurality of light emitting elements LE. Specifically, the common electrode CE is disposed on one surface of the substrate 110 on which the light emitting elements LE are formed, and may be disposed in the entire display area DA of the substrate 110. The common electrode CE is disposed to overlap each of the light emitting areas EA1, EA2, and EA3 and the non-light emitting area NEA, and may have a sufficiently small thickness to allow light emission.

[0129] Since the common electrode CE is completely disposed on the substrate 110 and a common voltage is applied, it may include a material having a low resistance. In addition, the common electrode CE may be formed to be thin for easy light transmission. For example, the common electrode CE may include a metal material having a low resistance such as aluminum (Al), silver (Ag) and / or copper (Cu), or a metal oxide such as ITO, IZO and / or ITZO. The thickness of the common electrode CE may be approximately 10Å to 200Å, but is not limited thereto.

[0130] The above-mentioned light emitting element LE can receive a pixel voltage or an anode voltage from each pixel electrode PE1, PE2 and PE3, and can receive a common voltage through the common electrode CE. The light emitting element LE can emit light with a suitable brightness (e.g., a predetermined brightness) according to the voltage difference between the pixel voltage and the common voltage. In one or more embodiments, by providing a plurality of light emitting elements LE (i.e., inorganic light emitting diodes) on the pixel electrodes PE1, PE2 and PE3, the situation that the organic light emitting diode is susceptible to external moisture or oxygen can be eliminated, and the life span and reliability can be improved.

[0131] The light emitting element unit LEP may further include a first insulating layer INS1 covering the common electrode CE. The first insulating layer INS1 may be directly disposed on the common electrode CE. The first insulating layer INS1 covers components disposed thereunder (e.g., the light emitting element LE and the common electrode CE) and is used to protect them from moisture or foreign matter. Therefore, the first insulating layer INS1 may also be referred to as a protective layer. The first insulating layer INS1 may include an inorganic material, for example, at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride.

[0132] The wavelength control unit 200 may be disposed on the light emitting element unit LEP. The wavelength control unit 200 may include a second via layer VIA2, a degradation prevention layer QBANK, a wavelength conversion layer QDL, a second insulating layer INS2, a reflective layer RF, and a partition wall unit PW.

[0133] The partition wall unit PW is disposed on the first insulating layer INS1 and may partition the plurality of light emitting regions EA1, EA2, and EA3. The partition wall unit PW is arranged to extend in the first direction DR1 and the second direction DR2 and may be formed in a grid-like pattern throughout the display area DA. In addition, the partition wall unit PW may not overlap the plurality of light emitting regions EA1, EA2, and EA3 and may overlap the non-light emitting region NEA.

[0134] The partition wall unit PW may serve to provide a space for forming the wavelength conversion layer QDL. To this end, the partition wall unit PW may include a first partition wall PW1 and a second partition wall PW2 disposed on the first partition wall PW1.

[0135] The partition wall unit PW may be composed of a double-layer structure of a first partition wall PW1 and a second partition wall PW2, and may be relatively thick to provide a space in which the wavelength conversion layer QDL is formed. For example, the width WH1 of the first partition wall PW1 is wider than the width WH2 of the second partition wall PW2. The width WH1 of the first partition wall PW1 may be approximately twice the width of the second partition wall PW2. For example, the width WH1 of the first partition wall PW1 may be in the range of 5 μm to 10 μm, and the width WH2 of the second partition wall PW2 may be in the range of 3 μm to 5 μm. In one or more embodiments, the width WH1 of the first partition wall PW1 may be 8 μm, and the width WH2 of the second partition wall PW2 may be 4 μm. The height HP1 of the first partition wall PW1 may be greater than or equal to the height HP2 of the second partition wall PW2. For example, the height HP1 of the first partition wall PW1 may be in the range of 8 μm to 12 μm, and the height HP2 of the second partition wall PW2 may be in the range of 4 μm to 8 μm. In one or more embodiments, the height HP1 of the first partition wall PW1 may be 10 μm, and the height HP2 of the second partition wall PW2 may be 6 μm. The first partition wall PW1 and the second partition wall PW2 may include an organic insulating material to be thick. The organic insulating material may include, for example, epoxy resin, acrylic resin, cardo resin and / or imide resin.

[0136] The second insulating layer INS2 may be disposed on the partition wall unit PW. The second insulating layer INS2 may be disposed along the side surface and the top surface of the partition wall unit PW. The second insulating layer INS2 may be disposed not to overlap the light emitting areas EA1, EA2, and EA3, and may overlap the non-light emitting area NEA. The second insulating layer INS2 may completely overlap the partition wall unit PW.

[0137] The reflective layer RF may be disposed on the first and second insulating layers INS1 and INS2. The reflective layer RF is disposed on the side of the partition wall unit PW on the second insulating layer INS2 and may be disposed on the first insulating layer INS1 to overlap the light emitting areas EA1, EA2, and EA3 where the light emitting elements LE are not disposed.

[0138] The reflective layer RF may reflect light emitted from the light emitting element LE upward (eg, toward the third direction DR3). The reflective layer RF may include a metal material having a high light reflectivity. For example, the reflective layer RF may include aluminum and / or silver, and / or may be an alloy thereof.

[0139] The second via layer VIA2 , the degradation prevention layer QBANK, and the wavelength conversion layer QDL may be sequentially disposed in each of the light emitting areas EA1 , EA2 , and EA3 .

[0140] The second via layer VIA2 may be disposed in each of the light emitting areas EA1, EA2, and EA3 divided by the partition wall unit PW. The second via layers VIA2 disposed in each of the light emitting areas EA1, EA2, and EA3 may be spaced apart from each other. That is, the second via layers VIA2 may be formed in an island pattern to be spaced apart from each other. The second via layer VIA2 may be disposed to overlap the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively.

[0141] The anti-degradation layer QBANK may be disposed on the second via layer VIA2. The anti-degradation layer QBANK is disposed between the second via layer VIA2 and the wavelength conversion layer QDL to prevent heat generated from the light emitting element LE from being directly transferred to the wavelength conversion layer QDL. The anti-degradation layer QBANK may prevent the wavelength conversion layer QDL from being degraded due to heat generated from the light emitting element LE.

[0142] The degradation prevention layer QBANK may include a base resin BRSO and a scatterer SCP dispersed in the base resin BRSO. The base resin BRSO may include a light-transmitting organic material. For example, the base resin BRSO may include epoxy resin, acrylic resin, cardo resin and / or imide resin.

[0143] The scatterer SCP may scatter the light of the light emitting element LE in random directions. The scatterer SCP may have a refractive index different from that of the base resin BRSO and may form an optical interface with the base resin BRSO. For example, the scatterer SCP may be light scattering particles. The scatterer SCP is not particularly limited as long as it is any material capable of scattering at least a portion of the transmitted light, but may be, for example, metal oxide particles or organic particles. Examples of metal oxide particles include titanium oxide (TiO 2 )、ZrO 2 )、Alumina(Al 2 O 3 )、Indium oxide(In 2 O 3 ), zinc oxide (ZnO) and / or tin oxide (SnO 2 ), examples of organic particles include acrylic resin or urethane resin. The scatterer SCP can scatter light in random directions regardless of the incident direction of the incident light without substantially converting the wavelength of the light.

[0144] The wavelength conversion layer QDL may be disposed on the anti-degradation layer QBANK. The wavelength conversion layer QDL may convert or shift the peak wavelength of the incident light into another specific peak wavelength and emit light of the other specific peak wavelength. The wavelength conversion layer QDL may convert the blue first light emitted from the light emitting element LE into a red second light, a green third light, or transmit the blue first light as is.

[0145] The wavelength conversion layer QDL may be disposed in each of the light emitting regions EA1, EA2, and EA3 divided by the partition wall unit PW, and may be disposed to be spaced apart from each other. That is, the wavelength conversion layer QDL may be formed in an island pattern to be spaced apart from each other. The wavelength conversion layer QDL may be disposed to overlap the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively. In one or more embodiments, the wavelength conversion layer QDL may completely overlap the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively.

[0146] The wavelength conversion layer QDL may include a first wavelength conversion pattern WCL1 overlapping the first light emitting region EA1 , a second wavelength conversion pattern WCL2 overlapping the second light emitting region EA2 , and a light transmitting pattern TPL overlapping the third light emitting region EA3 .

[0147] The first wavelength conversion pattern WCL1 may be disposed to overlap the first light emitting area EA1. The first wavelength conversion pattern WCL1 may convert or shift the peak wavelength of the incident light into another specific peak wavelength and emit light of the other specific peak. In one or more embodiments, the first wavelength conversion pattern WCL1 may convert the blue first light emitted from the light emitting element LE of the first light emitting area EA1 into a second light that is red light having a single peak wavelength in the range of about 610 nm to about 650 nm and emit the second light.

[0148] The first wavelength conversion pattern WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1, and a scatterer SCP. The first base resin BRS1 may be the same material as the base resin BRS0 of the degradation prevention layer QBANK, but is not limited thereto. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0149] The first wavelength conversion particle WCP1 may convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 may convert the light in the blue band into the light in the red band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, and / or a phosphorescent material. For example, a quantum dot may be a particle material that emits light of a specific color when an electron transitions from a conduction band to a valence band.

[0150] Quantum dots can be semiconductor nanocrystal materials. Depending on their composition and size, quantum dots can have a specific band gap to absorb light and emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or combinations thereof.

[0151] The II-VI compounds are binary compounds, ternary compounds and quaternary compounds, the binary compounds are selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; the ternary compounds are selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZn S, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; the quaternary compound is selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0152] The III-V compounds are binary compounds, ternary compounds and quaternary compounds. The binary compound is selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; the ternary compound is selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; the quaternary compound is selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0153] The IV-VI compound may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, the binary compound being selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; the ternary compound being selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; the quaternary compound being selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0154] The binary, ternary or quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0155] In one or more embodiments, the quantum dot may have a core-shell structure including a core comprising a nanocrystal as described above and a shell surrounding the core. The shell of the quantum dot may act as a protective layer to prevent chemical denaturation of the core to maintain semiconductor properties and / or act as a charged layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. Examples of the shell of the quantum dot include metal or non-metal oxides, semiconductor compounds and / or combinations thereof.

[0156] For example, the metal or nonmetal oxide may have a 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , binary compounds of NiO and / or such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2O 4 Examples of ternary compounds are given below, but the present disclosure is not limited thereto.

[0157] In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0158] The second wavelength conversion pattern WCL2 may be disposed to overlap the second light emitting area EA2. The second wavelength conversion pattern WCL2 may emit light of another specific peak wavelength by converting or shifting the peak wavelength of the incident light to another specific peak wavelength. In one or more embodiments, the second wavelength conversion pattern WCL2 may convert the blue first light emitted from the light emitting element LE of the second light emitting area EA2 into a green third light having a peak wavelength in the range of about 510 nm to 550 nm and emit the light.

[0159] The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0160] The second base resin BRS2 may be made of a material having high light transmittance, may be made of the same material as the first base resin BRS1, or may include at least one of the materials exemplified as constituent materials thereof.

[0161] The second wavelength conversion particles WCP2 can convert or shift the peak wavelength of the incident light to another specific peak wavelength. In one or more embodiments, the second wavelength conversion particles WCP2 can convert the blue first light provided from the light emitting element LE into a green third light having a peak wavelength in the range of about 510nm to 550nm and emit the light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods and / or phosphors. A more specific description of the second wavelength conversion particles WCP2 is substantially the same or similar to the above description in the description of the first wavelength conversion particles WCP1, and a more specific description of the second wavelength conversion particles WCP2 will be omitted.

[0162] The light-transmitting pattern TPL may be arranged to overlap with the third light-emitting area EA3. The light-transmitting pattern TPL may transmit incident light. The light-transmitting pattern TPL may directly transmit the blue first light emitted from the light-emitting element LE disposed in the third light-emitting area EA3. The light-transmitting pattern TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Since the third base resin BRS3 is substantially the same as or similar to the above-mentioned first base resin BRS1, a description thereof will be omitted.

[0163] Reference Figure 7 and Figure 8 , the light emitting element unit LEP and the wavelength control unit 200 will be described in detail.

[0164] The first light, the second light, and the third light emitted from the above-described wavelength control unit 200 may respectively pass through a color filter layer CFL to be described later to realize full color.

[0165] The wavelength control unit 200 may further include a cover layer CAP disposed on the partition wall unit PW and the wavelength conversion layer QDL. The cover layer CAP is used to cover the wavelength conversion layer QDL disposed below and protect the wavelength conversion layer QDL from moisture or debris. The cover layer CAP may include an inorganic material. For example, the cover layer CAP may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. In one or more embodiments, the accompanying drawings show that the cover layer CAP is formed as a single layer, but the present disclosure is not limited thereto. For example, the cover layer CAP may be formed of a multilayer in which inorganic layers are alternately stacked, and the inorganic layers include at least one of the materials that the cover layer CAP may contain. The thickness of the cover layer CAP may be in the range of 0.05 μm to 2 μm, but is not limited thereto.

[0166] In one or more embodiments, a color filter layer CFL may be disposed on the wavelength control unit 200. The color filter layer CFL may include a first coating layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second coating layer OC2.

[0167] The first coating layer OC1 may be disposed on the wavelength control unit 200. The first coating layer OC1 may be disposed directly on the cover layer CAP of the wavelength control unit 200. The first coating layer OC1 may be disposed throughout the entire display area DA and may have a flat surface. The first coating layer OC1 may flatten a step formed by the lower wavelength control unit 200 to facilitate formation of the color filter layer CFL.

[0168] The first coating layer OC1 may include a light-transmitting organic material. For example, the first coating layer OC1 may include epoxy resin, acrylic resin, cardo resin and / or imide resin. In one or more embodiments, the first coating layer OC1 is shown as a single layer, but it is not limited thereto and may be arranged to be stacked in multiple layers.

[0169] First, second, and third color filters CF1, CF2, and CF3 may be disposed on the first overcoat layer OC1. The first, second, and third color filters CF1, CF2, and CF3 may be disposed in the first, second, and third emission regions EA1, EA2, and EA3.

[0170] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter CF1 may selectively transmit the second light (e.g., red light) and block or absorb the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light) and block or absorb the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light) and block or absorb the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0171] In one or more embodiments, the light incident on the first color filter CF1 may be light converted into the second light in the first wavelength conversion pattern WCL1, the light incident on the second color filter CF2 may be light converted into the third light in the second wavelength conversion pattern WCL2, and the light incident on the third color filter CF3 may be the first light transmitted through the light-transmitting pattern TPL. Therefore, the second light transmitted through the first color filter CF1, the third light transmitted through the second color filter CF2, and the first light transmitted through the third color filter CF3 may be emitted to the top of the substrate 110 to achieve full color.

[0172] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light entering from the outside of the display device 10 to reduce reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion caused by reflection of external light.

[0173] The plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be larger than the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3. For example, the plane area of ​​the first color filter CF1 may be larger than the plane area of ​​the first light-emitting region EA1. The plane area of ​​the second color filter CF2 may be larger than the plane area of ​​the second light-emitting region EA2. The plane area of ​​the third color filter CF3 may be larger than the plane area of ​​the third light-emitting region EA3. However, it is not limited thereto, and the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be equal to the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3.

[0174] The second coating layer OC2 may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be disposed directly on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be disposed in the entire display area DA and may have a flat surface. The second coating layer OC2 may flatten the steps formed by the first color filter CF1, the second color filter CF2, and the third color filter CF3 below. The second coating layer OC2 may include a light-transmitting organic material and may be substantially the same as or similar to the first coating layer OC1 described above.

[0175] As described above, the display device 10 according to one or more embodiments can improve the light emitting efficiency of the light emitting element LE by forming a reflective layer RF on the substrate 110 and on the side of the partition wall unit PW in a region not overlapping the light emitting element LE between the partition wall and the adjacent partition wall.

[0176] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted. Figure 8 It shows reference Figure 6 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described. Fig. 9 is a plan view illustrating a light emitting region and a region of a reflective layer according to one or more embodiments. Fig.10 is a plan view illustrating a light emitting region and a region of a reflective layer according to one or more embodiments.

[0177] Reference Figure 7 and Figure 8 In the present embodiment, each of the pixel electrodes PE1, PE2 and PE3 may include a lower electrode layer P1 and an upper electrode layer P3. Hereinafter, the first pixel electrode PE1 will be described as an example.

[0178] The lower electrode layer P1 may be disposed at the bottom of the first pixel electrode PE1 and may be electrically connected to the switching element. The lower electrode layer P1 may be used to provide the first pixel electrode PE1 with adhesion to the second planarization layer 130. The lower electrode layer P1 may include a metal (eg, titanium).

[0179] The upper electrode layer P3 is disposed on the lower electrode layer P1 and may be in direct contact with the light emitting element LE. The upper electrode layer P3 may be disposed between the lower electrode layer P1 and the light emitting element LE and may be used to provide the first pixel electrode PE1 with adhesion to the light emitting element LE. The upper electrode layer P3 may include a metal (eg, copper).

[0180] The light emitting element LE may include a connection electrode 150, a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 arranged along a thickness direction (ie, a third direction DR3) of the substrate 110. The connection electrode 150, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 may be sequentially stacked along the third direction DR3. The light emitting element LE may include an element insulating layer INS0 surrounding the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0181] The light emitting element LE may have a cylindrical shape, a disc shape, or a rod shape whose height is longer than its width. However, the light emitting element LE is not limited thereto, and may have a shape such as a rod, a wire, a tube, a polygonal column shape such as a regular hexahedron, a cuboid, a hexagonal column, or a shape extending in one direction but having a partially inclined outer surface.

[0182] The connection electrode 150 may be disposed on top of each of the plurality of pixel electrodes PE1, PE2, and PE3. Hereinafter, the light emitting element LE disposed on the first pixel electrode PE1 will be described as an example, but is not limited thereto, and the structure of the light emitting element LE disposed on the second pixel electrode PE2 and the third pixel electrode PE3 may be constructed in the same manner.

[0183] The connection electrode 150 may include a reflective layer 151 and a connection layer 153. The reflective layer 151 may be used to reflect light emitted from the active layer MQW of the light emitting element LE. The reflective layer 151 may be disposed adjacent to the active layer MQW of the light emitting element LE. The reflective layer 151 may include a metal material that is conductive and has a high light reflectivity. The reflective layer 151 may include, for example, aluminum (Al) and / or silver (Ag) or may be an alloy thereof.

[0184] The connection layer 153 may be used to transmit the light emitting signal from the first pixel electrode PE1 to the light emitting element LE. The connection layer 153 may be an ohmic connection electrode. However, it may be a Schottky connection electrode. The connection layer 153 may be disposed at the bottom of the light emitting element LE and may be disposed further away from the active layer MQW than the reflective layer 151. The connection layer 153 may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection layer 153 may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (e.g., SAC305).

[0185] exist Figure 8 , the light emitting element LE is shown as including a connection electrode 150 having a double-layer structure of a reflective layer 151 and a connection layer 153, but the present disclosure is not limited thereto. In some cases, the light emitting element LE may include a connection electrode 150 having more stacked layers, or some layers may be omitted.

[0186] The first semiconductor layer SEM1 may be disposed on the connection electrode 150. The first semiconductor layer SEM1 may be disposed adjacent to the first pixel electrode PE1. The first semiconductor layer SEM1 may be a p-type semiconductor and may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, it may be one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer SEM1 may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, Sr, and / or Ba, etc. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be in the range of 30nm to 200nm, but is not limited thereto.

[0187] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength range of 450 nm to 495 nm (ie, light in a blue band).

[0188] The active layer MQW may include a single quantum well structure or a multi-quantum well structure. If the active layer MQW includes a material having a multi-quantum well structure, it may be a stacked structure having a plurality of well layers and barrier layers alternating with each other. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be approximately 1 nm to 4 nm, and the thickness of the barrier layer may be 3 nm to 10 nm.

[0189] Optionally, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked with each other, and other group III to group V semiconductor materials may be included according to the wavelength band of the emitted light. The light emitted from the active layer MQW is not limited to the first light, and the second light (e.g., light in the green band) or the third light (e.g., light in the red band) may be emitted according to the situation. In one or more embodiments, when indium is included in the semiconductor material included in the active layer MQW, the color of the emitted light may vary according to the amount of indium. For example, when the indium content is about 15%, light in the blue band may be emitted, when the indium content is about 25%, light in the green band may be emitted, and when the indium content is about 35% or more, light in the red band may be emitted.

[0190] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be an n-type semiconductor. The second semiconductor layer SEM2 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y The second semiconductor layer SEM2 may be a semiconductor material of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be one or more of n-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer SEM2 may be doped with an n-type dopant, and the n-type dopant may be Se, Si, Ge, and / or Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be in the range of 2 μm to 4 μm, but is not limited thereto.

[0191] In one or more embodiments, an electron blocking layer may be further included between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer for suppressing or preventing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be in the range of 10 nm to 50 nm, but is not limited thereto. In addition, the electron blocking layer may be omitted.

[0192] In addition, a superlattice layer may be further included between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for alleviating stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN or GaN. The thickness of the superlattice layer may be approximately 50 nm to 200 nm. The superlattice layer may be omitted.

[0193] The element insulating layer INS0 may be around (for example, may surround) the side (for example, outer surface (for example, outer peripheral surface or peripheral surface)) of the light emitting element LE. The element insulating layer INS0 may insulate the light emitting element LE from other layers. The element insulating layer INS0 may be directly disposed on and surround the outer surfaces (for example, outer peripheral surface or peripheral surface) of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2. In one or more embodiments, the element insulating layer INS0 may surround the entire outer surfaces (for example, outer peripheral surface or peripheral surface) of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0194] like Figure 8 As shown in FIG. 1 , the element insulating layer INS0 may be arranged to surround the light emitting element LE. The element insulating layer INS0 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y )、Alumina(Al x O y ) and / or an inorganic insulating material such as aluminum nitride (AlN). The thickness of the element insulating layer INS0 may be approximately 0.1 μm, but is not limited thereto.

[0195] The first via layer VIA1 may be disposed on the first pixel electrode PE1 and the bank BNL. The width WHP of the first pixel electrode PE1 may be two to three times the width WHB of the bank BNL, but is not limited thereto. For example, the width WHP of the first pixel electrode PE1 may be 19 μm, and the width WHB of the bank BNL may be 7 μm.

[0196] The first via layer VIA1 extends from the top surface of each pixel electrode PE1 , PE2 , and PE3 and the bank BNL in the third direction DR3 to surround the light emitting element LE, but the top surface of the first via layer VIA1 may be disposed lower than the height of the light emitting element LE.

[0197] The first via layer VIA1 may be formed at a suitable height (eg, a predetermined height) so that at least a portion of the plurality of light emitting elements LE (eg, the second semiconductor layer SEM2) may protrude above the first via layer VIA1. In other words, the height of the first via layer VIA1 may be shorter than that of the light emitting elements LE.

[0198] The first via layer VIA1 may include an organic material to planarize the lower step. For example, the first via layer VIA1 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or benzocyclobutene (BCB) resin.

[0199] The common electrode CE may be directly disposed on the top surface and the side surface of the plurality of light emitting elements LE. The common electrode CE may be in direct contact with the second semiconductor layer SEM2 exposed on the top surface of the light emitting element LE. The common electrode CE may be disposed around the side of the second semiconductor layer SEM2 protruding above the first via layer VIA1 (e.g., surrounding the side of the second semiconductor layer SEM2 protruding above the first via layer VIA1). Figure 6 As shown in , the common electrode CE covers the plurality of light emitting elements LE and may be a common layer provided to be commonly connected to the plurality of light emitting elements LE.

[0200] The first insulating layer INS1 disposed on the common electrode CE may include a transparent insulating material that may transmit light emitted from the light emitting element LE. The first insulating layer INS1 may protect the common electrode CE disposed at the bottom.

[0201] The second insulating layer INS2 disposed on the partition wall unit PW may include a transparent insulating material, and may be formed of the same material as the first insulating layer INS1.

[0202] In one or more embodiments, the first partition wall PW1 and the second partition wall PW2 may block the transmission of light in the non-luminous area NEA. The first partition wall PW1 and the second partition wall PW2 may also include a light blocking material, and may include a dye or pigment having a light blocking property. For example, the first partition wall PW1 and the second partition wall PW2 may be a black matrix. External light incident from the outside of the display device 10 may cause the problem of distorting the color gamut of the wavelength control unit 200. According to one or more embodiments, a partition wall unit PW including a light blocking material is provided in the wavelength control unit 200 so that at least a portion of the external light is absorbed by the partition wall unit PW. Therefore, color distortion caused by external light reflection may be reduced. In addition, the partition wall unit PW including a light blocking material may prevent light from entering between adjacent luminous areas and causing mixing, thereby further improving the color reproduction rate. The width of the partition wall unit PW may narrow as it moves from the first partition wall PW1 to the second partition wall PW2. A step may be formed at a point where the first partition wall PW1 and the second partition wall PW2 meet. Although the present embodiment shows the partition wall unit PW including the first partition wall PW1 and the second partition wall PW2, it is not limited thereto, and the partition wall unit PW may be a single layer.

[0203] The second insulating layer INS2 may completely surround the partition wall unit PW disposed at the bottom and protect the partition wall unit PW.

[0204] The second insulating layer INS2 may extend from the side of the first partition wall PW1 to the side of the second partition wall PW2, and may extend from the side of the second partition wall PW2 to the top surface of the second partition wall PW2. The second insulating layer INS2 may be around the side surfaces of the first partition wall PW1 and the second partition wall PW2 (e.g., may surround the side surfaces of the first partition wall PW1 and the second partition wall PW2) and cover the top surface of the second partition wall PW2. The second insulating layer INS2 may extend continuously at the contact point between the first partition wall PW1 and the second partition wall PW2.

[0205] In one or more embodiments, the reflective layer RF may include a first reflective layer RF1 around a side of the first partition wall PW1 (e.g., surrounding a side of the first partition wall PW1), a second reflective layer RF2 around a side of the second partition wall PW2 (e.g., surrounding a side of the second partition wall PW2), a third reflective layer RF3 disposed on a flat surface between the partition wall unit PW and the light emitting element LE, and a fourth reflective layer RF4 around a side of the light emitting element LE protruding upward from the first via layer VIA1 (e.g., surrounding a side of the light emitting element LE protruding upward from the first via layer VIA1).

[0206] The first reflective layer RF1 and the second reflective layer RF2 may be around the side of the partition wall unit PW (e.g., surround the side of the partition wall unit PW), but if the first partition wall PW1 and the second partition wall PW2 form a step, the first reflective layer RF1 and the second reflective layer RF2 may be disconnected from each other (e.g., spaced apart from each other). The third reflective layer RF3 may be disposed between the first reflective layer RF1 and the fourth reflective layer RF4 on the first insulating layer INS1. The first reflective layer RF1, the third reflective layer RF3, and the fourth reflective layer RF4 may be continuously connected. In one or more embodiments in which the light emitting element LE protrudes from the first insulating layer INS1 to the top of the second via layer VIA2, the fourth reflective layer RF4 may be around at least a portion of the side of the second semiconductor layer SEM2 (e.g., may surround at least a portion of the side of the second semiconductor layer SEM2). The distance between the fourth reflective layer RF4 (i.e., the side wall of the light emitting element LE) and the first partition wall PW1 may be about 4 μm, but is not limited thereto. The reflective layer RF may be disposed on the inner side of the wavelength conversion layer QDL between the partition wall units PW except for the top surface of the light emitting element LE.

[0207] like Fig. 9 As shown in , the reflective layer RF may be disposed to correspond to each of the light emitting areas EA1, EA2, and EA3 and overlap each of the light emitting areas EA1, EA2, and EA3. The reflective layer RF disposed in each of the light emitting areas EA1, EA2, and EA3 may be spaced apart from the reflective layer RF disposed in the adjacent light emitting areas EA1, EA2, and EA3. The reflective layer RF may include a plurality of holes disposed in a plane in an area corresponding to the light emitting element LE. That is, the reflective layer RF may not be formed in an area corresponding to each light emitting element LE.

[0208] The reflective layer RF may reflect light emitted from the light emitting element LE. For example, the first reflective layer RF1, the second reflective layer RF2, and the fourth reflective layer RF4 may reflect light emitted to the side (e.g., in the third direction DR3) from the active layer MQW of the light emitting element LE to the top. The third reflective layer RF3 may reflect light incident on the third reflective layer RF3 that is reflected by the first reflective layer RF1, the second reflective layer RF2, and the fourth reflective layer RF4 and fails to be reflected upward (e.g., in the third direction DR3). In other words, the reflective layer RF may improve the light emitting efficiency of the light emitting element LE.

[0209] In one or more embodiments, Fig. 9 As shown in , a single light emitting element LE can be disposed on a single pixel electrode PE1, PE2, and PE3. Fig.10 As shown in FIG. 1 , a plurality of light emitting elements LE may be disposed on one pixel electrode PE1 , PE2 , and PE3 .

[0210] The second via layer VIA2 , the degradation prevention layer QBANK, and the wavelength conversion layer QDL may be sequentially disposed in this order in the light emitting area EA1 in the space formed by the partition wall unit PW.

[0211] The second via layer VIA2 may planarize the step of the light emitting element LE. The second via layer VIA2 has an opening OP disposed on the light emitting element LE and exposing the first insulating layer INS1. The second via layer VIA2 is not disposed on the top of the light emitting element LE.

[0212] The height of the second via layer VIA2 may be lower than the height of the degradation prevention layer QBANK. The second via layer VIA2 may include the same material as the first via layer VIA1. For example, the second via layer VIA2 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and / or benzocyclobutene (BCB) resin.

[0213] The anti-degradation layer QBANK is disposed on the second via layer VIA2 and the light emitting element LE, and may be in direct contact with the first insulating layer INS1 on the second via layer VIA2 and the light emitting element LE. The anti-degradation layer QBANK prevents heat generated from the light emitting element LE from being directly transferred to the wavelength conversion layer QDL. The wavelength conversion layer QDL may be in direct contact with the anti-degradation layer QBANK. The thickness h1 of the anti-degradation layer QBANK may be smaller than the thickness h2 of the wavelength conversion layer QDL.

[0214] Fig.11 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0215] Reference Fig.11 , the first via layer VIA1 and the above Figures 6 to 10 The embodiment of is different in that the active layer MQW of the light emitting element LE protrudes to the top of the first via layer VIA1. Hereinafter, descriptions repeated with the above-mentioned embodiment will be omitted, and the differences will be described.

[0216] The active layer MQW and the second semiconductor layer SEM2 may protrude onto the top of the first via layer VIA1 , and at least a portion of the first semiconductor layer SEM1 may further protrude from the top of the first via layer VIA1 .

[0217] Therefore, the common electrode CE and the first insulating layer INS1 can be disposed around (for example, surrounding at least a portion of the top surface of the second semiconductor layer SEM2, the side of the second semiconductor layer SEM2, the side of the active layer MQW, and the side of the first semiconductor layer SEM1).

[0218] In addition, the reflective layer RF can be disposed around at least a portion of the side surfaces of the second semiconductor layer SEM2 of the light emitting element LE, the side surfaces of the active layer MQW, and the side surfaces of the first semiconductor layer SEM1 (for example, surrounding at least a portion of the side surfaces of the second semiconductor layer SEM2 of the light emitting element LE, the side surfaces of the active layer MQW, and the side surfaces of the first semiconductor layer SEM1).

[0219] The reflective layer RF is disposed around (eg, surrounds) the side of the active layer MQW that emits light, so that the light emitting efficiency of the light emitting element LE may be further improved.

[0220] Fig.12 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0221] Reference Fig.12 , the light emitting element LE is Fig.11 The embodiment of the present invention is different in that the light emitting element LE has a third semiconductor layer SEM3 on the second semiconductor layer SEM2. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0222] The light emitting element LE may include a connection electrode 150, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer SEM3 arranged along a thickness direction (i.e., a third direction DR3) of the substrate 110. The connection electrode 150, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 may be sequentially stacked along the third direction DR3. The light emitting element LE may include an element insulating layer INS0 around (e.g., surrounding) the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3.

[0223] The third semiconductor layer SEM3 may include the same material as the second semiconductor layer SEM2, but may be a material not doped with an n-type or p-type dopant. In one or more embodiments, the third semiconductor layer SEM3 may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0224] The active layer MQW, the second semiconductor layer SEM2 , and the third semiconductor layer SEM3 may protrude onto the top of the first via layer VIA1 , and at least a portion of the first semiconductor layer SEM1 may further protrude onto the top of the first via layer VIA1 .

[0225] The common electrode CE and the first insulating layer INS1 may be disposed around (for example, surrounding at least a portion of the top surface of the third semiconductor layer SEM3, the side of the third semiconductor layer SEM3, the side of the second semiconductor layer SEM2, the side of the active layer MQW, and the side of the first semiconductor layer SEM1) a top surface of the third semiconductor layer SEM3, a side of the third semiconductor layer SEM3, a side of the second semiconductor layer SEM2, a side of the active layer MQW, and a side of the first semiconductor layer SEM1.

[0226] In addition, the reflective layer RF can be disposed around at least a portion of the side surfaces of the third semiconductor layer SEM3, the side surfaces of the second semiconductor layer SEM2, the side surfaces of the active layer MQW, and the side surfaces of the first semiconductor layer SEM1 of the light emitting element LE (for example, surrounding at least a portion of the side surfaces of the third semiconductor layer SEM3, the side surfaces of the second semiconductor layer SEM2, the side surfaces of the active layer MQW, and the side surfaces of the first semiconductor layer SEM1 of the light emitting element LE).

[0227] The reflective layer RF may be disposed around (eg, surround) a side of the active layer MQW emitting light, so that the light emitting efficiency of the light emitting element LE may be further improved.

[0228] Fig.13 is a cross-sectional view of a pixel electrode and a light emitting element according to one or more embodiments.

[0229] Reference Fig.13 , which is the same as above Figures 6 to 10 The embodiment of FIG. 1 is different in that the element insulating layer INS0 is provided only on a portion of the side surface of the light emitting element LE. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0230] The element insulating layer INS0 is disposed on the sides of the first semiconductor layer SEM1 and the active layer MQW, and may be disposed on a portion of the side of the second semiconductor layer SEM2 . That is, the element insulating layer INS0 may expose at least a portion of the second semiconductor layer SEM2 .

[0231] The side of the second semiconductor layer SEM2 on which the element insulating layer INS0 is not disposed may directly contact the common electrode CE.

[0232] Fig.14 is a cross-sectional view schematically illustrating a display device according to one or more embodiments. Fig.15 is schematically shown with reference to Fig.14 An enlarged view of the first light emitting region is depicted. Fig.16 It shows reference Fig.14 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described.

[0233] Reference Figures 14 to 16 , the display device is the same as the above Figures 6 to 10 The embodiment of is different in that it further includes an element reflection layer RF0 around the side of the light emitting element (eg, surrounding the side of the light emitting element). Hereinafter, descriptions repeated with the above-mentioned embodiment will be omitted, and the differences will be described.

[0234] The element reflective layer RF0 may be disposed on each of the pixel electrodes PE1, PE2, and PE3 and the bank BNL. The element reflective layer RF0 may be disposed around the side of the light emitting element LE (e.g., surrounding the side of the light emitting element LE). For example, the element reflective layer RF0 may be around the outer surface (e.g., the outer peripheral surface or the peripheral surface) of the light emitting element LE (e.g., may surround the outer surface (e.g., the outer peripheral surface or the peripheral surface) of the light emitting element LE), and may be around the side of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE (e.g., may surround the side of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE). The element reflective layer RF0 may completely surround the side of the first semiconductor layer SEM1 and the active layer MQW of the light emitting element LE, and may be around at least a portion of the side of the second semiconductor layer SEM2 (e.g., may surround at least a portion of the side of the second semiconductor layer SEM2). The element reflection layer RF0 may extend from the top surface of each pixel electrode PE1, PE2, and PE3 in the third direction DR3 to be around the light emitting element LE (e.g., surrounding the light emitting element LE), but may be arranged to be lower than the height of the light emitting element LE. In one or more embodiments, an interlayer insulating layer (e.g., element insulating layer INS0) may also be arranged between the element reflection layer RF0 and each pixel electrode PE1, PE2, and PE3. The interlayer insulating layer (e.g., element insulating layer INS0) may insulate the element reflection layer RF0 from each pixel electrode PE1, PE2, and PE3. The element reflection layer RF0 may be arranged to be in direct contact with the element insulating layer INS0 of the light emitting element LE.

[0235] The element reflective layer RF0 may reflect light emitted from the light emitting element LE. For example, the element reflective layer RF0 may reflect light emitted from the active layer MQW of the light emitting element LE to the side (for example, in the third direction DR3) toward the top. That is, the element reflective layer RF0 may improve the light emitting efficiency of the light emitting element LE. To this end, the element reflective layer RF0 may be arranged at least around the side of the active layer MQW of the light emitting element LE (for example, at least around the side of the active layer MQW of the light emitting element LE). The height of the element reflective layer RF0 in contact with the light emitting element LE may be smaller than the height of the light emitting element LE (for example, at least 50% of the height of the light emitting element LE). For example, if the height of the light emitting element LE is 10 μm, the height of the element reflective layer RF0 may be 5 μm or more and 10 μm or less. Therefore, the element reflective layer RF0 may be arranged around the entire side of the active layer MQW of the light emitting element LE (for example, around the entire side of the active layer MQW of the light emitting element LE), and may reflect light emitted from the active layer MQW.

[0236] The element reflection layer RF0 may include a metal material having high reflectivity. For example, the element reflection layer RF0 may include aluminum and / or silver, and / or may be an alloy thereof.

[0237] The element reflective layer RF0 disposed in each light emitting area EA1, EA2, and EA3 may be spaced apart from the element reflective layer RF0 disposed in the adjacent light emitting areas EA1, EA2, and EA3. In addition, the element reflective layer RF0 may include a plurality of holes disposed in an area corresponding to the planar light emitting element LE. That is, the element reflective layer RF0 may not be formed in an area corresponding to each light emitting element LE.

[0238] The display device 10 according to the present embodiment can reflect light emitted from the light emitting element LE to the top by including the element reflection layer RF0 around the side of the light emitting element LE (eg, surrounding the side of the light emitting element LE). Therefore, the element reflection layer RF0 can improve the light emitting efficiency of the light emitting element LE.

[0239] Fig.17 is a cross-sectional view schematically illustrating a display device according to one or more embodiments. Fig.18 is schematically shown with reference to Fig.17 An enlarged view of the first light emitting region is depicted.

[0240] Reference Fig.17 and Fig.18 The wavelength control unit 200 is the same as described above. Figures 6 to 10 The embodiment of is different in that it does not include the degradation preventing layer QBANK. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and the differences will be described.

[0241] The wavelength control unit 200 may include a second via layer VIA2 , a wavelength conversion layer QDL, a second insulating layer INS2 , a reflective layer RF, and a partition wall unit PW.

[0242] The second via layer VIA2 and the wavelength conversion layer QDL may be sequentially disposed in a space overlapping each of the light emitting areas EA1, EA2, and EA3 and formed by the partition wall unit PW. That is, the wavelength conversion layer QDL may be disposed in contact with the second via layer VIA2 and the first insulating layer INS1 on the common electrode CE.

[0243] Fig.19 is a cross-sectional view schematically illustrating a display device according to one or more embodiments. Fig. 20 Refer to the detailed Fig.19 An enlarged layout diagram of one example of touch nodes is described.

[0244] Reference Fig.19 and Fig. 20, the display device is the same as above Figures 6 to 10 The embodiment of is different in that the display device further includes a touch detection unit TDU, and a light blocking pattern BM is further disposed under the color filters CF1, CF2, and CF3. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0245] The touch detection unit TDU may be disposed between the first overcoat layer OC1 and the color filters CF1 , CF2 , and CF3 .

[0246] The touch detection unit TDU includes a first touch insulation layer TINS1, a first connection unit BE1, a second touch insulation layer TINS2, a driving electrode TE, a sensing electrode RE, and a third touch insulation layer TINS3.

[0247] The first touch insulating layer TINS1 may be formed of an inorganic layer (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0248] The first connection unit BE1 may be disposed on the first touch insulating layer TINS1. The first connection unit BE1 may be formed as a single layer or multiple layers of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or alloys thereof.

[0249] The second touch insulating layer TINS2 is disposed on the first connection unit BE1. The second touch insulating layer TINS2 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer). Alternatively, the second touch insulating layer TINS2 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0250] The driving electrodes TE and the sensing electrodes RE may be disposed on the second touch insulating layer TINS2. In addition to the driving electrodes TE and the sensing electrodes RE, dummy patterns, first touch driving lines, second touch driving lines, and touch sensing lines may be disposed on the second touch insulating layer TINS2. The driving electrodes TE and the sensing electrodes RE may be formed as a single layer or multiple layers of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or alloys thereof.

[0251] The driving electrode TE and the sensing electrode RE may overlap the first connection unit BE1 in the third direction DR3. The driving electrode TE may be connected to the first connection unit BE1 through a touch contact hole TCNT1 passing through the second touch insulating layer TINS2.

[0252] The third touch insulating layer TINS3 is formed on the driving electrode TE and the sensing electrode RE. The third touch insulating layer TINS3 may be used to flatten the step formed by the driving electrode TE, the sensing electrode RE, and the first connection unit BE1. The third touch insulating layer TINS3 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0253] The touch node TN may be defined as a crossing point of the driving electrode TE and the sensing electrode RE.

[0254] Since the plurality of driving electrodes TE and the plurality of sensing electrodes RE are disposed in the same layer (eg, at the same layer), they may be spaced apart from each other. That is, a gap may be formed between the driving electrodes TE and the sensing electrodes RE adjacent to each other.

[0255] In addition, the plurality of dummy patterns may also be disposed on the same layer (eg, at the same layer) as the plurality of driving electrodes TE and sensing electrodes RE. That is, gaps may be formed between adjacent driving electrodes TE and dummy patterns and between adjacent sensing electrodes RE and dummy patterns.

[0256] The plurality of first connection units BE1 may be disposed at a different layer (eg, at a different layer) from the plurality of driving electrodes TE and the plurality of sensing electrodes RE. The plurality of first connection units BE1 may be formed to be bent at least once. Fig. 20 , the plurality of first connection units BE1 are shown as having a planar shape of an angle bracket ("<" or ">"), but the planar shape of the plurality of first connection units BE1 is not limited thereto. Since the driving electrodes TE adjacent to each other in the second direction DR2 are connected by the plurality of first connection units BE1, the connection between the driving electrodes TE adjacent to each other in the second direction DR2 can be maintained even if any one of the plurality of first connection units BE1 is disconnected. Fig. 20 It is shown that adjacent driving electrodes TE are connected through two first connection units BE1 , but the number of the first connection units BE1 is not limited thereto.

[0257] Each of the plurality of first connection units BE1 may overlap with the adjacent driving electrode TE in the third direction DR3 which is the thickness direction of the substrate 110. Each of the plurality of first connection units BE1 may overlap with the sensing electrode RE in the third direction DR3. One side of the first connection unit BE1 may be connected to one of the driving electrodes TE adjacent in the second direction DR2 through the touch contact hole TCNT1. The other side of the first connection unit BE1 may be connected to another driving electrode TE among the driving electrodes TE adjacent in the second direction DR2 through the touch contact hole TCNT1.

[0258] Due to the plurality of first connection units BE1, the plurality of driving electrodes TE and the plurality of sensing electrodes RE may be electrically separated at each of their intersection portions. Therefore, mutual capacitance may be formed at each intersection of the plurality of driving electrodes TE and the plurality of sensing electrodes RE.

[0259] Each of the plurality of driving electrodes TE, the plurality of sensing electrodes RE, and the plurality of first connection units BE1 may have a planar shape or a mesh structure. In addition, each of the plurality of dummy patterns may have a planar shape or a mesh structure. Therefore, each of the plurality of driving electrodes TE, the plurality of sensing electrodes RE, the plurality of first connection units BE1, and the plurality of dummy patterns may not overlap with the plurality of light emitting areas EA1, EA2, EA3, and EA4 of each of the plurality of pixels PX. Therefore, the light emitted from the plurality of light emitting areas EA1, EA2, EA3, and EA4 may not be blocked by the plurality of driving electrodes TE, the plurality of sensing electrodes RE, the plurality of first connection units BE1, and the plurality of dummy patterns to prevent the brightness of the light from being reduced.

[0260] Each of the plurality of pixels PX includes a first light emitting region EA1 emitting light of a first color, a second light emitting region EA2 emitting light of a second color, a third light emitting region EA3 emitting light of a third color, and a fourth light emitting region EA4 emitting light of the second color. For example, the first color may be red, the second color may be green, and the third color may be blue.

[0261] In the present embodiment, a single pixel PX includes four light emitting areas EA1, EA2, EA3, and EA4, but is not limited thereto.

[0262] Fig.19 It can be along Fig. 20 An example of a display panel taken along line II'.

[0263] In one or more embodiments, the first light emitting region EA1 and the second light emitting region EA2 of each of the plurality of pixels PX may be adjacent to each other in the fourth direction DR4, and the third light emitting region EA3 and the fourth light emitting region EA4 may be adjacent to each other in the fourth direction DR4. The first light emitting region EA1 and the fourth light emitting region EA4 of each of the plurality of pixels PX may be adjacent to each other in the fifth direction DR5, and the second light emitting region EA2 and the third light emitting region EA3 may be adjacent to each other in the fifth direction DR5.

[0264] Each of the first light emitting area EA1, the second light emitting area EA2, the third light emitting area EA3, and the fourth light emitting area EA4 may have a rhombus plane shape or a rectangular plane shape, but is not limited thereto. Each of the first light emitting area EA1, the second light emitting area EA2, the third light emitting area EA3, and the fourth light emitting area EA4 may have a polygonal, circular, and / or elliptical plane shape other than a square. In addition, Fig. 20 It is shown that the first light emitting area EA1, the second light emitting area EA2, the third light emitting area EA3, and the fourth light emitting area EA4 have the same area, but is not limited thereto.

[0265] The second light emitting area EA2 and the fourth light emitting area EA4 may be arranged in odd rows. The second light emitting area EA2 and the fourth light emitting area EA4 may be arranged side by side in each of the odd rows in the first direction DR1. The second light emitting area EA2 and the fourth light emitting area EA4 may be alternately arranged in each odd row. Each of the second light emitting areas EA2 may have a short side in the fourth direction DR4 and a long side in the fifth direction DR5, while each of the fourth light emitting areas EA4 may have a long side in the fourth direction DR4 and a short side in the fifth direction DR5. The fourth direction DR4 is a direction between the first direction DR1 and the second direction DR2, and may be a direction inclined 45 degrees relative to the first direction DR1. The fifth direction DR5 may be a direction perpendicular to the fourth direction DR4.

[0266] The first and third light emitting regions EA1 and EA3 may be arranged in even-numbered rows. The first and third light emitting regions EA1 and EA3 may be arranged side by side in the first direction DR1 in each of the even-numbered rows. The first and third light emitting regions EA1 and EA3 may be alternately arranged in each even-numbered row.

[0267] The second and fourth light emitting regions EA2 and EA4 may be arranged in odd columns. The second and fourth light emitting regions EA2 and EA4 may be arranged side by side in each of the odd columns in the second direction DR2. The second and fourth light emitting regions EA2 and EA4 may be alternately arranged in each odd column.

[0268] The first and third light emitting regions EA1 and EA3 may be arranged in even columns. The first and third light emitting regions EA1 and EA3 may be arranged side by side in each of the even columns in the second direction DR2. The first and third light emitting regions EA1 and EA3 may be alternately arranged in each of the even columns.

[0269] In one or more embodiments, a light blocking pattern BM may be further included between the touch detection unit TDU and the color filters CF1, CF2, and CF3. The light blocking pattern BM may be formed of a photosensitive resin capable of blocking light. For example, the light blocking pattern BM may include an inorganic black pigment such as carbon black or an organic black pigment. The light blocking pattern BM may overlap the non-luminous area NEA but not the luminous areas EA1, EA2, and EA3. Therefore, even if the light emitted from the light emitting element LE travels to the light blocking pattern BM, the light does not pass through the light blocking pattern BM. Therefore, the light blocking pattern BM can prevent color mixing between adjacent luminous areas.

[0270] Fig.21 is a cross-sectional view schematically illustrating a display device according to one or more embodiments. Fig. 22 is schematically shown with reference to Fig.21 An enlarged view of the first light emitting region is depicted. Fig.23 It shows reference Fig. 22 Cross-sectional views of a pixel electrode and a light emitting element according to one or more embodiments are described.

[0271] Reference Figure 21 to Figure 23 , the light emitting element PLE is the same as described above Figures 6 to 10 The embodiment of the present invention is different in that the light emitting element PLE is a flip chip type light emitting element and an anode pad electrode APD and a cathode pad electrode CPD are provided instead of the pixel electrodes PE1, PE2 and PE3 and the common electrode CE. Hereinafter, the description repeated with the above embodiment will be omitted and the differences will be described.

[0272] An anode pad electrode APD and a cathode pad electrode CPD may be disposed on the second planarization layer 130 .

[0273] Function and reference of anode pad electrode APD Figures 6 to 10 The pixel electrodes PE1, PE2 and PE3 described above correspond to each other, and the function of the cathode pad electrode CPD is the same as that of the reference Figures 6 to 10 The common electrode CE described corresponds to.

[0274] The anode pad electrode APD and the cathode pad electrode CPD may be disposed in each of the light emitting areas EA1, EA2, and EA3. The anode pad electrode APD and the cathode pad electrode CPD disposed in each of the light emitting areas EA1, EA2, and EA3 may be spaced apart from each other.

[0275] The anode pad electrode APD and the cathode pad electrode CPD may be formed as a single layer or a multilayer of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or alloys thereof.

[0276] The anode pad electrode APD is directly connected to the pixel connection electrode 125 through a contact hole passing through the second planarization layer 130 , and may be electrically connected to each of the switching elements T1 , T2 , and T3 through the pixel connection electrode 125 .

[0277] The cathode pad electrode CPD may be supplied with a first power supply voltage which is a low potential voltage.

[0278] A transparent conductive layer TCO may be included on each of the anode pad electrode APD and the cathode pad electrode CPD to enhance adhesion with the first contact electrode CTE1 and the second contact electrode CTE2 of the flip-chip light emitting element PLE. The transparent conductive layer TCO may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0279] The flip-chip light emitting element PLE is a flip-chip type micro LED in which the first contact electrode CTE1 and the second contact electrode CTE2 are disposed opposite to the anode pad electrode APD and the cathode pad electrode CPD.

[0280] The flip-chip light emitting element PLE may be an inorganic light emitting element made of an inorganic material such as GaN. The flip-chip light emitting element PLE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several μm to several hundred μm, respectively. For example, the flip-chip light emitting element PLE may be 10 μm×25 μm, but is not limited thereto.

[0281] The flip-chip light emitting element PLE may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the flip-chip light emitting elements PLE may be directly transferred from the silicon wafer to the anode pad electrode APD and the cathode pad electrode CPD of the substrate 110. Alternatively, each of the flip-chip light emitting elements PLE may be transferred to the anode pad electrode APD and the cathode pad electrode CPD of the substrate 110 by an electrostatic method using an electrostatic head or by a stamping method using an elastic polymer material such as PDMS or silicone resin as a transfer substrate.

[0282] The first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other through a welding process.

[0283] The flip-chip light emitting element PLE may be a light emitting structure including a base substrate PSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1 and a second contact electrode CTE2.

[0284] The base substrate PSUB of the flip-chip light emitting element PLE may be a sapphire substrate, but is not limited thereto.

[0285] The n-type semiconductor NSEM of the flip chip light emitting element PLE may be disposed on one side of the base substrate PSUB. For example, the n-type semiconductor NSEM may be disposed on the bottom surface of the base substrate PSUB. The n-type semiconductor NSEM may be made of GaN doped with n-type conductive dopants such as Se, Si, Ge, and / or Sn. Figures 6 to 10 The described second semiconductor layer SEM2 of the light emitting element LE corresponds.

[0286] The active layer MQW of the flip-chip light emitting element PLE may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, it may be a stacked structure having a plurality of well layers and barrier layers alternating with each other. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto.

[0287] Alternatively, the active layer MQW may be a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked on top of each other, and may include three to five semiconductor materials according to the wavelength of emitted light.

[0288] The p-type semiconductor PSEM may be disposed on one side of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Sr, Ba, etc. Figures 6 to 10 The described first semiconductor layer SEM1 of the light emitting element LE corresponds.

[0289] The first contact electrode CTE1 may be disposed on one side of the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on another portion of one surface of the n-type semiconductor NSEM. The first contact electrode CTE1 and the second contact electrode CTE2 do not directly contact each other. Another portion of one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed away from a portion of one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0290] As reference Figure 21 to Figure 23As described above, even in a display device using the flip-chip light emitting element PLE, the reflective layer RF may be arranged around the side surfaces of the partition wall unit PW, at least some side surfaces of the n-type semiconductor NSEM, and the bottom surface between the partition wall unit PW and the flip-chip light emitting element PLE on the first insulating layer INS1 (e.g., around the side surfaces of the partition wall unit PW, at least some side surfaces of the n-type semiconductor NSEM, and the bottom surface between the partition wall unit PW and the flip-chip light emitting element PLE on the first insulating layer INS1). Therefore, the light emitting efficiency of the flip-chip light emitting element PLE may be improved.

[0291] Figures 24 to 43 is a diagram for illustrating a method of manufacturing a display device according to one or more embodiments.

[0292] Figures 24 to 43 The structure of each layer of the display device 10 is shown in the cross-sectional view in the order of formation. Figures 24 to 43 Focusing on the manufacturing process of the light emitting element unit LEP, it can be respectively Figures 6 to 8 In addition, the following will focus on the first light emitting area EA1 of the display device 10.

[0293] Reference Fig.24 and Fig.25 , a plurality of light emitting elements LE are formed on the base substrate BSUB.

[0294] Specifically, a base substrate BSUB is prepared. The base substrate BSUB may be a sapphire base Al 2 O 3 Or a silicon wafer including silicon. However, it is not limited thereto, and in one or more embodiments, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0295] A plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L are formed on the base substrate BSUB. The plurality of semiconductor material layers grown by the epitaxial method can be formed by growing a seed crystal. The method for forming the semiconductor material layer includes electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD) and plasma laser deposition (PLD), dual-type thermal evaporation, sputtering and / or metal organic chemical vapor deposition (MOCVD), etc., and is preferably formed by metal organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0296] The precursor material used to form the plurality of semiconductor material layers is not particularly limited within the range that can be conventionally selected to form the target material. In one example, the precursor material can be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, it can be a precursor such as trimethylgallium (Ga(CH 3) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but not limited thereto.

[0297] Specifically, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although the drawings show a further stacked third semiconductor material layer SEM3L, it is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer SEM3L may be configured to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer SEM3L may include an undoped semiconductor, which may be an n-type undoped material or a p-type undoped material. In one or more embodiments, the third semiconductor material layer SEM3L may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0298] By using the above-described method, the second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L.

[0299] Next, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L are etched to form a plurality of light emitting elements LE.

[0300] Specifically, a plurality of first mask patterns MP1 are formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern MP1 prevents the underlying semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L from being etched. Next, a portion of the plurality of semiconductor material layers is etched using the plurality of first mask patterns MP1 as a mask to form a plurality of light emitting elements LE.

[0301] like Fig.25 As shown in FIG. 1 , on the base substrate BSUB, a plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L not overlapping the first mask pattern MP1 are etched and removed, and the unetched portions overlapping the first mask pattern MP1 may be formed into a plurality of light emitting elements LE.

[0302] The semiconductor material layer may be etched by conventional methods. For example, the process for etching the semiconductor material layer may be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE) and / or inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible and may be suitable for vertical etching. When the above etching methods are used, the etchant may be Cl 2 or 2 However, it is not limited thereto.

[0303] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L overlapping the first mask pattern MP1 are not etched and may be formed into a plurality of light emitting elements LE. Thus, the plurality of light emitting elements LE are formed to include the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1.

[0304] Next, refer to Fig.26 and Fig. 27 , an element insulating layer INS0 is formed on the base substrate BSUB on which the light emitting element LE is formed.

[0305] Specifically, an insulating material layer INSL is formed on the outer surfaces of the plurality of light emitting elements LE. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting elements LE but also on the top surface of the base substrate BSUB exposed by the light emitting elements LE.

[0306] Next, a second etching (secondary etching) process is performed to partially remove the insulating material layer INSL, thereby forming the light emitting element LE including the element insulating layer INS0.

[0307] Specifically, a second etching (secondary etching) process may be performed in which the insulating material layer INSL is partially removed so that the insulating material layer INSL exposes the top surface of the light emitting element LE but surrounds the side of the light emitting element LE. Specifically, in this process, a portion of the insulating material layer INSL may be removed to expose the top surface of the first semiconductor layer SEM1 of the light emitting element LE. The process of partially removing the insulating material layer INSL may be performed using an anisotropic dry etching or etch-back process.

[0308] Next, refer to Fig.28 , a connection electrode 150 is formed on the first semiconductor layer SEM1 of the light emitting element LE.

[0309] The connection electrode 150 may be formed on the first semiconductor layer SEM1 by stacking an electrode material layer on the base substrate BSUB and then etching the electrode material layer through an etching process. In one or more embodiments, the connection electrode 150 may include a reflective layer ( Figure 8 151 in) and the connection layer ( Figure 8 153 in ).

[0310] Next, refer to Fig.29 , will be Fig.28 The plurality of light emitting elements LE of the base substrate BSUB manufactured in the process are attached to the carrier substrate SPF1.

[0311] Specifically, the base substrate BSUB is positioned on the carrier substrate SPF1.

[0312] The carrier substrate SPF1 may be made of a transparent and mechanically stable material so that light can be transmitted. For example, the carrier substrate SPF1 may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene and / or polyethylene terephthalate.

[0313] An adhesive layer S1 having adhesive force may be further provided on the carrier substrate SPF1. The adhesive layer S1 may include an adhesive material for bonding the light emitting element LE. For example, the adhesive material may include polyurethane acrylate, epoxy acrylate, and / or polyester acrylate, etc. The adhesive material may be a material whose adhesiveness changes when ultraviolet (UV) or heat is applied, so that the adhesive layer can be easily separated from the light emitting element LE.

[0314] The plurality of light emitting elements LE may be aligned on the adhesive layer S1 and the connection electrodes 150 of the plurality of light emitting elements LE may be attached to the adhesive layer S1. The plurality of light emitting elements LE are arranged in large numbers and may be attached to the carrier substrate SPF1 without being separated therefrom.

[0315] Then, refer to Fig.30 The base substrate BSUB is irradiated with the first laser to separate the plurality of light emitting elements LE from the base substrate BSUB. The base substrate BSUB is separated from each third semiconductor layer SEM3 of the plurality of light emitting elements LE.

[0316] The process for separating the base substrate BSUB may be performed by a laser lift-off (LLO) process. The laser lift-off process utilizes laser, and KrF excimer laser (248 nm wavelength) may be used as a source. The energy density of the excimer laser is about 550 mJ / cm 2 Up to 950mJ / cm 2 The incident area can be 50×50μm 2 Up to 1×1cm2 The base substrate BSUB may be separated from the plurality of light emitting elements LE by irradiating the base substrate BSUB with laser. Subsequently, the adhesive layer S1 may be patterned by an etching process using the light emitting elements LE as a mask. Thereafter, wet cleaning may be performed to remove residues and debris on the carrier substrate SPF1.

[0317] Then, refer to Fig.31 and Fig.32 , the plurality of light emitting elements LE separated from the base substrate BSUB are selectively transferred to the relay substrate SPF2.

[0318] Specifically, a plurality of light emitting elements LE are disposed on a relay substrate SPF2. Each third semiconductor layer SEM3 of the plurality of light emitting elements LE is disposed on the relay substrate SPF2. The relay substrate SPF2 may include a support layer and an adhesive layer. The support layer may be made of a transparent and mechanically stable material that allows light to pass through. For example, the support layer may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene and / or polyethylene terephthalate.

[0319] An adhesive layer having adhesive force may be provided on the support layer. The adhesive layer may include an adhesive material for bonding the light emitting element LE. For example, the adhesive material may include polyurethane acrylate, epoxy acrylate, and / or polyester acrylate, etc. The adhesive material may be a material whose adhesiveness changes when ultraviolet (UV) or heat is applied, so that the adhesive layer can be easily separated from the light emitting element LE.

[0320] Considering the arrangement interval of the plurality of light emitting elements LE disposed on the relay substrate SPF2, the laser is selectively irradiated to the desired light emitting element LE. The adhesiveness of the adhesive layer attached to the light emitting element LE irradiated by the laser may be reduced, and the light emitting element LE may be physically or naturally separated from the carrier substrate SPF1.

[0321] Next, refer to Fig.33 and Fig.34 , the light emitting element LE on the relay substrate SPF2 is transferred to the substrate 110.

[0322] Specifically, a substrate 110 is prepared. Figure 6 As described above, the substrate 110 may have the pixel electrode PE1 and the bank BNL formed thereon.

[0323] The connection electrode 150 of the light emitting element LE disposed on the relay substrate SPF2 is aligned to face the substrate 110 .

[0324] Next, the substrate 110 is bonded to the relay substrate SPF2. Specifically, the connection electrode 150 of the light emitting element LE formed on the relay substrate SPF2 is contacted with the pixel electrode PE1 of the substrate 110. At this time, the connection electrode 150 of the light emitting element LE may be in contact with the pixel electrode PE1. Next, the connection electrode 150 of the light emitting element LE and the pixel electrode PE1 are melt-bonded to bond the substrate 110 and the relay substrate SPF2. At this time, a plurality of light emitting elements LE are attached to the top surface of the pixel electrode PE1.

[0325] The fusion bonding may be achieved by irradiating the pixel electrode PE1 with laser on the top of the relay substrate SPF2. The pixel electrode PE1 irradiated with laser may conduct the high heat of the laser to bond the interface of the connection electrode 150 of the light emitting element LE and the pixel electrode PE1. In particular, the pixel electrode PE1 may include copper (Cu) having excellent thermal conductivity, and thus may have excellent adhesion with the connection electrode 150 of the light emitting element LE. The laser source for the fusion bonding may be YAG.

[0326] Next, the relay substrate SPF2 is separated from the plurality of light emitting elements LE.

[0327] Specifically, the relay substrate SPF2 is separated from the light emitting element LE. The process of separating the relay substrate SPF2 can be completed using a laser lift-off (LLO) process. Since the laser lift-off process has been described above, the description will be omitted. By irradiating the relay substrate SPF2 with laser, the relay substrate SPF2 can be separated from the light emitting element LE.

[0328] As another example, the process of separating the relay substrate SPF2 may be a physical separation other than the laser lift-off process. Because the bonding force between the relay substrate SPF2 and the light emitting element LE is less than the molten bonding bonding force between the connection electrode 150 of the light emitting element LE and the pixel electrode PE1, the relay substrate SPF2 may be physically separated based on the difference in bonding force. At this time, the third semiconductor layer SEM3 of the light emitting element LE has low conductivity and may be removed for connection with the common electrode CE. The third semiconductor layer SEM3 may be removed using a dry etching process.

[0329] Next, refer to Fig.35 , a first via layer VIA1 is formed on the substrate 110 on which the light emitting element LE is formed.

[0330] Specifically, a first via layer VIA1 may be formed on the pixel electrode PE1 and the bank BNL. The first via layer VIA1 may be applied using a solution process such as spin coating or inkjet printing. The first via layer VIA1 may be formed to be lower than the height of the light emitting element LE. For example, the first via layer VIA1 may be formed to be greater than the height of the active layer MQW.

[0331] Next, refer to Fig.36 , a common electrode CE and a first insulating layer INS1 are formed on the first via layer VIA1 and the light emitting element LE.

[0332] The common electrode CE is continuously formed throughout the display area. The common electrode CE covers the first via layer VIA1 and the light emitting element LE and is in direct contact with the first via layer VIA1 and the light emitting element LE. The common electrode CE is formed to be in direct contact with at least a portion of the top surface and the side surface of the second semiconductor layer SEM2 of the light emitting element LE. The first insulating layer INS1 may be formed on the common electrode CE.

[0333] Next, refer to Fig.37 , a partition wall unit PW is formed on the first insulating layer INS1 (see Figure 7 ).

[0334] Specifically, the first partition wall PW1 is formed on the first insulating layer INS1 using various materials such as a polymer or a photoresist (PR) material using an inkjet printing method or the like. The first partition wall PW1 has a first width WH1 (see FIG. 1 ) in the first direction DR1. Figure 7 ) is formed in the non-emission area NEA. In addition, a first partition wall PW1 is formed on the bank BNL.

[0335] Then, the second partition wall PW2 is formed on the first partition wall PW1. The second partition wall PW2 is formed on the first partition wall PW1 to have a second width WH2 in the first direction DR1 (see FIG. 2 ). Figure 7 ). The second width WH2 may be narrower than the first width WH1.

[0336] Next, refer to Fig.38 , a second insulating layer INS2 and a reflective material layer RFL are formed on the partition wall unit PW.

[0337] The second insulating layer INS2 may be formed to cover all the light emitting elements LE and the partition wall unit PW protruding on the first via layer VIA1. Next, a reflective material layer RFL is formed on the second insulating layer INS2. The reflective material layer RFL may be formed on the second insulating layer INS2 to cover all the light emitting elements LE and the partition wall unit PW protruding on the first via layer VIA1.

[0338] Next, refer to Fig.39 , a second via layer VIA2 is formed in the opening formed between the partition wall units PW.

[0339] The second via layer VIA2 may be manufactured in the same manner as the first via layer VIA1 described above and may be spaced apart from each other between adjacent light emitting areas in each light emitting area EA1. The second via layer VIA2 may be formed to have a height lower than that of the reflective material layer RFL covering the light emitting element LE.

[0340] Next, refer to Fig.40 , etching the reflective material layer RFL to form the reflective layer RF. The reflective material layer RFL may be etched using the second via layer VIA2 as a mask. A large voltage difference is formed in the third direction DR3 using the second via layer VIA2 as a mask, and the reflective material layer RFL is etched using an etching material. In this case, the etchant moves in the third direction DR3 (i.e., from the top to the bottom) by voltage control, and the reflective material layer RFL may be etched. Therefore, the reflective material layer RFL disposed on the horizontal plane defined by the first direction DR1 and the second direction DR2 is removed, while the reflective material layer RFL disposed on the vertical plane defined by the third direction DR3 may not be removed. Therefore, the reflective material layer RFL formed by the step difference between the first partition wall PW1 and the second partition wall PW2 and the reflective material layer RFL formed on the light emitting element LE may be removed. The reflective material layer RFL disposed on the side of the first partition wall PW1 and the second partition wall PW2 may not be removed. In addition, the reflective material layer RFL disposed at the bottom of the second via layer VIA2 may not be removed.

[0341] Next, refer to Fig.41 and Fig.42 , in the opening OP1 (see Fig.40 ) is formed in a degradation prevention layer QBANK and a wavelength conversion layer QDL.

[0342] The degradation preventing layer QBANK is formed on the second via layer VIA2 between the partition wall unit PW and the adjacent partition wall unit PW and the light emitting element LE, and the first wavelength conversion pattern WCL1 is formed on the degradation preventing layer QBANK.

[0343] The degradation prevention layer QBANK may be formed by a solution process (such as inkjet printing, embossing, etc.) of a solution in which the third base resin BRS3 is mixed with the scatterer SCP, but is not limited thereto. Each of the degradation prevention layers QBANK may be formed in a plurality of openings OP1 and may be formed to overlap with a plurality of light emitting regions. The height of the degradation prevention layer QBANK may be formed to be lower than the height of the wavelength conversion layer QDL.

[0344] The first wavelength conversion pattern WCL1 may be formed by a solution process (such as inkjet printing, embossing, etc.) of a solution including a first matrix resin BRS1, first wavelength conversion particles WCP1, and scatterers SCP, but is not limited thereto. Each wavelength conversion layer QDL may be formed within a plurality of openings OP1 and may be formed to overlap a plurality of light emitting regions.

[0345] like Fig.43 As shown in FIG, a capping layer CAP, a first overcoating layer OC1, a color filter CF1, and a second overcoating layer OC2 are formed.

[0346] The color filter CF1 may be formed by a patterning process. The thickness of the color filter CF1 may be 1 μm or less, but is not limited thereto. Similarly, other color filters are also formed by a patterning process to overlap each opening.

[0347] Fig.44 is an exemplary diagram illustrating a virtual reality device including a display device according to one or more embodiments. Fig.44 A virtual reality device 1 is shown in which a display device 10 according to one or more embodiments is used.

[0348] Reference Fig.44 The virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, left legs 30a and right legs 30b, a reflective member 40, and a display device housing 50.

[0349] Fig.44 The virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used for a head-mounted display including a head-mounted band that can be worn on the head instead of the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Fig.44 The examples shown in the figure can be applied in various electronic devices in various forms.

[0350] The display device housing 50 can accommodate the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0351] Fig.44The display device housing 50 is shown to be disposed at the right end of the supporting frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the supporting frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and provided to the left eye of the user via the left eye lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be disposed at each of the left and right ends of the supporting frame 20. In this case, the user may view the virtual reality image displayed on the display device 10 via both the left eye and the right eye.

[0352] Fig.45 is an exemplary diagram illustrating a smart device including a display device according to one or more embodiments.

[0353] Reference Fig.45 , the display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of smart devices.

[0354] Fig.46 is an exemplary diagram illustrating a vehicle including a display device according to one or more embodiments. Fig.46 A vehicle in which a display device according to one or more embodiments is used is shown.

[0355] Reference Fig.46 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, to a central dashboard of a vehicle, or to a central information display (CID) provided on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display that replaces each of the side mirrors of the vehicle.

[0356] Fig.47 is an exemplary diagram illustrating a transparent display device including a display device according to one or more embodiments.

[0357] Reference Fig.47 , the display device according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device may not only see the image IM displayed on the display device 10, but also see an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 The substrate 110 of the display device 10 shown in FIG. 1 may include a light transmitting portion through which light may be transmitted, or may be made of a material through which light may be transmitted.

[0358] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to one or more embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used only in a general and descriptive sense, and not for the purpose of limitation.

[0359] In addition, the aspects and features of the disclosed embodiments are not limited to the aspects and features set forth herein. The above and other aspects and features of the disclosed embodiments will become more apparent to those skilled in the art by referring to the claims and their functional equivalents included therein.

Claims

1. A display device, comprising: A pixel electrode, on the substrate; A bank layer, on the substrate and the pixel electrode, and dividing the light-emitting area and the non-light-emitting area; a light emitting element, which is on the pixel electrode and includes a first semiconductor layer, a second semiconductor layer and an active layer disposed between the first semiconductor layer and the second semiconductor layer; A first via layer, on the pixel electrode and around at least a portion of a side surface of the light emitting element; a common electrode on the first via layer, a side surface of the light emitting element protruding from the first via layer, and a top surface of the light emitting element; a first insulating layer, on the common electrode; a partition wall unit on the first insulating layer and overlapping the bank layer; a second insulating layer on the partition wall unit; a reflective layer located around the side of the partition wall unit on the second insulating layer and around the side of the light emitting element on the first insulating layer, and located on the first insulating layer between the partition wall unit and the light emitting element; a second via layer between the partition wall units and having an opening exposing the first insulating layer on the light emitting element; as well as The wavelength conversion layer is on the second via layer. 2 . The display device according to claim 1 , further comprising a degradation prevention layer located between the second via layer and the wavelength conversion layer and comprising a base resin and a scatterer.

3. The display device according to claim 2, wherein: The partition wall unit includes a first partition wall on the first insulating layer and having a first width and a second partition wall on the first partition wall and having a second width, Wherein, the first width is greater than the second width.

4. The display device according to claim 3, wherein: The reflective layer includes a first reflective layer around a side surface of the first partition wall, a second reflective layer around a side surface of the second partition wall, a third reflective layer around a portion of the side surface of the light emitting element, and a fourth reflective layer located between the first reflective layer and the third reflective layer and between the second via layer and the first insulating layer.

5. The display device according to claim 4, wherein: The third reflective layer contacts the first insulating layer and has a height equal to that of the second via layer.

6. The display device according to claim 5, wherein: The third reflective layer is located on the first insulating layer around at least a portion of a side surface of the second semiconductor layer of the light emitting element.

7. The display device according to claim 4, wherein: The first via layer covers the bank layer and the portion of the pixel electrode on which the light emitting element is not disposed. The second via layer covers the fourth reflective layer between the partition wall units and surrounds the third reflective layer.

8. The display device according to claim 1, wherein: The light emitting element further includes an element insulating layer around the first semiconductor layer, the active layer, and the second semiconductor layer, and a connection electrode between the first semiconductor layer and the pixel electrode. 9 . The display device according to claim 8 , further comprising an element reflection layer spaced apart from the common electrode and located around at least a portion of a side surface of the light emitting element on the element insulating layer. 10 . The display device according to claim 2 , further comprising a capping layer, a coating layer, and a color filter layer sequentially disposed on the wavelength conversion layer and the partition wall unit. 11 . The display device according to claim 10 , further comprising a touch sensing unit between the overcoat layer and the color filter layer.

12. A display device, comprising: a first electrode and a second electrode on the substrate; a bank layer on the substrate, the first electrode and the second electrode, and dividing a light emitting area and a non-light emitting area; A light emitting element, comprising a first contact electrode, a second contact electrode, a first semiconductor layer on the first contact electrode, an active layer, and a second semiconductor layer on the second contact electrode and the active layer; a first via layer on the first electrode and the second electrode and around at least a portion of a side surface of the light emitting element; a first insulating layer on the first via layer, a side surface of the light emitting element protruding from the first via layer, and a top surface of the light emitting element; a partition wall unit on the first insulating layer and overlapping the bank layer; a second insulating layer on the partition wall unit; a reflective layer located around the side of the partition wall unit on the second insulating layer and around the side of the light emitting element on the first insulating layer, and located on the first insulating layer between the partition wall unit and the light emitting element; A second via layer, located between the partition wall units; as well as The wavelength conversion layer is on the second via layer. 13 . The display device according to claim 12 , further comprising a degradation prevention layer located between the second via layer and the wavelength conversion layer and comprising a base resin and a scatterer.

14. The display device according to claim 13, wherein: The partition wall unit includes a first partition wall on the first insulating layer and having a first width and a second partition wall on the first partition wall and having a second width, Wherein, the first width is greater than the second width.

15. The display device according to claim 14, wherein: The reflective layer includes a first reflective layer around a side surface of the first partition wall, a second reflective layer around a side surface of the second partition wall, a third reflective layer around a portion of the side surface of the light emitting element, and a fourth reflective layer located between the first reflective layer and the third reflective layer and between the second via layer and the first insulating layer.

16. The display device according to claim 15, wherein: The third reflective layer contacts the first insulating layer and has a height equal to that of the second via layer.

17. The display device according to claim 16, wherein: The third reflective layer is located on the first insulating layer around at least a portion of a side surface of the second semiconductor layer of the light emitting element.

18. The display device according to claim 15, wherein: The first via layer covers the bank layer and the first electrode and the second electrode, where the light emitting element is not disposed thereon. The second via layer covers the fourth reflective layer between the partition wall units and surrounds the third reflective layer.

19. The display device according to claim 14, wherein: The height of the first partition wall is greater than or equal to the height of the second partition wall. 20 . The display device of claim 12 , further comprising a capping layer, a coating layer, and a color filter layer sequentially disposed on the wavelength conversion layer and the partition wall unit.

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