Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor provided with an external electrode in which the surface of a base electrode layer is reliably covered with a plating layer. A laminated ceramic capacitor (1) is provided with: a laminated body (2) in which dielectric layers (4) and internal electrode layers (5) are alternately laminated; and external electrodes (3) that are respectively arranged on both end surfaces (C) of the laminated body (2) on both sides in the longitudinal direction (L) orthogonal to the lamination direction (T), and that are connected to the internal electrode layers (5), a base electrode layer (30) disposed on the end surface (C), a Ni plating layer (31a) disposed on the base electrode layer (30), and a Sn plating layer (31b) disposed on the Ni plating layer (31a) are laminated, and a region (R) in which Sn is deposited is provided between the base electrode layer (30) and the Ni plating layer (31a).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, in a laminated ceramic capacitor, an external electrode that is conductive to the internal electrode layer is provided on the surface of a ceramic body having an internal electrode layer built therein in order to mount the capacitor on a wiring substrate. The external electrode generally includes a base electrode layer made of a conductive metal and glass, but in order to prevent corrosion caused by solder used when mounting the capacitor on a circuit, the surface of the base electrode layer is covered with a Ni plating layer and further with a Sn plating layer.

[0003] When forming the plating layer, the electroplating method is generally used. In the electroplating method, the plating film is precipitated and grown with the conductive metal exposed on the surface of the base electrode layer as a core, thereby forming a plating layer so as to cover the base electrode layer. However, when the precipitated plating film is uneven, a uniform plating layer cannot be formed, and when mounted on a wiring substrate, the laminated body is damaged due to corrosion by the solder, resulting in failure of the laminated ceramic capacitor.

[0004] On the other hand, in order to improve the film-forming property of the coating, it is also considered to form the coating thicker, but the increase of the current in the electroplating and the extension of the electroplating treatment time are easy to cause the thickness of the coating to deviate in mass production, and it is difficult to stably ensure the quality. In addition, in order to limit the size of the stacked ceramic capacitor to the standard size, it is necessary to further reduce the thickness of the ceramic body corresponding to forming the coating thicker. As a result, in the ceramic body, thinning will further progress, and therefore, the decrease in the capacitance of the stacked ceramic capacitor becomes a problem.

[0005] Therefore, there is a need to develop a multilayer ceramic capacitor including external electrodes formed by reliably covering the surface of a base electrode layer with a plating layer.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 8-102425 Summary of the invention

[0009] Problems to be solved by the invention

[0010] An object of the present invention is to provide a multilayer ceramic capacitor including external electrodes formed by reliably covering the surface of a base electrode layer with a plating layer.

[0011] Means for solving problems

[0012] The present inventors have found that by providing a region where Sn is precipitated on the surface of a base electrode layer constituting an external electrode, the precipitation and growth of a plating film proceed smoothly, thereby completing the present invention.

[0013] That is, the present invention is a laminated ceramic capacitor having:

[0014] A laminated body in which dielectric layers and internal electrode layers are alternately laminated; and

[0015] external electrodes, which are respectively arranged on end surfaces on both sides of the stacked body in a longitudinal direction perpendicular to the stacking direction and connected to the internal electrode layer,

[0016] in,

[0017] In the external electrode, a base electrode layer arranged on the end surface, a Ni plating layer arranged on the base electrode layer, and a Sn plating layer arranged on the Ni plating layer are stacked, and a region where Sn is precipitated is provided between the base electrode layer and the Ni plating layer.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide a multilayer ceramic capacitor including external electrodes formed by reliably covering the surface of a base electrode layer with a plating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic perspective view of the multilayer ceramic capacitor 1 .

[0021] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II.

[0022] Figure 3 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0023] Figure 4 This is a flowchart for explaining a method for manufacturing the multilayer ceramic capacitor 1 .

[0024] Figure 5 It is a figure which shows the state of the cross section of the external electrode 3 observed by an electron microscope. DETAILED DESCRIPTION

[0025] The following describes a multilayer ceramic capacitor according to an embodiment of the present invention, but the present invention is not limited thereto. In addition, sometimes the drawings are schematically and briefly depicted to illustrate the contents of the invention, and the depicted components or the ratio of the dimensions between the components are sometimes inconsistent with the ratio of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings or depicted with the number omitted.

[0026] (Multilayer ceramic capacitor 1)

[0027] Figure 1 to Figure 3 The shape and structure of the multilayer ceramic capacitor 1 are shown. Figure 1 It is a schematic perspective view of the multilayer ceramic capacitor 1 . Figure 2 is Figure 1 FIG. 1 is a cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line II-II in the center portion in the width direction W shown. Figure 3 is along the stacked ceramic capacitor 1 Figure 1 Cross-sectional view along line III-III (WT cross-sectional view). Figure 4 This is a flowchart for explaining a method for manufacturing the multilayer ceramic capacitor 1 . Figure 5 3 is a diagram showing a state of a cross section of an external electrode 3 observed by an electron microscope. In addition, the direction of stacking dielectric layers and internal electrode layers is set as a stacking direction T, and the structure of the stacked ceramic capacitor 1 is described using a length direction L orthogonal to the stacking direction T, and a width direction W orthogonal to the stacking direction T and the length direction L. In addition, in the embodiment, the width direction W, the length direction L, and the stacking direction T are orthogonal to each other, but they are not necessarily orthogonal to each other, and may be mutually intersecting.

[0028] The multilayer ceramic capacitor 1 is substantially in the shape of a rectangular parallelepiped and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 6 including a plurality of sets of dielectric layers 4 and internal electrode layers 5.

[0029] In addition, among the six outer surfaces of the stacked body 2, a pair of outer surfaces facing each other in the stacking direction T are set as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W are set as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L are set as the first end surface C1 and the second end surface C2.

[0030] In addition, when there is no need to distinguish the first main surface A1 and the second main surface A2, they are collectively described as main surface A; when there is no need to distinguish the first side surface B1 and the second side surface B2, they are collectively described as side surface B; and when there is no need to distinguish the first end surface C1 and the second end surface C2, they are collectively described as end surface C.

[0031] (Laminate 2)

[0032] The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the main surface A side of the inner layer portion 6, and a side gap portion 8. The laminate 2 preferably has roundness at the ridge portion E. The ridge portion E is a portion where two surfaces of the laminate 2 intersect, that is, a portion where the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C intersect, and also includes a corner where the main surface A, the side surface B, and the end surface C intersect.

[0033] (Inner layer 6)

[0034] The inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5 alternately stacked along the stacking direction T.

[0035] (Dielectric layer 4)

[0036] The dielectric layer 4 is formed of a ceramic material. As the ceramic material, for example, a dielectric ceramic having BaTiO3 as a main component is used. In addition, as the ceramic material, a material obtained by adding at least one of the auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components can also be used.

[0037] (Internal electrode layer 5)

[0038] The internal electrode layer 5 is preferably formed of a metal material represented by Ni, Cu, Ag, Pd, Ag—Pd alloy, Au, or the like.

[0039] The internal electrode layer 5 includes a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are alternately arranged. When there is no need to distinguish between the first internal electrode layers 5A and the second internal electrode layers 5B, they are collectively described as the internal electrode layers 5.

[0040] The internal electrode layer 5 includes an opposing portion 52 between the first internal electrode layer 5A and the second internal electrode layer 5B, and a lead portion 51 that is not opposed to each other between the first internal electrode layer 5A and the second internal electrode layer 5B but is led out from the opposing portion 52 to one end surface C. The end of the lead portion 51 is exposed at the end surface C and is electrically connected to the external electrode 3. The direction in which the lead portion 51 extends is different between the first internal electrode layer 5A and the second internal electrode layer 5B, and the lead portion 51 is alternately led out to the first end surface C1 side and the second end surface C2 side. In addition, electric charges are accumulated between the opposing portions 52 of the first internal electrode layer 5A and the second internal electrode layer 5B adjacent in the stacking direction T, thereby functioning as a capacitor.

[0041] (Outer layer 7)

[0042] The outer layer portion 7 is disposed on both principal surface A sides of the inner layer portion 6 , and is formed of the same material as that of the dielectric layer 4 of the inner layer portion 6 .

[0043] (Side clearance portion 8)

[0044] The side gaps 8 are provided on both side surfaces B of the inner layer portion 6 in the laminate 2. The side gaps 8 are formed integrally with the dielectric layer 4 using the same material.

[0045] (External electrode 3)

[0046] The external electrodes 3 are provided at both end surfaces C of the laminate 2 . The external electrodes 3 cover not only the end surfaces C but also a portion of the principal surface A and the side surface B on the end surface C side. The external electrodes 3 include a base electrode layer 30 and a plating layer 31 formed on the surface of the base electrode layer 30 .

[0047] (Base electrode layer 30)

[0048] The base electrode layer 30 is electrically connected to the end of the lead-out portion 51 of the internal electrode layer 5 exposed at the end surface C. The base electrode layer preferably contains a conductive metal, and either glass or ceramic, or contains both glass and ceramic. In the embodiment, the base electrode layer 30 contains a conductive metal and glass. As a result, the adhesion between the end surface C of the stack 2 and the base electrode layer 30 is improved, and the infiltration of moisture into the interior of the stack 2 can be suppressed.

[0049] The conductive metal forming the base electrode layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like.

[0050] In addition, the glass forming the base electrode layer 30 includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. In addition, when a ceramic component is contained, as the ceramic component, a ceramic component of the same type as that of the dielectric layer may be used, or a ceramic component of a different type from that of the dielectric layer may be used.

[0051] (Region R)

[0052] A region R where Sn is precipitated is formed on the surface of the conductive metal exposed on the surface of the base electrode layer 30. The region R is formed by precipitating Sn or an alloy of Sn and Ni by a chemical plating method or the like described later.

[0053] Figure 5 The cross-section of the external electrode 3 observed by an electron microscope is shown, and the region R is formed to protrude by 0.1 to 3.0 μm from the surface of the base electrode layer 30. The region R serves as a core for forming the Ni plating layer 31a, and the Ni plating layer 31a can be formed smoothly.

[0054] (Plating layer 31)

[0055] The plating layer 31 is composed of a Ni plating layer 31a configured to cover the surface and region R of the base electrode layer 30, and a Sn plating layer 31b configured to cover the Ni plating layer 31a. The Ni plating layer 31a includes a plating layer of Ni or an alloy containing Ni. The Ni plating layer 31a prevents the base electrode layer 30 from being corroded by solder. The Sn plating layer 31b includes a plating layer of Sn or an alloy containing Sn. By forming the Sn plating layer 31b, when the multilayer ceramic capacitor 1 is mounted on a wiring substrate, the wettability of the solder is improved, and thus mounting becomes easy.

[0056] The molar ratio of Sn to Ni (Sn / Ni) in the region R measured by energy dispersive X-ray spectroscopy (EDX) is preferably 0.2 or more and 0.4 or less. By configuring the region R with such a molar ratio (Sn / Ni), the region R can be stably formed in mass production, and the Ni plating layer 31 a can be smoothly stacked on the surface of the base electrode layer 30 .

[0057] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0058] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. Figure 4 This is a flowchart for explaining a method for manufacturing the multilayer ceramic capacitor 1 .

[0059] The manufacturing process of the multilayer ceramic capacitor 1 includes a multilayer body manufacturing process S1 , a base electrode layer forming process S2 , a region R forming process S3 , a Ni plating layer forming process S4 , and a Sn plating layer forming process S5 .

[0060] (Laminate Manufacturing Step S1)

[0061] First, in the laminate production step S1 , a raw material sheet is prepared by printing a pattern of the internal electrode layer 5 on a laminated ceramic green sheet formed into a sheet shape using a ceramic slurry using a conductive paste.

[0062] Then, a plurality of green sheets are stacked so that the internal electrode patterns are shifted by half a pitch in the longitudinal direction between adjacent green sheets.

[0063] Furthermore, ceramic green sheets for outer layer portions, which will become outer layer portions, are stacked on both sides of the stacked plurality of green sheets, and are bonded by thermocompression to form a mother block member.

[0064] The mother block member is divided along the cutting line corresponding to the size of the stacked body to produce a plurality of stacked chips. The stacked chips are then barrel-polished to give rounded corners and ridges, and then fired. Thus, the ceramic material and metal material contained in the stacked chips are fired to form a stacked body 2 including a plurality of dielectric layers 4 and a plurality of internal electrode layers 5.

[0065] (Base Electrode Layer Formation Step S2)

[0066] Next, in the base electrode layer forming step S2, base electrode layers 30 are formed at both ends of the stacked body 2. The base electrode layer 30 is formed, for example, by applying a conductive paste containing a conductive metal and glass to both ends of the stacked body 2 and sintering the conductive paste. The base electrode layer may be obtained by simultaneously sintering the stacked small pieces and the conductive paste applied to the stacked small pieces, or by applying a conductive paste to the stacked body 2 and sintering the stacked body 2 after sintering the stacked small pieces. Figure 2 As shown, the base electrode layer 30 is formed so as to not only cover the end surfaces C on both sides of the laminate 2 but also extend to the main surface A side to cover a portion of the main surface A on the end surface C side.

[0067] (Region R Forming Step S3)

[0068] Region R can be formed by an immersion-based chemical plating method. The stacked body 2 formed with the base electrode layer 30 is immersed in a plating bath so that Sn is precipitated on the surface of the conductive metal exposed to the surface of the base electrode layer 30. The precipitated metal is not only Sn, but also an alloy of Sn and Ni. These metals are supplied to the plating bath as cationic species. Regarding the plating bath, although both the metal salt and the reducing agent are present in the bath, the metal layer is precipitated due to the action of the reducing agent added to the aqueous solution of the metal salt, covering the surface of the conductive metal exposed to the surface of the base electrode layer. In addition, region R can also be formed by electroplating or other plating methods.

[0069] (Ni plating layer forming step S4)

[0070] In the Ni plating layer forming step S3 , the Ni plating layer 31 a is formed so as to cover the surface of the base electrode layer 30 where the region R is formed. The Ni plating layer 31 a is preferably formed by electroplating. As the plating method, barrel plating can be used.

[0071] (Sn plating layer forming step S5)

[0072] Next, the Sn plating layer 31b is formed so as to cover the Ni plating layer 31a. The Sn plating layer 31b is preferably formed by electroplating. As a plating method, barrel plating can be used.

[0073] Through the above-described steps, the multilayer ceramic capacitor 1 in which the external electrodes 3 are formed on the multilayer body 2 is manufactured.

[0074] As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment, It can implement in various forms within the range which does not deviate from the summary of this invention.

[0075] Description of Reference Numerals

[0076] 1. Multilayer ceramic capacitor;

[0077] 2 laminates;

[0078] 3 External electrodes;

[0079] 4 dielectric layer;

[0080] 5 Internal electrode layer;

[0081] 6 inner part;

[0082] 7 outer part;

[0083] 30 base electrode layer;

[0084] 31 coating;

[0085] 31a Ni coating;

[0086] 31b Sn plating layer;

[0087] R-region;

[0088] A main surface;

[0089] A1 first main surface;

[0090] A2 second main surface;

[0091] B side;

[0092] B1 first side;

[0093] B2 Second side;

[0094] C end face;

[0095] C1 first end face;

[0096] C2 Second end face.

Claims

1. A laminated ceramic capacitor comprising: A laminated body in which dielectric layers and internal electrode layers are alternately laminated; and external electrodes, which are respectively arranged on end surfaces on both sides of the stacked body in a longitudinal direction perpendicular to the stacking direction and connected to the internal electrode layer, in, In the external electrode, a base electrode layer arranged on the end surface, a Ni plating layer arranged on the base electrode layer, and a Sn plating layer arranged on the Ni plating layer are stacked, and a region where Sn is precipitated is provided between the base electrode layer and the Ni plating layer.

2. The multilayer ceramic capacitor according to claim 1, wherein The molar ratio of Sn to Ni in the region where Sn is precipitated, that is, Sn / Ni, measured by energy dispersive X-ray spectroscopy (EDX), is 0.2 or more and 0.4 or less.

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