Periodic signal sampling circuit

Abstract

The embodiment of the present application provides a periodic signal sampling circuit, which relates to the technical field of power supply circuit design, including a charge pump detection module, a charge pump output comparison module and a logic judgment module, which generates a first comparison value for the charging / discharging time of the charge pump capacitor through upper and lower bias currents, obtains the corresponding charge pump capacitor voltage, generates a sawtooth voltage corresponding to the charge pump capacitor voltage, compares the sawtooth voltage with the reference voltage, and outputs a second comparison value, controls the on or off of the switch device according to the phase difference, and adjusts the charging time of the capacitor by the upper and lower bias currents. The embodiment of the present application can accurately obtain the rising edge of the sampling signal at any time within a PWM signal cycle by reasonably configuring the upper and lower bias currents and controlling the charging / discharging time of the charge pump capacitor, and using the negative feedback output by the circuit to control the switch device in the periodic signal sampling circuit, thereby obtaining the status of the circuit load in real time.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of power supply circuit design, and specifically to a periodic signal sampling circuit. Background Art

[0002] When designing a DC-DC converter, an important information to know is the real-time load condition, which is used for current sharing of multi-phase DC-DC converters or for converter state switching (such as switching from forced continuous conduction mode FCCM to discontinuous conduction mode DCM).

[0003] Related technologies use external sampling resistors to detect real-time load conditions, or they can use internal sampling circuits to detect real-time loads. Figure 1 The step-down DC-DC converter shown in the figure includes input voltage VIN, upper power tube HS, lower power tube LS, inductor Ls, inductor current I_Ls, filter capacitor Cout, output voltage OUT, and load current I_LOAD. In the case of FCCM, the average value of the inductor current is the load information. Since the upper power tube HS / lower power tube LS is integrated inside the chip, the current flowing through HS or LS can be detected and the middle point can be sampled ( Figure 1 The load information is obtained by using the current information of points A and B in the circuit. The difficulty of the related technology lies in how to obtain an accurate intermediate point signal, and this technical difficulty needs to be improved urgently. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a periodic signal acquisition circuit to solve the problem in the related art that it is difficult to accurately obtain the accurate time signal of the circuit waveform.

[0005] According to one aspect of an embodiment of the present application, a periodic signal sampling circuit is provided, which is applied to a power conversion circuit, and includes: a charge pump detection module, a charge pump output comparison module and a logic judgment module, wherein: the charge pump detection module is configured to, by turning on or off a switching device, allow a PWM signal to charge or discharge a charge pump capacitor using a preset upper bias current and a lower bias current to obtain a charge pump capacitor voltage, and a ratio of the charging / discharging time of the charge pump capacitor is a first comparison value; the charge pump output comparison module is configured to generate a sawtooth wave voltage corresponding to the charge pump capacitor voltage, the sawtooth wave voltage is compared with a reference voltage, and a second comparison value is output, and the second comparison value corresponds to the phase difference between the PWM signal and the first comparison value; the logic judgment module is configured to control the turning on or off of the switching device according to the phase difference.

[0006] According to at least one specific implementation of the embodiments of the present application, the second comparison value is a sampling signal, and the phase difference between the second comparison value and the PWM signal corresponds to the first comparison value, specifically: the upper bias current is equal to the lower bias current, or: the lower bias current is equal to twice the upper bias current.

[0007] According to at least one specific implementation of the embodiments of the present application, the charge pump detection module includes a pull-up switch device and a pull-down switch device, one end of the pull-up switch device is connected to a power supply, and the other end is connected to one end of the pull-down switch device, and the other end of the pull-down switch device is grounded; one end of the charge pump capacitor is connected between the pull-up switch device and the pull-down switch device, and the other end is grounded.

[0008] According to at least one specific implementation of the embodiments of the present application, the charge pump output comparison module includes a voltage-controlled current source, an operational amplifier comparator, a first capacitor and a capacitor discharge switch device, the input end of the voltage-controlled current source is connected to a power supply, the control end of the voltage-controlled current source is connected to the charge pump capacitor, the output end of the voltage-controlled current source is connected to the non-inverting end of the operational amplifier comparator, one end of the first capacitor is connected between the voltage-controlled current source and the non-inverting end of the operational amplifier comparator, and the other end is grounded, and one end of the capacitor discharge switch device is connected between the voltage-controlled current source and the non-inverting end of the operational amplifier comparator, and the other end is grounded.

[0009] According to at least one specific implementation of the embodiment of the present application, the voltage-controlled current source includes a low clamping module and a voltage-controlled current module, the low clamping module is used to configure the minimum value of the charge pump capacitor voltage, and the voltage-controlled current module is used to output current.

[0010] According to at least one specific implementation of the embodiments of the present application, the low clamping module includes a first MOS tube and a second MOS tube, the source of the first MOS tube is used to receive the charge pump capacitor voltage, the drain of the first MOS tube is connected to the power supply, the gate of the first MOS tube is connected to the drain of the second MOS tube, the gate of the second MOS tube is connected to the source of the first MOS tube, and the source of the second MOS tube is grounded.

[0011] According to at least one specific implementation of the embodiment of the present application, the voltage-controlled current module also includes a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sampling resistor, the gate of the third MOS tube is connected to the gate of the second MOS tube, the drain of the third MOS tube is connected to the drain of the fourth MOS tube, the source of the third MOS tube is connected to one end of the sampling resistor, the other end of the sampling resistor is grounded, the source of the fourth MOS tube is connected to a power supply, the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube, the gate and drain of the fourth MOS tube are connected, the source of the fifth MOS tube is connected to the power supply, and the drain of the fifth MOS tube is used to output current.

[0012] According to at least one specific implementation of the embodiments of the present application, the logic judgment module obtains a sampling signal, inverts the sampling signal to obtain an inverted sampling signal, and the logic judgment module performs logical operations on the sampling signal and the inverted sampling signal to control the pull-up switch device and the pull-down switch device in the charge pump detection module, and the capacitor discharge switch device of the charge pump output comparison module.

[0013] According to at least one specific implementation of the embodiment of the present application, a first inverter, a second inverter, a third inverter, a fourth inverter, a first logic NAND gate and a second logic NAND gate are provided in the logic judgment module, the input end of the first inverter is connected to the output end of the comparator in the charge pump output comparison module, the input end of the second inverter is used to input the PWM signal, the output end of the second inverter is connected to the capacitor discharge switch device in the charge pump output comparison module, the input end of the first logic NAND gate is respectively connected to the output end of the comparator and the PWM signal, the inverting output end of the first logic NAND gate is connected to the input end of the third inverter, the output end of the third inverter is connected to the pull-down switch device in the charge pump detection module, the input end of the second logic NAND gate is respectively connected to the output end of the first inverter and the PWM signal, the output end of the first inverter is used to output an inverted sampling signal, the inverting output end of the second logic NAND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the pull-up switch device in the charge pump detection module.

[0014] According to at least one specific implementation of the embodiment of the present application, in the charge pump detection module, the upper bias current is the charging current from the power supply to the charge pump capacitor, the lower bias current is the current from the charge pump capacitor to the ground, and the switching device is a MOS tube or a triode.

[0015] The beneficial technical effects of the embodiments of the present application are:

[0016] When the input signal is PWM, by reasonably configuring the upper bias current and the lower bias current, and controlling the on or off of the switch device in the charge pump detection module through the negative feedback provided at the output end of the circuit, a first comparison value and a second comparison value are formed, the first comparison value is the ratio of the upper and lower bias currents to the charging / discharging time of the charge pump capacitor C0, wherein the second comparison value is in a corresponding relationship with the phase difference of the PWM signal and the first comparison value, for example, when the upper bias current is equal to the lower bias current, the sampling signal at 50% of the time in a PWM signal cycle can be accurately obtained, that is, the circuit load status can be known in real time. In addition, the switch device of the periodic signal sampling circuit can be negatively feedback controlled to output a sampling signal Vout of any desired phase, obtain the rising edge of the sampling signal Vout at any time in the PWM signal cycle, and obtain the corresponding load information according to the current information at the time of the rising edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 The circuit principles and signal waveform diagrams of the related technologies involved in the embodiments of the present application;

[0019] Figure 2 It is a principle block diagram of the embodiment of the present application in a specific application scenario;

[0020] Figure 3 It is the schematic diagram of the periodic signal sampling circuit;

[0021] Figure 4 It is the schematic diagram of the voltage-controlled current source circuit;

[0022] Figure 5 It is the waveform diagram of the periodic signal sampling circuit in the initial stage of the input PWM signal;

[0023] Figure 6 It is the waveform diagram of the periodic signal sampling circuit after the input PWM signal stabilizes. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only implementation methods of a part of the embodiments of the present application, rather than all implementation methods. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0027] It should be noted that, in the absence of conflict, the implementation methods and features in the embodiments of the present application can be combined with each other. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] like Figure 1The embodiment of the present application shown relates to the circuit principle and signal waveform diagram of the related technology. The technical problem to be solved by the embodiment of the present application is explained by describing the DC-DC converter of the related technology. In the design and application of the DC-DC converter, real-time monitoring of the load condition is crucial to realize the current sharing control of the multi-phase DC-DC converter and the switching of the converter state. The load monitoring method in the related technology relies on an external sampling resistor to detect the real-time load condition, but this method has certain limitations. With the development of technology, an internal sampling circuit is proposed to detect the real-time load, especially in FCCM (forced continuous conduction mode), the average value of the inductor current can be used as a direct indication of the load information. In the buck DC-DC converter shown in the figure, the upper power tube HS and the lower power tube LS are usually integrated inside the chip. The load information can be obtained by detecting the current flowing through HS or LS and sampling the current information of the intermediate point (point A, point B). However, the key difficulty in this process is how to obtain point A and point B at the exact moment.

[0029] like Figure 2 As shown, an embodiment of the present application provides a periodic signal sampling circuit, in which the upper bias current IB0 and the lower bias current IB1 are reasonably set, the upper and lower bias currents are used to control the charging / discharging time of the charge pump capacitor C0, and the phase of the sampling signal Vout and the input signal PWM is judged, and the circuit input end is controlled by the negative feedback provided by the circuit output end, and finally the sampling signal Vout that matches the expected phase is output. The periodic signal sampling circuit provided in the embodiment of the present application can be applied to a power conversion circuit, such as the DC-DC converter circuit mentioned above. It is easy to understand that the main application scenarios of the periodic signal sampling circuit explained in the embodiment of the present application do not represent a restriction on other application scenarios. The DC-DC converter circuit is used as an example to illustrate the embodiment of the present application only for the purpose of facilitating understanding, not for the purpose of limiting the scope of application.

[0030] The periodic signal sampling circuit of the embodiment of the present application mainly includes: a charge pump detection module A, a charge pump output comparison module B and a logic judgment module C, wherein:

[0031] The charge pump detection module A is configured to charge or discharge the charge pump capacitor C0 by turning on or off the switch device, using the pre-set upper bias current and lower bias current to obtain the corresponding charge pump capacitor voltage VC, and the ratio of the upper and lower bias currents to the charging / discharging time of the charge pump capacitor is a first comparison value. In the charge pump detection module A, the upper bias current IB0 is the charging current from the power supply VCC to the charge pump capacitor C0, and the lower bias current IB1 is the current from the charge pump capacitor C0 to the ground. In the embodiment of the present application, the switch devices in the three modules can be selected from MOS tubes or triodes. Between the pull-up switch device S0 and the pull-down switch device S1 is a switch node, and an upper bias current source can be set above the switch node, and a lower bias current source can be set below the switch node. The upper and lower bias current sources are used to generate upper and lower bias currents, respectively. In the embodiment of the present application, the ratio of the upper and lower bias currents is pre-set. If it is desired to obtain a signal at a duty cycle of 50%, the upper and lower bias currents are pre-set to be equal. If it is desired to obtain a signal at a duty cycle of 25%, the upper bias current is pre-set to be 3 times the lower bias current.

[0032] The charge pump output comparison module B is configured to generate a sawtooth voltage Vramp corresponding to the charge pump capacitor voltage VC. In the embodiment of the present application, the charge pump capacitor voltage VC is converted into a corresponding sawtooth voltage Vramp mainly through a voltage-controlled current source. The formation of the sawtooth voltage Vramp will be described in the following specific implementation. The sawtooth voltage is compared with the reference voltage Vref to output a second comparison value (sampling signal Vout). The phase difference between the second comparison value and the PWM signal corresponds to the first comparison value.

[0033] The second comparison value is the phase difference between the sampling signal Vout and the PWM signal. The second comparison value is in a corresponding relationship with the first comparison value. For example, the upper bias current IB0 can be preset to be equal to the lower bias current IB1, or the lower bias current IB1 can be preset to be equal to twice the upper bias current IB0. The PWM signal is a periodic signal. When the PWM signal enters the steady-state period, the charge pump capacitor voltage VC will remain unchanged. When the upper bias current IB0 is equal to the lower bias current IB1, the rising edge of the sampling signal appears at 1 / 2 (50% time) in the period when the PWM signal is high. If the lower bias current IB1=2*upper bias current IB0, the rising edge of the sampling signal Vout appears at 2 / 3 of the time when the PWM signal is high. It can be seen that by reasonably setting the upper bias current IB0 and the lower bias current IB1, and controlling the charging / discharging time (first comparison value) of the upper bias current and the lower bias current on the charge pump capacitor C0 through the PWM signal, not only can the rising edge of the sampling signal appear at what time, but also the sampling signal at any desired time within the high level period of the PWM signal can be obtained by adjusting the first comparison value. When the signal cycle reaches a stable state, the ratio of the upper bias current IB0 and the lower bias current IB1 is inversely correlated to the charging and discharging time of the capacitor (first comparison value), and the charging and discharging time of the upper and lower bias currents on the capacitor is positively correlated with the second comparison value and the phase difference of the PWM signal.

[0034] The logic judgment module C is configured to control the on or off of the switch device according to the phase difference between the second comparison value and the PWM signal, and adjust the first comparison value by controlling the charging / discharging time of the charge pump capacitor C0. It can be understood that in the embodiment of the present application, the phase represents the specific moment when the PWM signal samples the signal within a cycle. The logic judgment module C controls the switch device in the charge pump detection module A by judging the phase difference between the sampling signal Vout and the PWM signal, and controls the charging / discharging time of the upper and lower bias currents on the charge pump capacitor C0 by turning on or off. It can be seen that in the embodiment of the present application, the negative feedback control of the logic judgment module C regulates the charging and discharging time of the upper and lower bias currents on the capacitor, or the on time of the switch device. At the beginning, the upper bias current charging time is long and the lower bias current discharging time is short. When the system is stable, the charging time is equal to the discharging time.

[0035] The function of the logic judgment module C is to take the sampling signal Vout as input, invert the sampling signal Vout, and obtain an inverted sampling signal. The logic judgment module C performs logic operations on the sampling signal Vout and the inverted sampling signal xVout. The logic operations include logic AND operations and inverting operations, and control the pull-up switch device S0 and the pull-down switch device S1 in the charge pump detection module A, and the capacitor discharge switch device S2 of the charge pump output comparison module B.

[0036] like Figure 3 As shown, the input signal in the embodiment of the present application is a PWM signal, and the charge pump detection module A includes a pull-up switch device S0 and a pull-down switch device S1, one end of the pull-up switch device S0 is connected to the power supply VCC, and the other end is connected to one end of the pull-down switch device S1, and the other end of the pull-down switch device S1 is grounded, and one end of the charge pump capacitor C0 is connected between the pull-up switch device S0 and the pull-down switch device S1, and the other end is grounded.

[0037] The charge pump output comparison module B includes a voltage-controlled current source VCCS, an operational amplifier comparator CMP, a first capacitor C1 and a capacitor discharge switch device S2. The input terminal b of the voltage-controlled current source VCCS is connected to the power supply VCC, the control terminal a of the voltage-controlled current source VCCS is connected to the charge pump capacitor C0, the output terminal c of the voltage-controlled current source VCCS is connected to the non-inverting terminal of the operational amplifier comparator CMP, and the input signal sawtooth wave voltage Vramp is between the output terminal c of the voltage-controlled current source VCCS and the non-inverting terminal of the operational amplifier comparator CMP. One end of the first capacitor C1 is connected between the voltage-controlled current source VCCS and the non-inverting terminal of the operational amplifier comparator CMP, and the other end is grounded. One end of the capacitor discharge switch device S2 is connected between the voltage-controlled current source VCCS and the non-inverting terminal of the operational amplifier comparator CMP, and the other end is grounded.

[0038] The pull-up switch device S0 and the pull-down switch device S1 are arranged in the current path from the power supply VCC to the ground. The switch node voltage SW is between the pull-up switch device S0 and the pull-down switch device S1. One end of the charge pump capacitor C0 is connected to the switch node voltage SW. The switch node voltage SW is the charge pump capacitor voltage VC. During the period of the PWM signal, the charge pump capacitor C0 is charged or discharged by two bias currents to maintain the high level of the charge pump capacitor voltage VC, and the voltage-controlled current source VCCS is controlled to gradually increase the sawtooth wave voltage Vramp. The sawtooth wave voltage Vramp is compared with the reference voltage Vref by the operational amplifier comparator CMP, and the sampling signal Vout is output.

[0039] In the logic judgment module C, a first inverter V1, a second inverter V2, a third inverter V3, a fourth inverter V4, a first logic NAND gate A1, and a second logic NAND gate A2 are provided in the logic judgment module C. The input end of the first inverter V1 is connected to the output end of the comparator CMP in the charge pump output comparison module B. The output end of the first inverter V1 is used to output the inverted sampling signal xVout. The input end of the second inverter V2 is used to input the PWM signal. The output end of the second inverter V2 is connected to the capacitor discharge switch device S2 in the charge pump output comparison module B. The first logic NAND gate A1 and the second logic NAND gate A2 are connected to the capacitor discharge switch device S2 in the charge pump output comparison module B. The input end of the NOT gate A1 is connected to the output end of the comparator (sampling signal Vout) and the PWM signal respectively, the inverting output end of the first logic NAND gate A1 is connected to the input end of the third inverter V3, the output end of the third inverter V3 is connected to the pull-down switch device S1 in the charge pump detection module A, the input end of the second logic NAND gate A2 is connected to the output end of the first inverter V1 and the PWM signal respectively, the inverting output end of the second logic NAND gate A2 is connected to the input end of the fourth inverter V4, and the output end of the fourth inverter V4 is connected to the pull-up switch device S0 in the charge pump detection module A. In the logic judgment module C, negative feedback control of the pull-up switch device S0 and the pull-down switch device S1 in the charge pump detection module A is formed through multiple inverters and logic gate circuits, and the charging time of the charge pump capacitor C0 and the first capacitor C1 is adjusted. By changing the first comparison value, the sampling signal Vout of any desired phase is output, and the rising edge of the sampling signal Vout at any time within the PWM signal cycle is obtained, and the corresponding load information is obtained according to the current information at the time of the rising edge.

[0040] like Figure 4 As shown, the voltage-controlled current source includes a low clamping module D and a voltage-controlled current module E. The low clamping module D is used to configure the minimum value of the charge pump capacitor voltage. The low clamping module D sets the minimum value of the charge pump capacitor voltage VC so that the charge pump capacitor voltage VC does not rise from 0, thereby accelerating the time from the start to the stability of the system. The voltage-controlled current module E is used to output the current I_VC. The low clamping module D includes a first MOS tube Q1 and a second MOS tube Q2. The source of the first MOS tube Q1 is used to receive the charge pump capacitor voltage VC. The drain of the first MOS tube Q1 is connected to the power supply VCC. The gate of the first MOS tube Q1 is connected to the drain of the second MOS tube Q2. The gate of the second MOS tube Q2 is connected to the source of the first MOS tube Q1. The source of the second MOS tube Q2 is grounded.

[0041] The voltage-controlled current module E also includes a third MOS tube Q3, a fourth MOS tube Q4, a fifth MOS tube Q5 and a sampling resistor Rs. The gate of the third MOS tube Q3 is connected to the gate of the second MOS tube Q2, the drain of the third MOS tube Q3 is connected to the drain of the fourth MOS tube Q4, the source of the third MOS tube Q3 is connected to one end of the sampling resistor Rs, the other end of the sampling resistor Rs is grounded, the source of the fourth MOS tube Q4 is connected to the power supply VCC, the gate of the fourth MOS tube Q4 is connected to the gate of the fifth MOS tube Q5, the gate and drain of the fourth MOS tube Q4 are connected, the source of the fifth MOS tube Q5 is connected to the power supply VCC, and the drain of the fifth MOS tube Q5 is used to output the current I_VC.

[0042] In the low clamp module D, if the charge pump capacitor voltage VC is very high, assuming that the second MOS tube Q2 is in the saturation region, the current generated by it is ,in is the drain current, is the mobility of electrons, is the capacitance of the oxide layer, W is the width of the transistor, L is the length of the transistor, VC is the charge pump capacitor voltage (gate voltage), is the threshold voltage, the current The drain voltage of the second MOS tube Q2 will be pulled down, so that the second MOS tube Q2 is in the linear region, which is equivalent to a resistor. At this time, the drain voltage of the second MOS tube Q2 is approximately equal to , is relatively close to 0, and the first MOS tube Q1 is in the off state. As the charge pump capacitor voltage VC decreases, the second MOS tube Q2 is still in the linear region, but according to the formula It can be seen that the drain voltage of the second MOS tube Q2 gradually increases until the second MOS tube Q2 is slowly in the saturation region, and the first MOS tube Q1 is slowly turned on to prevent the charge pump capacitor voltage VC from continuing to decrease. Therefore, at this time, the charge pump capacitor voltage VC is at its lowest value, and ,Right now .

[0043] The function of the voltage-controlled current module E is to convert the charge pump capacitor voltage VC into the current I_VC. The third MOS tube Q3 is always in the saturation region, and its current can be expressed as , we can get by solving If the size W / L (ratio of the width W to the length L of the communication) of the third MOS tube Q3 is very large, it can be approximated as The fourth MOS tube Q4 and the fifth MOS tube Q5 form a current mirror to obtain the output current .

[0044] like Figure 5 and Figure 6As shown, first take the case where the upper bias current IB0 = the lower bias current IB1 (If IB1 = IB0) as an example to illustrate: when the circuit just starts working, the PWM signal is at a low level, the pull-up switch device S0 and the pull-down switch device S1 are both in the off state, the charge pump capacitor voltage VC is 0, the capacitor discharge switch device S2 is in the on state, the sawtooth wave voltage Vramp is 0, and the output sampling signal Vout is also 0.

[0045] In the first cycle of the PWM signal being at a high level, the capacitor discharge switch device S2 is turned off, the sawtooth voltage Vramp is less than the reference voltage Vref, the sampled voltage Vout output by the circuit is 0, the pull-up switch device S0 is turned on, the pull-down switch device S1 is turned off, the upper bias current IB0 charges the charge pump capacitor C0, and the charge pump capacitor voltage VC increases. If the sawtooth voltage Vramp is lower than the reference voltage Vref, the sampled voltage Vout output by the circuit continues to be 0. As the PWM signal becomes a low level again, the pull-up switch device S0 and the pull-down switch device S1 are turned off, the capacitor discharge switch device S2 is turned on, the charge pump capacitor voltage VC remains in the increased state, the sawtooth voltage Vramp is 0, and the sampled voltage Vout output by the circuit continues to be 0.

[0046] In the second PWM high cycle, before the sawtooth voltage Vramp is greater than the reference voltage Vref, the sampling voltage Vout is 0, the pull-up switch device S0 is turned on, the upper bias current IB0 charges the charge pump capacitor C0, and the charge pump capacitor voltage VC charges the first capacitor C1 through the voltage-controlled current source VCCS. After the sawtooth voltage Vramp is greater than the reference voltage Vref, the sampling voltage Vout is high, the pull-up switch device S0 is turned off, the pull-down switch device S1 is turned on, and the lower bias current discharges the charge pump capacitor C0 until the PWM signal is 0 again, the charge pump capacitor voltage VC is in a holding state, the sawtooth voltage Vramp is 0, and the sampling voltage Vout is 0.

[0047] After more PWM cycles, the whole system enters a stable state. After a steady-state cycle, the charge pump capacitor voltage VC remains unchanged, which means that if the upper bias current IB0 = the lower bias current IB1, the charging / discharging time of the charge pump capacitor voltage VC is consistent during the time when the PWM signal is high, so that the rising edge (Rising edge) of the sampling signal Vout output by the circuit appears at 50% of the time during the period when the PWM signal is high. If the lower bias current IB1 = 2*upper bias current IB0 (If IB1=2*IB0), the rising edge (Rising edge) of the sampling signal Vout output by the circuit appears at 2 / 3 of the time during the period when the PWM signal is high. In summary, it can be seen that the first comparison value formed by the upper and lower bias currents on the charging / discharging time of the capacitor forms a corresponding relationship with the rising edge (Rising edge) of the sampling signal Vout. By adjusting the on or off of the switch device, the ratio of the upper and lower bias currents to the charging / discharging time of the charge pump capacitor C0 can be controlled to obtain the sampling signal Vout at any desired time point.

[0048] The above specific implementation method takes the time period when the PWM signal is at a high level as an example, and obtains the midpoint signal at 50% of the high level in one cycle. By reasonably adjusting the logic judgment module C, it is also possible to achieve the time period when the output PWM signal is at a low level, and obtain the midpoint signal at 50% of the low level in one cycle. It is only necessary to make corresponding adjustments to the circuit devices such as the inverter and logic gate circuit in the logic judgment module C.

[0049] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the description of the embodiments of the present application.

[0050] In the description of the specification of the embodiments of the present application, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0051] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition, they may be divided into multiple submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in the specification of the embodiments of the present application (including the corresponding claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in the specification of the embodiments of the present application (including the corresponding claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0052] Although the implementation methods of the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the embodiments of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A periodic signal sampling circuit, applied to a power conversion circuit, characterized in that: include: Charge pump detection module, charge pump output comparison module and logic judgment module, wherein: The charge pump detection module is configured to, by turning on or off the switch device, enable the PWM signal to charge or discharge the charge pump capacitor using a preset upper bias current and a preset lower bias current to obtain a charge pump capacitor voltage, and the ratio of the charge / discharge time of the charge pump capacitor is a first comparison value; The charge pump detection module includes a pull-up switch device and a pull-down switch device, one end of the pull-up switch device is connected to a power supply, and the other end is connected to one end of the pull-down switch device, and the other end of the pull-down switch device is grounded, and one end of the charge pump capacitor is connected between the pull-up switch device and the pull-down switch device, and the other end is grounded; The charge pump output comparison module is configured to generate a sawtooth wave voltage corresponding to the charge pump capacitor voltage, compare the sawtooth wave voltage with a reference voltage, and output a second comparison value, wherein the second comparison value corresponds to the phase difference between the PWM signal and the first comparison value; The charge pump output comparison module includes a voltage-controlled current source, an operational amplifier comparator, a first capacitor and a capacitor discharge switch device, wherein the input end of the voltage-controlled current source is connected to a power supply, the control end of the voltage-controlled current source is connected to the charge pump capacitor, the output end of the voltage-controlled current source is connected to the non-inverting end of the operational amplifier comparator, one end of the first capacitor is connected between the voltage-controlled current source and the non-inverting end of the operational amplifier comparator, and the other end is grounded, and one end of the capacitor discharge switch device is connected between the voltage-controlled current source and the non-inverting end of the operational amplifier comparator, and the other end is grounded; The logic judgment module is configured to control the on or off of the switching device according to the phase difference.

2. The periodic signal sampling circuit according to claim 1, characterized in that: The second comparison value is a sampling signal, and the phase difference between the second comparison value and the PWM signal corresponds to the first comparison value, specifically: the upper bias current is equal to the lower bias current, or: the lower bias current is equal to twice the upper bias current.

3. The periodic signal sampling circuit according to claim 1, characterized in that: The voltage-controlled current source includes a low clamping module and a voltage-controlled current module. The low clamping module is used to configure the lowest value of the charge pump capacitor voltage, and the voltage-controlled current module is used to output current.

4. The periodic signal sampling circuit according to claim 3, characterized in that: The low clamp module includes a first MOS tube and a second MOS tube, wherein the source of the first MOS tube is used to receive the charge pump capacitor voltage, the drain of the first MOS tube is connected to a power supply, the gate of the first MOS tube is connected to the drain of the second MOS tube, the gate of the second MOS tube is connected to the source of the first MOS tube, and the source of the second MOS tube is grounded.

5. The periodic signal sampling circuit according to claim 4, characterized in that: The voltage-controlled current module also includes a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sampling resistor. The gate of the third MOS tube is connected to the gate of the second MOS tube, the drain of the third MOS tube is connected to the drain of the fourth MOS tube, the source of the third MOS tube is connected to one end of the sampling resistor, the other end of the sampling resistor is grounded, the source of the fourth MOS tube is connected to a power supply, the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube, the gate and drain of the fourth MOS tube are connected, the source of the fifth MOS tube is connected to the power supply, and the drain of the fifth MOS tube is used to output current.

6. The periodic signal sampling circuit according to claim 1, characterized in that: The logic judgment module obtains a sampling signal, inverts the sampling signal to obtain an inverted sampling signal, and controls the pull-up switch device and the pull-down switch device in the charge pump detection module and the capacitor discharge switch device of the charge pump output comparison module through a logic operation on the sampling signal and the inverted sampling signal.

7. The periodic signal sampling circuit according to claim 6, characterized in that: The logic judgment module is provided with a first inverter, a second inverter, a third inverter, a fourth inverter, a first logic NAND gate and a second logic NAND gate. The input end of the first inverter is connected to the output end of the comparator in the charge pump output comparison module, the input end of the second inverter is used to input a PWM signal, the output end of the second inverter is connected to the capacitor discharge switch device in the charge pump output comparison module, the input end of the first logic NAND gate is respectively connected to the output end of the comparator and the PWM signal, the inverting output end of the first logic NAND gate is connected to the input end of the third inverter, the output end of the third inverter is connected to the pull-down switch device in the charge pump detection module, the input end of the second logic NAND gate is respectively connected to the output end of the first inverter and the PWM signal, the output end of the first inverter is used to output an inverted sampling signal, the inverting output end of the second logic NAND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the pull-up switch device in the charge pump detection module.

8. The periodic signal sampling circuit according to claim 1, characterized in that: In the charge pump detection module, the upper bias current is the charging current from the power supply to the charge pump capacitor, the lower bias current is the current from the charge pump capacitor to the ground, and the switch device is a MOS tube or a triode.

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