Dynamic multi-clock domain soc chip signal observation device and method

Abstract

The invention discloses a dynamic multi-clock domain soc chip signal observation device and method.The dynamic multi-clock domain soc chip signal observation device comprises a plurality of first selection modules, a plurality of second selection modules, a plurality of clock domain crossing signal splicing modules and a third selection module, the cross-clock-domain signal splicing module carries out cross-time-domain and splicing operation on the signals to be detected, and finally the third selection module carries out the last round of screening and sends the signals to a pad port for observation. Static signals, quasi-static signals and high-speed dynamic signals are processed in a unified mode, an additional high-speed IO port is not needed for achieving a debug function, and real-time observation can be conducted on clocks, control signals and data signals.

Description

Technical Field

[0001] The present invention relates to the technical field of dynamic multi-clock domain real-time debugging of SOC chips, and more specifically, to a dynamic multi-clock domain SOC chip signal observation device and method. Background Art

[0002] With the continuous expansion of the scale of integrated circuits and the widespread application of low-power technologies such as multi-clock domains and dynamic clock domains, a real-time debugging solution for SoC chips with dynamic multi-clock domains is needed. The existing test solution processes high-speed signals, quasi-static signals and static signals separately, tests static signals and quasi-static signals through JTAG, and pulls high-speed dynamic signals to the pad port for observation. Among them, static signals refer to signals that remain unchanged, quasi-static signals refer to signals with a signal rate between 1M-100M, and high-speed dynamic signals refer to signals with a rate of >100M.

[0003] The existing test solutions have the technical problem of not being able to observe key signals in real time. Testing through JTAG technology is actually the process of reading and writing registers, which cannot achieve the purpose of real-time observation. Secondly, there is no clear debug solution for SoCs with dynamic multi-clock domains (different clocks are used between IPs, and each IP has its own clock domain that changes dynamically). Summary of the invention

[0004] One of the purposes of the present invention is to provide a dynamic multi-clock domain SOC chip signal observation device to solve the technical problem in the prior art that the signals of the SOC chip using dynamic multi-clock domain technology cannot be observed in real time; the second purpose of the present invention is to provide a dynamic multi-clock domain SOC chip signal observation method.

[0005] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A first aspect of the present invention provides a dynamic multi-clock domain SOC chip signal observation device, comprising a plurality of first selection modules, a plurality of second selection modules, a plurality of cross-clock domain signal splicing modules and a third selection module, wherein:

[0007] The inputs of the multiple input ends of each of the first selection modules are different signals to be observed in the SOC chip function module, and the output ends of several first selection modules whose inputs are signals to be observed from the same clock domain are respectively connected to the multiple input ends of the same second selection module, and the multiple first selection modules whose inputs are signals to be observed from different clock domains are respectively connected to different second selection modules;

[0008] Each of the second selection modules is respectively connected to a cross-clock domain signal splicing module to send the signal to be observed selected and output by the second selection module to the cross-clock domain signal splicing module. The cross-clock domain signal splicing module divides the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located according to the frequency division factor of the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located relative to the reference clock signal of the preset clock rate to obtain a divided clock signal, and performs a cross-time domain operation on the signal to be observed selected and output by the second selection module according to the divided clock signal. Finally, the signal to be observed after crossing the clock domain is spliced ​​with the frequency division factor and output, and the output ends of all the cross-clock domain signal splicing modules are connected to the input end of the third selection module;

[0009] The output of the third selection module is sent to the pad port for observation.

[0010] In the above technical solution, according to the bottom-up principle of soc design, it is divided into three levels: module → IP → top. The signal to be observed is selected by pre-setting the module-level default register. At the IP layer, the first selection module and the second selection module are used to select the signals selected from each functional module. At the top layer, the cross-clock domain signal splicing module is used to calculate the clock rate that meets the PAD port, and then the asynchronous FIFO is used to cross the clock domain. Finally, the third selection module is used to perform the final round of screening on the signals selected by each IP and send them to the PAD port for observation, which solves the technical problem that the signals of the soc chip using dynamic multi-clock domain technology cannot be observed in real time.

[0011] Furthermore, the signal to be observed includes a key signal, and the default value of the selection end of the first selection module, the default value of the selection end of the second selection module, and the default value of the selection end of the third selection module are bound as the key signal.

[0012] Furthermore, the first selection module, the second selection module and the third selection module all include a multiplexer.

[0013] Furthermore, the cross-clock domain signal splicing module includes a frequency division factor calculation submodule, a frequency division submodule, a FIFO submodule and a splicing submodule, wherein:

[0014] The input end of the frequency division factor calculation submodule receives a reference clock signal of a preset clock rate, a clock signal of a clock domain where the signal to be observed is located, and a reset signal respectively, and the frequency division factor calculation submodule outputs a frequency division factor, and outputs the frequency division factor to the frequency division submodule and the splicing submodule respectively;

[0015] The input end of the frequency division submodule receives the frequency division factor and the clock signal of the clock domain where the signal to be observed is located respectively, and the frequency division submodule outputs the frequency division clock signal to the FIFO submodule;

[0016] The input end of the FIFO submodule receives the clock signal of the clock domain where the signal to be observed is located, the frequency-divided clock signal and the signal to be observed respectively. The FIFO submodule uses the clock signal of the clock domain where the signal to be observed is located as a write clock and the frequency-divided clock signal as a read clock to cache the signal to be observed and obtain the signal to be observed after crossing the clock domain;

[0017] The inputs of the input end of the splicing submodule are the frequency division factor and the signal to be observed after crossing the clock domain. The splicing submodule splices the frequency division factor and the signal to be observed after crossing the clock domain together and sends them out.

[0018] The second aspect of the present invention provides a method for observing a SOC chip signal in a dynamic multi-clock domain of the SOC chip signal observation device in a dynamic multi-clock domain, comprising the following steps:

[0019] Inputting the signals to be observed in each functional module of the chip to the input terminals of different first selection modules for preliminary selection;

[0020] The outputs of all the second selection modules are grouped according to clock domains, and the output ends of the second selection modules in the same group are connected to the input end of one of the cross-clock domain signal splicing modules;

[0021] The cross-clock domain signal splicing module uses the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected by the second selection module to calculate the frequency division factor, and uses the frequency division factor to divide the clock signal of the clock domain where the signal to be observed is located and the second selection module to obtain the divided clock signal, and performs a cross-time domain operation on the signal to be observed selected by the second selection module according to the divided clock signal, and finally splices the signal to be observed after crossing the clock domain with the frequency division factor and outputs it to obtain the spliced ​​signal;

[0022] The third selection module selects all the spliced ​​signals and sends them to the pad port for observation.

[0023] Furthermore, the output signals of the first selection module, the second selection module and the third selection module are controlled by controlling the values ​​of the selection terminals of the first selection module, the second selection module and the third selection module respectively.

[0024] Furthermore, the signal to be observed includes a key signal, and the default value of the selection end of the first selection module, the default value of the selection end of the second selection module, and the default value of the selection end of the third selection module are bound as the key signal.

[0025] Furthermore, the cross-clock domain signal splicing module uses the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected and output by the second selection module to calculate the frequency division factor, including:

[0026] The second selection module is used to select the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate to calculate the division factor, so that the clock signal / division factor of the clock domain where the signal to be observed is located selected by the second selection module is less than or equal to 100M and locked.

[0027] Furthermore, the second selection module is used to select the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate to calculate the frequency division factor, including:

[0028] A first latch, a second latch, a first AND gate, a second AND gate, a first multiplexer and a second multiplexer, a first D-type flip-flop and a second D-type flip-flop are provided, wherein:

[0029] The input signals of the two input terminals of the first latch are respectively an enable signal and a reference clock signal of a preset clock rate, the output terminal of the first latch is connected to an input terminal of a first AND gate, the input of the other input terminal of the first AND gate is the reference clock signal of the preset clock rate, and the output terminal of the first AND gate is connected to the clock input terminal of the first D-type flip-flop;

[0030] The data input terminal of the first D-type flip-flop is connected to the output terminal of the first multiplexer, and the main output terminal of the first D-type flip-flop outputs an analysis signal of the reference clock;

[0031] The input of the control end of the first multiplexer is the enable signal, and the inputs of the two input ends of the first multiplexer are respectively the analysis signal of the current reference clock and the analysis signal of the reference clock after +1;

[0032] A judgment unit is also provided, wherein the input of the input end of the judgment unit is the current analysis signal of the reference clock, and the output end of the judgment unit outputs the judgment signal of the reference clock, when the analysis signal of the reference clock is a preset value, the judgment signal of the reference clock is a first state value, and when the analysis signal of the reference clock is not a preset value, the judgment signal of the reference clock is a second state value;

[0033] The input signals of the two input terminals of the second latch are respectively the clock signal of the clock domain where the signal to be observed is located and the determination signal of the reference clock, the output terminal of the second latch is connected to one input terminal of the second AND gate, the input of the other input terminal of the second AND gate is the clock signal of the clock domain where the signal to be observed is located, and the output terminal of the second AND gate is connected to the clock input terminal of the second D-type flip-flop;

[0034] The data input terminal of the second D-type flip-flop is connected to the output terminal of the second multiplexer, the input of the control terminal of the second multiplexer is the determination signal of the reference clock, and the inputs of the two input terminals of the second multiplexer are respectively the feedback signal output by the main output terminal of the second D-type flip-flop and the signal obtained by adding 1 to the feedback signal output by the main output terminal of the second D-type flip-flop;

[0035] The main output terminal of the second D-type flip-flop outputs a frequency division factor.

[0036] Furthermore, if the current output of the second selection module does not require dynamic frequency modulation, the cross-clock domain signal splicing module directly outputs a fixed frequency division factor.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] The present invention uniformly processes static signals, quasi-static signals, and high-speed dynamic signals, does not require additional high-speed IO ports for debug functions, and can perform real-time observation of clocks, control signals, and data signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A structural schematic diagram of a dynamic multi-clock domain SOC chip signal observation device provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a default transmission path of a key signal of a signal to be observed provided by an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of the structure of a cross-clock domain signal splicing module provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of a flow chart of a dynamic multi-clock domain SOC chip signal observation method provided by an embodiment of the present invention;

[0043] Figure 5 A schematic diagram of a method for calculating a frequency division factor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0045] In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0046] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0047] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0048] Example

[0049] This embodiment provides a dynamic multi-clock domain SOC chip signal observation device, such as Figure 1 As shown, it includes multiple first selection modules, multiple second selection modules, multiple cross-clock domain signal splicing modules and a third selection module, wherein:

[0050] The inputs of the multiple input ends of each of the first selection modules are different signals to be observed in the SOC chip function module, and the output ends of several first selection modules whose inputs are signals to be observed from the same clock domain are respectively connected to the multiple input ends of the same second selection module, and the multiple first selection modules whose inputs are signals to be observed from different clock domains are respectively connected to different second selection modules;

[0051] It should be noted that the input signal to be observed of the first selection module can be a static signal, a quasi-static signal or a high-speed dynamic signal. It should be noted that, unlike the prior art, this embodiment uniformly processes static signals, quasi-static signals or high-speed dynamic signals, and does not require additional high-speed IO ports. In each observation cycle, the first selection module is used to select and send an input signal to be observed of the first selection module to the second selection module to achieve the first screening at the module level; the input signal to be observed of the second selection module is the signal to be observed that has been screened for the first time from various functional modules of the soc chip. In each observation cycle, the second selection module is used to select an input signal to be observed to achieve the secondary screening at the IP level;

[0052] Each of the second selection modules is respectively connected to a cross-clock domain signal splicing module to send the signal to be observed selected and output by the second selection module to the cross-clock domain signal splicing module. The cross-clock domain signal splicing module divides the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located according to the frequency division factor of the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located relative to the reference clock signal of the preset clock rate to obtain a divided clock signal, and performs a cross-time domain operation on the signal to be observed selected and output by the second selection module according to the divided clock signal. Finally, the signal to be observed after crossing the clock domain is spliced ​​with the frequency division factor and output, and the output ends of all the cross-clock domain signal splicing modules are connected to the input end of the third selection module;

[0053] It should be noted that the cross-clock domain signal splicing module first calculates the division factor, divides the clock rate of the observed signal according to the division factor, and then uses the divided clock rate to perform cross-clock operations on the observed signal. After crossing the time domain, all the signals to be observed are placed in the same clock domain to achieve real-time observation of the observed signal. At the same time, the division factor during division is spliced ​​with the signal after crossing the time domain, which can facilitate the reverse calculation of the original clock rate of the observed signal, and thus the observed signal can be debugged.

[0054] The output of the third selection module is sent to the pad port for observation.

[0055] In a further embodiment, the signal to be observed includes a key signal, and the default value of the selection end of the first selection module, the default value of the selection end of the second selection module and the default value of the selection end of the third selection module are bound as the key signal.

[0056] It should be noted that by binding the default value of the selection end of each selection module as the key signal in the signal to be observed, when the CPU is not started or the CPU cannot work normally, at this time, the selection end signal of each selection module cannot be controlled by the configuration register, and the key signal in the signal to be observed can still be obtained for observation and debugging.

[0057] It should be noted that on the soc chip, a register is pre-configured to control the value of the selection end of each selection module, and under the control of the default value of the register, the signal selected by the default of each selection module is the key signal in the signal to be observed. Specifically, Figure 2 The transmission paths of key signals are marked in the figure, but the transmission paths of other signals are not marked, such as Figure 2As shown, when the first input end of a first selection module is connected to a key signal in the signal to be observed, when setting the selection end of the first selection module, the first input end of the first selection module is selected by default, and the output end of the first selection module is connected to the second input end of a second selection module. At this time, when setting the selection end of the second selection module, the second input end of the second selection module is selected by default, so that by default, the signal entering the cross-clock domain signal splicing module is the key signal in the signal to be observed, and at the same time, the output of the cross-clock domain signal splicing module is connected to the third input end of the third selection module. When setting the selection end of the third selection module, the third input end of the third selection module is selected by default. Through such a setting, the signal finally sent to the pad port is the key signal in the signal to be observed.

[0058] In a further embodiment, the first selection module, the second selection module and the third selection module all include a multiplexer.

[0059] It should be noted that each selection module is composed of a multiplexer, and each input end of the multiplexer can input a signal to be observed. The number of signals to be observed can be set as much as possible to achieve comprehensive observation of the SOC chip signal.

[0060] In a further embodiment, Figure 3 As shown, the cross-clock domain signal splicing module includes a frequency division factor calculation submodule, a frequency division submodule, a FIFO submodule and a splicing submodule, wherein:

[0061] The frequency division factor calculation submodule is used to calculate and lock the frequency division factor. The input end of the frequency division factor calculation submodule receives a reference clock signal of a preset clock rate, a clock signal of a clock domain where the signal to be observed is located, and a reset signal. The frequency division factor calculation submodule outputs the frequency division factor, and outputs the frequency division factor to the frequency division submodule and the splicing submodule respectively.

[0062] It should be noted that the frequency division factor calculation submodule can be composed of a frequency division circuit.

[0063] The frequency division submodule divides the input clock according to the frequency division factor, the input end of the frequency division submodule receives the frequency division factor and the clock signal of the clock domain where the signal to be observed is located respectively, and the frequency division submodule outputs the divided clock signal to the FIFO submodule;

[0064] The FIFO submodule is used to perform cross-time domain operations on the signal. The input end of the FIFO submodule receives the clock signal of the clock domain where the signal to be observed is located, the frequency-divided clock signal and the signal to be observed respectively. The FIFO submodule uses the clock signal of the clock domain where the signal to be observed is located as a write clock and the frequency-divided clock signal as a read clock to cache the signal to be observed and obtain the signal to be observed after crossing the clock domain.

[0065] The splicing submodule is used to bind the frequency division factor and the data together. The input of the input end of the splicing submodule is the frequency division factor and the signal to be observed after crossing the clock domain. The splicing submodule splices the frequency division factor and the signal to be observed after crossing the clock domain together and sends them out.

[0066] It should be noted that after the signal to be observed passes through the cross-clock domain signal splicing module, the cross-time domain operation is completed and the signal is spliced ​​together with the frequency division factor of the clock used for the cross-time domain.

[0067] This embodiment also provides a dynamic multi-clock domain SOC chip signal observation method based on the dynamic multi-clock domain SOC chip signal observation device, such as Figure 4 As shown, the following steps are included:

[0068] Inputting the signals to be observed in each functional module of the chip to the input terminals of different first selection modules for preliminary selection;

[0069] In this step, the signals to be observed in the chip functional modules are selected as the signals to be observed in the chip design stage, and are respectively input into different input terminals of the first selection module to achieve the first screening at the module level;

[0070] In a specific embodiment, the signal to be observed is a signal that needs to be observed during chip debugging, and may include the following signals:

[0071] Power management signals are used to ensure that the power supply of each module of the chip is normal, including core voltage, I / O voltage, etc., as well as parameters such as power conversion efficiency, voltage fluctuation and noise, to ensure that the chip works in a stable power environment;

[0072] Clock management signal, used to confirm that all clock signal frequencies are working properly;

[0073] Reset signal, check whether the reset signal meets the specification requirements, including reset width, reset delay, etc.;

[0074] Interface and bus signals are used to verify whether the interfaces and bus protocols between various modules inside the chip are normal, including data transmission, address mapping, command parsing, etc., which are the key to ensure smooth data flow inside the chip;

[0075] Logical function signals are used to debug the logical functions of the chip and check whether the functions of each module meet the design requirements;

[0076] Memory signals are used to check the memory modules inside the chip, such as RAM, ROM, Flash, etc., to ensure that they are working properly without data errors and read and write failures;

[0077] Specific debug signals: Add specific debug signals according to design needs, such as FIFO empty and full signals, debug signals for reading data in handshake mode (such as o_wait_read), debug signals for multi-state machines, etc., which can help quickly locate problems.

[0078] Among the above signals, the signal that remains unchanged is a static signal.

[0079] The outputs of all the second selection modules are grouped according to clock domains, and the output ends of the second selection modules in the same group are connected to the input end of one of the cross-clock domain signal splicing modules;

[0080] It should be noted that in this step, the secondary screening at the IP level is completed by the second selection module;

[0081] The cross-clock domain signal splicing module uses the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected by the second selection module to calculate the frequency division factor, and uses the frequency division factor to divide the clock signal of the clock domain where the signal to be observed is located and the second selection module to obtain the divided clock signal, and performs a cross-time domain operation on the signal to be observed selected by the second selection module according to the divided clock signal, and finally splices the signal to be observed after crossing the clock domain with the frequency division factor and outputs it to obtain the spliced ​​signal;

[0082] It should be noted that in this step, the cross-time domain operation is performed on the signal to be observed through the cross-clock domain signal, and then it is spliced ​​with the frequency division factor and output to the pad port for observation;

[0083] The third selection module selects all the spliced ​​signals and sends them to the pad port for observation;

[0084] It should be noted that, in this step, the last round of screening at the top level is completed through the third selection module.

[0085] It should be noted that the first selection module is responsible for selecting the key signals from the signals to be observed in the functional module, the second selection module is responsible for further selecting the signals output by the first selection module, and the third selection module performs the final round of selection on the signals output by the cross-clock domain signal splicing module, and then sends them to the pad port for observation. The cross-time domain operation is performed on the signal through the cross-clock domain signal splicing module so that the signal is in the same clock domain, and the frequency division factor is bound to the signal. When observing at the pad port, the original signal clock rate can be conveniently calculated through the frequency division factor, thereby realizing real-time observation of the signal.

[0086] In a further embodiment, the output signals of the first selection module, the second selection module and the third selection module are controlled by controlling the values ​​of the selection terminals of the first selection module, the second selection module and the third selection module respectively.

[0087] In a further embodiment, the signal to be observed includes a key signal, and the default value of the selection end of the first selection module, the default value of the selection end of the second selection module and the default value of the selection end of the third selection module are bound as the key signal.

[0088] It should be noted that on the soc chip, a register is pre-configured to control the value of the selection end of each selection module, and under the control of the default value of the register, the signal selected by the default of each selection module is the key signal in the signal to be observed. Specifically, Figure 2 The transmission paths of key signals are marked in the figure, but the transmission paths of other signals are not marked, such as Figure 2 As shown, when the first input end of a first selection module is connected to a key signal in the signal to be observed, when setting the selection end of the first selection module, the first input end of the first selection module is selected by default, and the output end of the first selection module is connected to the second input end of a second selection module. At this time, when setting the selection end of the second selection module, the second input end of the second selection module is selected by default, so that by default, the signal entering the cross-clock domain signal splicing module is the key signal in the signal to be observed, and at the same time, the output of the cross-clock domain signal splicing module is connected to the third input end of the third selection module. When setting the selection end of the third selection module, the third input end of the third selection module is selected by default. Through such a setting, the signal finally sent to the pad port is the key signal in the signal to be observed.

[0089] In a further embodiment, the cross-clock domain signal splicing module uses the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected and output by the second selection module to calculate the frequency division factor, including:

[0090] The second selection module is used to select the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate to calculate the division factor, so that the clock signal / division factor of the clock domain where the signal to be observed is located selected by the second selection module is less than or equal to 100M and locked.

[0091] In a further embodiment, the second selection module is used to select the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate to calculate the frequency division factor. The frequency division factor can be calculated based on the clock frequency and the baud rate. The calculation formula is: N = BRCLK / baud rate, where N is the frequency division factor, BRCLK is the clock frequency, and the baud rate is the required communication rate. At the same time, the frequency division factor can also be set based on the frequency division circuit, such as Figure 5 As shown, including:

[0092] A first latch, a second latch, a first AND gate, a second AND gate, a first multiplexer and a second multiplexer, a first D-type flip-flop and a second D-type flip-flop are provided, wherein:

[0093] The input signals of the two input terminals of the first latch are respectively an enable signal and a reference clock signal of a preset clock rate, the output terminal of the first latch is connected to an input terminal of a first AND gate, the input of the other input terminal of the first AND gate is the reference clock signal of the preset clock rate, and the output terminal of the first AND gate is connected to the clock input terminal of the first D-type flip-flop;

[0094] The data input terminal of the first D-type flip-flop is connected to the output terminal of the first multiplexer, and the main output terminal of the first D-type flip-flop outputs an analysis signal of the reference clock;

[0095] The input of the control end of the first multiplexer is the enable signal, and the inputs of the two input ends of the first multiplexer are respectively the analysis signal of the current reference clock and the analysis signal of the reference clock after +1; when working, under the control of the enable signal, the first multiplexer outputs the analysis signal of the reference clock after +1;

[0096] A judgment unit is also provided, wherein the input of the input end of the judgment unit is the current analysis signal of the reference clock, and the output end of the judgment unit outputs the judgment signal of the reference clock, when the analysis signal of the reference clock is a preset value, the judgment signal of the reference clock is a first state value, and when the analysis signal of the reference clock is not a preset value, the judgment signal of the reference clock is a second state value;

[0097] The input signals of the two input terminals of the second latch are respectively the clock signal of the clock domain where the signal to be observed is located and the determination signal of the reference clock, the output terminal of the second latch is connected to one input terminal of the second AND gate, the input of the other input terminal of the second AND gate is the clock signal of the clock domain where the signal to be observed is located, and the output terminal of the second AND gate is connected to the clock input terminal of the second D-type flip-flop;

[0098] The data input end of the second D-type flip-flop is connected to the output end of the second multiplexer, the input of the control end of the second multiplexer is the judgment signal of the reference clock, and the inputs of the two input ends of the second multiplexer are respectively the feedback signal output by the main output end of the second D-type flip-flop and the signal obtained by adding 1 to the feedback signal output by the main output end of the second D-type flip-flop; when working, when the judgment signal of the reference clock is a first state value, the output end of the second multiplexer outputs the signal obtained by adding 1 to the feedback signal output by the main output end of the second D-type flip-flop, and when the judgment signal of the reference clock is not the first state value, the output end of the second multiplexer outputs the feedback signal output by the main output end of the second D-type flip-flop;

[0099] The output terminal of the second D-type flip-flop outputs the frequency division factor. During operation, after the feedback signal output from the main output terminal of the second D-type flip-flop is stable, the value of the feedback signal is the frequency division factor.

[0100] In a specific embodiment, under the control of an enable signal, in each cycle of a reference clock, the output of the first D-type flip-flop is increased by 1 based on the output of the previous cycle; when the output of the first D-type flip-flop is equal to 1, the output of the second D-type flip-flop is increased by 1 based on the output of the second D-type flip-flop in the previous cycle in each cycle of a clock signal in a clock domain where the signal to be observed is located; when the output of the first D-type flip-flop is not equal to 1, the output of the second D-type flip-flop maintains the output of the previous cycle unchanged.

[0101] In a further embodiment, if the current output of the second selection module does not require dynamic frequency modulation, the signal at this time satisfies the requirement of real-time observation, and the cross-clock domain signal splicing module directly outputs a fixed frequency division factor.

[0102] It should be noted that during the chip design phase, the signals that need to be observed by each functional module of the chip are connected to the first selection module, and then selected by the selection module and processed by the cross-clock domain signal splicing module. At the same time, the most critical signals to be observed need to be considered, and the default values ​​of the selection terminals of each level of selection modules are bound to the most critical observation signals, so that the critical signals can be debugged when the CPU cannot work normally;

[0103] Each cross-clock domain signal splicing module corresponds to a clock domain. Theoretically, as many cross-clock domain signal splicing modules are needed as there are clock domains. The input signals of the cross-clock domain signal splicing module should come from the same clock domain. Therefore, during the chip design stage, all signals output by the first selection modules need to be grouped by clock domain and then connected to the input of the cross-clock domain signal module.

[0104] After completing the above chip design, the specific debugging process after the chip is returned is as follows:

[0105] 1. When the CPU is not started, that is, when the configuration register cannot control the selection end signals of each selection module, because the most critical signals to be observed have been bound to the selection end during the chip design stage, these debug signals can be used directly;

[0106] 2. After starting the CPU, by default, observe the signal bound to the default value of the selection end. First, modify the selection end signal of each level of selection module through the configuration register to bind the signal you want to observe;

[0107] 3. The cross-clock domain signal splicing module calculates the frequency division factor, crosses the clock domain, and splices the signals in different clock domains;

[0108] 4. The third selection module performs the final round of selection on the data sent by different cross-clock domain signal splicing modules and sends it to the pad port for observation and debugging. At the same time, because the previous division factor has been bound to the data, the original clock rate can be calculated through the division factor bound to the upper four bits of the signal.

[0109] The same or similar reference numerals correspond to the same or similar components;

[0110] The terms used in the drawings to describe positional relationships are only used for illustrative purposes and should not be construed as limiting this patent;

[0111] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A dynamic multi-clock domain soc chip signal observation device, characterized in that: It includes multiple first selection modules, multiple second selection modules, multiple cross-clock domain signal splicing modules and a third selection module, wherein: The inputs of the multiple input ends of each of the first selection modules are different signals to be observed in the SOC chip function module, and the output ends of several first selection modules whose inputs are signals to be observed from the same clock domain are respectively connected to the multiple input ends of the same second selection module, and the multiple first selection modules whose inputs are signals to be observed from different clock domains are respectively connected to different second selection modules; Each of the second selection modules is respectively connected to a cross-clock domain signal splicing module to send the signal to be observed selected and output by the second selection module to the cross-clock domain signal splicing module. The cross-clock domain signal splicing module divides the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located according to the frequency division factor of the clock signal of the clock domain where the signal to be observed selected and output by the second selection module is located relative to the reference clock signal of the preset clock rate to obtain a divided clock signal, and performs a cross-time domain operation on the signal to be observed selected and output by the second selection module according to the divided clock signal. Finally, the signal to be observed after crossing the clock domain is spliced ​​with the frequency division factor and output, and the output ends of all the cross-clock domain signal splicing modules are connected to the input end of the third selection module; The output of the third selection module is sent to the pad port for observation.

2. The dynamic multi-clock domain soc chip signal observation device according to claim 1, characterized in that: The signal to be observed includes a key signal, and a default value of a selection end of the first selection module, a default value of a selection end of the second selection module, and a default value of a selection end of the third selection module are bound as the key signal.

3. The dynamic multi-clock domain soc chip signal observation device according to claim 1, characterized in that: The first selection module, the second selection module and the third selection module all include a multiplexer.

4. The dynamic multi-clock domain soc chip signal observation device according to claim 1, characterized in that: The cross-clock domain signal splicing module includes a frequency division factor calculation submodule, a frequency division submodule, a FIFO submodule and a splicing submodule, wherein: The input end of the frequency division factor calculation submodule receives a reference clock signal of a preset clock rate, a clock signal of a clock domain where the signal to be observed is located, and a reset signal respectively, and the frequency division factor calculation submodule outputs a frequency division factor, and outputs the frequency division factor to the frequency division submodule and the splicing submodule respectively; The input end of the frequency division submodule receives the frequency division factor and the clock signal of the clock domain where the signal to be observed is located respectively, and the frequency division submodule outputs the frequency division clock signal to the FIFO submodule; The input end of the FIFO submodule receives the clock signal of the clock domain where the signal to be observed is located, the frequency-divided clock signal and the signal to be observed respectively. The FIFO submodule uses the clock signal of the clock domain where the signal to be observed is located as a write clock and the frequency-divided clock signal as a read clock to cache the signal to be observed and obtain the signal to be observed after crossing the clock domain; The inputs of the input end of the splicing submodule are the frequency division factor and the signal to be observed after crossing the clock domain. The splicing submodule splices the frequency division factor and the signal to be observed after crossing the clock domain together and sends them out.

5. A method for observing SOC chip signals in a dynamic multi-clock domain based on the SOC chip signal observation device in a dynamic multi-clock domain according to any one of claims 1 to 4, characterized in that: The following steps are involved: Inputting the signals to be observed in each functional module of the chip to the input terminals of different first selection modules for preliminary selection; The outputs of all the second selection modules are grouped according to clock domains, and the output ends of the second selection modules in the same group are connected to the input end of one of the cross-clock domain signal splicing modules; The cross-clock domain signal splicing module uses the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected by the second selection module to calculate the frequency division factor, and uses the frequency division factor to divide the clock signal of the clock domain where the signal to be observed is located and the second selection module to obtain the divided clock signal, and performs a cross-time domain operation on the signal to be observed selected by the second selection module according to the divided clock signal, and finally splices the signal to be observed after crossing the clock domain with the frequency division factor and outputs it to obtain the spliced ​​signal; The third selection module selects all the spliced ​​signals and sends them to the pad port for observation.

6. The method for observing the signal of a SOC chip in a dynamic multi-clock domain according to claim 5, characterized in that: The output signals of the first selection module, the second selection module and the third selection module are controlled by controlling the values ​​of the selection terminals of the first selection module, the second selection module and the third selection module respectively.

7. The method for observing the signal of a SOC chip in a dynamic multi-clock domain according to claim 6, characterized in that: The signal to be observed includes a key signal, and a default value of a selection end of the first selection module, a default value of a selection end of the second selection module, and a default value of a selection end of the third selection module are bound as the key signal.

8. The method for observing the signal of a SOC chip in a dynamic multi-clock domain according to claim 7, characterized in that: The cross-clock domain signal splicing module calculates the frequency division factor using the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate selected and output by the second selection module, including: The second selection module is used to select the clock signal of the clock domain where the signal to be observed is located and the reference clock signal of the preset clock rate to calculate the division factor, so that the clock signal / division factor of the clock domain where the signal to be observed is located selected by the second selection module is less than or equal to 100M and locked.

9. The method for observing the signal of a SOC chip in a dynamic multi-clock domain according to claim 8, characterized in that: The method uses the second selection module to select and output a clock signal of a clock domain where the signal to be observed is located and a reference clock signal of a preset clock rate to calculate a frequency division factor, including: A first latch, a second latch, a first AND gate, a second AND gate, a first multiplexer and a second multiplexer, a first D-type flip-flop and a second D-type flip-flop are provided, wherein: The input signals of the two input terminals of the first latch are respectively an enable signal and a reference clock signal of a preset clock rate, the output terminal of the first latch is connected to an input terminal of a first AND gate, the input of the other input terminal of the first AND gate is the reference clock signal of the preset clock rate, and the output terminal of the first AND gate is connected to the clock input terminal of the first D-type flip-flop; The data input terminal of the first D-type flip-flop is connected to the output terminal of the first multiplexer, and the main output terminal of the first D-type flip-flop outputs an analysis signal of the reference clock; The input of the control end of the first multiplexer is the enable signal, and the inputs of the two input ends of the first multiplexer are respectively the analysis signal of the current reference clock and the analysis signal of the reference clock after +1; A judgment unit is also provided, wherein the input of the input end of the judgment unit is the current analysis signal of the reference clock, and the output end of the judgment unit outputs the judgment signal of the reference clock, when the analysis signal of the reference clock is a preset value, the judgment signal of the reference clock is a first state value, and when the analysis signal of the reference clock is not a preset value, the judgment signal of the reference clock is a second state value; The input signals of the two input terminals of the second latch are respectively the clock signal of the clock domain where the signal to be observed is located and the determination signal of the reference clock, the output terminal of the second latch is connected to one input terminal of the second AND gate, the input of the other input terminal of the second AND gate is the clock signal of the clock domain where the signal to be observed is located, and the output terminal of the second AND gate is connected to the clock input terminal of the second D-type flip-flop; The data input terminal of the second D-type flip-flop is connected to the output terminal of the second multiplexer, the input of the control terminal of the second multiplexer is the determination signal of the reference clock, and the inputs of the two input terminals of the second multiplexer are respectively the feedback signal output by the main output terminal of the second D-type flip-flop and the signal obtained by adding 1 to the feedback signal output by the main output terminal of the second D-type flip-flop; The main output terminal of the second D-type flip-flop outputs a frequency division factor.

10. The method for observing the signal of a SOC chip in a dynamic multi-clock domain according to claim 9, characterized in that: If the current output of the second selection module does not require dynamic frequency modulation, the cross-clock domain signal splicing module directly outputs a fixed frequency division factor.

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