Analog state signal and synchronization between integrated circuits

Abstract

The invention relates to analog state signal and synchronization between integrated circuits. Disclosed herein are methods for fault detection and communication in an analog power electronic circuit having a plurality of electronic fuses (e.g., a primary fuse and at least one secondary fuse). Current flow is monitored through each fuse. Fault conditions in the electronic fuses are identified. Upon detection, a fault signal line common to all fuses is driven to a voltage indicative of a detected fault condition. Then, the main electronic fuse latches the voltage on the fault signal line. The detection and communication circuitry enables a corrective action determined by the latched voltage to be performed at the fuse level.

Description

Technical Field

[0001] The present disclosure relates to the field of simulating power electronic circuits, and in particular to techniques for simulating communication between a plurality of electronic fuses connected in parallel in a power electronic circuit. Background Art

[0002] Electronic fuses are safety devices embedded within analog power electronic circuits that can cover a variety of applications such as power supplies, converters, and power amplifiers. For example, electronic fuses are used to protect systems such as computer servers and telecommunications peripherals. In these applications, fuses help implement hot-swap features (e.g., the ability to insert or remove components from an electronic device while the electronic device remains powered), thereby providing a safe connection between the power supply and the load.

[0003] An electronic fuse includes a power metal oxide semiconductor field effect transistor (MOSFET) located within an analog power electronic circuit where it can effectively cut off the current when necessary. Under normal operating conditions, the MOSFET is maintained in the "on" state, providing a steady flow of current through the components of the power electronic circuit. However, when the current monitored by the current sensor exceeds a predefined safety threshold or an unexpected voltage surge is detected, the controller switches the MOSFET to the "off" state. This rapid action interrupts the flow of current, providing protection for the remaining components of the power electronic circuit.

[0004] In this context, a master device refers to an electronic fuse that has a direct communication link with a digital control component of the system, thereby enabling it to receive information from and send information to this digital control component of the system. On the other hand, secondary devices are the remaining electronic fuses in the parallel topology that lack such a direct digital communication link, thereby limiting their ability to relay or receive status updates from the digital control component of the system.

[0005] In topologies where multiple e-fuses are used in parallel, this disconnection can become a problem. The lack of information exchange reduces the robustness of the topology and causes the secondary devices to operate essentially "blind".

[0006] Consider an event in which one secondary device, sensing an abnormal condition, limits the current through its MOSFET or shuts off its MOSFET entirely. Without direct communication with the rest of the devices, the state change of the affected secondary device is not immediately known to the other devices, including the primary device. This lack of immediate information exchange can cause the remaining devices to overload, a situation that can trigger a "cascading failure," a series of failures in a system of interconnected components, where the failure of one component can trigger the failure of subsequent components—for example, the shutting off of the MOSFET of one secondary device can trigger the shutting off of the MOSFETs of other devices. This indirect information exchange further complicates fault detection because the true root cause can be masked or obscured, leading to potential system instability or failure.

[0007] Therefore, there is an urgent need for a solution that not only enhances the robustness of power electronic circuits with parallel e-fuse topologies, but also improves the direct communication between e-fuses to provide effective fault detection and proactive fault management. Summary of the invention

[0008] A method for fault detection and communication in an analog power electronic circuit having a plurality of electronic fuses is disclosed herein, wherein the plurality of electronic fuses include a single main fuse and at least one secondary fuse. The method includes: monitoring the current through each of the plurality of electronic fuses; detecting a fault condition in at least one of the plurality of electronic fuses; driving a fault signal line common to each of the plurality of electronic fuses to a voltage corresponding to the detected fault condition; latching the voltage on the fault signal line using the main electronic fuse; performing corrective actions at the plurality of electronic fuses based on the latched voltage; and releasing the latching of the voltage.

[0009] Driving the fault signal line to a voltage corresponding to the detected fault condition can be performed as follows: at each of a plurality of electronic fuses, providing a constant current to a feedback node coupled to the fault signal line; and at the electronic fuse experiencing the fault condition, sinking current from the feedback node to set the voltage at the fault signal line to a voltage corresponding to the detected fault condition, the sinking current depending on the detected fault condition.

[0010] When a fault condition is detected within a plurality of the plurality of electronic fuses, the fault signal line may be driven to a voltage corresponding to the most severe fault condition.

[0011] When multiple fault conditions are detected within one of the multiple electronic fuses, the fault signal line may be driven to a voltage corresponding to the most severe fault condition.

[0012] When a fault condition is detected within at least one secondary fuse, driving the fault signal line to a voltage corresponding to the detected fault condition may include: generating a voltage pulse on the fault signal line by at least one secondary fuse using a timing circuit within at least one secondary fuse, the voltage pulse having an amplitude corresponding to the detected fault condition; and at a single main fuse, latching the voltage on the fault signal line in response to detecting the voltage pulse on the fault signal line.

[0013] Upon subsequent detection of normal operation of the at least one secondary fuse, resetting by the at least one secondary fuse may reset the timing circuit. Prior to resetting the timing circuit, the timing circuit may generate no further voltage pulses on the fault signal line.

[0014] The method may further include latching, by the main fuse, a voltage on the fault signal line, detecting the voltage on the fault signal line, driving the fault signal line to the detected voltage, and latching the voltage on the fault signal line.

[0015] The present invention also discloses an analog power electronic circuit, including: an input node and a voltage node; and a main fuse configured to conduct current between the input node and the voltage node. The main fuse may include: a logic circuit configured to generate an output indicating a fault within the analog power electronic circuit and the severity of the fault; a priority encoder configured to receive an output from the logic circuit and assert one of a plurality of control signals corresponding to the severity of the fault; a plurality of switches, each switch being controlled by a different one of a plurality of control signals to selectively couple an intermediate node to a voltage corresponding to the severity of the fault; and a current sink circuit configured to sink sufficient current from a feedback node so as to set the feedback node to a voltage corresponding to the severity of the fault. The analog power electronic circuit may also include: a fault signal line coupled to the feedback node; and a secondary fuse connected in parallel with the main fuse and configured to conduct current between the input node and the voltage node. The secondary fuse may be configured to: detect whether a fault is present in the secondary fuse; and in response to detecting a fault in the secondary fuse, set the fault signal line to a voltage corresponding to a severity of the fault for the duration of the pulse.

[0016] The controller may be configured to generate a reset signal to reset the priority encoder of the master fuse to release latching of the voltage of the fault signal line.

[0017] The main fuse may also include: a plurality of comparators, each comparator being configured to compare a voltage at a feedback node with a different threshold comparison voltage; a priority decoder being configured to receive outputs from the plurality of comparators and asserting a fault remediation signal from a plurality of fault remediation signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and a fault action block being configured to modify conduction of current through the secondary fuse based on the asserted fault remediation signal.

[0018] The main fuse may also include a fault detection circuit configured to generate an output indicating a fault within the main fuse and the severity of the fault. The logic circuit may include a plurality of logic OR gates, each logic OR gate performing a logic OR operation on a different corresponding output of the fault detection circuit and a corresponding fault remediation signal.

[0019] The current sinking circuit may be a current sinking buffer.

[0020] The secondary fuse may include: a fault detection circuit configured to generate an output indicating a fault within the secondary fuse and a severity of the fault; a timing circuit configured to generate pulses corresponding to those outputs of the fault detection circuit indicating all faults except the least severe fault; a priority encoder configured to receive pulses from the timing circuit and receive the output of the fault detection circuit indicating the least severe fault, and assert one of a plurality of control signals corresponding to the most severe fault indicated by the pulse and the output of the fault detection circuit indicating the least severe fault; a plurality of switches, each switch being controlled by a different control signal of the plurality of control signals to selectively couple an intermediate node to a voltage corresponding to the severity of the fault; and a current sink circuit configured to sink sufficient current from a feedback node to set the feedback node to a voltage corresponding to the severity of the fault.

[0021] The secondary fuse may also include: a plurality of comparators, each comparator being configured to compare a voltage at a feedback node with a different threshold comparison voltage; a priority decoder being configured to receive outputs from the plurality of comparators and asserting a fault recovery signal from a plurality of fault recovery signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and a fault action block being configured to modify conduction of current through the secondary fuse based on the asserted fault recovery signal.

[0022] Assertion of the fault remediation signal corresponding to the least severe fault may reset the timing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a block diagram of the analog power electronics circuit described in this article.

[0024] Figure 2 yes Figure 1 Schematic block diagram of the controller of the primary fuse and secondary fuse of the simulated power electronic circuit.

[0025] Figure 3-Figure 4 yes Figure 2 A graph of the voltage values ​​of the primary fuse and the secondary fuse during operation. DETAILED DESCRIPTION

[0026] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications other than those described above without departing from the spirit and scope of the disclosure. It is not intended to limit the disclosure to the embodiments shown, but rather to have the widest scope consistent with the principles and features disclosed or suggested herein.

[0027] Reference now Figure 1 An analog power electronic circuit 5 is described, which includes a plurality of electronic fuses controlled by a system controller 6 and connected in parallel between a power node (where an input voltage VIN is present) and a load 7. A plurality of such electronic fuses are connected in parallel to increase the total current handling capability. For example, if the current expected to flow between the power node and the load is higher than the current supported by a single electronic fuse, a plurality of such electronic fuses are connected in parallel to provide the desired current handling level. This can also provide better heat dissipation and distribution. The electronic fuses herein include a single main fuse 10 and n secondary fuses 30(1), ..., 30(n), where n is an integer, so there can be any number of secondary fuses 30(1), ..., 30(n).

[0028] The main fuse 10 includes a controller 11 that receives an ON / OFF signal from the system controller 6 and performs bidirectional communication with the system controller 6 via a data communication bus formed by a serial data line (SDA), a serial clock line (SCL), and a bus alert (BA) line. The main fuse includes an n-channel power transistor Tp, the drain of which is connected to the input voltage VIN, the source of which is connected to the load 7, and the gate of which is controlled by the controller 11. The controller 11 controls the gate of the transistor Tp based on feedback from a current sensor 27 that senses a drain current Ip of the transistor Tp, a voltage on a fault signal line FAULT, a state of the ON / OFF signal, and data received via the data communication bus.

[0029] Each secondary fuse 30(1), ..., 30(n) includes an n-channel power transistor Ts1, ..., Tsn, whose drains are connected to the input voltage VIN, sources are connected to the load 7, and gates are controlled by the corresponding controller 31(1), ..., 31(n) based on feedback from the corresponding current sensor 47(1), ..., 47(n), the voltage on the fault signal line FAULT, and the state of the ON / OFF signal.

[0030] First, the operation of the analog power electronic circuit 5 will be generally described, and then a description will be given of the specific details of the controllers 11 and 31 ( 1 ), . . . , 31 ( n ) and their operations.

[0031] Now to the general description, a fault signal line FAULT is connected to the controller 10 and 31 (1), ..., 31 (n) of each fuse 10 and 30 (1), ..., 30 (n). Its function is to facilitate communication between the main fuse 10 and the secondary fuses 30 (1), ..., 30 (n), in particular when a fault condition is detected. In the event of a fault condition in one of the secondary fuses 30 (1), ..., 30 (n), the relevant controller 31 (1), ..., 31 (n) performs corrective action. This may be to reduce the current through the corresponding power transistor Ts1, ..., Tsn or to completely shut down the power transistor. At the same time, the secondary fuse 31 (1), ..., 31 (n) experiencing the fault sinks current from the fault signal line FAULT for a given time period, thereby causing the voltage on FAULT to change to alert the other fuses of the fault condition - the voltage on FAULT pulsates for a given time period.

[0032] After detecting the voltage change on the fault signal line FAULT, the controller 11 of the main fuse 10 and the controllers 31(1), ..., 31(n) each perform a corrective action, and the controller 11 of the main fuse 10 latches the voltage so that it lasts for more than a given period of time, thereby substantially retaining the fault alarm. The latching mechanism persists until reset by the system controller 6.

[0033] The controller 11 will initiate the same corrective action process in the event that the fault condition originates within the primary fuse 10. In this case, the controller 11 will also sink current from the fault signal line FAULT and subsequently sink the voltage value on FAULT, making it visible to the system controller 6 and the secondary fuses 30(1), ..., 30(n) for detection and appropriate response.

[0034] Note that faults of varying severity may occur, and the voltage level on the fault signal line FAULT indicates the severity of the fault experienced by the associated fuse.

[0035] In some cases, multiple fuses may experience a fault. In this case, the fault signal line FAULT indicates the most severe fault due to the design of the controller 10 and 31 (1), ..., 31 (n), and therefore, the most severe fault experienced is given priority (e.g., the controller 10 and 31 (1), ..., 31 (n) takes corrective action in response to experiencing the most severe fault).

[0036] Now refer to Figure 2 , showing specific details of the controller 11 of the primary fuse 10 and the controller 31(1) of one of the secondary fuses 30(1), while it should be understood that the controller of each of the other secondary fuses is identical.

[0037] The controller 11 includes a fault detector 12 that determines the presence and severity of a fault based on feedback such as from a current sensor 27 that senses the drain current Ip of the transistor Tp, the voltage on the fault signal line FAULT, the state of the ON / OFF signal, and data received via the data communication bus. Other sources of fault indications read by the fault detector 12 may be undervoltage protection (UVP) triggers, overvoltage protection (OVP) triggers, thermal protection triggers, MOSFET diagnostics, etc. In this example, five levels of severity of faults may occur, so the fault detector 12 has five outputs O1, O2, O3, O4, O5, each output for indicating a fault of a different severity—output O1 is used to indicate the least severe fault, and the fault severity increases from O2 to O5, so output O5 is used to indicate the most severe fault.

[0038] The OR gate 13 has a first input connected to the output O2 of the fault detector 12, a second input connected to the output F2Y of the priority decoder 25, and an output at which a fault indication signal F2A is generated. The fault indication signal F2A indicates a fault whose severity is indicated by the assertion of O2. The OR gate 14 has a first input connected to the output O3 of the fault detector 12, a second input connected to the output F3Y of the priority decoder 25, and an output at which a fault indication signal F3A is generated. The fault indication signal F3A indicates a fault whose severity is indicated by the assertion of O3. The OR gate 15 has a first input connected to the output O4 of the fault detector 12, a second input connected to the output F4Y of the priority decoder 25, and an output at which a fault indication signal F4A is generated. The fault indication signal F4A indicates a fault whose severity is indicated by the assertion of O4. The OR gate 16 has a first input connected to the output O5 of the fault detector 12, a second input connected to the output F5Y of the priority decoder 25, and an output at which a fault indication signal F5A is generated. Fault indication signal F5A indicates a fault whose severity is indicated by assertion of O5.

[0039] The priority encoder 17 receives the fault indication signal F1A from the output O1 of the fault detector 12, the fault indication signal F2A from the output of the OR gate 13, the fault indication signal F3A from the output of the OR gate 14, the fault indication signal F4A from the output of the OR gate 15, and the fault indication signal F5A from the output of the OR gate 16. The priority encoder 17 generates control signals C1, C2, C3, C4, C5, C6 for controlling the actuation of the switches S1, S2, S3, S4, S5, S6.

[0040] The switch S1 selectively connects the first voltage V1 to the input of the current sink buffer 18 in response to the assertion of the control signal C1. The switch S2 selectively connects the second voltage V2 to the input of the current sink buffer 18 in response to the assertion of the control signal C2. The switch S3 selectively connects the third voltage V3 to the input of the current sink buffer 18 in response to the assertion of the control signal C3. The switch S4 selectively connects the fourth voltage V4 to the input of the current sink buffer 18 in response to the assertion of the control signal C4. The switch S5 selectively connects the fifth voltage V5 to the input of the current sink buffer 18 in response to the assertion of the control signal C5. The switch S6 selectively connects the sixth voltage V6 to the input of the current sink buffer 18 in response to the assertion of the control signal C6. Voltage V1 (e.g., 3V) is greater than voltage V2 (e.g., 2V), voltage V2 is greater than voltage V3 (e.g., 1.5V), voltage V3 is greater than voltage V4 (e.g., 1.0V), voltage V4 is greater than voltage V5 (e.g., 0.5V), and voltage V5 is greater than voltage V6 (e.g., 0V).

[0041] The constant current source 24 provides a constant current to the node Nn. When none of the fault indication signals F1A, F2A, F3A, F4A, F5A are asserted, the priority encoder 17 asserts the control signal C1, thereby connecting the input of the current sink buffer 18 to the voltage V1, causing the current sink buffer 18 to sink sufficient current from its output at the node Nn so that the voltage at the node Nn is set to V1. When one or more of the fault indication signals F1A, F2A, F3A, F4A, and F5A are asserted, the priority encoder 17 asserts a corresponding one of the control signals C2, C3, C4, C5, and C6—when F1A is asserted, the priority encoder 17 asserts the control signal C2 to set the voltage at the node Nn to the voltage V2; when F2A is asserted, the priority encoder 17 asserts the control signal C3 to set the voltage at the node Nn to the voltage V3; when F3A is asserted, the priority encoder 17 asserts the control signal C4 to set the voltage at the node Nn to the voltage V4; when F4A is asserted, the priority encoder 17 asserts the control signal C5 to set the voltage at the node Nn to the voltage V5; and when F5A is asserted, the priority encoder 17 asserts the control signal C6 to set the voltage at the node Nn to the voltage V6.

[0042] The lower the voltage level at which node Nn is set, the more severe the fault that has occurred. A chart showing an example mapping of specific fault types to voltage can be seen below:

[0043]

[0044] Only one of the control signals C1, C2, C3, C4, C5 may be asserted at a time. When multiple of the fault indication signals F1A, F2A, F3A, F4A, F5A are asserted, the priority encoder 17 will take action based on the fault indication that represents the most severe fault (highest priority). For example, if both F2A and F4A are asserted, the priority encoder 17 asserts the control signal C5 to connect the voltage V5 to the input of the current sink buffer 18 because the assertion of the fault indication signal F4A represents a more severe fault than the assertion of the fault indication signal F2A.

[0045] The first hysteresis comparator 19 has an inverting input terminal connected to the first threshold comparison voltage Vt1, a non-inverting input terminal connected to the node Nn, and an output generating a comparison signal Cs1. The second hysteresis comparator 20 has an inverting input terminal connected to the second threshold comparison voltage Vt2, a non-inverting input terminal connected to the node Nn, and an output generating a comparison signal Cs2. The third hysteresis comparator 21 has an inverting input terminal connected to the third threshold comparison voltage Vt3, a non-inverting input terminal connected to the node Nn, and an output generating a comparison signal Cs3. The fourth hysteresis comparator 22 has an inverting input terminal connected to the fourth threshold comparison voltage Vt4, a non-inverting input terminal connected to the node Nn, and an output generating a comparison signal Cs4. The fifth hysteresis comparator 23 has an inverting input terminal connected to the fifth threshold comparison voltage Vt5, a non-inverting input terminal connected to the node Nn, and an output generating a comparison signal Cs5.

[0046] The first threshold comparison voltage Vt1 (e.g., 2.25V) is greater than the second threshold comparison voltage Vt2 (e.g., 1.75V), the second threshold comparison voltage Vt2 is greater than the third threshold comparison voltage Vt3 (e.g., 1.25V), the third threshold comparison voltage Vt3 is greater than the fourth threshold comparison voltage Vt4 (e.g., 0.75V), and the fourth threshold comparison voltage Vt4 is greater than the fifth threshold comparison voltage Vt5 (e.g., 0.25V).

[0047] The priority decoder 25 receives comparison signals Cs1, Cs2, Cs3, Cs4, Cs5 as inputs and asserts the corresponding highest priority output signal among the output signals F1Y, F2Y, F3Y, F4Y, F5Y when at least one of these comparison signals is asserted. Therefore, the output signal F1Y is asserted to indicate that the comparison signal Cs1 is asserted (indicating that the fault indication signal F1A is the most serious fault indicated by the fault detector 12), the output signal F2Y is asserted to indicate that the comparison signal Cs2 is asserted (indicating that the fault indication signal F2A is the most serious fault indicated by the fault detector 12), the output signal F3Y is asserted to indicate that the comparison signal Cs3 is asserted (indicating that the fault indication signal F3A is the most serious fault indicated by the fault detector 12), the output signal F4Y is asserted to indicate that the comparison signal Cs4 is asserted (indicating that the fault indication signal F4A is the most serious fault indicated by the fault detector 12), and the output signal F5Y is asserted to indicate that the comparison signal Cs5 is asserted (indicating that the fault indication signal F5A is the most serious fault indicated by the fault detector 12).

[0048] The fault action block 26 takes corrective actions depending on which of the output signals F1Y, F2Y, F3Y, F4Y, F5Y is asserted. These corrective actions may be, for example, turning off the transistor Tp, modulating the gate voltage of the transistor Tp, etc.

[0049] In operation, the hysteresis comparators 19, 20, 21, 22, 23 each compare the voltage at the node Nn with its corresponding threshold comparison voltage Vt1, Vt2, Vt3, Vt4, Vt5, and when the voltage at the node Nn is greater than those corresponding comparison threshold voltages Vt1, Vt2, Vt3, Vt4, Vt5 by the hysteresis threshold, assert their outputs to generate corresponding comparison signals Cs1, Cs2, Cs3, Cs4, Cs5. The priority decoder 25 receives the comparison signals Cs1, Cs2, Cs3, Cs4, Cs5 as inputs, and when at least one of these comparison signals is asserted, asserts the corresponding highest priority output signal among the output signals F1Y, F2Y, F3Y, F4Y, F5Y, and the fault action block takes corrective action based thereon. OR gates 13, 14, 15, 16 perform a logical OR operation between the signals on outputs O2, O3, O4, O5 from the fault detector 12 and the output signals F2Y, F3Y, F4Y, F5Y, and generate fault indication signals F2A, F3A, F4A, F5A as a result. Priority encoder 17 receives fault indication signals F1A, F2A, F3A, F4A, F5A as inputs, and when at least one of these fault indication signals is asserted, asserts one of control signals C2, C3, C4, C5, C6 corresponding to the one with the highest priority among fault indication signals F1A, F2A, F3A, F4A, F5A, thereby closing the associated switches S2, S3, S4, S5, S6, and latching the control signal. As a result, the voltage V2, V3, V4, V5, V6 associated with the closed switch appears at the input of the current sink buffer 18, causing the current sink buffer 18 to sink sufficient current from the node Nin to set the voltage at that node to the voltage associated with the closed switch. If and when the reset signal RES is asserted (which may be asserted periodically by the system controller 6, or may be asserted by the system controller 6 in response to other conditions or received commands), the priority encoder 17 releases the latched control signals C2, C3, C4, C5, C6. If the same highest priority fault still exists, the same corresponding fault indication signal F1A, F2A, F3A, F4A, F5A will be re-asserted, and if the fault indication signal is F2A, F3A, F4A, F5A, then the fault indication signal will be asserted regardless of whether the fault is detected by the fault detector 12 of the primary fuse 10 or by the fault detector 32 of one of the secondary fuses 30(1), ..., 30(n).

[0050] Note that if none of the fault indication signals F1A, F2A, F3A, F4A, F5A are asserted, the priority encoder 17 asserts the control signal C1 but does not latch it - once one of the fault indication signals F1A, F2A, F3A, F4A, F5A is asserted, the priority encoder 17 responds as described above. Therefore, unless and until one of the fault indication signals F1A, F2A, F3A, F4A, F5A is asserted in the primary fuse 11 or one of the secondary fuses 31(1), ..., 31(n), the voltage at the node Nn remains at the voltage V1.

[0051] The controller 31(1) includes a fault detector 32 that determines the presence and severity of a fault based on feedback from a current sensor 47(1) that senses the drain current Is1 of the transistor Ts1, the voltage on the fault signal line FAULT, and the state of the ON / OFF signal. In this example, five levels of fault severity may occur, so the fault detector 32 has five outputs Os1, Os2, Os3, Os4, Os5, each output for indicating a fault of a different severity—output Os1 for indicating the least severe fault, and fault severity increases from Os2 to Os5, so output Os5 for indicating the most severe fault.

[0052] The timing circuit 33 has inputs connected to the outputs Os2, Os3, Os4, Os5 of the fault detector 32, and generates relevant fault indication pulses Ft2A, Ft3A, Ft4A, Ft5A at corresponding outputs in response to assertion of the outputs Os2, Os3, Os4, Os5 of the fault detector 32. In particular, the timing circuit 33 generates the fault indication pulse Ft2A when the output Os2 is asserted, the timing circuit 33 generates the fault indication pulse Ft3A when the output Os3 is asserted, the timing circuit 33 generates the fault indication pulse Ft4A when the output Os4 is asserted, and the timing circuit 33 generates the fault indication pulse Ft5A when the output Os5 is asserted.

[0053] The priority encoder 37 receives the fault indication signal Ft1A (which is not a pulse but remains at a logic low when there is no error and is asserted to a logic high when a lowest priority error occurs) from the output Os1 of the fault detector 32, and receives the fault indication signals Ft2A, Ft3A, Ft4A, Ft5A from the timing circuit 33. The priority encoder 37 generates control signals Cc1, Cc2, Cc3, Cc4, Cc5, Cc6 for the switches Sw1, Sw2, Sw3, Sw4, Sw5, Sw6 in response to the state of Ft1A and in response to the pulses of Ft2A, Ft3A, Ft4A and Ft5A.

[0054] The switch Sw1 selectively connects the first voltage V1 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc1. The switch Sw2 selectively connects the second voltage V2 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc2. The switch Sw3 selectively connects the third voltage V3 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc3. The switch Sw4 selectively connects the fourth voltage V4 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc4. The switch Sw5 selectively connects the fifth voltage V5 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc5. The switch Sw6 selectively connects the sixth voltage V6 to the input of the current sink buffer 38 in response to the assertion of the control signal Cc6. Voltage V1 (e.g., 3V) is greater than voltage V2 (e.g., 2V), voltage V2 is greater than voltage V3 (e.g., 1.5V), voltage V3 is greater than voltage V4 (e.g., 1.0V), voltage V4 is greater than voltage V5 (e.g., 0.5V), and voltage V5 is greater than voltage V6 (e.g., 0V).

[0055] The constant current source 34 provides a constant current to the node Nd. When the fault indication signal Ft1A is de-asserted and there are no pulses of Ft2A, Ft3A, Ft4A, Ft5A, the priority encoder 37 asserts the control signal Cc1, thereby connecting the input of the current sink buffer 38 to the voltage V1, causing the current sink buffer 38 to sink sufficient current from its output at the node Nd so that the voltage at the node Nd is set to V1. When the fault indication signal Ft1A is asserted or a pulse of Ft2A, Ft3A, Ft4A, Ft5A arrives, the priority encoder 37 asserts a corresponding one of the control signals Cc2, Cc3, Cc4, Cc5, Cc6 - when Ft1A is asserted, the priority encoder 37 asserts the control signal Cc2 to set the voltage at the node Nd to the voltage V2; when Ft2A is pulsed, the priority encoder 37 asserts the control signal Cc3 to set the voltage at the node Nd to the voltage V2 for the duration of the pulse. The voltage is set to voltage V3; when Ft3A is pulsed, the priority encoder 37 asserts the control signal Cc4 to set the voltage at node Nd to voltage V4 for the duration of the pulse; when Ft4A is asserted, the priority encoder 37 asserts the control signal Cc5 to set the voltage at node Nd to voltage V5 for the duration of the pulse; and when Ft5A is asserted, the priority encoder 37 asserts the control signal Cc6 to set the voltage at node Nd to voltage V6 for the duration of the pulse.

[0056] Only one of the control signals Cc1, Cc2, Cc3, Cc4, Cc5 may be asserted at a time. When multiple of the fault indication signals Ft1A, Ft2A, Ft3A, Ft4A, Ft5A are asserted / pulsated, the priority encoder 37 will act according to the fault indication that represents the most severe fault (highest priority). For example, if both Ft2A and Ft4A are pulsed, then the priority encoder 37 asserts the control signal Cc5 to connect the voltage V5 to the input of the current sink buffer 38 for the length of the pulse because the assertion of the fault indication signal Ft4A represents a more severe fault than the assertion of the fault indication signal Ft2A.

[0057] The lower the voltage level at which node Nd is set, the more severe the fault that has occurred. A graph showing an example mapping of specific fault types to voltage can be seen below:

[0058]

[0059] The first hysteresis comparator 39 has an inverting input terminal connected to the first threshold comparison voltage Vt1, a non-inverting input terminal connected to the node Nd, and an output generating a comparison signal Cs1. The second hysteresis comparator 40 has an inverting input terminal connected to the second threshold comparison voltage Vt2, a non-inverting input terminal connected to the node Nd, and an output generating a comparison signal Cs2. The third hysteresis comparator 41 has an inverting input terminal connected to the third threshold comparison voltage Vt3, a non-inverting input terminal connected to the node Nd, and an output generating a comparison signal Cs3. The fourth hysteresis comparator 42 has an inverting input terminal connected to the fourth threshold comparison voltage Vt4, a non-inverting input terminal connected to the node Nd, and an output generating a comparison signal Cs4. The fifth hysteresis comparator 43 has an inverting input terminal connected to the fifth threshold comparison voltage Vt5, a non-inverting input terminal connected to the node Nd, and an output generating a comparison signal Cs5.

[0060] The first threshold comparison voltage Vt1 (e.g., 2.25V) is greater than the second threshold comparison voltage Vt2 (e.g., 1.75V), the second threshold comparison voltage Vt2 is greater than the third threshold comparison voltage Vt3 (e.g., 1.25V), the third threshold comparison voltage Vt3 is greater than the fourth threshold comparison voltage Vt4 (e.g., 0.75V), and the fourth threshold comparison voltage Vt4 is greater than the fifth threshold comparison voltage Vt5 (e.g., 0.25V).

[0061] The priority decoder 35 receives comparison signals Cs1, Cs2, Cs3, Cs4, Cs5 as inputs and asserts the corresponding highest priority output signal among the output signals Ft1Y, Ft2Y, Ft3Y, Ft4Y, Ft5Y when at least one of these comparison signals is asserted. Therefore, the output signal Ft1Y is asserted to indicate that the comparison signal Cs1 is asserted (indicating that the fault indication signal Ft1A is the most serious fault indicated by the fault detector 32), the output signal Ft2Y is asserted to indicate that the comparison signal Cs2 is asserted (indicating that the fault indication signal Ft2A is the most serious fault indicated by the fault detector 32), the output signal Ft3Y is asserted to indicate that the comparison signal Cs3 is asserted (indicating that the fault indication signal Ft3A is the most serious fault indicated by the fault detector 32), the output signal Ft4Y is asserted to indicate that the comparison signal Cs4 is asserted (indicating that the fault indication signal Ft4A is the most serious fault indicated by the fault detector 32), and the output signal Ft5Y is asserted to indicate that the comparison signal Cs5 is asserted (indicating that the fault indication signal Ft5A is the most serious fault indicated by the fault detector 32).

[0062] The fault action block 26 takes corrective actions depending on which of the output signals Ft1Y, Ft2Y, Ft3Y, Ft4Y, Ft5Y is asserted. These corrective actions may be, for example, turning off the transistor Ts1, modulating the gate voltage of the transistor Ts1, etc.

[0063] In operation, the timing circuit 33 is connected to receive the outputs Os2, Os3, Os4, Os5 and to generate pulses of Ft2A, Ft3A, Ft4A, Ft5A with the same given duration and corresponding to which of the outputs Os2, Os3, Os4, Os5 are asserted.

[0064] The priority encoder 37 receives as input the fault indication signals / pulses Ft1A, Ft2A, Ft3A, Ft4A, Ft5A and, when at least one of these fault indication signals is asserted / pulsed, asserts one of the control signals Cc2, Cc3, Cc4, Cc5, Cc6 corresponding to the one with the highest priority among the fault indication signals Ft1A, Ft2A, Ft3A, Ft4A, Ft5A, thereby closing the associated switches Sw2, Sw3, Sw4, Sw5, Sw6. As a result, the voltages V2, V3, V4, V5, V6 associated with the closed switches appear at the input of the current sink buffer 38, causing the current sink buffer 38 to sink sufficient current from the node Nd to set the voltage at that node to the voltage associated with the closed switch. The main fuse 10 then acts as described above to latch the voltage until reset.

[0065] When the fault indication signals / pulses Ft1A, Ft2A, Ft3A, Ft4A, Ft5A are not asserted, the priority encoder asserts the control signal Cc1, thereby closing the switch Sw1, connecting the input of the current sink buffer 38 to the voltage V1, and setting the voltage at the node Nd to the voltage V1.

[0066] The hysteresis comparators 39, 40, 41, 42, 43 each compare the voltage at the node Nd with its corresponding threshold comparison voltage Vt1, Vt2, Vt3, Vt4, Vt5, and when the voltage at the node Nd is greater than those corresponding comparison threshold voltages Vt1, Vt2, Vt3, Vt4, Vt5 by the hysteresis threshold, assert their outputs to generate corresponding comparison signals Cs1, Cs2, Cs3, Cs4, Cs5. The priority decoder 35 receives the comparison signals Cs1, Cs2, Cs3, Cs4, Cs5 as inputs, and when at least one of these comparison signals is asserted, asserts the corresponding highest priority control signal among the output signals Ft1Y, Ft2Y, Ft3Y, Ft4Y, Ft5Y, and the fault action block takes corrective action based thereon.

[0067] When the priority decoder 35 asserts the output signal Ft1Y, the timing circuit 33 is reset, thereby allowing new pulses of Ft2A, Ft3A, Ft4A, Ft5A to be generated in response to the assertion of the corresponding inputs Os2, Os3, Os4, Os5. Thus, if the same highest priority fault persists, another corresponding pulse of Ft2A, Ft3A, Ft4A, Ft5A is generated.

[0068] Reference now Figure 3 An example iteration is described. Initially, neither the primary fuse 10 nor the secondary fuses 30(1), ..., 30(n) experience a fault, and thus their respective fault detectors 12 and 32 do not assert their outputs O1, O2, O3, O4, O5 and Os1, Os2, Os3, Os4, Os5. Thereafter, a fault is detected by the fault detector 32 of one of the secondary fuses 30(1), ..., 30(n), as Figure 3 As shown in the transition of the fault event in FIG. 1 , the fault signal line FAULT is ultimately driven to an appropriate voltage level by the secondary device causing the buffer 38 to indicate that a particular fault has occurred—as shown by arrow 1. This voltage level is then latched by the primary fuse 10—as shown by arrow 2. The actual voltage on the fault signal line FAULT drops to indicate that a fault has occurred—as shown by arrow 3.

[0069] In response to the fault detection by the fault detector 32, the fault action block 36 takes action so that the fault in the secondary fuse ends, such as Figure 3The end of the pulse in the middle is shown, indicating the secondary fuse driving of FAULT. Next, the reset signal RST is asserted, causing the priority encoder 17 to reset, ending the driving of FAULT by the primary fuse, as shown in FIG. Figure 4 As a result, the voltage across FAULT returns to its idle value, as shown by arrow 4.

[0070] The advantages provided by the analog power electronic circuit 5 including the primary fuse 10 and secondary fuses 31(1), ..., 31(n) designed as described above are numerous.

[0071] For example, multiple voltage level communications via a single fault signal line allow faults of varying severity to be communicated using that single line, enabling precise and appropriate responses without requiring additional signal lines that take up space. Additionally, latching and holding the fault indication on the fault signal line until it is reset reduces the risk of cascading failures by giving each fuse time to react.

[0072] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0073] Although the present disclosure has been described by a limited number of embodiments, those skilled in the art, after benefiting from this disclosure, may conceive of other embodiments that do not depart from the disclosed scope. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. A method of fault detection and communication in a simulated power electronic circuit, the simulated power electronic circuit having a plurality of electronic fuses, the plurality of electronic fuses including a single primary fuse and at least one secondary fuse, the method comprising: monitoring current through each of the plurality of electronic fuses; detecting a fault condition within at least one electronic fuse of the plurality of electronic fuses; driving a fault signal line common to each of the plurality of electronic fuses to a voltage corresponding to a detected fault condition; latching the voltage on the fault signal line using the main electronic fuse; performing corrective actions on the plurality of electronic fuses based on the latched voltage; as well as Release the latch of the voltage.

2. The method according to claim 1, wherein: Driving the fault signal line to the voltage corresponding to the detected fault condition is performed by: providing, at each of the plurality of electronic fuses, a constant current to a feedback node coupled to the fault signal line; as well as At the electronic fuse experiencing the fault condition, current is sunk from the feedback node to set the voltage at the fault signal line to a voltage corresponding to the detected fault condition, the sunk current being dependent on the detected fault condition.

3. The method according to claim 1, further comprising: When a fault condition is detected within a plurality of the plurality of electronic fuses, the fault signal line is driven to a voltage corresponding to a most severe fault condition.

4. The method according to claim 1, further comprising: Wherein when multiple fault conditions are detected in one of the plurality of electronic fuses, the fault signal line is driven to a voltage corresponding to a most severe fault condition.

5. The method according to claim 1, wherein: When a fault condition is detected within the at least one secondary fuse, driving the fault signal line to a voltage corresponding to the detected fault condition comprises: generating, by the at least one secondary fuse, a voltage pulse on the fault signal line using a timing circuit within the at least one secondary fuse, the voltage pulse having an amplitude corresponding to the detected fault condition; and At the single main fuse, in response to detecting the voltage pulse on the fault signal line, the voltage on the fault signal line is latched.

6. The method according to claim 5, wherein: Upon subsequent detection of normal operation of the at least one secondary fuse, a reset by the at least one secondary fuse causes the timing circuit to reset; And, before resetting the timing circuit, the timing circuit will not generate other voltage pulses on the fault signal line.

7. The method according to claim 1, further comprising: The voltage on the fault signal line is latched by the main fuse, the voltage on the fault signal line is detected, the fault signal line is driven to the detected voltage, and the voltage on the fault signal line is latched.

8. An analog power electronic circuit comprising: Input nodes and voltage nodes; A main fuse configured to conduct current between the input node and the voltage node, the main fuse comprising: a logic circuit configured to generate an output indicative of a fault within the simulated power electronic circuit and a severity of the fault; a priority encoder configured to receive the output from the logic circuit and assert one of a plurality of control signals corresponding to a severity of the fault; a plurality of switches, each switch being controlled by a different one of the plurality of control signals to selectively couple the intermediate node to a voltage corresponding to a severity of the fault; and a current sink circuit configured to sink sufficient current from a feedback node to set the feedback node to a voltage corresponding to a severity of the fault; a fault signal line coupled to the feedback node; A secondary fuse is connected in parallel with the primary fuse and is configured to conduct current between the input node and the voltage node, the secondary fuse being configured to: detecting whether a fault exists in the secondary fuse; and In response to detecting the presence of a fault in the secondary fuse, the fault signal line is set to a voltage corresponding to the severity of the fault for the duration of a pulse. 9 . The analog power electronic circuit of claim 8 , further comprising a controller configured to generate a reset signal to reset the priority encoder of the main fuse.

10. The analog power electronic circuit according to claim 8, wherein: The main fuse also includes: a plurality of comparators, each comparator being configured to compare the voltage at the feedback node with a different threshold comparison voltage; a priority decoder configured to receive outputs from the plurality of comparators and assert one of the plurality of fault remedy signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and A fault action block is configured to modify conduction of current through the secondary fuse based on the asserted fault remediation signal.

11. The analog power electronic circuit according to claim 10, in, The main fuse also includes a fault detection circuit configured to generate an output indicative of a fault within the main fuse and a severity of the fault; as well as The logic circuit includes a plurality of logic OR gates, each of which performs a logic OR operation on different corresponding outputs of the fault detection circuit and a corresponding fault remediation signal.

12. The analog power electronic circuit according to claim 8, wherein: The current sink circuit includes a current sink buffer.

13. The analog power electronic circuit according to claim 8, wherein: The secondary fuse comprises: a fault detection circuit configured to generate an output indicative of a fault within the secondary fuse and a severity of the fault; a timing circuit configured to generate pulses corresponding to those outputs of the fault detection circuit that are indicative of all but the least severe fault; a priority encoder configured to receive the pulse from the timing circuit and to receive the output of the fault detection circuit indicating the least severe fault, and to assert one of a plurality of control signals corresponding to the most severe fault indicated by the pulse and the output of the fault detection circuit indicating the least severe fault; a plurality of switches, each switch being controlled by a different one of the plurality of control signals to selectively couple the intermediate node to a voltage corresponding to a severity of the fault; and A current sink circuit is configured to sink sufficient current from the feedback node to set the feedback node to a voltage corresponding to the severity of the fault.

14. The analog power electronic circuit according to claim 13, wherein: The secondary fuse also includes: a plurality of comparators, each comparator being configured to compare the voltage at the feedback node with a different threshold comparison voltage; a priority decoder configured to receive outputs from the plurality of comparators and assert one of the plurality of fault remedy signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and A fault action block is configured to modify conduction of current through the secondary fuse based on the asserted fault remediation signal.

15. The analog power electronic circuit according to claim 14, wherein: Assertion of the fault remediation signal corresponding to the least severe fault resets the timing circuit.

16. An analog power electronic circuit comprising: A main fuse configured to conduct current between an input node and a voltage node, the main fuse comprising: a priority encoder configured to receive a fault indication and assert one of a plurality of control signals corresponding to a severity of a fault indicated by the fault indication; a plurality of switches configured to selectively couple the intermediate node to a voltage corresponding to a severity of the fault; and a current sink circuit configured to sink sufficient current from a feedback node to set the feedback node to a voltage corresponding to a severity of the fault; a fault signal line coupled to the feedback node; A secondary fuse is connected in parallel with the primary fuse and is configured to conduct current between the input node and the voltage node, the secondary fuse being configured to: detecting whether a fault exists in the secondary fuse; and In response to detecting the presence of a fault in the secondary fuse, the fault signal line is set to a voltage corresponding to the severity of the fault for the duration of a pulse. 17 . The analog power electronic circuit of claim 16 , further comprising a controller configured to generate a reset signal to reset a priority encoder of the primary fuse.

18. The analog power electronic circuit according to claim 16, wherein: The main fuse also includes: a plurality of comparators, each comparator being configured to compare the voltage at the feedback node with a different threshold comparison voltage; a priority decoder configured to receive outputs from the plurality of comparators and assert one of the plurality of fault remedy signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and A fault action block is configured to modify conduction of current through the secondary fuse based on the asserted fault remediation signal.

19. The analog power electronic circuit according to claim 18, in, The main fuse also includes a fault detection circuit configured to generate an output indicative of a fault within the main fuse and a severity of the fault.

20. The analog power electronic circuit according to claim 16, wherein: The secondary fuse comprises: a fault detection circuit configured to generate an output indicative of a fault within the secondary fuse and a severity of the fault; a timing circuit configured to generate pulses corresponding to those outputs of the fault detection circuit that are indicative of all but the least severe fault; a priority encoder configured to receive a pulse from the timing circuit and to receive an output of the fault detection circuit indicating a least severe fault, and to assert one of a plurality of control signals corresponding to the most severe fault indicated by the pulse and the output of the fault detection circuit indicating the least severe fault; a plurality of switches, each switch being controlled by a different one of the plurality of control signals to selectively couple the intermediate node to a voltage corresponding to a severity of the fault; a current sink circuit configured to sink sufficient current from the feedback node to set the feedback node to a voltage corresponding to a severity of the fault; a plurality of comparators, each comparator being configured to compare the voltage at the feedback node with a different threshold comparison voltage; a priority decoder configured to receive outputs from the plurality of comparators and assert one of the plurality of fault remedy signals corresponding to a lowest threshold comparison voltage among the threshold comparison voltages that the voltage at the feedback node is less than; and A fault action block is configured to modify conduction of current through the secondary fuse based on the asserted fault remediation signal.

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