Data access method, device and system

Abstract

The invention provides a data access method, device and system, and belongs to the technical field of storage, and the method comprises the steps: receiving a data request which is used for indicating a plurality of source storage addresses and a target data type; based on the data request, a first memory block indicated by each source storage address in a plurality of source storage addresses is read from a memory, and the length of the first memory block is a basic unit for accessing the memory; extracting data of each source storage address from the first memory block indicated by each source storage address; merging the data of each source storage address according to the length of the cache line to obtain a second memory block; and sending the second memory block to the processing subsystem, so that the processing subsystem caches the second memory block. According to the method and the device, the chip manufacturing cost can be reduced, and the data loading performance of other data access scenes except non-sparse address and discontinuous address access cannot be influenced. The method is used for data access.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data access method, device and system. Background Art

[0002] Sparse data access is widely used in high performance computing (HPC), big data, and graph theory. The processor accesses data from memory to cache in units of cache lines. When reading data at a storage address, the entire cache line corresponding to the storage address is read. The length of a cache line is usually 64 bytes. When accessing data at multiple discontinuous addresses or sparse addresses, only 4 / 8 bytes of data can usually be read from the cache line corresponding to each address, resulting in the utilization rate of the 64-byte cache line and the efficiency of memory loading data as low as 1 / 16 float (for single-precision floating point numbers) or 1 / 8 double (for double-precision floating point numbers), resulting in a waste of cache space and memory bandwidth.

[0003] The related art provides a technology for accessing data through a sub cache line, in which a sparse data access buffer is newly added, and the sparse data access buffer is used to detect whether the sparse data is accessed multiple times. When the sparse data is not accessed multiple times, the data is accessed by bypassing the cache and using the length of the sub cache line as the basic unit. When the sparse data is accessed multiple times, the data is accessed by using the length of the cache line as the basic unit according to the previous access method.

[0004] However, in the related art, it is necessary to add new memory access channels and memory access protocols to implement data access through sub-cache lines, so it is necessary to modify the current cache mechanism or add flying wires, resulting in higher chip manufacturing costs. In addition, when accessing data, the sparse data access buffer is first required to determine the access channel, which increases the complexity of the access process for non-sparse data, thereby affecting the data loading performance of other data access scenarios other than sparse data access. Summary of the invention

[0005] The present application provides a data access method, device and system, which solves the problem in the related technology that the current cache mechanism needs to be modified or flying wires are added, and the complexity of the access process of non-sparse data is increased. It can reduce the chip manufacturing cost and will not affect the data loading performance of other data access scenarios other than non-sparse address and discontinuous address access.

[0006] In a first aspect, the present application provides a data access method, the method comprising: receiving a data request, the data request being used to indicate multiple source storage addresses and a target data type; based on the data request, reading a first memory block indicated by each source storage address in the multiple source storage addresses from a memory, the length of the first memory block being a basic unit for accessing the memory; extracting data of each source storage address from the first memory block indicated by each source storage address; merging the data of each source storage address according to the length of the cache line to obtain a second memory block; and sending the second memory block to a processing subsystem so that the processing subsystem caches the second memory block.

[0007] The source storage address is the address of the main memory, and multiple source storage addresses may be continuous or discontinuous.

[0008] The beneficial effect is that there will be multiple valid data in the length of a cache line, thus effectively improving the utilization rate of the cache line and the efficiency of memory loading data. In addition, in the embodiment of the present application, the data of each source storage address is merged according to the length of the cache line, so the existing bus transmission protocol and channel can be used to send the second memory block to the processing subsystem, without modifying the transmission protocol from the memory controller to the processing subsystem, and without modifying the existing cache mechanism or adding flying wires, thereby reducing the chip manufacturing cost. In addition, the embodiment of the present application does not need to make a judgment before accessing sparse address data, so it will not affect the data loading performance of other data access scenarios other than non-sparse address and discontinuous address access.

[0009] In a possible implementation, the length of the first memory block is smaller than the length of the cache line.

[0010] The beneficial effect is that data with a length less than the cache line length can be read based on each source storage address, thereby improving the effective memory bandwidth without modifying the cache mechanism.

[0011] In a second aspect, the present application provides a data access method, the method comprising: receiving a data copy instruction, the data copy instruction carrying multiple source storage addresses, a target data type and a destination storage address; based on the data copy instruction, sending a data request to each target memory controller, the target memory controller being a memory controller corresponding to the source storage address among multiple memory controllers, the data request being used to indicate the multiple source storage addresses and the target data type corresponding to the target memory controller, the data request being used by the target memory controller to determine a memory block; receiving a memory block sent by at least one target memory controller, the memory block sent by the target memory controller including data of the multiple source storage addresses corresponding to the target memory controller, the length of the memory block being equal to the length of a cache line; based on the destination storage address, caching each received memory block.

[0012] Illustratively, the data lengths of the plurality of source storage addresses are integer multiples of the cache line length.

[0013] In one possible implementation, based on the destination storage address, the process of caching each received memory block includes: when receiving memory blocks sent by multiple target memory controllers respectively, aggregating the data in the received memory blocks into at least one target cache line; based on the destination storage address, caching at least one target cache line.

[0014] In a third aspect, the present application provides a data access system, which includes: a processing subsystem and multiple memory controllers; the processing subsystem is used to receive a data copy instruction, the data copy instruction carries multiple source storage addresses, target data types and destination storage addresses; the processing subsystem is also used to send a data request to each target memory controller based on the data copy instruction, the target memory controller is a memory controller corresponding to the source storage address among multiple memory controllers, and the data request is used to indicate the multiple source storage addresses and target data types corresponding to the target memory controller; the target memory controller is used to read the first memory block indicated by each corresponding source storage address from the memory based on the data request, and the length of the first memory block is the basic unit for accessing the memory; the target memory controller is also used to extract the data corresponding to each source storage address from each first memory block read, and merge the data corresponding to each source storage address according to the length of the cache line to obtain a second memory block; the target memory controller is also used to send the second memory block to the processing subsystem; the processing subsystem is also used to cache each received second memory block based on the destination storage address.

[0015] In one possible implementation, the processing subsystem is specifically configured to: upon receiving second memory blocks respectively sent by multiple target memory controllers, aggregate data in the received second memory blocks into at least one target cache line; and cache at least one target cache line based on a destination storage address.

[0016] In a fourth aspect, the present application provides a data access device, which includes: a transceiver module for receiving a data request, the data request is used to indicate multiple source storage addresses and a target data type; a processing module for reading a first memory block indicated by each source storage address in the multiple source storage addresses from the memory based on the data request, the length of the first memory block being the basic unit for accessing the memory; the processing module is also used to extract the data of each source storage address from the first memory block indicated by each source storage address; the processing module is also used to merge the data of each source storage address according to the length of the cache line to obtain a second memory block; the transceiver module is also used to send the second memory block to the processing subsystem so that the processing subsystem caches the second memory block.

[0017] In a possible implementation, the length of the first memory block is smaller than the length of the cache line.

[0018] In a possible implementation, the multiple source storage addresses are not continuous.

[0019] In a fifth aspect, the present application provides a data access device, which includes: a transceiver module, used to receive a data copy instruction, the data copy instruction carries multiple source storage addresses, a target data type and a destination storage address; the transceiver module is also used to send a data request to each target memory controller based on the data copy instruction, the target memory controller is a memory controller corresponding to the source storage address among multiple memory controllers, the data request is used to indicate the multiple source storage addresses and target data type corresponding to the target memory controller, and the data request is used for the target memory controller to determine the memory block; the transceiver module is also used to receive a memory block sent by at least one target memory controller; the processing module is used to cache each received memory block based on the destination storage address.

[0020] In a possible implementation, the processing module is specifically configured to: upon receiving memory blocks respectively sent by multiple target memory controllers, aggregate data in the received memory blocks into at least one target cache line; and cache at least one target cache line based on a destination storage address.

[0021] In a sixth aspect, the present application provides a data access device, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by one or more processors, the one or more processors implement a method as described in any one of the first aspects.

[0022] In the seventh aspect, the present application provides a data access device, which includes: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by the one or more processors, the one or more processors implement the method as described in any one of the second aspects.

[0023] In an eighth aspect, the present application provides a data access device, comprising a processor, configured to execute a method as described in any one of the first aspects.

[0024] In a ninth aspect, the present application provides a data access device, comprising a processor for executing a method as described in any one of the second aspects.

[0025] In the tenth aspect, the present application provides a data access device, comprising: a processing circuit and an interface circuit; wherein the interface circuit is used to couple with a memory outside the positioning device and provide a communication interface for the processing circuit to access the memory; the processing circuit is used to execute program instructions in the memory to implement a method as described in any one of the first and second aspects.

[0026] In the specific implementation process, the data access device can be a chip, the input circuit can be an input pin, the output circuit can be an output pin, and the processing circuit can be a transistor, a gate circuit, a trigger, and various logic circuits. The input signal received by the input circuit can be, for example, but not limited to, received and input by a receiver, and the signal output by the output circuit can be, for example, but not limited to, output to a transmitter and transmitted by the transmitter, and the input circuit and the output circuit can be the same circuit, which is used as an input circuit and an output circuit at different times. The embodiments of the present application do not limit the specific implementation methods of the processor and various circuits.

[0027] In one implementation, the data access device may be a wireless communication device, that is, a computer device that supports wireless communication functions. Specifically, the wireless communication device may be a terminal such as a smart phone, or a wireless access network device such as a base station. The network chip may also be referred to as a system on chip (SoC), or simply as an SoC chip. The communication chip may include a baseband processing chip and a radio frequency processing chip. The baseband processing chip is sometimes also referred to as a modem or a baseband chip. The radio frequency processing chip is sometimes also referred to as a radio frequency transceiver or a radio frequency chip. In a physical implementation, some or all of the chips in the communication chip may be integrated inside the SoC chip. For example, the baseband processing chip is integrated in the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip. The interface circuit may be a radio frequency processing chip in a wireless communication device, and the processing circuit may be a baseband processing chip in a wireless communication device.

[0028] In another implementation, the data access device may be a part of a wireless communication device, such as an integrated circuit product such as a network chip or a communication chip. The interface circuit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip or chip network. The processor may also be embodied as a processing circuit or a logic circuit.

[0029] In an eleventh aspect, the present application provides a computer-readable storage medium, in which a program code is stored. When the program code is executed by a processor, the method as described in any one of the first and second aspects is implemented.

[0030] In a twelfth aspect, the present application provides a chip, comprising: at least one processor. The at least one processor is used to execute the method as described in any one of the first aspect and the second aspect.

[0031] Optionally, the chip further includes a memory. At least one processor is used to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method as described in any one of the first aspect and the second aspect.

[0032] Optionally, the above chip may also be an integrated circuit.

[0033] In a thirteenth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method as described in any one of the first and second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a data access system provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of another data access system provided in an embodiment of the present application;

[0036] Figure 3 A flowchart of a data access method provided in an embodiment of the present application;

[0037] Figure 4 A flowchart of another data access method provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a data copy instruction provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of another data copy instruction provided in an embodiment of the present application;

[0040] Figure 7 A block diagram of a data access device provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0042] Fig. 9 A structural diagram of a data access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, networks, products, or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0045] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0046] An embodiment of the present application provides a data access method that can be used for accessing sparse addresses and discontinuous addresses. While improving the utilization of cache lines and the efficiency of memory loading data, it does not require modifying the existing cache mechanism or adding flying wires, and will not affect the data loading performance of other data access scenarios other than non-sparse and discontinuous address access.

[0047] The data access method can be applied to a data access system, and the data access system may include a processing subsystem and a plurality of memory controllers (MC). The processing subsystem may include a processor and a newly added combine unit, and the processor may include a central processing unit (CPU). In addition, an embodiment of the present application adds a memory controller combine MC unit in each existing memory controller. Each memory controller is used to manage the main memory (memory) of an address area, and the main memory includes but is not limited to double data rate synchronous dynamic random access memory (DDR SDRAM) and high bandwidth memory (HBM).

[0048] The newly added merging unit and memory controller merging unit may be only units divided according to logical functions, and there may be other ways in actual implementation, for example, the two units may be combined or integrated into another network, or some features may be ignored or not executed. The two units may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the two units may be integrated into one processing unit, or they may exist physically separately.

[0049] The merging unit may be located in the processor, in any memory controller, or outside the processor and the memory controller, for example, between the processor and the memory controller. This embodiment of the application does not limit this.

[0050] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a data access system provided in an embodiment of the present application is provided. Figure 1 The data access system includes: a CPU 10, a plurality of memory controllers, a main memory managed by the plurality of memory controllers, and a merging unit 13.

[0051] The CPU 10 includes a plurality of CPU cores. Figure 1Two CPU cores core 0 and core 1 are shown. Each CPU core has a level 1 cache (L1 cache) and a level 2 cache (L2 cache), and multiple CPU cores share a level 3 cache (L3 cache).

[0052] Each memory controller includes a memory controller merging unit. Figure 1 The memory controller 110 and the memory controller 111 are shown. The memory controller 110 includes a memory controller merging unit 110a, and the memory controller 111 includes a memory controller merging unit 111b. The memory controller 110 manages the main memory 120 and the main memory 121, and the memory controller 111 manages the main memory 122 and the main memory 123.

[0053] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of another data access system provided in an embodiment of the present application, Figure 2 Taking the case where the merging unit is located in the processor as an example, the data access system includes: a CPU 20, multiple memory controllers, main memories managed by the multiple memory controllers, and a Hydra root agent.

[0054] The CPU 20 includes a plurality of CPU cores, Figure 2 Four CPU cores core0 to core3 are shown. Each CPU core corresponds to a merging unit, an L1 cache, and an L2 cache, and core0 and core1 share L3 cache1, and core2 and core3 share L3 cache2. L3 cache1 includes L3 cache tag (TAG) 1 and L3 cache1 storage body, and L3 cache2 includes L3 cacheTAG2 and L3 cache2 storage body. L3cache TAG is used to record the location of data in the L3 cache storage body.

[0055] Each memory controller includes a memory controller merging unit. Figure 2 Memory controllers 210, 211, 212, and 213 are shown, as well as Hydra root agents 230 and 231. Memory controllers 210 and 211 are connected to CPU 20 via Hydra root agent 230, and memory controllers 212 and 213 are connected to CPU 20 via Hydra root agent 231.

[0056] The memory controller 210 includes a memory controller merging unit 210a, the memory controller 211 includes a memory controller merging unit 211a, the memory controller 212 includes a memory controller merging unit 212a, and the memory controller 213 includes a memory controller merging unit 213a. The memory controller 210 manages the main memory 220 and the main memory 221, the memory controller 211 manages the main memory 222 and the main memory 223, the memory controller 212 manages the main memory 224 and the main memory 225, and the memory controller 213 manages the main memory 226 and the main memory 227.

[0057] Please refer to Figure 3 , Figure 3 A flow chart of a data access method provided in an embodiment of the present application is provided. The method can be applied to a memory controller in a data access system, for example Figure 1 and Figure 2 Any memory controller shown. The method may include the following process:

[0058] 301. Receive a data request, where the data request is used to indicate multiple source storage addresses and target data types.

[0059] The source storage address is the address of the main memory, and multiple source storage addresses may be continuous or discontinuous, which is not limited in the embodiment of the present application.

[0060] 302. Based on a data request, read a first memory block indicated by each source storage address in a plurality of source storage addresses from a memory, where a length of the first memory block is a basic unit for accessing the memory.

[0061] The memory controller first determines whether the data of each source storage address is in the cache. The memory controller can map the source storage address to the source cache address, and then determine whether the data of the source storage address is in the cache based on the source cache address. When the data of the source storage address is in the cache, the memory controller reads the data of the source storage address from the cache. When the data of the source storage address is not in the cache, the memory controller reads the data from the main memory.

[0062] As can be seen from the above description, the basic unit for reading data from the main memory is a cache line. In the embodiment of the present application, data can be read from the main memory using a first memory block as a basic unit, and the length of the first memory block is smaller than the length of the cache line.

[0063] By way of example, methods for implementing the length of the first memory block being smaller than the length of the cache line include but are not limited to: the main memory is DDR5, DDR5 is in "burst chop 8 on the fly" (BC8 OTF) mode, the shortest burst length is 8 bytes, and 32 bytes of data can be returned each time, that is, the length of the first memory block is 32 bytes; the main memory is HBM2, HBM2 is in pseudo channel mode, and 32 bytes of data can be returned each time, that is, the length of the first memory block is 32 bytes.

[0064] The memory controller can read data whose length is less than the cache line length based on each source storage address, thereby improving the effective memory bandwidth without modifying the cache mechanism.

[0065] 303. Extract data of each source storage address from the first memory block indicated by each source storage address.

[0066] The memory controller discards data other than the source stored data in the first memory block.

[0067] 304. Merge the data of each source storage address according to the length of the cache line to obtain a second memory block.

[0068] The length of the second memory block is equal to the length of the cache line. The memory controller stores the data of all source storage addresses continuously according to the length of the cache line. When the data of all source storage addresses do not fill an integer number of second memory blocks (that is, when the data length of the source storage address is not an integer multiple of the cache line length), the free position is filled with 0 to obtain at least one second memory block.

[0069] 305. Send the second memory block to the processing subsystem, so that the processing subsystem caches the second memory block.

[0070] For example, the second memory block may be transparently transmitted to the processing subsystem.

[0071] Since the memory controller in the existing protocol transmits data to the processor according to the length of the cache line, the data of each source storage address is merged according to the length of the cache line in the embodiment of the present application. Therefore, the second memory block can be sent to the processing subsystem using the existing bus transmission protocol, without modifying the transmission protocol from the memory controller to the processing subsystem, thereby reducing the chip manufacturing cost.

[0072] To summarize, the data access method provided in the embodiment of the present application first receives a data request, where the data request is used to indicate multiple source storage addresses and a target data type, and then based on the data request, reads a first memory block indicated by each source storage address in the multiple source storage addresses from the memory, where the length of the first memory block is the basic unit for accessing the memory, extracts the data of each source storage address from the first memory block indicated by each source storage address, and merges the data of each source storage address according to the length of the cache line to obtain a second memory block, and finally sends the second memory block to the processing subsystem so that the processing subsystem caches the second memory block, and the memory controller performs data filtering and continuous storage of the source storage address, and then returns the second memory block of the cache line length. Compared with the situation in which there is only one valid data in a cache line length in the related art, there are multiple valid data in a cache line length in the embodiment of the present application, thereby effectively improving the utilization rate of the cache line and the efficiency of memory loading data. In addition, in the embodiment of the present application, the data of each source storage address is merged according to the length of the cache line, so the existing bus transmission protocol and channel can be used to send the second memory block to the processing subsystem, without modifying the transmission protocol from the memory controller to the processing subsystem, nor modifying the existing cache mechanism or adding flying wires, thereby reducing the chip manufacturing cost. In addition, the embodiment of the present application does not need to make a judgment before accessing sparse address data, so it will not affect the data loading performance of other data access scenarios other than non-sparse address and discontinuous address access.

[0073] Please refer to Figure 4 , Figure 4 This is a flow chart of another data access method provided in an embodiment of the present application. This method can be applied to a processing subsystem in a data access system, such as Figure 1 and Figure 2 The processing subsystem shown. The method may include the following processes:

[0074] 401. Receive a data copy instruction, where the data copy instruction carries multiple source storage addresses, target data types, and destination storage addresses.

[0075] The multiple source storage addresses may be continuous or discontinuous, which is not limited in the embodiments of the present application. For example, the data length of the multiple source storage addresses is an integer multiple of the cache line length.

[0076] The data copy instruction triggers a process of copying data from a plurality of source storage addresses to a destination storage address, where the destination storage address may indicate a space in a cache or a space in a register.

[0077] For example, please refer to Figure 5 , Figure 5 A schematic diagram of a data copy instruction provided in an embodiment of the present application, Figure 5Take the destination storage address in the data copy instruction to indicate the space in the vector register as an example. The source storage address is generated by adding the scalar base to the vector index, and the target data type is double word. The vector index value can be 32 to 64 bits, signed or unsigned, and can be optionally multiplied by 8.

[0078] like Figure 5 As shown, the length of the data copy instruction is 32 bytes (0 to 31), and Rn, Pg and Zt represent the numbers of the registers, that is, the numbers of the vector registers or general registers. The instruction can be: LD1GC{ <zt> .D}， <pg> / WITH,[<Xn|SP> , <zm> .D， <mod>#3], Zt and Zm represent vector registers, Xn represents general registers, and SP represents special registers.

[0079] Please refer to Figure 6 , Figure 6 A schematic diagram of another data copy instruction provided in an embodiment of the present application, Figure 6 Take the space corresponding to the scalar register storage address indicated by the destination storage address in the data copy instruction as an example for explanation. Figure 6 As shown, the length of the data copy instruction is 32 bytes (0 to 31), and Rn and Rt represent the register numbers, that is, the numbers of the vector registers or general registers. The instruction can be: LD64G C[ <xt> ]， <xs> ，[ <xn>{, #0}], Xt represents the destination register, Xs represents the status register, and Xn represents the source storage address. This instruction indicates to read data of the length indicated by the target data type from the memory addresses stored in the consecutive registers Xn to X(n+7), and then copy it to the space corresponding to the 64-bit scalar address stored in the destination register Xt, and write the stored status result into the status register Xs.

[0080] 402. Based on the data copy instruction, a data request is sent to each target memory controller, where the target memory controller is a memory controller corresponding to a source storage address among multiple memory controllers. The data request is used to indicate multiple source storage addresses and target data types corresponding to the target memory controller. The data request is used by the target memory controller to determine a memory block.

[0081] The processing subsystem determines the memory controller that manages the source memory address as the target memory controller.

[0082] 403. Receive a memory block sent by at least one target memory controller, where the memory block sent by the target memory controller includes data of multiple source storage addresses corresponding to the target memory controller, and the length of the memory block is equal to the length of the cache line.

[0083] 404. Cache each received memory block based on the destination storage address.

[0084] For example, when receiving memory blocks respectively sent by multiple target memory controllers, the processing subsystem aggregates data in the received memory blocks into at least one target cache line, and then caches the at least one target cache line based on the destination storage address.

[0085] Taking the destination storage address indicating the space in the vector register as an example, the processing subsystem may cache at least one target cache line in the valid bit of the vector register, and the invalid bit may be set to 0.

[0086] In summary, the data access method provided in the embodiment of the present application first receives a data copy instruction, the data copy instruction carries multiple source storage addresses, target data types and destination storage addresses, and then based on the data copy instruction, sends a data request to each target memory controller, the target memory controller is a memory controller corresponding to the source storage address among multiple memory controllers, the data request is used to indicate the multiple source storage addresses and target data types corresponding to the target memory controller, the data request is used for the target memory controller to determine the memory block, and when receiving the memory block sent by at least one target memory controller, caches each received memory block based on the destination storage address, the memory block sent by the target memory controller includes data of multiple source storage addresses corresponding to the target memory controller, and when receiving the memory blocks sent by multiple target memory controllers respectively, aggregates the data in the received memory blocks into at least one target cache line, compared with the situation in which there is only one valid data in a cache line length in the related art, there will be multiple valid data in a cache line length in the embodiment of the present application, thereby effectively improving the utilization rate of the cache line and the efficiency of memory loading data. In addition, the length of the memory block in the embodiment of the present application is equal to the length of the cache line, so the existing bus transmission protocol and channel can be used to receive the memory block, without modifying the transmission protocol from the memory controller to the processing subsystem, nor modifying the existing cache mechanism or adding flying wires, thereby reducing the chip manufacturing cost. In addition, the embodiment of the present application does not need to make a judgment before accessing sparse address data, so it will not affect the data loading performance of other data access scenarios other than non-sparse address and discontinuous address access.

[0087] The sequence of the methods provided in the embodiments of the present application can be adjusted appropriately, and the process can be increased or decreased accordingly according to the situation. Any technician familiar with the technical field can easily think of a method of change within the technical scope disclosed in this application, which should be included in the protection scope of this application, and the embodiments of the present application do not limit this.

[0088] The functions of each module in the data access system are described below based on the aforementioned data access method. Among them, the processing subsystem is used to receive a data copy instruction. The processing subsystem is also used to send a data request to each target memory controller based on the data copy instruction. The target memory controller is used to read the first memory block indicated by each corresponding source storage address from the memory based on the data request, and the length of the first memory block is the basic unit for accessing the memory. The target memory controller is also used to extract the data of each corresponding source storage address from each first memory block read, and merge the data of each corresponding source storage address according to the length of the cache line to obtain a second memory block. The target memory controller is also used to send the second memory block to the processing subsystem. The processing subsystem is also used to store each received second memory block based on the destination storage address.

[0089] The process of obtaining the second memory block according to the read first memory block can be performed by the memory controller merging unit in the target memory controller. As mentioned above, the processing subsystem includes a processor and a merging unit. When the merging unit is located outside the processor and the memory controller, the processor core is used to receive the data copy instruction and identify the data copy instruction. Then, based on the data copy instruction, a data request is sent to each target memory controller. The target memory controller is used to send the second memory block to the merging unit, and the merging unit is used to store each received second memory block based on the destination storage address.

[0090] For example, Figure 1 For example, CPU 10 receives a data copy instruction, and the data copy instruction carries multiple source storage addresses A1 to A8, the target data type is L, and the destination storage address is Ad / Zd, where Ad represents the address in the cache and Zd represents the address in the register. CPU 10 determines that the target memory controller is memory controller 110 and memory controller 111 based on the source storage addresses A1 to An, and CPU 10 sends data requests memcp to memory controller 110 and memory controller 111 respectively. The memcp sent to memory controller 110 is used to indicate multiple source storage addresses A1, A2, A3 and A4, L and Ad1, Ad1 represents the target address, indicating the location where the memcp sent to memory controller 110 needs to be loaded, which is determined by the memcp. The memcp sent to memory controller 111 is used to indicate multiple source storage addresses A5, A6, A7 and A8, L and Ad2, Ad2 represents the target address, indicating the location where the memcp sent to memory controller 111 needs to be loaded, which is determined by the memcp. The memory controller 110 sends a load instruction Load(A1, A3) to the main memory 120 and a load instruction Load(A2, A4) to the main memory 121. The memory controller 111 sends a load instruction Load(A5, A6) to the main memory 122 and a load instruction Load(A7, A8) to the main memory 123.

[0091] Afterwards, the memory controller 110 receives multiple first memory blocks returned by the memory: [A1.d……], [A2.d……], [A3.d……], [A4.d……]. The memory controller 111 receives multiple first memory blocks returned by the memory: [A5.d……], [A6.d……], [A7.d……], [A8.d……], Ai.d represents the data at the address Ai, Ai.d…… represents the first memory block indicated by Ai, 1≤i≤8, and is an integer.

[0092] The memory controller merging unit 110a extracts A1.d, A2.d, A3.d, A4.d from [A1.d…], [A2.d…], [A3.d…], [A4.d…], and assuming that the total length of A1.d, A2.d, A3.d, A4.d is half the cache line length, 0s are filled in the free positions so that the total length of A1.d, A2.d, A3.d, A4.d and the filled 0s is equal to the cache line length, and a second memory block is obtained: [A1.d, A2.d, A3.d, A4.d, 0, 0, 0, 0].

[0093] The memory controller merging unit 111b extracts A5.d, A6.d, A7.d, A8.d from [A5.d…], [A6.d…], [A7.d…], [A8.d…], and assuming that the total length of A5.d, A6.d, A7.d, A8.d is half the cache line length, 0s are filled in the free positions so that the total length of A5.d, A6.d, A7.d, A8.d and the filled 0s is equal to the cache line length, and the second memory block is obtained: [A5.d, A6.d, A7.d, A8.d, 0, 0, 0, 0].

[0094] The memory controller 110 sends [A1.d, A2.d, A3.d, A4.d, 0, 0, 0, 0] to the merging unit 13. The memory controller 111 sends [A5.d, A6.d, A7.d, A8.d, 0, 0, 0, 0] to the merging unit 13. The merging unit 13 aggregates the non-zero data in the two second memory blocks into one cache line: [A1.d, A2.d, A3.d, A4.d, A5.d, A6.d, A7.d, A8.d]. The merging unit 13 caches [A1.d, A2.d, A3.d, A4.d, A5.d, A6.d, A7.d, A8.d] in the L3 cache based on Ad / Zd.

[0095] When the merging unit is located in the processor, the processor core is used to receive and identify the data copy instruction, convert the data copy instruction into an instruction of the processor (load request), and send the load request to the corresponding merging unit. The merging unit that receives the load request is used to send a data request to each target memory controller based on the load request. The target memory controller is used to send a second memory block to the merging unit, and the merging unit is used to store each received second memory block based on the destination storage address.

[0096] For example, Figure 2 For example, core0 receives a data copy instruction, and the data copy instruction carries multiple source storage addresses A1 to A8, the target data type is L, and the destination storage address is Zd. core0 converts the data copy instruction into a load request and sends the load request to the corresponding merging unit. The merging unit determines that the target memory controller is the memory controller 210 and the memory controller 212 based on the source storage addresses A1 to A8 indicated by the load request. The merging unit sends a data request memcp to the memory controller 210 and the memory controller 212 respectively. The memcp type is a device request, and the memcp is converted into a standard request at the Hydra root agent 230 and the Hydra root agent 231.

[0097] The memcp sent to the memory controller 210 is used to indicate multiple source storage addresses A1, A3, A5, A6, and L. The memcp sent to the memory controller 212 is used to indicate multiple source storage addresses A2, A4, A7, A8, and L. The memory controller 210 sends a load instruction Load (A1, A3, A5, A6) to the main memory 220 and the main memory 221, and the memory controller 212 sends a load instruction Load (A2, A4, A7, A8) to the main memory 224 and the main memory 225.

[0098] Afterwards, the memory controller 210 receives multiple first memory blocks returned by the memory: [A1.d...], [A3.d...], [A5.d...], [A6.d...]. The memory controller 212 receives multiple first memory blocks returned by the memory: [A2.d...], [A4.d...], [A7.d...], [A8.d...], Ai.d represents the data at the address Ai, Ai.d... represents the first memory block indicated by Ai, 1≤i≤8, and is an integer.

[0099] The memory controller merging unit 210a extracts A1.d, A3.d, A5.d, A6.d from [A1.d…], [A3.d…], [A5.d…], [A6.d…], and assuming that the total length of A1.d, A3.d, A5.d, A6.d is half the cache line length, 0s are filled in the free positions so that the total length of A1.d, A3.d, A5.d, A6.d and the filled 0s is equal to the cache line length, and the second memory block is obtained: [A1.d, 0, A3.d, 0, A5.d, A6.d, 0, 0].

[0100] The memory controller merging unit 212a extracts A2.d, A4.d, A7.d, A8.d from [A2.d…], [A4.d…], [A7.d…], [A8.d…], and assuming that the total length of A2.d, A4.d, A7.d, A8.d is half the cache line length, 0s are filled in the free positions so that the total length of A2.d, A4.d, A7.d, A8.d and the filled 0s is equal to the cache line length, and the second memory block is obtained: [0, A2.d, 0, A4.d, 0, 0, A7.d, A8.d].

[0101] The memory controller 210 sends [A1.d, 0, A3.d, 0, A5.d, A6.d, 0, 0], c0, c0 is a temporary address, which is allocated by the memory controller merging unit 210a or the merging unit corresponding to core0. The memory controller 212 sends [0, A2.d, 0, A4.d, 0, 0, A7.d, A8.d], c1, c1 is a temporary address, which is allocated by the memory controller merging unit 212a or the merging unit corresponding to core0 to the merging unit corresponding to core0. The merging unit corresponding to core0 aggregates the non-zero data in the two second memory blocks into a cache line: [A1.d, A2.d, A3.d, A4.d, A5.d, A6.d, A7.d, A8.d]. The merging unit corresponding to core0 caches [A1.d, A2.d, A3.d, A4.d, A5.d, A6.d, A7.d, A8.d] in the L3 cache based on Zd.

[0102] In the above process, the processor core or the merging unit will directly send a data request to the memory controller through the bus, bypassing the L1 cache and L2 cache to ensure cache consistency.

[0103] When the merging unit is located in the memory controller, the corresponding process can refer to the aforementioned process, and the embodiments of the present application will not be described in detail here.

[0104] The above mainly introduces the data access method provided by the embodiment of the present application from the perspective of the device. It is understandable that, in order to realize the above functions, the device includes a hardware structure and / or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiment disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0105] The embodiment of the present application can divide the functional modules of the device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing subsystem. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0106] Figure 7 A block diagram of a data access device provided in an embodiment of the present application, in the case of dividing each functional module according to each function, the data access device 500 may include a transceiver module 501 and a processing module 502. Exemplarily, the data access device may be a processing subsystem or a memory controller, or a chip therein or other combined devices, components, etc. having the functions of the above-mentioned data access device. When the data access device 500 is a processing subsystem or a memory controller, the transceiver module 501 may be a transceiver, and the transceiver may include an antenna and a radio frequency circuit, etc.; the processing module 502 may be a processor (or a processing circuit), such as a baseband processor, and the baseband processor may include one or more CPUs. When the data access device 500 is a device or component having the above-mentioned functions, the transceiver module 501 may be a radio frequency unit; the processing module 502 may be a processor (or a processing circuit), such as a baseband processor. When the data access device 500 is a chip system, the transceiver module 501 may be an input and output interface of a chip (such as a baseband chip); the processing module 502 may be a processor (or a processing circuit) of the chip system, and may include one or more central processing units. It should be understood that the transceiver module 501 in the embodiment of the present application can be implemented by a transceiver or a transceiver-related circuit component; the processing module 502 can be implemented by a processor or a processor-related circuit component (or, referred to as a processing circuit).

[0107] The transceiver module 501 can be used to execute Figure 3 and Figure 4 All transceiver operations in the embodiment shown, and / or other processes for supporting the technology described herein; the processing module 502 can be used to perform Figure 3 and Figure 4 All operations except the transceiver operation in the illustrated embodiment, and / or other processes for supporting the technology described herein. The transceiver module 501 may include a sending module and / or a receiving module, respectively, for performing Figure 3 and Figure 4 The operations of transmission and reception in the illustrated embodiment.

[0108] When the data access device is a memory controller, or a chip in a memory controller, or other combined devices, components, etc. having the functions of the above-mentioned data access device, the data access device includes:

[0109] A transceiver module, used for receiving a data request, the data request is used for indicating a plurality of source storage addresses and a target data type;

[0110] A processing module, configured to read, based on a data request, from a memory a first memory block indicated by each source storage address of a plurality of source storage addresses, wherein a length of the first memory block is a basic unit for accessing the memory;

[0111] The processing module is further used to extract data of each source storage address from the first memory block indicated by each source storage address;

[0112] The processing module is further used to merge the data of each source storage address according to the length of the cache line to obtain a second memory block;

[0113] The transceiver module is further used to send the second memory block to the processing subsystem, so that the processing subsystem caches the second memory block.

[0114] In combination with the above solution, the length of the first memory block is smaller than the length of the cache line.

[0115] In combination with the above solution, multiple source storage addresses are not continuous.

[0116] When the data access device is a processing subsystem, or a chip in the processing subsystem, or other combined devices, components, etc. having the functions of the above-mentioned data access device, the data access device includes:

[0117] The transceiver module is used to receive a data copy instruction, which carries a plurality of source storage addresses, a target data type and a destination storage address;

[0118] The transceiver module is further used to send a data request to each target memory controller based on the data copy instruction, the target memory controller is a memory controller corresponding to the source storage address among the multiple memory controllers, the data request is used to indicate the multiple source storage addresses and the target data type corresponding to the target memory controller, and the data request is used for the target memory controller to determine the memory block;

[0119] The transceiver module is further used to receive a memory block sent by at least one target memory controller;

[0120] The processing module is used for caching each received memory block based on the destination storage address.

[0121] In combination with the above scheme, the processing module is specifically used to: when receiving memory blocks respectively sent by multiple target memory controllers, aggregate the data in the received memory blocks into at least one target cache line; based on the destination storage address, cache at least one target cache line.

[0122] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 600 may be a memory controller or a chip or functional module in a memory controller, or a processing subsystem or a chip or functional module in a processing subsystem. Figure 8 As shown, the electronic device 600 includes a processor 601 , a transceiver 602 and a communication circuit 603 .

[0123] The processor 601 is used to execute the following Figure 3 and Figure 4 In any step of the method embodiment shown, when executing a process such as receiving a data request, the transceiver 602 and the communication line 603 may be selectively called to complete the corresponding operation.

[0124] Furthermore, the electronic device 600 may further include a memory 604 . The processor 601 , the memory 604 and the transceiver 602 may be connected via a communication line 603 .

[0125] The transceiver 602 is used to communicate with other devices or other communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The transceiver 602 can be a module, a circuit, a transceiver or any device capable of achieving communication.

[0126] The transceiver 602 is mainly used for sending and receiving requests, etc., and may include a transmitter and a receiver, which respectively send and receive requests, etc.; operations other than sending and receiving requests, etc. are implemented by the processor, such as reading the first memory block indicated by each source storage address in multiple source storage addresses from the memory based on a data request, etc.

[0127] The communication line 603 is used to transmit information between the components included in the electronic device 600.

[0128] In one design, the processor may be considered as the logic circuit and the transceiver may be considered as the interface circuit.

[0129] The memory 604 is used to store instructions, where the instructions may be computer programs.

[0130] It should be noted that the memory 604 can exist independently of the processor 601, or can be integrated with the processor 601. The memory 604 can be used to store instructions or program codes or some data, etc. The memory 604 can be located inside the electronic device 600, or outside the electronic device 600, without limitation. The processor 601 is used to execute the instructions stored in the memory 604 to implement the method provided in the above embodiment of the present application.

[0131] In one example, the processor 601 may include one or more processors, such as Figure 8 Processor 0 and processor 1 in.

[0132] As an optional implementation, the electronic device 600 includes multiple processors, for example, Figure 8 In addition to the processor 601, a processor 607 may also be included.

[0133] As an optional implementation, the electronic device 600 further includes an output device 605 and an input device 606. Exemplarily, the input device 606 is a keyboard, a mouse, a microphone, a joystick, and the like, and the output device 605 is a display screen, a speaker, and the like.

[0134] It should be noted that the electronic device 600 may be a chip system or a Figure 8 Devices with similar structures in the chip system. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message name or parameter name in the message exchanged between the various devices in the embodiment of this application is only an example, and other names can also be used in the specific implementation without limitation. In addition, Figure 8 The components shown in the figure do not constitute a limitation on the electronic device 600. Figure 8 In addition to the components shown, the electronic device 600 may include Figure 8 More or fewer components may be shown, or certain components may be combined, or the components may be arranged differently.

[0135] The processor and transceiver described in the present application can be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0136] Fig. 9 The following is a schematic diagram of a data access device provided in an embodiment of the present application. The data access device can be applied to the scenario shown in the above method embodiment. For ease of explanation, Fig. 9 Only the main components of the data access device are shown, including a processor, a memory, a control circuit, and an input-output device. The processor is mainly used to process the communication protocol and communication data, execute the software program, and process the data of the software program. The memory is mainly used to store the software program and data. The control circuit is mainly used for power supply and transmission of various electrical signals. The input-output device is mainly used to receive data input by the user and output data to the user.

[0137] When the data access device is a memory controller or a processing subsystem, the control circuit can be a mainboard, the memory includes a hard disk, RAM, ROM and other media with storage functions, the processor can include a baseband processor and a central processing unit, the baseband processor is mainly used to process the communication protocol and communication data, the central processing unit is mainly used to control the entire data access device, execute software programs, and process the data of the software programs, and the input and output devices include a display screen, a keyboard and a mouse, etc.; the control circuit can further include or connect a transceiver circuit or a transceiver, such as: a network cable interface, etc., for sending or receiving data or signals, such as data transmission and communication with other devices. Furthermore, it can also include an antenna for sending and receiving requests, and for data / request transmission with other devices.

[0138] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes any of the methods described in the embodiments of the present application.

[0139] The present application embodiment also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be executed by a computer or a device with data access capability to execute a computer program or instruction to control the relevant hardware to complete, and the computer program or the group of instructions can be stored in the above computer-readable storage medium, and the computer program or the group of instructions can include the processes of the above method embodiments when executed. The computer-readable storage medium can be an internal storage unit of the memory controller or processing subsystem of any of the above embodiments, such as a hard disk or memory of the memory controller or processing subsystem. The above computer-readable storage medium can also be an external storage device of the above memory controller or processing subsystem, such as a plug-in hard disk equipped on the above memory controller or processing subsystem, a smart memory card (smartmedia card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both the internal storage unit of the above memory controller or processing subsystem and an external storage device. The above computer-readable storage medium is used to store the above computer program or instruction and other programs and data required by the above memory controller or processing subsystem. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0140] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0141] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0142] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0143] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0145] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0146] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims. The above mainly introduces the data access method provided by the embodiment of the present application from the perspective of the device. It can be understood that in order to achieve the above functions, the device includes a hardware structure and / or software module corresponding to each function. It should be easy for those skilled in the art to realize that, in combination with the algorithm steps of each example described in the embodiment disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.< / xn> < / xs> < / xt> < / mod> < / zm> < / pg> < / zt>

Claims

1. A data access method, characterized in that: The method comprises: receiving a data request, wherein the data request is used to indicate a plurality of source storage addresses and a target data type; Based on the data request, read a first memory block indicated by each source storage address in the plurality of source storage addresses from a memory, wherein a length of the first memory block is a basic unit for accessing the memory; Extracting data of each source storage address from the first memory block indicated by each source storage address; Merge the data of each source storage address according to the length of the cache line to obtain a second memory block; The second memory block is sent to a processing subsystem so that the processing subsystem caches the second memory block.

2. The method according to claim 1, characterized in that The length of the first memory block is smaller than the length of the cache line.

3. The method according to claim 1 or 2, characterized in that: The multiple source storage addresses are not consecutive.

4. A data access method, characterized in that: The method comprises: receiving a data copy instruction, wherein the data copy instruction carries a plurality of source storage addresses, a target data type, and a destination storage address; Based on the data copy instruction, a data request is sent to each target memory controller, the target memory controller being a memory controller corresponding to the source storage address among the multiple memory controllers, the data request is used to indicate the multiple source storage addresses and the target data type corresponding to the target memory controller, and the data request is used by the target memory controller to determine a memory block; Receiving the memory block sent by at least one target memory controller, wherein the memory block sent by the target memory controller includes data of a plurality of source storage addresses corresponding to the target memory controller, and the length of the memory block is equal to the length of the cache line; Based on the destination storage address, each of the received memory blocks is cached.

5. The method according to claim 4, characterized in that The step of caching each of the received memory blocks based on the destination storage address includes: When receiving the memory blocks respectively sent by the plurality of target memory controllers, aggregating data in the received memory blocks into at least one target cache line; Based on the destination storage address, the at least one target cache line is cached.

6. A data access system, characterized in that: The system includes: a processing subsystem and a plurality of memory controllers; The processing subsystem is used to receive a data copy instruction, wherein the data copy instruction carries a plurality of source storage addresses, a target data type, and a destination storage address; The processing subsystem is further used to send a data request to each target memory controller based on the data copy instruction, wherein the target memory controller is a memory controller corresponding to the source storage address among the multiple memory controllers, and the data request is used to indicate the multiple source storage addresses corresponding to the target memory controller and the target data type; The target memory controller is used to read, based on a data request, a first memory block indicated by each corresponding source storage address from a memory, wherein the length of the first memory block is a basic unit for accessing the memory; The target memory controller is further configured to extract data corresponding to each of the source storage addresses from each of the first memory blocks read, and merge the data corresponding to each of the source storage addresses according to the length of the cache line to obtain a second memory block; The target memory controller is further configured to send the second memory block to the processing subsystem; The processing subsystem is further configured to cache each received second memory block based on the destination storage address.

7. The system according to claim 6, characterized in that The processing subsystem is specifically used for: When receiving the second memory blocks respectively sent by the plurality of target memory controllers, aggregating the data in the received second memory blocks into at least one target cache line; Based on the destination storage address, the at least one target cache line is cached.

8. A data access device, characterized in that: The device comprises: A transceiver module, used for receiving a data request, wherein the data request is used for indicating a plurality of source storage addresses and a target data type; a processing module, configured to read, based on the data request, from a memory a first memory block indicated by each source storage address of the plurality of source storage addresses, wherein a length of the first memory block is a basic unit for accessing the memory; The processing module is further used to extract data of each source storage address from the first memory block indicated by each source storage address; The processing module is further used to merge the data of each source storage address according to the length of the cache line to obtain a second memory block; The transceiver module is further configured to send the second memory block to the processing subsystem, so that the processing subsystem caches the second memory block.

9. A data access device, characterized in that: The device comprises: A transceiver module, used for receiving a data copy instruction, wherein the data copy instruction carries a plurality of source storage addresses, a target data type and a destination storage address; The transceiver module is further used to send a data request to each target memory controller based on the data copy instruction, the target memory controller is a memory controller corresponding to the source storage address among the multiple memory controllers, the data request is used to indicate the multiple source storage addresses and the target data type corresponding to the target memory controller, and the data request is used for the target memory controller to determine a memory block; The transceiver module is further used to receive the memory block sent by at least one target memory controller; A processing module is used to cache each of the received memory blocks based on the destination storage address.

10. A data access device, characterized in that: The device comprises: one or more processors; a memory for storing one or more computer programs or instructions; When one or more computer programs or instructions are executed by one or more processors, the one or more processors implement the method according to any one of claims 1 to 3.

11. A data access device, characterized in that: The device comprises: one or more processors; a memory for storing one or more computer programs or instructions; When one or more computer programs or instructions are executed by one or more processors, the one or more processors implement the method as claimed in claim 4 or 5.

12. A data access device, characterized in that: The device comprises: Processing circuits and interface circuits; Wherein, the interface circuit is used to couple with a memory outside the data access device and provide a communication interface for the processing circuit to access the memory; The processing circuit is used to execute program instructions in the memory to implement the method according to any one of claims 1 to 5.

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